JP2006086272A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2006086272A
JP2006086272A JP2004268273A JP2004268273A JP2006086272A JP 2006086272 A JP2006086272 A JP 2006086272A JP 2004268273 A JP2004268273 A JP 2004268273A JP 2004268273 A JP2004268273 A JP 2004268273A JP 2006086272 A JP2006086272 A JP 2006086272A
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film
gate electrode
insulating film
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Atsuyuki Aoyama
敬幸 青山
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo

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  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract

<P>PROBLEM TO BE SOLVED: To suppress low the amount of variation of threshold voltage by suppressing variation of a work function when adopting a high dielectric gate insulating film and a metal gate electrode, and hence restrain the increase of a gate leak current for preventing reliability from being lowered. <P>SOLUTION: A semiconductor device, when a gate electrode 1 is a metal gate electrode or a gate insulating film 4 is the high dielectric gate insulating film, includes a silicon oxide film 2 and a silicon nitride film 3 in order from the side of the gate electrode 1 between the gate electrode 1 and the gate insulating film 4. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、例えばＭＯＳ(Metal Oxide Semiconductor)デバイスのゲートスタック構造に用いて好適の半導体装置に関する。   The present invention relates to a semiconductor device suitable for use in, for example, a gate stack structure of a MOS (Metal Oxide Semiconductor) device.

従来、ＭＯＳデバイスでは、ゲート絶縁膜としてＳｉＯ2ゲート絶縁膜が広く用いられてきた。しかし、ＳｉＯ2ゲート絶縁膜の薄膜化が進み、その厚さが原子数個分にまで薄くなると、ゲートリーク電流が増大してしまい、消費電力や発熱量の増大という問題が深刻になり、その抑制が重要な課題となってきた。
そこで、近年、ゲート絶縁膜として、ＳｉＯ2ゲート絶縁膜よりも誘電率の高い絶縁膜（高誘電率ゲート絶縁膜，High-kゲート絶縁膜）を用いることが提案されている。 Conventionally, in a MOS device, a SiO 2 gate insulating film has been widely used as a gate insulating film. However, as the thickness of the SiO 2 gate insulating film is reduced and the thickness is reduced to several atoms, the gate leakage current increases and the problem of increased power consumption and heat generation becomes serious. Suppression has become an important issue.
Therefore, in recent years, it has been proposed to use an insulating film (high dielectric constant gate insulating film, high-k gate insulating film) having a higher dielectric constant than the SiO 2 gate insulating film as the gate insulating film.

一方、ゲート電極としては、従来、ポリシリコンゲート電極が広く用いられてきた。しかし、ゲート絶縁膜の薄膜化が進むにつれて、ゲート空乏化によってトランジスタのオン電流が低下してしまうという問題が深刻になり、その抑制が重要な課題となってきた。
また、ポリシリコンゲート電極は、高誘電率ゲート絶縁膜と組み合わせて使った場合に、ゲート絶縁膜とゲート電極との界面で欠陥が生じやすく、動作電圧（閾値電圧）が上昇してしまう傾向がある。さらにフォノン振動が発生して、トランジスタのチャネル内での電子の移動を阻害するという問題も発生する。 On the other hand, a polysilicon gate electrode has been widely used as the gate electrode. However, as the gate insulating film becomes thinner, the problem that the on-current of the transistor decreases due to gate depletion becomes serious, and the suppression thereof has become an important issue.
In addition, when a polysilicon gate electrode is used in combination with a high dielectric constant gate insulating film, defects tend to occur at the interface between the gate insulating film and the gate electrode, and the operating voltage (threshold voltage) tends to increase. is there. Further, phonon oscillation occurs, which causes a problem of inhibiting the movement of electrons in the channel of the transistor.

そこで、近年、ゲート電極として、メタルゲート電極を用いることが提案されている。
なお、従来、半導体デバイスにおいて、誘電率の高い膜（高誘電率膜，強誘電率膜）を設ける場合には、この膜からの酸素の拡散が問題の一つとされており、この問題を解決するために種々の提案がなされている（例えば特許文献１〜３参照）。また、リーク電流を抑制するために、高誘電率絶縁膜を設ける技術もある（例えば特許文献４参照）。
特開平５−２４３５６２号公報 特開２０００−２０８７２０号公報 特開２００２−３５９３７０号公報 特開２００３−１８８３５６号公報 In recent years, therefore, it has been proposed to use a metal gate electrode as the gate electrode.
Conventionally, when a film having a high dielectric constant (high dielectric constant film, ferroelectric film) is provided in a semiconductor device, oxygen diffusion from this film has been one of the problems. Various proposals have been made for this purpose (see, for example, Patent Documents 1 to 3). In addition, there is a technique of providing a high dielectric constant insulating film in order to suppress leakage current (see, for example, Patent Document 4).
JP-A-5-243562 JP 2000-208720 A JP 2002-359370 A JP 2003-188356 A

ところで、高誘電率(High-k)ゲート絶縁膜やメタルゲート電極を採用する場合、例えば図４に示すように、高誘電率(High-k)ゲート絶縁膜５０又はＳｉＯ2ゲート絶縁膜５１上に直接メタルゲート電極５２を設けることが考えられる。
しかしながら、高誘電率(High-k)ゲート絶縁膜５０又はＳｉＯ2ゲート絶縁膜５１上に直接メタルゲート電極５２を設けると、高誘電率ゲート絶縁膜５０又はＳｉＯ2ゲート絶縁膜５１とメタルゲート電極５２とが激しく反応してしまうという問題がある。特に、高誘電率ゲート絶縁膜５０とメタルゲート電極５２との反応は、低い温度（例えば５００℃程度）でも進行することが多いため、問題が大きい。このように、ゲート絶縁膜５０，５１とゲート電極５２とが反応してしまうと、ゲートリーク電流の増大（極度の場合には絶縁性の喪失）を招き、信頼性の低下につながることになる。 By the way, when a high dielectric constant (High-k) gate insulating film or a metal gate electrode is adopted, for example, as shown in FIG. 4, the high dielectric constant (High-k) gate insulating film 50 or the SiO 2 gate insulating film 51 is formed. It is conceivable to provide the metal gate electrode 52 directly.
However, when the metal gate electrode 52 is provided directly on the high dielectric constant (High-k) gate insulating film 50 or the SiO 2 gate insulating film 51, the high dielectric constant gate insulating film 50 or the SiO 2 gate insulating film 51 and the metal gate electrode There is a problem that 52 reacts violently. In particular, the reaction between the high dielectric constant gate insulating film 50 and the metal gate electrode 52 often progresses even at a low temperature (for example, about 500 ° C.), which is a serious problem. Thus, if the gate insulating films 50 and 51 and the gate electrode 52 react with each other, an increase in gate leakage current (loss of insulation in an extreme case) is caused, leading to a decrease in reliability. .

また、高誘電率ゲート絶縁膜５０上にポリシリコン（Poly-Si）ゲート電極５３を設けることも考えられる。
しかしながら、この場合にも、上記の組み合わせの場合と同様に、高誘電率ゲート絶縁膜５０とポリシリコンゲート電極５３とが反応してしまうという問題がある。
このような高誘電率ゲート絶縁膜５０とポリシリコンゲート電極５３との反応を抑えるために、図５に示すように、高誘電率ゲート絶縁膜５０とポリシリコンゲート電極５３との間にシリコン窒化膜（ＳｉＮ膜）５４を挟むことが提案されている（例えば上記特許文献３など）。 It is also conceivable to provide a polysilicon (Poly-Si) gate electrode 53 on the high dielectric constant gate insulating film 50.
However, also in this case, there is a problem that the high dielectric constant gate insulating film 50 and the polysilicon gate electrode 53 react as in the case of the above combination.
In order to suppress such a reaction between the high dielectric constant gate insulating film 50 and the polysilicon gate electrode 53, silicon nitride is interposed between the high dielectric constant gate insulating film 50 and the polysilicon gate electrode 53 as shown in FIG. It has been proposed to sandwich a film (SiN film) 54 (for example, Patent Document 3 above).

しかしながら、高誘電率ゲート絶縁膜５０とポリシリコンゲート電極５３との間にＳｉＮ膜５４を挟むと、ＳｉＮ膜５４に含まれる窒素Ｎがゲート電極５３を構成するポリシリコンと反応してしまい、仕事関数が変動してしまう場合がある。そして、仕事関数が変動してしまうと、閾値電圧（Ｖｔｈ）が変動（例えば０．１Ｖ以上）してしまうため、目標とする閾値電圧に調整することが難しくなる。   However, if the SiN film 54 is sandwiched between the high dielectric constant gate insulating film 50 and the polysilicon gate electrode 53, the nitrogen N contained in the SiN film 54 reacts with the polysilicon constituting the gate electrode 53, and the work The function may fluctuate. When the work function varies, the threshold voltage (Vth) varies (for example, 0.1 V or more), and it is difficult to adjust the target threshold voltage.

なお、上記特許文献１〜３には、誘電率の高い膜からの酸素の拡散を抑制するための技術が開示されているに過ぎず、上記の問題については何ら考慮されていない。
また、上記特許文献４は、浮遊電極及び強誘電体層を備えるＭＦＭＩＳ型トランジスタにおいて、上部電極金属と強誘電体層との間や強誘電体層と浮遊電極金属層との間に、絶縁体層として、ＳｉＯ2，Ｓｉ3Ｎ4，ＳｉＯＮのうちのひとつあるいは複数と、高誘電率絶縁膜とを積層させる技術が開示されている。また、Ｓｉ基板と浮遊電極（白金，ポリシリコン，シリサイドなど）との間に、ゲート絶縁膜（ＳｉＯ2膜，Ｓｉ3Ｎ4膜，ＳｉＯＮ膜）と、高誘電率絶縁膜とを設けることも記載されている（例えば段落番号００４９，図５参照）。しかしながら、この文献には、Ｓｉ基板と浮遊電極との間に、絶縁体層として、ゲート絶縁膜（ＳｉＯ2膜，Ｓｉ3Ｎ4膜，ＳｉＯＮ膜）と、高誘電率絶縁膜とを設けることが記載されているに過ぎず、浮遊電極と高誘電率絶縁膜とが反応してしまうという上記の問題については何ら考慮されていない。 Note that Patent Documents 1 to 3 merely disclose a technique for suppressing diffusion of oxygen from a film having a high dielectric constant, and the above problem is not taken into consideration at all.
Further, in Patent Document 4, in an MFMIS transistor having a floating electrode and a ferroelectric layer, an insulator is provided between the upper electrode metal and the ferroelectric layer, or between the ferroelectric layer and the floating electrode metal layer. As a layer, a technique of laminating one or more of SiO 2 , Si 3 N 4 , and SiON and a high dielectric constant insulating film is disclosed. Further, a gate insulating film (SiO 2 film, Si 3 N 4 film, SiON film) and a high dielectric constant insulating film may be provided between the Si substrate and the floating electrode (platinum, polysilicon, silicide, etc.). (See paragraph number 0049, FIG. 5, for example). However, in this document, a gate insulating film (SiO 2 film, Si 3 N 4 film, SiON film) and a high dielectric constant insulating film are provided as an insulator layer between the Si substrate and the floating electrode. Is merely described, and the above problem that the floating electrode reacts with the high dielectric constant insulating film is not considered at all.

本発明は、このような課題に鑑み創案されたもので、高誘電率ゲート絶縁膜やメタルゲート電極を採用する場合に、仕事関数の変動を抑えて閾値電圧の変動量を低く抑えることができるようにした、半導体装置を提供することを目的とする。
また、高誘電率ゲート絶縁膜やメタルゲート電極を採用する場合に、ゲートリーク電流の増大を抑えて、信頼性の低下を招かないようにすることも目的とする。 The present invention has been devised in view of such problems. When a high dielectric constant gate insulating film or a metal gate electrode is employed, the variation of the threshold voltage can be suppressed by suppressing the variation of the work function. An object of the present invention is to provide a semiconductor device.
Another object of the present invention is to suppress an increase in gate leakage current and prevent a decrease in reliability when a high dielectric constant gate insulating film or a metal gate electrode is employed.

このため、本発明の半導体装置は、ゲート電極と、高誘電率ゲート絶縁膜とを備え、ゲート電極がメタルゲート電極であるか、又は、ゲート絶縁膜が高誘電率ゲート絶縁膜である場合に、ゲート電極と高誘電率ゲート絶縁膜との間に、ゲート電極側から順に、シリコン酸化膜、シリコン窒化膜を備えることを特徴としている（請求項１）。
また、本発明の半導体装置は、ゲート電極と、高誘電率ゲート絶縁膜とを備え、ゲート電極がメタルゲート電極であるか、又は、ゲート絶縁膜が高誘電率ゲート絶縁膜である場合に、ゲート電極と高誘電率ゲート絶縁膜との間に、シリコン酸化膜を備えることを特徴としている（請求項２）。 For this reason, the semiconductor device of the present invention includes a gate electrode and a high dielectric constant gate insulating film, and the gate electrode is a metal gate electrode or the gate insulating film is a high dielectric constant gate insulating film. A silicon oxide film and a silicon nitride film are provided in this order from the gate electrode side between the gate electrode and the high dielectric constant gate insulating film.
The semiconductor device of the present invention includes a gate electrode and a high dielectric constant gate insulating film, and when the gate electrode is a metal gate electrode or when the gate insulating film is a high dielectric constant gate insulating film, A silicon oxide film is provided between the gate electrode and the high dielectric constant gate insulating film (claim 2).

特に、ゲート電極をメタルゲート電極とする場合に適用するのが好ましい。この場合、メタルゲート電極は、Ｍｏ，Ｗ，Ｔａ，Ｔｉ，Ｈｆ，Ｚｒ，Ｖ，Ｃｒ，Ｎｂを含む金属群から選ばれるいずれか１種の金属を含むものとして構成するのが好ましい（請求項３）。また、高誘電率ゲート絶縁膜は、酸化ハフニウム，酸化ジルコニウム，酸化アルミニウム，酸化イットリウム，ランタン族酸化物、又は前記各酸化物のシリケート、又は前記各酸化物若しくは前記各シリケートを含む混合物により構成するのが好ましい（請求項４）。   In particular, it is preferable to apply when the gate electrode is a metal gate electrode. In this case, the metal gate electrode is preferably configured to include any one metal selected from a metal group including Mo, W, Ta, Ti, Hf, Zr, V, Cr, and Nb. 3). The high dielectric constant gate insulating film is made of hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, lanthanum group oxide, silicate of each oxide, or each oxide or a mixture containing each silicate. (Claim 4).

さらに、本発明の半導体装置は、Ｍｏ，Ｗ，Ｔａ，Ｔｉ，Ｈｆ，Ｚｒ，Ｖ，Ｃｒ，Ｎｂを含む金属群から選ばれるいずれか１種の金属を含む金属膜と、高誘電率膜とを備え、金属膜と高誘電率膜との間に、金属膜側から順に、シリコン酸化膜、シリコン窒化膜を備えることを特徴としている（請求項５）。   Furthermore, the semiconductor device of the present invention includes a metal film containing any one metal selected from a metal group including Mo, W, Ta, Ti, Hf, Zr, V, Cr, and Nb, a high dielectric constant film, And a silicon oxide film and a silicon nitride film in that order from the metal film side between the metal film and the high dielectric constant film.

したがって、本発明によれば、ゲート電極と高誘電率ゲート絶縁膜との間にシリコン酸化膜が設けられているため、仕事関数の変動を抑えることができ、これにより、閾値電圧の変動量を低く抑えることができるという利点がある。
また、本発明によれば、ゲート電極と高誘電率ゲート絶縁膜との間にシリコン窒化膜が設けられているため、ゲートリーク電流の増大を抑えることができ、ひいては信頼性を確保できるようになるという利点がある。 Therefore, according to the present invention, since the silicon oxide film is provided between the gate electrode and the high dielectric constant gate insulating film, it is possible to suppress the work function fluctuation, thereby reducing the threshold voltage fluctuation amount. There is an advantage that it can be kept low.
In addition, according to the present invention, since the silicon nitride film is provided between the gate electrode and the high dielectric constant gate insulating film, an increase in gate leakage current can be suppressed, and as a result, reliability can be ensured. There is an advantage of becoming.

以下、図面により、本発明の実施の形態にかかる半導体装置について説明する。
本実施形態にかかる半導体装置[例えばＣＭＯＳ(Complementary Metal Oxide Semiconductor)デバイスなどのＭＯＳデバイス（例えばＭＯＳトランジスタを含む）]は、図１に示すように、ゲート電極１と、シリコン酸化膜２と、シリコン窒化膜３と、ゲート絶縁膜４とを備えるものとして構成される。 Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.
As shown in FIG. 1, the semiconductor device according to the present embodiment [for example, a MOS device (including a MOS transistor) such as a CMOS (Complementary Metal Oxide Semiconductor) device] includes a gate electrode 1, a silicon oxide film 2, and a silicon oxide film. It is configured to include a nitride film 3 and a gate insulating film 4.

つまり、本半導体装置は、ゲート電極１がメタルゲート電極であるか、又は、ゲート絶縁膜４が高誘電率ゲート絶縁膜である場合に、ゲート電極１とゲート絶縁膜４との間に、ゲート電極１側から順に、シリコン酸化膜２、シリコン窒化膜３を備えるものとする。
ここで、ゲート電極１は、メタルゲート電極とするのが好ましい。特に、製造工程において活性化のために１０００℃以上の高温にする熱処理（アニール処理）を行なうことを考慮すると、熱処理工程における上限温度よりも高い融点を有する高融点金属により構成するのが好ましい。例えば、Ｍｏ，Ｗ，Ｔａ，Ｔｉ，Ｈｆ，Ｚｒ，Ｖ，Ｃｒ，Ｎｂを含む金属群から選ばれるいずれか１種の金属を含む金属膜とするのが好ましい。つまり、Ｍｏ，Ｗ，Ｔａ，Ｔｉ，Ｈｆ，Ｚｒ，Ｖ，Ｃｒ，Ｎｂを含む金属群から選ばれるいずれか１種の金属、又はこれらの金属の化合物、又はこれらの金属や化合物を含む混合物により構成される金属膜とするのが好ましい。 That is, in the semiconductor device, when the gate electrode 1 is a metal gate electrode or when the gate insulating film 4 is a high dielectric constant gate insulating film, the gate electrode 1 is interposed between the gate insulating film 4 and the gate insulating film 4. It is assumed that a silicon oxide film 2 and a silicon nitride film 3 are provided in order from the electrode 1 side.
Here, the gate electrode 1 is preferably a metal gate electrode. In particular, in consideration of performing a heat treatment (annealing) at a high temperature of 1000 ° C. or higher for activation in the manufacturing process, it is preferable to use a refractory metal having a melting point higher than the upper limit temperature in the heat treatment process. For example, a metal film containing any one metal selected from a metal group containing Mo, W, Ta, Ti, Hf, Zr, V, Cr, and Nb is preferable. That is, by any one metal selected from the metal group containing Mo, W, Ta, Ti, Hf, Zr, V, Cr, and Nb, or a compound of these metals, or a mixture containing these metals and compounds. The metal film is preferably configured.

なお、ゲート絶縁膜を高誘電率ゲート絶縁膜とする場合には、ゲート電極はポリシリコンなどの一般に用いられている材料によって構成しても良い。
ゲート絶縁膜４は、高誘電率ゲート絶縁膜（High-kゲート絶縁膜，高誘電率膜）とするのが好ましい。例えば、酸化ハフニウム（ＨｆＯ2），酸化ジルコニウム（ＺｒＯ2），酸化アルミニウム（Ａｌ2Ｏ3），酸化イットリウム（Ｙ2Ｏ3），ランタン族酸化物（例えばＬａ２０３）、又はこれらの酸化物のシリケート（例えば、ＨｆＯ2の場合、Ｈｆ ＳｉxＯy；Ｈｆシリケート）［Ｎを含んだシリケート（例えば、ＨｆＯ2の場合、Ｈｆ ＳｉxＯyＮz；Ｈｆシリケート）でも良い］、又はこれらの酸化物やそのシリケートを含む混合物（例えばＨｆＡｌＯx）などにより構成するのが好ましい。 When the gate insulating film is a high dielectric constant gate insulating film, the gate electrode may be made of a commonly used material such as polysilicon.
The gate insulating film 4 is preferably a high dielectric constant gate insulating film (High-k gate insulating film, high dielectric constant film). For example, hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), yttrium oxide (Y 2 O 3 ), lanthanum group oxide (eg, La203), or silicates of these oxides (For example, in the case of HfO 2 , Hf Si x O y ; Hf silicate) [It may be a silicate containing N (for example, in the case of HfO 2 , Hf Si x O y N z ; Hf silicate)] or oxidation thereof It is preferable to constitute the product or a mixture containing the silicate (for example, HfAlO x ).

なお、ゲート電極をメタルゲート電極とする場合には、ゲート絶縁膜はＳｉＯ2などの一般に用いられている材料によって構成しても良い。
シリコン窒化膜３は、ゲートリーク電流の増大を抑えるために、ゲート電極１とゲート絶縁膜４との間に設けられる。ここでは、シリコン窒化膜をＳｉＮ（窒化ケイ素）により形成している。 When the gate electrode is a metal gate electrode, the gate insulating film may be made of a commonly used material such as SiO 2 .
The silicon nitride film 3 is provided between the gate electrode 1 and the gate insulating film 4 in order to suppress an increase in gate leakage current. Here, the silicon nitride film is formed of SiN (silicon nitride).

シリコン酸化膜２は、仕事関数の変動を抑えて閾値電圧の変動量を低く抑えるために、シリコン窒化膜３とゲート電極１との間に設けられる。ここでは、シリコン酸化膜をＳｉＯ2（酸化シリコン）により形成している。
上述のように、ゲートリーク電流の増大を抑えるために、シリコン窒化膜３を設けると、ゲート電極１とシリコン窒化膜３とが接することになる。一方、高融点金属に窒素が導入されると仕事関数が変化してしまう。例えば、モリブデンＭｏに窒素が導入されると仕事関数が変化してしまうことについては、例えば、IEEE Electron Device Letters, vol.23, no.1, Page:49-51に記載されている。このため、特に、ゲート電極１を高融点金属により構成する場合に、高融点金属からなるメタルゲート電極１にシリコン窒化膜３から窒素が導入され、仕事関数が変化してしまう可能性が高い。したがって、特に、ゲート電極１を高融点金属により構成する場合に、シリコン窒化膜３とゲート電極１との間にシリコン酸化膜２を設けることが重要になる。 The silicon oxide film 2 is provided between the silicon nitride film 3 and the gate electrode 1 in order to suppress a variation in the threshold voltage by suppressing a variation in work function. Here, the silicon oxide film is formed of SiO 2 (silicon oxide).
As described above, when the silicon nitride film 3 is provided in order to suppress an increase in gate leakage current, the gate electrode 1 and the silicon nitride film 3 are in contact with each other. On the other hand, when nitrogen is introduced into the refractory metal, the work function changes. For example, the fact that the work function changes when nitrogen is introduced into molybdenum Mo is described in, for example, IEEE Electron Device Letters, vol. 23, no. 1, Page: 49-51. For this reason, in particular, when the gate electrode 1 is made of a refractory metal, it is highly possible that nitrogen is introduced from the silicon nitride film 3 into the metal gate electrode 1 made of the refractory metal and the work function changes. Therefore, particularly when the gate electrode 1 is made of a refractory metal, it is important to provide the silicon oxide film 2 between the silicon nitride film 3 and the gate electrode 1.

ここでは、ゲート電極１とゲート絶縁膜４との間に、シリコン酸化膜２と、シリコン窒化膜３とを設け、ゲート絶縁膜／シリコン窒化膜／シリコン酸化膜／ゲート電極（例えばHigh-k／ＳｉＮ／ＳｉＯ2／ゲート電極）の積層構造にし、その厚さ（膜厚）を、その後の熱処理やゲート電極１の材料の種類（例えばメタルの種類）によって調整するようにしている。このように構成することで、例えばゲート絶縁膜／シリコン酸化膜／ゲート電極（例えばHigh-k／ＳｉＯ2／ゲート電極）という積層構造にする場合と比較して、全体の厚さを薄くすることができるという効果もある。 Here, a silicon oxide film 2 and a silicon nitride film 3 are provided between the gate electrode 1 and the gate insulating film 4, and a gate insulating film / silicon nitride film / silicon oxide film / gate electrode (for example, High-k / A laminated structure (SiN / SiO 2 / gate electrode) is formed, and the thickness (film thickness) is adjusted by the subsequent heat treatment and the type of material of the gate electrode 1 (for example, the type of metal). By configuring in this way, the overall thickness is reduced as compared with, for example, a stacked structure of gate insulating film / silicon oxide film / gate electrode (for example, High-k / SiO 2 / gate electrode). There is also an effect that can be done.

逆に言うと、全体の厚さを薄くする点をそれほど考慮しなくてもよい場合には、上述の構成において、シリコン窒化膜３を設けずに、ゲート絶縁膜／シリコン酸化膜／ゲート電極（例えばHigh-k／ＳｉＯ2／ゲート電極）という積層構造にすることもできる。
次に、本実施形態にかかる半導体装置の製造方法について説明する。ここでは、２つの代表的な例について説明するが、これに限られるものではない。以下、説明を分かり易くするため、本発明に関わる部分を中心に説明する。
（第１の製造方法）
まず、第１の製造方法について、図２を参照しながら説明する。 Conversely, in the case where it is not necessary to consider so much that the entire thickness is reduced, in the above configuration, without providing the silicon nitride film 3, the gate insulating film / silicon oxide film / gate electrode ( For example, a stacked structure of High-k / SiO 2 / gate electrode) may be used.
Next, a method for manufacturing the semiconductor device according to the present embodiment will be described. Here, two typical examples will be described, but the present invention is not limited to this. Hereinafter, in order to make the explanation easy to understand, the description will focus on the parts related to the present invention.
(First manufacturing method)
First, the first manufacturing method will be described with reference to FIG.

第１の製造方法は、基本的に、ＭＯＳデバイスを製造する際の一般的な製造方法である。この方法によれば、従来の製造装置をそのまま使えることになる。
まず、図２（Ａ）に示すように、ＳＴＩ（Shallow Trench Isolation）技術を用いて、Ｓｉ基板５に浅い溝を形成し、絶縁物で埋めて素子分離領域６を形成する。
次に、図２（Ｂ）に示すように、Ｎウエル（Ｎ−ＷＥＬＬ）７及びＰウェル（Ｐ−ＷＥＬＬ）８を形成し、チャネル注入を行なう。 The first manufacturing method is basically a general manufacturing method for manufacturing a MOS device. According to this method, the conventional manufacturing apparatus can be used as it is.
First, as shown in FIG. 2A, shallow trenches are formed in the Si substrate 5 using an STI (Shallow Trench Isolation) technique, and an element isolation region 6 is formed by filling with an insulator.
Next, as shown in FIG. 2B, an N well (N-WELL) 7 and a P well (P-WELL) 8 are formed, and channel implantation is performed.

次いで、図２（Ｃ）に示すように、例えばＨｆシリケートをＭＯＣＶＤ(Metal Organic Chemical Vapor Deposition)法により堆積させて、例えば１．５ｎｍのＨｆシリケート膜（高誘電率膜）９［これがゲート絶縁膜（高誘電率ゲート絶縁膜）となる］を形成する。なお、Ｈｆシリケート膜９の下側に他の膜を形成しておいても良い。
次に、図２（Ｄ）に示すように、例えばＬＰＣＶＤ(Low Pressure Chemical Vapor Deposition)法によりＳｉＨ2Ｃｌ2（ＤＣＳ；ジクロロシラン）−ＮＨ3（アンモニア）のガス系で、例えば６８０℃程度の所定の温度条件として、ＳｉＮを堆積させて、例えば０．２ｎｍのＳｉＮ膜（シリコン窒化膜）１０を形成する。 Next, as shown in FIG. 2C, for example, Hf silicate is deposited by MOCVD (Metal Organic Chemical Vapor Deposition) method, for example, a 1.5 nm Hf silicate film (high dielectric constant film) 9 [this is a gate insulating film. (To be a high dielectric constant gate insulating film). Another film may be formed below the Hf silicate film 9.
Next, as shown in FIG. 2D, for example, a gas system of SiH 2 Cl 2 (DCS; dichlorosilane) -NH 3 (ammonia) by LPCVD (Low Pressure Chemical Vapor Deposition) method, for example, at about 680 ° C. As a predetermined temperature condition, SiN is deposited to form, for example, a 0.2 nm SiN film (silicon nitride film) 10.

なお、例えばＬＰＣＶＤ法によりＳｉＨ4（モノシラン）−ＮＨ3（アンモニア）のガス系で、例えば６００℃程度の所定の温度条件として、ＳｉＮを堆積させて、ＳｉＮ膜（シリコン窒化膜）１０を形成しても良い。
次いで、図２（Ｅ）に示すように、ＣＶＤ(Chemical Vapor Deposition)法により堆積させたＳｉＮ膜（ＣＶＤ−ＳｉＮ）の表面を、オゾン中で、かつ常温で酸化して、ＳｉＯ2膜（シリコン酸化膜）１１を形成する。 For example, SiN is deposited by a LPCVD method in a gas system of SiH 4 (monosilane) -NH 3 (ammonia) under a predetermined temperature condition of, for example, about 600 ° C. to form a SiN film (silicon nitride film) 10. May be.
Next, as shown in FIG. 2 (E), the surface of the SiN film (CVD-SiN) deposited by the CVD (Chemical Vapor Deposition) method is oxidized in ozone at room temperature to form an SiO 2 film (silicon Oxide film) 11 is formed.

なお、ＣＶＤ法により堆積させたＳｉＮ膜（ＣＶＤ−ＳｉＮ）の表面を、酸素中で、例えば６００℃程度の所定の温度条件で酸化して、ＳｉＯ2膜（シリコン酸化膜）１１を形成しても良い。
その後、図２（Ｆ）に示すように、ＭＯＣＶＤ法によりモリブデンＭｏを堆積させてＭｏ膜（モリブデン膜，金属膜）１２［これがゲート電極（メタルゲート電極）となる］を形成する。 The surface of the SiN film (CVD-SiN) deposited by the CVD method is oxidized in oxygen at a predetermined temperature condition of, for example, about 600 ° C. to form a SiO 2 film (silicon oxide film) 11. Also good.
Thereafter, as shown in FIG. 2F, molybdenum Mo is deposited by MOCVD to form a Mo film (molybdenum film, metal film) 12 [this becomes a gate electrode (metal gate electrode)].

そして、図２（Ｇ）に示すように、ゲート加工を行なう。この結果、ゲート電極（メタルゲート電極，モリブデンゲート電極）１２Ａ／ＳｉＯ2膜（シリコン酸化膜）１１Ａ／ＳｉＮ膜（シリコン窒化膜）１０Ａ／ゲート絶縁膜（高誘電率ゲート絶縁膜，Ｈｆシリケートゲート絶縁膜）９Ａの積層構造が形成される。
以降、通常のプロセスにしたがって、図２（Ｈ）に示すように、不純物を注入してエクステンション・ソースドレイン１３を形成する。また、サイドウォール１４も形成する。さらに、不純物を注入してコンタクト・ソースドレイン１５も形成する。そして、熱処理（アニール処理）を行なって不純物を活性化させる。その後、メタル配線、層間絶縁膜の形成工程へ進む。
（第２の製造方法）
次に、第２の製造方法について、図３を参照しながら説明する。 Then, gate processing is performed as shown in FIG. As a result, the gate electrode (metal gate electrode, molybdenum gate electrode) 12A / SiO 2 film (silicon oxide film) 11A / SiN film (silicon nitride film) 10A / gate insulation film (high dielectric constant gate insulation film, Hf silicate gate insulation) A laminated structure of film 9A is formed.
Thereafter, according to a normal process, as shown in FIG. 2H, impurities are implanted to form the extension / source drain 13. A sidewall 14 is also formed. Further, impurities are implanted to form contact / source drain 15. Then, heat treatment (annealing) is performed to activate the impurities. Thereafter, the process proceeds to the formation process of the metal wiring and the interlayer insulating film.
(Second manufacturing method)
Next, the second manufacturing method will be described with reference to FIG.

第２の製造方法は、ダマシン法による製造方法である。ダマシン法は、例えば、Conference: Proceedings of IEEE International Electron Devices Meeting, 1992, Page: 301-4 やInternational Electron Devices Meeting 1998. Technical Digest Page: 785-8に詳しい。この方法によれば、工程は多くなるものの、膜厚を薄くできるという利点がある。   The second manufacturing method is a manufacturing method based on the damascene method. The damascene method is detailed in, for example, Conference: Proceedings of IEEE International Electron Devices Meeting, 1992, Page: 301-4 and International Electron Devices Meeting 1998. Technical Digest Page: 785-8. This method has an advantage that the film thickness can be reduced although the number of steps is increased.

まず、上述したような通常の製造プロセス（図２参照）にしたがって、チャネル、ソース・ドレインを形成する。つまり、図３（Ａ）に示すように、後で除去しやすい材料［通常、ポリシリコン（ｐｏｌｙ−Ｓｉ），シリコン窒化物（ＳｉＮ）等］でダミー・ゲート絶縁膜９Ｂ及びダミー・ゲート１２Ｂを形成し、これを用いてチャネル及びソース・ドレイン領域のプロファイルを形成する。なお、上述の第１の製造方法（図２参照）と同じものには同じ符号を付している。   First, a channel, a source and a drain are formed according to a normal manufacturing process (see FIG. 2) as described above. That is, as shown in FIG. 3A, the dummy gate insulating film 9B and the dummy gate 12B are made of a material that is easily removed later [usually polysilicon (poly-Si), silicon nitride (SiN), etc.]. Then, the profile of the channel and the source / drain region is formed using this. In addition, the same code | symbol is attached | subjected to the same thing as the above-mentioned 1st manufacturing method (refer FIG. 2).

次に、図３（Ｂ）に示すように、層間絶縁膜を形成するための材料（例えば低誘電率材料）１６Ａを堆積させた後、図３（Ｃ）に示すように、ダミー・ゲート１２Ｂの上部表面が出るまでＣＭＰ(Chemical Mechanical Polishing)法により研磨・除去して、層間絶縁膜１６を形成する。
次いで、図３（Ｄ）に示すように、選択性のある溶液でダミー・ゲート１２Ｂ及びダミー・ゲート絶縁膜９Ｂを除去する。 Next, as shown in FIG. 3B, after depositing a material (for example, a low dielectric constant material) 16A for forming an interlayer insulating film, as shown in FIG. 3C, the dummy gate 12B. The interlayer insulating film 16 is formed by polishing and removing by CMP (Chemical Mechanical Polishing) method until the upper surface of the film is exposed.
Next, as shown in FIG. 3D, the dummy gate 12B and the dummy gate insulating film 9B are removed with a selective solution.

次に、図３（Ｅ）に示すように、例えばＨｆＯ2をＡＬＣＶＤ(Atomic Layer Chemical Vapor Deposition)法により堆積させて、例えば３ｎｍのＨｆＯ2膜（高誘電率膜）１７［これがゲート絶縁膜（高誘電率ゲート絶縁膜）となる］を形成する。
次いで、図３（Ｆ）に示すように、例えばＬＰＣＶＤ法によりＳｉＨ4−ＮＨ3のガス系で、例えば６００℃程度の所定の温度条件として、ＳｉＮを堆積させて、例えば０．３ｎｍのＳｉＮ膜（シリコン窒化膜）１８を形成する。 Next, as shown in FIG. 3E, for example, HfO 2 is deposited by ALCVD (Atomic Layer Chemical Vapor Deposition) method, for example, a 3 nm HfO 2 film (high dielectric constant film) 17 [this is a gate insulating film ( A high dielectric constant gate insulating film) is formed.
Next, as shown in FIG. 3F, SiN is deposited under a predetermined temperature condition of, for example, about 600 ° C. in a gas system of SiH 4 —NH 3 by, for example, LPCVD, for example, to form a 0.3 nm SiN film, for example. A (silicon nitride film) 18 is formed.

なお、例えばＬＰＣＶＤ法によりＤＣＳ（ＳｉＨ2Ｃｌ2）−ＮＨ3のガス系で、例えば６８０℃程度の所定の温度条件として、ＳｉＮを堆積させて、ＳｉＮ膜（シリコン窒化膜）１８を形成しても良い。
以下、図３（Ｇ）〜図３（Ｊ）では、説明を分かり易くするために、一方のゲート部分のみを拡大して示すこととする。 For example, a SiS film (silicon nitride film) 18 is formed by depositing SiN in a gas system of DCS (SiH 2 Cl 2 ) —NH 3 by LPCVD, for example, under a predetermined temperature condition of about 680 ° C., for example. Also good.
In the following, in FIGS. 3G to 3J, only one gate portion is enlarged and shown for easy understanding.

次に、図３（Ｇ）に示すように、ＣＶＤ法により堆積させたＳｉＮ膜（ＣＶＤ−ＳｉＮ）１８の表面を、酸素中で、例えば６００℃程度の所定の温度条件で酸化して、ＳｉＯ2膜（シリコン酸化膜）１９を形成する。
なお、ＣＶＤ法により堆積させたＳｉＮ膜（ＣＶＤ−ＳｉＮ）１８の表面を、オゾン中で、かつ常温で酸化して、ＳｉＯ2膜（シリコン酸化膜）１９を形成しても良い。 Next, as shown in FIG. 3G, the surface of the SiN film (CVD-SiN) 18 deposited by the CVD method is oxidized in oxygen at a predetermined temperature condition of, for example, about 600 ° C. Two films (silicon oxide films) 19 are formed.
The surface of the SiN film (CVD-SiN) 18 deposited by the CVD method may be oxidized in ozone and at room temperature to form the SiO 2 film (silicon oxide film) 19.

次いで、図３（Ｈ）に示すように、ＭＯＣＶＤ法によりタングステンＷを堆積させてＷ膜（タングステン膜，金属膜）２０［これがゲート電極（メタルゲート電極）となる］を形成する。
その後、図３（Ｉ）に示すように、反応性イオンエッチング(ＲＩＥ；Reactive Ion Etching)によりゲート加工を行なう。なお、図３（Ｊ）に示すように、ＣＭＰ法によって削り落とすことでゲート加工を行なっても良い。この結果、ゲート電極（メタルゲート電極，タングステンゲート電極）２０Ａ（２０Ｂ）／ＳｉＯ2膜（シリコン酸化膜）１９／ＳｉＮ膜（シリコン窒化膜）１８／ゲート絶縁膜（高誘電率ゲート絶縁膜，ＨｆＯ2ゲート絶縁膜）１７の積層構造が形成される。以降、メタル配線、層間絶縁膜の形成工程へ進む。 Next, as shown in FIG. 3H, tungsten W is deposited by MOCVD to form a W film (tungsten film, metal film) 20 [this becomes a gate electrode (metal gate electrode)].
Thereafter, as shown in FIG. 3I, gate processing is performed by reactive ion etching (RIE). Note that as shown in FIG. 3J, gate processing may be performed by scraping off by a CMP method. As a result, the gate electrode (metal gate electrode, tungsten gate electrode) 20A (20B) / SiO 2 film (silicon oxide film) 19 / SiN film (silicon nitride film) 18 / gate insulating film (high dielectric constant gate insulating film, HfO) A stacked structure of ( 2 gate insulating films) 17 is formed. Thereafter, the process proceeds to the formation process of the metal wiring and the interlayer insulating film.

したがって、本実施形態にかかる半導体装置によれば、ゲート電極とゲート絶縁膜との間にシリコン酸化膜が設けられているため、仕事関数の変動を抑えることができ、これにより、閾値電圧の変動量を低く抑えることができるという利点がある。例えば、閾値電圧Ｖthの変動量を５ｍＶ以下に抑えることができる。
また、ゲート電極とゲート絶縁膜との間にシリコン窒化膜が設けられているため、ゲートリーク電流の増大を抑えることができ、ひいては信頼性を確保できるようになるという利点もある。例えば、寿命を２倍以上（多くの場合、数桁）長くすることができる。 Therefore, according to the semiconductor device according to the present embodiment, since the silicon oxide film is provided between the gate electrode and the gate insulating film, it is possible to suppress the work function fluctuation, and thereby the threshold voltage fluctuation. There is an advantage that the amount can be kept low. For example, the variation amount of the threshold voltage V th can be suppressed to 5 mV or less.
In addition, since the silicon nitride film is provided between the gate electrode and the gate insulating film, there is an advantage that an increase in gate leakage current can be suppressed and reliability can be secured. For example, the lifetime can be increased by a factor of 2 or more (in many cases, several orders of magnitude).

なお、本発明は、上述した実施形態に限定されず、上記以外にも、本発明の趣旨を逸脱しない範囲で種々変形して実施することができる。
例えば、上述の実施形態では、ＭＯＳデバイスを例に説明したが、本発明はその他の構造の半導体装置（半導体デバイス）に適用することもできる。この場合、半導体装置は、Ｍｏ，Ｗ，Ｔａ，Ｔｉ，Ｈｆ，Ｚｒ，Ｖ，Ｃｒ，Ｎｂを含む金属群から選ばれるいずれか１種の金属を含む金属膜と、高誘電率膜とを備え、金属膜と高誘電率膜との間に、金属膜側から順に、シリコン酸化膜、シリコン窒化膜を備えるものとして構成される。 In addition, this invention is not limited to embodiment mentioned above, In addition to the above, various deformation | transformation can be implemented in the range which does not deviate from the meaning of this invention.
For example, in the above-described embodiment, the MOS device has been described as an example, but the present invention can also be applied to a semiconductor device (semiconductor device) having another structure. In this case, the semiconductor device includes a metal film containing any one metal selected from a metal group containing Mo, W, Ta, Ti, Hf, Zr, V, Cr, and Nb, and a high dielectric constant film. A silicon oxide film and a silicon nitride film are arranged in this order from the metal film side between the metal film and the high dielectric constant film.

本発明の一実施形態にかかる半導体装置の構成を示す模式図である。It is a mimetic diagram showing the composition of the semiconductor device concerning one embodiment of the present invention. （Ａ）〜（Ｈ）は、本発明の一実施形態にかかる半導体装置の製造方法（第１の製造方法）を説明するための模式図である。(A)-(H) are the schematic diagrams for demonstrating the manufacturing method (1st manufacturing method) of the semiconductor device concerning one Embodiment of this invention. （Ａ）〜（Ｊ）は、本発明の一実施形態にかかる半導体装置の製造方法（第２の製造方法）を説明するための模式図である。(A)-(J) are the schematic diagrams for demonstrating the manufacturing method (2nd manufacturing method) of the semiconductor device concerning one Embodiment of this invention. 本発明の課題を説明するための模式図である。It is a schematic diagram for demonstrating the subject of this invention. 本発明の課題を説明するための模式図である。It is a schematic diagram for demonstrating the subject of this invention.

符号の説明Explanation of symbols

１ ゲート電極（メタルゲート電極，金属膜）
２，１１，１１Ａ，１９ ＳｉＯ2膜（シリコン酸化膜）
３，１０，１０Ａ，１８ ＳｉＮ膜（シリコン窒化膜）
４ ゲート絶縁膜（高誘電率ゲート絶縁膜，高誘電率膜）
５ Ｓｉ基板
６ シャロー・トレンチ
７ Ｎウェル
８ Ｐウェル
９ Ｈｆシリケート膜
９Ａ Ｈｆシリケートゲート絶縁膜
１２ モリブデン膜
１２Ａ モリブデンゲート電極
１３ エクステンション・ソースドレイン
１４ サイドウォール
１５ コンタクト・ソースドレイン
１６ 層間絶縁膜
１６Ａ 層間絶縁膜材料
１７ ＨｆＯ2ゲート絶縁膜
２０ タングステン膜
２０Ａ，２０Ｂ タングステンゲート電極 1 Gate electrode (metal gate electrode, metal film)
2, 11, 11A, 19 SiO 2 film (silicon oxide film)
3, 10, 10A, 18 SiN film (silicon nitride film)
4 Gate insulation film (high dielectric constant gate insulation film, high dielectric constant film)
5 Si substrate 6 Shallow trench 7 N well 8 P well 9 Hf silicate film 9A Hf silicate gate insulation film 12 Molybdenum film 12A Molybdenum gate electrode 13 Extension source drain 14 Side wall 15 Contact source drain 16 Interlayer insulation film 16A Interlayer insulation Film material 17 HfO 2 gate insulating film 20 Tungsten film 20A, 20B Tungsten gate electrode

Claims (5)

ゲート電極と、
ゲート絶縁膜とを備え、
前記ゲート電極がメタルゲート電極であるか、又は、前記ゲート絶縁膜が高誘電率ゲート絶縁膜である場合に、前記ゲート電極と前記ゲート絶縁膜との間に、前記ゲート電極側から順に、シリコン酸化膜、シリコン窒化膜を備えることを特徴とする、半導体装置。 A gate electrode;
A gate insulating film,
When the gate electrode is a metal gate electrode or the gate insulating film is a high dielectric constant gate insulating film, silicon is sequentially formed between the gate electrode and the gate insulating film from the gate electrode side. A semiconductor device comprising an oxide film and a silicon nitride film. ゲート電極と、
ゲート絶縁膜とを備え、
前記ゲート電極がメタルゲート電極であるか、又は、前記ゲート絶縁膜が高誘電率ゲート絶縁膜である場合に、前記ゲート電極と前記ゲート絶縁膜との間に、シリコン酸化膜を備えることを特徴とする、半導体装置。 A gate electrode;
A gate insulating film,
When the gate electrode is a metal gate electrode or the gate insulating film is a high dielectric constant gate insulating film, a silicon oxide film is provided between the gate electrode and the gate insulating film. A semiconductor device. 前記メタルゲート電極が、Ｍｏ，Ｗ，Ｔａ，Ｔｉ，Ｈｆ，Ｚｒ，Ｖ，Ｃｒ，Ｎｂを含む金属群から選ばれるいずれか１種の金属を含むものとして構成されることを特徴とする、請求項１又は２記載の半導体装置。   The metal gate electrode is configured to include any one metal selected from a metal group including Mo, W, Ta, Ti, Hf, Zr, V, Cr, and Nb. Item 3. The semiconductor device according to Item 1 or 2. 前記高誘電率ゲート絶縁膜が、酸化ハフニウム，酸化ジルコニウム，酸化アルミニウム，酸化イットリウム，ランタン族酸化物、又は前記各酸化物のシリケート、又は前記各酸化物若しくは前記各シリケートを含む混合物により構成されることを特徴とする、請求項１〜３のいずれか１項に記載の半導体装置。   The high dielectric constant gate insulating film is composed of hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, lanthanum group oxide, silicate of each oxide, or each oxide or a mixture containing each silicate. The semiconductor device according to claim 1, wherein: Ｍｏ，Ｗ，Ｔａ，Ｔｉ，Ｈｆ，Ｚｒ，Ｖ，Ｃｒ，Ｎｂを含む金属群から選ばれるいずれか１種の金属を含む金属膜と、
高誘電率膜とを備え、
前記金属膜と前記高誘電率膜との間に、前記金属膜側から順に、シリコン酸化膜、シリコン窒化膜を備えることを特徴とする、半導体装置。 A metal film containing any one metal selected from a metal group containing Mo, W, Ta, Ti, Hf, Zr, V, Cr, and Nb;
High dielectric constant film,
A semiconductor device comprising a silicon oxide film and a silicon nitride film in order from the metal film side between the metal film and the high dielectric constant film.
JP2004268273A 2004-09-15 2004-09-15 Semiconductor device Pending JP2006086272A (en)

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JP2007266552A (en) * 2006-03-30 2007-10-11 Fujitsu Ltd Semiconductor device and its manufacturing method
KR101116349B1 (en) * 2006-05-31 2012-03-16 주식회사 하이닉스반도체 Semiconductor device and method for fabricating the same
US8575012B2 (en) 2010-08-04 2013-11-05 Fujitsu Semiconductor Limited Semiconductor device production method and semiconductor device
US8637929B2 (en) 2010-12-28 2014-01-28 Fujitsu Semiconductor Limited LDMOS transistor having a gate electrode formed over thick and thin portions of a gate insulation film

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JPH05243562A (en) * 1991-11-06 1993-09-21 Ramtron Internatl Corp Field-effect transistor and dielectric layered structure used for the same and manufacturing method of the same
JPH0677402A (en) * 1992-07-02 1994-03-18 Natl Semiconductor Corp <Ns> Dielectric structure for semiconductor device and its manufacture
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007266552A (en) * 2006-03-30 2007-10-11 Fujitsu Ltd Semiconductor device and its manufacturing method
KR101116349B1 (en) * 2006-05-31 2012-03-16 주식회사 하이닉스반도체 Semiconductor device and method for fabricating the same
US8575012B2 (en) 2010-08-04 2013-11-05 Fujitsu Semiconductor Limited Semiconductor device production method and semiconductor device
US8637929B2 (en) 2010-12-28 2014-01-28 Fujitsu Semiconductor Limited LDMOS transistor having a gate electrode formed over thick and thin portions of a gate insulation film

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