JP2006040535A - Semiconductor memory device and dynamic type semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a large-capacity DRAM reduced in data holding current and capable of stably supplying an operation power supply voltage. <P>SOLUTION: Internal step-down circuits are arranged corresponding to memory mats MM#i: MM#0 to MM#3. In a normal operation mode, a plurality of memory mats are simultaneously set in selected states. During a refreshing operation, in one memory mat MM"i, refreshing operations are simultaneously executed for a plurality of memory subarrays. During this refreshing operation, the supplied current of the internal step-down circuit is reduced by setting a switching transistor 46b in a noconductive state in a current driving part. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device, and more particularly to a configuration for reducing current consumption in a data holding mode for holding data stored in a dynamic memory cell.

  In a dynamic semiconductor memory device (hereinafter referred to as DRAM), a 1-bit memory cell is composed of one MOS transistor (insulated gate field effect transistor) and one capacitor. As a memory device with a large storage capacity, the occupied area of a 1-bit memory cell is small and the unit price per bit is lower than that of a static random access memory (SRAM) that requires a plurality of transistor elements in a 1-bit memory cell. DRAM is widely used.

  In this DRAM, information is stored in a capacitor in the form of electric charge, and in order to prevent the stored data from being destroyed due to a reduction in the amount of stored charge due to a leakage current, the stored data in the memory cell is periodically stored. It is necessary to perform a refresh operation for reading and rewriting.

  In recent years, DRAMs have been widely used as main storage devices for portable terminals such as laptop computers. An information device such as a portable terminal uses a battery as an operating power source, and it is necessary to make the current consumption of the portable terminal as small as possible in order to make the battery life as long as possible. Even when information processing is not performed in the portable terminal, it is necessary to periodically refresh the data stored in the DRAM. As described above, an operation mode in which only data stored in the memory cell is refreshed without inputting / outputting data to / from the DRAM is called a “data holding mode”.

  In such a data holding mode, for example, the power consumption is reduced by decreasing the power supply voltage of the DRAM or by extending the refresh interval.

  However, in order to extend the life of the battery in this battery-driven device, it is possible to further reduce the data retention current (current during the refresh operation and current during standby) consumed in the data retention mode in the DRAM. It is requested. Further, it is required to stably supply the operation power supply voltage even in the normal operation mode.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor memory device and a dynamic semiconductor memory device that can stably supply an operating power supply voltage in a normal operation mode and can further reduce current consumption in a data holding mode.

  A semiconductor memory device according to a first aspect of the present invention is a semiconductor memory device including a plurality of memory mats each including a memory cell array having a configuration in which memory cells are arranged in a matrix, and is external to the semiconductor memory device. Data access is performed from the first operation mode in which the first operation current flows, and data access is not performed from the outside of the semiconductor memory device, the stored data in the memory cell is refreshed, and is less than the first operation current. A second operation mode in which a second operation current flows, and is provided in each memory mat, and an internal power supply potential applied from the outside of the semiconductor memory device is reduced to a corresponding memory mat. Provide internal pressure drop means. This internal voltage step-down means is activated by a memory mat designation signal for designating a memory mat, and compared with the first operation mode, the amount of current flowing from the power supply external to the semiconductor memory device to the corresponding memory mat in the second operation mode Reduce the current to supply current.

  A dynamic semiconductor memory device according to a second aspect of the present invention includes a plurality of memory mats each including a memory cell array having a configuration in which memory cells are arranged in a matrix. In this dynamic semiconductor memory device, data is accessed from outside the semiconductor memory device, the normal operation mode in which the first operating current flows, and data access from outside the semiconductor memory device is not performed. A data holding mode in which the second operating current is refreshed and a second operating current smaller than the first operating current flows.

  The dynamic semiconductor memory device according to the second aspect of the present invention is further provided in each memory mat, and an internal power supply potential obtained by lowering the power supply potential applied from the outside of the semiconductor memory device is supplied to the corresponding memory mat. Step-down means is provided. This internal voltage step-down means is activated by a memory mat designation signal for designating a memory mat, and reduces the amount of current flowing from the power supply external to the semiconductor memory device to the corresponding memory mat in the data holding mode as compared with the normal operation mode. Supply current.

  By providing an internal step-down circuit corresponding to each memory mat and supplying the internal power supply voltage to the corresponding memory mat, the power supply voltage can be stably supplied to each memory mat.

[Embodiment 1]
FIG. 1 shows an arrangement of selected memory cells in a DRAM according to the first embodiment of the present invention. FIG. 1A shows the arrangement of selected memory cells in the normal operation mode, and FIG. 1B shows the arrangement of selected memory cells (refresh memory cells) in the refresh operation in the data holding mode.

  1A, semiconductor memory device 1 includes four memory mats MM # 0 to MM # 3. In the following description, “memory mat” is used as a term including both a memory array in which memory cells are arranged in a matrix and a peripheral circuit for driving the memory cells to a selected state. Each of memory mats MM # 0 to MM # 3 has a plurality of subarrays (in the following description, eight subarrays MB # 0 to MB # 7 are exemplarily shown).

  In the normal operation mode in which data access for inputting or outputting data to / from the selected memory cell is performed, each memory mat MM # 0 to MM # 3 has one subarray (MB # 0 in FIG. 1A). Is selected. A memory cell is selected in subarray MB # 0 in the selected state. As shown in FIG. 1A, the sense amplifier operation is performed in each of memory mats MM # 0 to MM # 3 by distributing the sub-array driven to the selected state to each of memory mats MM # 0 to MM # 3. The peak current at the time (detection and amplification of selected memory cell data) can be reduced, and power line noise is reduced accordingly. As a result, even during high-speed operation, it is not necessary to consider a margin for the influence of power supply noise, and high-speed operation can be performed.

  As shown in FIG. 1B, when data stored in the memory cell is refreshed during the data holding mode operation, one memory mat (memory mat MM) among the four memory mats MM # 0 to MM # 3. # 0 is shown as an example). In memory mat MM # 0 in the selected state, a plurality of subarrays (MB # 0, MB # 2, MB # 4 and MB # 6 in FIG. 1B) are driven to the selected state, In the sub-arrays MB # 0, MB # 2, MB # 4 and MB # 6, the stored data of the memory cells are refreshed. By concentrating the sub-array on which the refresh operation is performed on one memory mat, the local activation signal for activating the sub-array can be activated only for one memory mat during the refresh operation. Therefore, it is not necessary to drive the local activation signal to the active state in the control circuit provided in each memory mat, and the current consumption can be greatly reduced.

  FIG. 2 is a block diagram schematically showing a configuration of a portion related to the refresh operation during the data holding mode operation of the semiconductor memory device (DRAM 1) according to the first embodiment of the present invention. In FIG. 2, each of memory mats MM # 0-MM # 3 includes memory array MA # 0-MA # 3 having a plurality of memory cells arranged in a matrix, and corresponding memory array MA # when activated. 0 to MA # 3 include row decoders RD0 to RD3 for driving the row of memory cells to be refreshed to a selected state.

  DRAM 1 is further designated in data retention mode in response to a row address strobe signal / RAS externally applied via input terminal 2a and a column address strobe signal / CAS externally applied via input terminal 2b. A data holding mode detection circuit 4 for detecting whether or not the data is detected, a refresh control circuit 6 for performing various controls required for refresh in response to the data holding mode detection signal REF from the refresh detection circuit 4, and refresh control. Activated in response to the data holding mode detection from the circuit 6 and activated in response to the control signal from the timer 8 that outputs the refresh request signal φref at a predetermined interval and the refresh control circuit 6 and refreshed. A riff that generates a refresh address that specifies the memory cell to be Tsu, including the shoe counter 10. The refresh counter 10 outputs a refresh array designating address RAA designating a memory mat and subarray to be refreshed and a refresh row address RRA designating a subarray and a row of memory cells to be refreshed therein.

  Further, in response to a control signal from the refresh control circuit 6, the DRAM 1 selectively passes one of the refresh row address RRA from the refresh counter 10 and an address signal externally applied via the input terminal 2c. A row address buffer 16 that is activated in response to a control signal (refresh operation activation signal) from the refresh control circuit 6 and generates an internal row address signal by buffering the internal row address signal applied from the multiplexer 14. Activated in response to a control signal from refresh control circuit 6, decodes array designation address RAA from refresh counter 10, and selects one of the memory mats MM # 0-MM # 3. An array that outputs the signal Including the control circuit 12.

  When the data holding mode is designated, the multiplexer 14 selects the refresh address RRA given from the refresh counter 10 and gives it to the row address buffer 16 under the control of the refresh control circuit 6. Although the internal configuration of the row address buffer 16 will be described in detail later, when the data holding mode is detected, the sub-array designated address is set in a degenerated state so that a plurality of sub-arrays are simultaneously selected. Here, “degenerate” indicates a state where both complementary address signals are selected.

  Under the control of the refresh control circuit 6, the array control circuit 12 decodes the array address RAA from the refresh counter 10 and selects only one memory mat when the data holding mode is designated. The array control circuit 12 selects all the memory mats MM # 0 to MM # 3 when the data holding mode is not detected, that is, in the normal operation mode. Next, the configuration and operation of each unit will be described.

  FIG. 3 is a waveform diagram showing operations of the refresh detection circuit 4 and the refresh control circuit 6 shown in FIG. In FIG. 3, when the column address strobe signal / CAS is set to L level before the fall of the row address strobe signal / RAS, the refresh detection circuit 4 determines that the data holding mode is designated and holds data. The mode detection signal REF is set to the active H level. The refresh control circuit 6 starts the timer 8 in response to the data holding mode detection signal REF from the refresh detection circuit 4. In response to the activation signal from the refresh control circuit 6, the timer 8 outputs a refresh request signal φref when a predetermined period tu has elapsed.

  In response to refresh request signal φref from timer 8, refresh control circuit 6 sets refresh operation activation signal ZRAS to an L level active state. Refresh operation activation signal ZRAS has the same function as internal row address strobe signal / RAS generated in response to activation of externally applied row address strobe signal / RAS during normal operation. The difference is that the period during which the refresh operation activation signal ZRAS is in the active state at the L level is predetermined. In response to the activation of refresh operation activation signal ZRAS, the refresh operation of the data in the memory cell is executed according to the refresh address. Refresh control circuit 6 activates timer 8 when data holding mode detection signal REF from refresh detection circuit 4 is activated (while row address strobe signal / RAS is at L level).

  In response to the activation signal from the refresh control circuit 6, the timer 8 activates the refresh request signal φref at the H level every predetermined period Tr. In accordance with refresh request signal φref, refresh operation activation signal ZRAS is set to the active state L level for a predetermined period, and the refresh operation is executed. Every time this refresh operation is completed, the count value of the refresh counter 10 is changed, and the position of the next memory cell row to be refreshed is designated.

  The configuration of the refresh detection circuit 4 has the same configuration as that of a normal so-called “CBR detector”.

  FIG. 4 is a diagram exemplarily showing allocation of address signals of the memory mat shown in FIG. FIG. 4 shows a configuration of a subarray of one memory array MA. Memory array MA includes eight subarrays MB # 0-MB # 7. Internal row address signal bits RAa and / RAa designate groups of four subarrays of subarrays MB # 0-MB # 3 and subarrays MB # 4-MB # 7. When internal row address signal bit RAa is at the H level, subarrays MB # 0 to MB # 3 are designated, and when row address signal bit / RAa is at the H level, subarrays MB # 4 to MB # 7 are designated. Here, bits RAa and / RAa have complementary logics.

  Row address signal bits RAb and / RAb are used to select two of the four subarrays. When row address signal bit RAb is at H level, subarrays MB # 0 and MB # 1 or subarrays MB # 4 and MB # 5 are designated. When row address signal bit / RAb is at H level, subarrays MB # 2 and MB # are designated. 3 or subarrays MB # 6 and MB # 7 are designated. Of the eight subarrays MB # 0 to MB # 7, an even-numbered subarray is designated by a row address signal bit RAc, and an odd-numbered subarray is designated by a row address signal bit / RAc. Each of sub-arrays MB # 0-MB # 7 is selected when all of the 3-bit row address signal bits assigned to it are at the H level.

  FIG. 5 schematically shows configurations of the refresh counter, the multiplexer, and the row address buffer shown in FIG. In FIG. 5, a multiplexer for switching between a refresh address and an externally applied address is not shown in order to simplify the drawing. It simply shows an address signal supplied from the refresh counter 10 to the row address buffer 16 and the array control circuit 12 and a generated row address signal bit during the refresh operation.

  In FIG. 5, a refresh counter 10 includes a refresh cell counter 10a for generating address signal bits RRAc to RRAe designating memory cells and row blocks to be refreshed, and a rising edge of an address signal bit RRAc output from the refresh cell counter 10a. It includes an array counter 10b that counts down. The refresh cell counter 10a outputs the address signal bit RRAc as the most significant bit and the address signal bit RRAe as the least significant bit. Address signal bits RRAc to RRAe designate memory cells to be refreshed in memory mats M # 0 to M # 3.

  When the row address signal bit RRAc falls, the array counter 10b increments (or decrements) the count value indicated by the output address signal bits RAA0 to RAA1. That is, when address signal bit RRAc falls from the H level to the L level, it indicates that all the memory cells are refreshed in one memory mat.

  Row address buffer 16 buffers address signal bits RRAc to RRAe applied from refresh cell counter 10a to generate complementary address signal bits RAa, / RAa to RAe, / RAe. In the data holding mode, row address buffer 16 degenerates address signal bits RAa, / RAa, RAb, and / RAb designating subarray groups in each of memory mats M # 0-M # 3. Therefore, in each of memory mats M # 0-M # 3, an odd-numbered subarray or an even-numbered subarray is selected according to address signal bits RAc, / RAc.

  Array control circuit 12 decodes address signal bits RAA0 and RAA1 output from array counter 10b when data holding mode instruction signal REF is activated, and designates mats for designating memory mats M # 0 to M # 3, respectively. One of the signals MS0 to MS3 is selected. The decoder 12a selects all the mat designation signals MS0 to MS3 when the data holding mode designation signal REF is inactivated. Thereby, when refreshing is performed in the data holding mode, a plurality of subarrays (odd number subarrays or even numbered subarrays) are refreshed in one memory mat, and predetermined in all memory mats in the normal operation mode. A number (one) of subarrays are selected and data is accessed.

  FIG. 6 is a diagram showing a configuration of a portion of row address buffer 16 shown in FIG. 5 for generating address signal bits RAa, RAb and / RAa, / RAb for designating subarray groups. Since address signal bits RAa, / RAb and RAb, / RAb are output from the buffer circuit having the same configuration, only one buffer circuit portion is shown in FIG.

  In FIG. 6, a row address buffer 16 receives an inverter 16a which receives and inverts an address signal bit Aa (Ab) externally applied through a multiplexer during normal operation, and receives an output signal of the address signal bit Aa and the inverter 16a. A bit change circuit 16b which is in a degenerated state in the data holding mode, a NAND circuit 16c receiving the output signal of the bit change circuit 16b and the address buffer activation signal RADE, an output signal of the bit change circuit 16e and the address buffer activation signal RADE Receiving NAND circuit 16d, inverter 16e receiving the output signal of NAND circuit 16c, and inverter 16f receiving the output signal of NAND circuit 16e. Internal row address signal bit RAa (RAb) is output from inverter 16e, and internal row address signal bit / RAa (/ RAb) is output from inverter 16f.

  Bit change circuit 16b includes an OR circuit 16ba receiving address signal bit Aa and data holding mode designating signal REF, and an OR circuit 16bb receiving an output signal of inverter 16a and data holding mode designating signal REF. The output signal of RO circuit 16ba is applied to one input of NAND circuit 16c, and the output signal of OR circuit 16bb is applied to one input of NAND circuit 16d.

  In the normal operation mode, data retention mode designating signal REF is at L level, and OR circuits 16ba and 16bb operate as buffer circuits. Therefore, the bit change circuit 16b outputs address signal bits Aa (Ab) and / Aa (/ Ab) which are complementary to each other from the address signal bit Aa. As shown in FIG. 7, address buffer activation signal RADE is set to an active H level in response to activation of refresh operation activation signal ZRAS when the refresh operation is activated. In response to activation of buffer activating signal RADE, NAND circuits 16c and 16d operate as inverters, respectively, and internal row address signal bits RAa (RAb) and / RAa (in accordance with a signal applied from bit changing circuit 16b / RAb) is generated. Therefore, in the data holding mode, row address signal bits RAa, / RAa, RAb and / RAb are all set to the H level. Therefore, as shown in FIG. 4, in memory mat MA, among subarrays MB # 0-MB # 7, even-numbered subarrays or even-numbered subarrays are selected according to internal row address signal bits RAc / RAc. .

  The lower address signal bits RAc to RAe of the row address buffer 16 have a configuration in which the bit change circuit 16b shown in FIG. 6 is deleted.

  The refresh operation activation signal ZRAS is generated with a predetermined time width in the refresh operation mode. In the normal operation mode, the active state is activated in response to a row address strobe signal / RAS applied from the outside, and the active period is determined by external row address strobe signal / RAS.

  In the configuration of row address buffer 16 shown in FIG. 6, the logic level of address signal bit Aa (Ab) provided from the multiplexer may be either H level or L level during the data holding mode operation. Therefore, in the data holding mode operation, the multiplexer may be configured to be in an output high impedance state in the portion corresponding to address signal bits Aa and Ab, or may not be provided in particular.

  FIG. 8 is a diagram showing a schematic configuration of the decoder 12a shown in FIG. FIG. 8 shows a portion of the decoder circuit that selects memory mat M # 0. Decoder 12a includes NAND circuit 12aa receiving array address signal bits / RAA0 and / RAA1 output from array counter (see FIG. 5) 10b, and NAND circuit 12ab receiving the output signal of NAND circuit 12aa and data holding mode designating signal REF. including. NAND circuit 12ab outputs mat designating signal MS0 designating memory mat M # 0. In the normal operation mode, data holding mode designating signal REF is at L level, and mat designating signal MS0 output from NAND circuit 12ab is at H level. Since the same configuration is provided in the circuit portion designating other memory mats, all of the memory mats M # 0 to M # 3 are selected in the normal operation mode.

  In the data holding mode operation, data holding mode designating signal REF is set to an active H level, and NAND circuit 12ab functions as an inverter. NAND circuit 12aa outputs a signal at L level when both bits / RAA0 and / RAA1 output from array counter 10b are at H level. In each of memory mats M # 1-M # 3, signals of a predetermined combination of array counter output bits RAA0, / RAA0, RAA1, / RAA1 are applied. Therefore, in the data holding mode operation, only one memory mat designating signal among memory mat designating signals MS0 to MS3 designating memory mats M # 0 to M # 3 is selected. Thereby, the data holding operation, that is, the refresh operation can be performed only for one memory mat.

  FIG. 9 schematically shows a configuration of row decoders RD0-RD3 shown in FIG. FIG. 9 schematically shows a configuration of a decoding circuit for one word line WL in memory mat M # i (i = 0 to 3). The row decoder RDi receives a memory mat designation signal MSi and a predetermined combination of internal row address signal bits RAc to RAe, and selects a word line WL according to an output signal of the NAND circuit 13a (normal internal high voltage The word line drive circuit 13b is driven to the (Vpp level).

  NAND circuit 13a outputs an L level signal indicating a selected state when all applied signals are at an H level. In the normal operation mode, memory mat designation signal MSi is at the H level. On the other hand, in the data holding mode operation, only one memory mat designation signal among memory mat designation signals MS0 to MS3 is set to the H level selected state. Therefore, since the row decoder performs the decoding operation only on the selected memory mat, the refresh operation is performed only on one memory mat.

  In the configuration shown in FIG. 9, the NAND circuit 13a functionally shows the configuration of a row decoder. Address signal bit RAc designating a subarray is applied to a so-called block decoder, and in each subarray, a row decode circuit provided corresponding to the subarray is activated according to an output signal of this block decoder (decoder for driving the subarray to a selected state). A configuration in a state may be used. Needless to say, a so-called predecoder configuration may be used.

[Example of change]
FIG. 10 shows a structure of a modification of the DRAM according to the first embodiment of the present invention. FIG. 10A shows the arrangement of address signals for four memory mats MM # 0-MM # 3 and subarrays MB # 0-MB # 7. In the arrangement shown in FIG. 10A, column addresses signal bits CAa, / CAa, CAb and / CAb are assigned to memory mats MM # 0-MM # 3 in the normal operation mode. In the normal operation mode, these column address signal bits CAa, / CAa, CAb and / CAb are in a degenerated state and are all in a selected state. In each of memory mats MM # 0 to MM # 3, row address signal bits RAa, / RAa, RAb and / RAb for selecting subarrays MB # 0 to MB # 7 are assigned in the same manner as in the previous embodiment (see FIG. 4). The same.

  In the data holding mode, one memory mat is designated, and a plurality of subarrays are selected in this selected memory mat. In view of this, column address signal bits CAa and CAb which are in a degenerated state in the normal operation mode and row address signal bits RAa and RAb in a non-degenerated state in the normal operation mode are exchanged in the data holding mode.

  That is, as shown in FIG. 10B, in the data holding mode, column address signal bits CAa and CAb are converted into row address signal bits RAa and RAb, respectively, and row address signal bits RAa and RAb are converted into column address signals. Converted to bits CAa and CAb. In DRAM, column address signal bits CAa and CAb which are in a degenerated state are internally selected (at the time of memory cell selection operation). Therefore, even if the column address signal bit is used as the row address signal bit, in the internal operation, the memory cell selection operation is performed according to the refresh operation activation signal ZRAS. Therefore, as shown in parentheses in FIG. 10A, in the data holding mode operation, one of the group of subarrays MB # 0-MB # 3 and the group of subarrays MB # 4-MB # 7 is column. Address signal bits CAa and / CAa are selected, and two subarrays in each group are selected by column address signal bits CAb and / CAb. Since column address signal bits CAa, / CAa, CAb, / CAb are in a degenerated state, they are all in a selected state. Therefore, in the data holding mode, odd-numbered sub-arrays or even-numbered sub-arrays are selected according to row address signal bits RAc, / RAc (see FIG. 4).

  In the data holding mode operation, the memory mat is designated by row address signal bits RAa, / RAa, RAb and / RAb. Since this row address signal bit is in a non-degenerate state, one of the four memory mats MM # 0 to MM # 3 is selected.

  FIG. 11 is a diagram schematically showing a configuration of a portion that performs address conversion shown in FIG. Also in FIG. 11, a multiplexer for switching between an external address signal and an internally generated refresh address is not shown in order to simplify the drawing. In FIG. 11, in the data holding mode, the address conversion unit receives a refresh address RRAa, RRAb, RRAc to RRAe supplied from the refresh counter 10 and generates an internal row address signal bit, and this row address buffer. 16 receives row address signal bits RAa, / RAa, RAb, / RAb from column 16 and degenerated column address signal bits CAa ', CAb' provided from a column address buffer (not shown), and receives data holding mode instruction signal REF. A scrambler 19 is provided for exchanging column address signal bits CAa 'and CAb' and row address signal bits from row address buffer 16 when activated. Row address buffer 16 generates internal row address signal bits RAc, / RAc to RAe, / RAe and supplies them to a row decoder provided in each memory mat. The scrambler 19 outputs the column address signal bits CAa ′ and CAb ′ as internal row address signal bits RAa and RAb and activates the row address signal bits from the row address buffer 16 when the data holding mode instruction signal REF is activated. Output as column address signal bits CAa and CAb. When the data holding mode instruction signal REF is inactivated, the scrambler 19 does not perform bit exchange and outputs a given address signal bit.

  In the configuration shown in FIG. 11, when the count value changes from the minimum count value to the maximum count value in the refresh counter 10, it indicates that all the memory cells have been refreshed once in all the memory mats. Therefore, the column address signal bits CAa ′ and CAb ′ that are always in a degenerated state in the scrambler 19 and the row address signal bits RAa ′ and RAb ′ output from the row address buffer 16 are simply scrambled, and a simple circuit is provided. With the configuration, a plurality of subarrays can be selected in one memory mat when in the data holding mode.

  FIG. 12 is a diagram showing a portion of the scrambler shown in FIG. 11 for a 1-bit address signal. The number of bits required for the configuration shown in FIG. 12 is provided. In FIG. 12, scrambler 19 conducts when data holding mode instruction signal REF is activated, and bi-directional transmission gate XF1 for outputting column address signal bit CAa 'as internal column address signal bit CAa, and data holding mode instruction signal Bi-directional transmission gate XF2 that conducts when REF is activated and outputs column address signal bit CAa 'as row address signal bit RAa, and conducts when data holding mode instruction signal REF is activated, and row address signal bit RAa' is activated. Bi-directional transmission gate XF3 output as internal column address signal bit CAa is rendered conductive when data retention mode instruction signal REF is inactive, and row address signal bit RAa 'is output as internal row address signal bit RAa. Including a bi-directional transmission gate XF4. Each of bidirectional transmission gates XF1-XF4 is formed of a CMOS transistor, and an inverter IV for inverting data holding mode instruction signal REF is provided to control conduction of the CMOS transistor. Conduction / non-conduction of these transmission gates XF1 to XF4 is realized by this data retention mode instruction signal REF and the inverted data retention mode instruction signal output from inverter IV.

  In the configuration shown in FIG. 12, the transmission paths of column address signal bit CAa 'and row address signal bit RAa' are only switched by transmission gates XF1-XF4. In the normal operation mode, address signal bits CAa 'and RAa' are output as internal address signal bits CAa and RAa, respectively, and in the data holding mode operation, address signal bits CAa 'and RAa' are respectively address signals. Output as bits RAa and CAa. Column address signal bit CAa 'is in a degenerated state and is always in a selected state. Therefore, it is possible to easily obtain an address signal bit that is in a degenerated state in the data holding mode simply by switching the propagation path.

  In the configuration shown in FIG. 12, the portion to which address signal bits CAa and RAa are transmitted is not shown. Internal column address signal bit CAa is applied to a mat decoder portion for selecting a memory mat, and internal row address signal bit RAa is applied to a row decoder (RD0 to RD3) for each memory mat.

  In the configuration using this scrambler 19, normal operation is performed when the number of address signal bits to be degenerated differs depending on the configuration of the DRAM (for example, a 3-bit address is degenerated in the case of the x8 bit configuration). If an address signal bit that is in a degenerated state in the mode is exchanged with an address signal bit that should be in a degenerated state in the data holding mode, a refresh operation is always performed with one memory mat selected in the data holding mode. It can be performed.

  As described above, by selectively degenerating signals specifying the memory mat and the sub-array in the data holding mode, a group composed of a predetermined number of sub-arrays in one memory mat in the data holding mode. Only the refresh operation can be performed. In other memory mats, peripheral circuits are not operating. Therefore, a circuit for driving other peripheral circuits and the operation of the other peripheral circuits are stopped, so that current consumption is reduced.

  FIG. 13A schematically shows a configuration of a sense amplifier driving unit. FIG. 13A representatively shows sense amplifiers provided for a pair of bit lines in one subarray. The sense amplifier is arranged corresponding to each column of memory cells, and when activated, senses and amplifies data of the memory cell read to the corresponding memory cell column (bit line pair).

  In FIG. 13A, a sense amplifier 20 is provided for a pair of bit lines BL and / BL. One column of memory cells is connected to bit line pair BL and / BL. FIG. 13A representatively shows memory cells MC provided corresponding to the intersections of word lines WL and bit lines BL. One row of memory cells is connected to the word line WL.

  The sense driver includes a sense activation circuit 24 that activates the sense amplifier activation signals SOP and SON at a predetermined timing in accordance with a refresh operation activation signal ZRAS and row block designation address signal bits RAa, RAb, and RAc, and a sense activation circuit An activation transistor 27a formed of an n-channel MOS transistor which is rendered conductive in response to sense amplifier activation signal SOP from activation circuit 24 to bring sense amplifier drive signal SAP into an active state at the level of ground potential Vss; A sense activation transistor 28a composed of a p-channel MOS transistor which is rendered conductive in response to sense amplifier activation signal SON from activation circuit 24 and drives sense drive signal SAN to the active state of power supply potential Vint, and sense amplifier In response to the drive signal SAP Sense amplifier 20 is turned on in response to sense amplifier drive signal SAN, and sense amplifier drive transistor 22a formed of a p-channel MOS transistor transmitting power supply potential Vint to one node of sense amplifier 20, and to the other node of sense amplifier 20 Sense drive transistor 22b formed of an n-channel MOS transistor for transmitting ground potential Vss is included.

  Sense amplifier 20 includes a normal cross-coupled p-channel MOS transistor and a cross-coupled n-channel MOS transistor. Power supply potential Vint is transmitted to the p channel MOS transistor portion via sense amplifier driving transistor 22a, and ground potential Vss is transmitted to the n channel MOS transistor portion via sense amplifier driving transistor 22b.

  The sense driver further conducts in response to an AND circuit 26a receiving the sense amplifier activation signal SOP and the inverted data holding mode designating signal / REF from the sense activation circuit 24, in response to an output signal of the AND circuit 26a. An auxiliary drive transistor 27b formed of an n-channel MOS transistor for driving the amplifier drive signal SAP to the ground potential Vss level, an OR circuit 26b for receiving the sense amplifier activation signal SON and the data holding mode designating signal REF, and an OR circuit 26b An auxiliary drive transistor 28b formed of a p-channel MOS transistor that is selectively turned on in response to the output signal and drives sense amplifier drive signal SAN to power supply potential Vint level is included.

  The current driving capability of the transistor 27a is preferably smaller than the current driving capability of the transistor 27b. The current driving capability of the driving transistor 28b is preferably smaller than that of the auxiliary driving transistor 28b. Next, the operation of the sense amplifier driving unit shown in FIG. 13A will be described with reference to FIG.

  In the data holding mode, data holding mode designating signal REF is at the H level, and inverted data holding mode designating signal / REF is at the L level. In this state, the output signal of AND circuit 26a is fixed at the L level, and the output signal of OR circuit 26b is fixed at the H level, so that auxiliary drive transistors 27b and 28b are both held in the non-passing state. Is done.

  In the standby state (the H level of refresh operation activation signal ZRS and the inactive state of internal RAS signal during normal operation), sense amplifier activation signals SOP and SON from sense activation circuit 24 are at L level and H level. Therefore, sense drive transistors 27a and 28a are turned off.

  In the refresh operation, first, the refresh operation activation signal ZRAS is set to L level. When subarray designating signal bits RAa, RAb and RAc are all selected, sense activation circuit 24 drives sense amplifier activation signal SON to L level at a predetermined timing, and sense amplifier activation signal SOP Drive to H level. As a result, drive transistors 27a and 28a are rendered conductive, and sense amplifier drive signals SAN and SAP are set to active H level and L level, respectively. The sense driving transistors 27a and 28a have a relatively small current driving capability, and the potentials of the sense amplifier driving signals SAN and SAP change relatively slowly as indicated by broken lines in FIG. In response to sense amplifier activation signals SAN and SAP, sense amplifier activation transistors 22a and 22b are rendered conductive, and power supply potential Vint and ground potential Vss are transmitted to sense amplifier 20 to activate sense amplifier 20. The memory cell data appearing on the bit lines BL and / BL are detected and amplified. Since the potential changes in sense amplifier drive signals SAP and SAN are gradual, the change in conductance of sense amplifier activation transistors 22a and 22b is relatively gradual, and the operation speed of sense amplifier 20 is also slowed accordingly (sense The amplifier 20 charges and discharges the bit lines BL and / BL via the activation transistors 22a and 22b).

  Accordingly, in FIG. 13B, the potentials of the bit lines BL and / BL change gently as indicated by the broken line waveform.

  By gently charging / discharging the bit lines BL and / BL, the peak current of the charge / discharge current during the operation of the sense amplifier 20 can be reduced, and power line noise (reduction of the power supply potential Vint and ground potential) can be reduced. The rise of Vss is prevented, and the sense operation can be performed stably even when the sense operation is performed in a plurality of subarrays in one memory mat. In this refresh operation, no high speed operability is required (since no external input / output of data is performed), no problem arises.

  In the normal operation mode, data holding mode designating signal REF is at L level, and AND circuit 26a and OR circuit 26b each operate as a buffer circuit. Therefore, in this normal operation mode, in response to activation of an internal RAS signal (following row address strobe signal / RAS applied from the outside) corresponding to refresh operation activation signal ZRAS, address signal bits RAa, Sense activation circuit 24 selected by RAb and RAc is activated, and sense amplifier activation signals SOP and SON are activated at an H level and an L level, respectively, at predetermined timings.

  In response to activation of sense amplifier activation signals SOP and SON, drive transistors 27a and 27b and drive transistors 28a and 28b are turned on, and sense amplifier drive signals SAP and SAN are activated at an L level and an H level in an active state at high speed. And Thereby, sense amplifier activation transistors 22a and 22b are turned on at high speed, and sense amplifier 20 charges and discharges bit lines BL and / BL via sense amplifier activation transistors 22a and 22b. As a result, as indicated by the solid line in FIG. 13B, the potentials of the bit lines BL and / BL change at high speed.

  In the configuration shown in FIG. 13A, sense activation circuit 24a activates sense amplifier activation signals SOP and SON in response to refresh operation activation signal ZRAS and subarray designation address signal bits RAa, RAb and RAc. Driving to the state. The configuration of sense activation circuit 24 is arbitrary, and this sense activation circuit 24 may be provided corresponding to each sub-array, and the sense amplifier activation signal is sent to each memory in response to refresh operation activation signal ZRAS. A configuration may be used in which the sense activation circuit corresponding to the subarray is activated to the corresponding sense amplifier activation signal in accordance with the subarray designation signal, transmitted to the sense activation circuit of the mat.

  In FIG. 13B, the potential change of bit lines BL and / BL when H level data is read on bit line BL is shown, but when L level memory cell data is read. The same effect can be obtained in. Sense amplifier 24 drives the high potential bit line of bit lines BL and / BL to power supply potential Vint level, and drives the low potential bit line potential to ground potential Vss level.

  FIG. 14 is a diagram showing a configuration of a portion for switching the internal RAS signal in the data holding mode and the normal operation mode. Refresh control circuit 6 includes a ZRAS generation circuit 6a that generates refresh operation activation signal ZRAS having a predetermined time width in response to a refresh request signal (applied from a timer) φref. In the normal operation mode, RAS buffer 30 is supplied with row address strobe signal ext. / RAS is buffered to generate an internal row address strobe signal / RAS. In order to switch the path of the drive signal in the normal operation mode and the refresh operation mode, an OR gate 32 receiving the internal row address strobe signal and the data holding mode designating signal REF supplied from the RAS buffer 30, and the ZRAS generating circuit 6a An AND circuit 34 receiving the refresh operation activation signal ZRAS and the output signal of the OR circuit 32 is provided. Internal RAS signal φRASZ applied from AND circuit 34 to a RAS system circuit (a circuit driven according to signal RAS, including a row decoder, a row address buffer, and a sense amplifier driving circuit) provided in DRAM. Is generated.

  During the data holding mode operation, data holding mode designating signal REF is at H level, and the output signal of OR circuit 32 is fixed at H level. In this state, the state of internal row address strobe signal / RAS output from RAS buffer 30 is ignored. Therefore, AND circuit 34 activates internal RAS signal φRASZ at the L level in accordance with refresh operation activation signal ZRAS applied from ZRAS generating circuit 6a.

  In the normal operation mode, refresh operation activation signal ZRAS from ZRAS generation circuit 6a included in refresh control circuit 6 is fixed at the H level. Further, the data holding mode designation signal REF is fixed at the L level. Therefore, OR circuit 32 and AND circuit 34 each operate as a buffer, and internal RAS signal φRASZ is output in accordance with internal row address strobe signal / RAS applied from RAS buffer 30. Thus, the internal circuit of the DRAM operates in accordance with the internal RAS signal φRASZ in both the normal operation mode and the refresh operation mode.

  As described above, according to the first embodiment of the present invention, the number of memory mats to be selected can be changed in the normal operation mode and the data holding mode operation. In this case, current consumption can be reduced by adjusting the number of memory mats to be operated as necessary. Further, during the data holding mode operation, it is only necessary to transmit an activation signal to only one memory mat by performing a refresh operation with a plurality of sub-arrays selected in only one memory mat. Since all activation signals are maintained in the non-selected state in the mats, the current consumption in the peripheral circuits of these other memory mats is reduced, and accordingly the current consumption in the data holding mode is reduced.

  Further, in the refresh operation mode, the peak current can be reduced by performing the sensing operation gently, and thereby the refresh operation can be accurately performed simultaneously in a plurality of subarrays of one memory mat.

[Embodiment 2]
FIG. 15 schematically shows an arrangement of an array of DRAMs according to the second embodiment of the present invention. FIG. 15A shows the arrangement of the selected memory sub-array in the normal operation mode, and FIG. 15B shows the arrangement of the sub-array selected for refresh in the data holding mode operation. As shown in FIGS. 15A and 15B, DRAM 1 includes four memory mats MM # 0 to MM # 3. Corresponding to memory mats MM # 0 to MM # 3, internal voltage down converters VDC0 to VDC3 are provided. The internal configuration of each of internal voltage down converters VDC0 to VDC3 will be described later, but converts an externally applied power supply potential to generate an internal power supply potential to corresponding memory mats MM # 0 to MM # 3. Supply. Each of memory mats MM # 0 to MM # 3 operates with power supply potential supplied from corresponding internal voltage down converters VDC0 to VDC3. This memory mat includes a row decoder and a column decoder as peripheral circuits, a sense amplifier activation circuit, and the like, and for the memory array, a power supply potential Vint for activating the sense amplifier (FIG. 13A). See)) etc. are supplied.

  As shown in FIG. 15A, in the normal operation mode, one sub-array (sub-array MB # 0 is exemplarily shown) is selected in each of memory mats MM # 0-MM # 3. Access is made to the selected memory cell in subarray MB # 0. An internal voltage down converting circuit is arranged corresponding to each of memory mats MM # 0 to MM # 3, and each of internal voltage down converting circuits VDC0 to VDC3 supplies a power supply potential only to corresponding memory mat MM # 0 to MM # 3. By doing so, power supply noise can be reduced.

  That is, when the power supply potential is supplied to all the memory mats MM # 0 to MM # 3 using one internal step-down circuit, the following problems occur. When internal power supply potential Vint is supplied to memory mats MM # 0-MM # 3 using an internal voltage down converter provided in common to all memory mats MM # 0-MM # 3, memory mats MM # 0-MM # In operation 3, current consumption of all memory mats MM # 0 to MM # 3 is supplied via a common internal voltage down converter, and supplied to compensate for the decrease in internal power supply potential and this. The internal power supply potential rises and ringes due to a large current, and the internal power supply potential becomes unstable. On the other hand, by arranging internal voltage down converters VDC0 to VDC3 for memory mats MM # 0 to MM # 3, internal voltage down converters VDC0 to VDC3 are connected to corresponding memory mats MM # 0 to MM # 3, respectively. It is only required to supply the potential Vint. Therefore, the current consumption to be compensated by internal voltage down converters VDC0 to VDC3 is only the current consumption of one memory mat, and the current consumption is distributed accordingly, so that the power supply during operation of memory mats MM # 0 to MM # 3 Since the noise can be reduced and the internal power supply potential can be stably supplied even when the internal power supply potential is slightly reduced, each of the memory mats MM # 0 to MM # 3 has a large operating margin (internal It can operate stably with respect to the power supply potential.

  In the second embodiment, one memory mat (memory mat MM # 0 is exemplarily shown in FIG. 15B) when refreshing in the data holding mode operation according to the first embodiment. The refresh operation is executed only in step. Internal voltage down converters (VDC0 to VDC3) provided for the unselected memory mats (MM # 1 to MM # 3) stop the supply of internal power supply voltage Vint. As a result, the current consumption for the memory mat in the non-selected state is eliminated, so that the current consumption during the data holding mode operation is greatly reduced. In the selected memory mat (MM # 0), the peak current can be reduced by slowing the operation of the peripheral circuits such as the sense amplifier, and one internal step-down circuit (VDC0) is used. The internal power supply potential can be stably supplied to a plurality of subarrays (since current consumption is small, the power supply potential lowers slowly, and the current consumption can be sufficiently compensated by one internal voltage down converter. ).

  FIG. 16A shows an example of the structure of the internal voltage down converter. 16A, internal voltage down converter VDC selectively activates comparator 40 that compares reference potential Vref and internal power supply potential Vint, and comparator 40 in response to memory mat designation signal MSi. And a drive transistor 44 formed of a p-channel MOS transistor for supplying a current from external power supply potential supply node Vext onto internal power supply line 41 in response to the output signal of comparator 40. The transistor 42 is turned on when the memory mat designation signal MSi is in an active state, and forms a current path of the comparator 40. When the memory mat designation signal MSi is inactivated, the activation transistor 42 is turned off and the comparator 40 is inactivated. This transistor 42 thus acts as a current source transistor for the comparator 40.

  During operation, the comparator 40 outputs an L level signal and increases the contactance of the drive transistor 44 when the reference potential Vref is higher than the internal power supply potential Vint. Thereby, drive transistor 44 supplies a current from external power supply potential supply node Vext onto internal power supply line 41, and raises the potential of internal power supply potential Vint. On the other hand, when internal power supply potential Vint is higher than reference potential Vref, comparator 40 outputs an H level signal to turn drive transistor 44 off. As a result, supply of current through the drive transistor 44 is stopped. Therefore, internal power supply potential Vint is held at the potential level of reference potential Vref.

  As shown in FIG. 16B, this internal voltage down converter VDC supplies external power supply potential Vint to only one memory mat. Therefore, current consumption i is relatively small, and even when the corresponding memory mat is selected and operated, the peak current is small, the decrease in internal power supply potential Vint is small, and internal power supply potential Vint is at a predetermined potential level. Held at Vref.

  In the data holding mode operation, more subarrays are driven than in the normal operation mode. However, since the operation speed of the circuit for driving the subarray is low, the change speed of the consumption current i is small, and the peak current is the same as that in the normal operation mode. Thus, even when a large number of subarrays are driven simultaneously in one memory mat in the data holding mode, internal power supply potential Vint is held at a predetermined potential level.

  In the data holding mode operation, this memory mat designation signal MSi is set to the H level only for the selected memory mat. Therefore, for the non-selected memory mat, comparator 40 is deactivated and its output signal is set to H level, and drive transistor 44 maintains the off state. Since the non-selected memory mat maintains the standby state, its current consumption is only leakage current, and even when current is not supplied from the corresponding internal step-down circuit, the internal power supply potential must maintain a substantially constant potential level. Can do.

  FIG. 17 is a diagram showing a configuration for slowing down the circuit operation in the selected memory mat. In FIG. 17, a p-channel MOS transistor 46a functioning as a current source is provided between a peripheral circuit (row decoder, column decoder, sense amplifier activation circuit, etc.) of one memory mat MM # and an internal power supply line 41, and data holding is performed. There is provided a p-channel MOS transistor 46b which is turned off in response to the data holding mode designating signal REF in the mode. The p-channel MOS transistor 46a receives the ground potential Vss at its gate, maintains a conductive state at all times, and functions as a current source.

  In the normal operation mode, MOS transistors 46a and 46b are both conductive, and peripheral circuit 48 receives power supply potential Vint on internal power supply line 41. When the peripheral circuit 48 operates, a current is supplied with a large current driving capability via the MOS transistors 46a and 46b, and the peripheral circuit 48 operates stably at high speed.

  In the data holding mode operation, data holding mode designating signal REF is at H level, and MOS transistor 46b is turned off. Therefore, in the data holding mode, peripheral circuit 48 is supplied with current from internal power supply line 41 only through MOS transistor 46a functioning as a current source. Therefore, the current driving capability of the peripheral circuit 48 is determined by the MOS transistor 46a, and the current driving capability is made smaller than that in the normal operation, and the operating speed of the peripheral circuit 48 is reduced. Thereby, the peak current in the data holding mode can be suppressed.

  In the configuration shown in FIG. 17, instead of the data holding mode designation signal REF, a logical product signal REF · MSi of the data holding mode designation signal REF and the memory mat designation signal MSi may be used. In the non-selected memory mat, MOS transistor 46b is turned on in the data holding mode, but the corresponding internal voltage down converter is inactive, and the corresponding memory mat is also in the non-selected state. Is not consumed, so there is no problem.

  Further, as the configuration for delaying the circuit operation, the configuration for delaying the sensing operation in FIG. 13A may be used.

  As described above, according to the second embodiment of the present invention, the internal voltage down converter provided corresponding to each of the plurality of memory mats is activated only in the data holding mode. Since it is configured to be in the state, current consumption in the data holding mode can be greatly reduced. At this time, the peak current can be reduced by delaying the circuit operation in the data holding mode, and even if the number of selected sub-arrays in the selected memory mat is increased, the peak current can be stably increased. A refresh operation can be performed.

[Embodiment 3]
In the DRAM, various operation modes are provided in addition to the data holding mode including the self-refresh mode. For example, when setting the test mode of the DRAM, the WCBR timing is used, and the CBR timing is used for resetting the test mode. The WCBR timing is determined by the external row address strobe signal ext. / RAS before the fall of the external write enable signal ext. / WE and external column address strobe signal ext. / CAS falls to L level. At the CBR timing, the external row address strobe signal ext. / RAS falls before external column address strobe signal ext. / CAS falls to L level. At that time, the external write enable signal ext. / WE is normally set to the H level. FIG. 18 shows a configuration of a part for setting each operation mode.

  In FIG. 18, a test mode set circuit 54 and a test mode reset circuit 52 are shown as an example. The test mode set circuit 54 includes a WCBR detector 54a that detects WCBR timing, and the test mode reset circuit 52 includes a CBR detector 52 that detects CBR timing. When the test mode is reset, the CBR detection signal CBR is output to reset the test mode, and the WCBR detection signal WCBR is output from the WCBR detector 54a to set the test mode. When the data holding mode is designated, the DRAM enters the self-refresh mode when the CBR detection signal CBR is activated for a predetermined time or longer. This CBR detection signal is therefore equivalent to the data holding mode detection signal REF.

  External row address strobe signal ext. Is supplied to test mode set circuit 54 and test mode reset circuit 52 via input buffers 50a, 50b and 50c. / RAS, external column address strobe signal ext. / CAS and external write enable signal ext. / WE is given.

  In the DRAM, the internal component is a CMOS transistor, and a CMOS level signal is propagated.

  On the other hand, in an external device of a DRAM, the input / output signal may be at a TTL level (or LV (low voltage) TTL level), for example. When the external device is composed of, for example, a bipolar transistor, its output signal level is reduced to ensure high-speed operation, and a signal such as TTL or LVTTL is used. At the TTL level, the high level signal voltage Vih is 2.0V, and the L level signal voltage Vin is 0.8V. When a buffer serving as an interface with an external device provided at the first input stage has a CMOS configuration, a through current may flow when a TTL (or LVTTL) level signal is applied. A configuration for reducing the through current in the data holding mode will be described below.

  FIG. 19A shows a configuration of an input buffer circuit according to the third embodiment of the present invention, and FIG. 19B shows an equivalent logic gate thereof. In FIG. 19A, input buffer 50 is connected between power supply node Vcc and internal output node Nb, and has p-channel MOS transistor Qa whose gate is connected to input node Na, internal output node Nb, P channel MOS transistor Qb connected between internal node Nc and its gate connected to receive power cut instruction signal PC, connected between internal node Nc and ground node Vss, and having its gate connected An n channel MOS transistor Qc connected to input node Na and an n channel MOS transistor Qd connected between internal node Nc and ground node Vss and having its gate connected to receive power cut designating signal PC Including.

  A power supply potential Vcc applied to power supply node Vcc (a node and a potential thereon are indicated by the same sign) is 3.0 V, and an H level of input signal IN applied to input node Na is 2.0 V which is a TTL level. It is. Power cut instruction signal PC is activated at the H level in the data holding mode operation, MOS transistor Qb is turned off, MOS transistor Qd is turned on, and node Nc is fixed at the ground potential level. Since MOS transistor Qb is rendered non-conductive at the time of data holding mode operation, a path through which a current flows from power supply node Vcc to ground node Vss is cut off. Therefore, even if the input signal IN is at the TTL level of 2.0 V, no through current is generated in the input buffer 50, and current consumption in the data holding mode is reduced.

  FIG. 19B shows an equivalent logic gate of the input buffer circuit 50, and is represented as a two-input NOR circuit that receives the input signal IN and the power cut instruction signal PC. When power cut instruction signal PC is at H level, its internal output signal Iint is fixed at L level. The level of the input signal IN may be H level or L level. Therefore, the potential of node Nb is actually determined by the potential level of input signal IN when power cut instruction signal PC is activated. Here, in FIG. 19B, a two-input NOR circuit is shown to indicate that the potential level of internal input signal Iint is fixed when power cut designation signal PC is activated (at the H level). However, the internal signal Iint may be output from the node Nc.

  When power cut mode instruction signal PC is at the L level, it is in the normal operation mode, MOS transistor Qb is turned on, and MOS transistor Qd is turned off. In this state, MOS transistor Qc is turned on or off according to the potential level of input signal IN. In this state, since MOS transistor Qb is conductive, a path is formed through which current flows from power supply node Vcc to ground node Vss via MOS transistors Qa and Qc. The internal input signal Iint (CMOS level) can be generated.

  Here, MOS transistor Qd is provided because internal node Nc is brought into a floating state when power cut instruction signal PC is activated, and MOS transistors Qb and Qc are rendered conductive by the influence of noise, thereby penetrating. This is to prevent the formation of a path through which current flows. Internal output node Nb is charged by MOS transistor Qa, and its potential level is fixed.

  FIG. 20A schematically shows a configuration of a portion that generates power cut instruction signal PC. 20A, the power cut instruction signal generator generates an external row address strobe signal ext. / RAS and external column address strobe signal ext. In response to / CAS, a refresh detection circuit 4 for identifying whether or not a data holding mode is designated, a data holding mode designation signal REF from the refresh detection circuit 4, and a refresh request signal φref applied from the refresh timer 18 Inverter 57 for receiving, and AND circuit 59 for receiving data holding mode designating signal REF and the output signal of inverter 57 are included. A power cut instruction signal PC is generated from AND circuit 59 and applied to buffer circuit 55. Buffer circuit 55 includes buffers 50a and 50b shown in FIG. Refresh detector 4 includes a CBR detector 4a for detecting whether row address strobe signal / RAS and column address strobe signal / CAS applied from buffer circuit 55 satisfy the CBR timing. A data holding mode designation signal REF is output from the CBR detector 4a. The CBR detector 4a also supplies the external write enable signal ext. / WE may be received via the buffer circuit 55. Next, the operation of the power cut instruction signal generator shown in FIG. 20 will be described with reference to FIG.

  When row address strobe signal / RAS and column address strobe signal / CAS applied through buffer circuit 55 satisfy the CBR timing, data holding mode designating signal RRF output from CBR detector 4a is activated to an H level. The The refresh timer 18 is driven under the control of the refresh control circuit (see FIG. 2), and outputs a refresh request signal φref at regular time intervals when a predetermined time has elapsed. This refresh request signal φref is activated when it is at the H level. Therefore, during the data holding mode period, when this refresh request signal φref is at L level, power cut instruction signal PC is at H level. As shown in FIG. 19A, during the period when the power cut designation signal PC is at the H level, the current path is cut off in the input buffer. When refresh request signal φref is activated to an H level, the output signal of inverter 57 is set to L level, and power cut designating signal PC is accordingly set to L level. During this period, a path through which a current flows between the power supply node Vcc and the ground node Vss is formed in the buffer circuit 55, the input buffer (buffer circuit 55) is brought into an operating state, and control signals (/ RAS and / CAS).

  At the time of resetting the data holding mode, the external row address strobe signal ext. RAS is set to H level. The external row address strobe signal ext. Even if / RAS is at the H level, if the power cut designation signal PC is at the H level, the buffer circuit 55 is in an inoperative state, and the potential level of the output signal of the buffer circuit 55 does not change. After a certain period of time, external row address strobe signal ext. / RAS and column address strobe signal ext. In a state where both / CAS are at the H level, when the refresh request signal φref is activated, the power cut designating signal PC is set at the L level, and the signal ext. / RAS and ext. / CAS is applied to the refresh control detection circuit 4 through the buffer circuit 55, and the data holding mode designating signal REF is set to the L level by the H level signal / RAS. In response to the fall of data holding mode designating signal REF to L level, power cut instruction signal PC is set to L level, and buffer circuit 55 (input buffers 50a to 50c) is always in an operating state.

  Therefore, in the configuration shown in FIG. 20A, when data holding mode is reset, control signal ext. / RAS and ext. By holding / CAS at the H level for one refresh cycle period (1φref period), the data holding mode is released. When the data holding mode is released, the refresh request signal φref is activated to an H level, and a refresh operation is performed internally. Therefore, it is necessary to prohibit external access to the DRAM for one refresh period (period in which the refresh operation is actually performed) after the refresh data holding mode is released.

[Example of change]
FIG. 21A shows a configuration of a modification of the third embodiment of the present invention. In FIG. 21A, a frequency divider 58 is provided between an inverter 57 that receives a refresh request signal φref and an AND circuit 59 that outputs a power cut instruction signal PC. Other configurations are the same as those shown in FIG. 20A, and corresponding portions bear the same reference numerals. In the case of the configuration shown in FIG. 21A, as clearly seen in the operation waveform diagram shown in FIG. 21B, the power cut instruction signal PC divides the refresh request signal φref by a predetermined frequency division ratio. The L level is set at the cycle. Here, in FIG. 21B, a case where the frequency division ratio is 1/2 is shown as an example. Therefore, when the data holding mode is reset, the control signal ext. / RAS and ext. The period during which / CAS is held at the H level is the period of the frequency of the divided refresh request signal, and the next access can be performed at a fast timing. The frequency division ratio of the frequency divider 58 is determined in consideration of the charge / discharge current required for driving the power cut instruction signal PC to the H level and the L level and the magnitude of the through current in the buffer circuit 55. Set to the correct value. This makes it possible to perform the next access at a fast timing with low current consumption and at the time of resetting the data holding mode.

  As described above, according to the third embodiment of the present invention, since the path through which the through current of the input buffer flows is configured to be cut off during the data holding mode, current consumption during the data holding mode operation can be reduced. it can.

  Further, when the refresh request signal is activated, the data holding mode can be surely set to the reset state by setting the input buffer circuit to the operating state. The signal obtained by dividing the refresh request signal is used to selectively turn on the through-current path of the input buffer circuit, so that the state of the external control signal when the data holding mode is reset is set to a predetermined state (H level). (Inactive state) is shortened, and the next access start timing can be accelerated accordingly.

[Embodiment 4]
FIG. 22 shows a structure of a main portion of the DRAM according to the fourth embodiment of the present invention. In the configuration shown in FIG. 22, the configuration of the portion generating internal row address signals RA, / RA during the refresh operation is shown.

  In FIG. 19, a buffer control circuit 62 for statically operating the row address buffer 16 when the data holding mode detection signal REF from the refresh detection circuit 4 is activated is provided.

  Refresh mode detection circuit 4 receives external row address strobe signal ext. / RAS in response to the fall of external column address strobe signal ext. / CAS latch circuit 4aa and set / reset flip-flop 4ab which is set when the output signal (latch signal) of latch circuit 4aa is at the H level and sets data holding mode designating signal REF to the H level active state. including. This set / reset flip-flop 4ab is connected to external row address strobe signal ext. Reset in response to rising of / RAS.

  Latch circuit 4aa receives external row address strobe signal ext. / RAS is rendered conductive when H level, external column address strobe signal ext. Transfer gate 4ca formed of an n-channel MOS transistor that passes / CAS, inverter 4cb that inverts the signal transmitted from transfer gate 4ca, and the output signal of inverter 4cb is inverted and transmitted to the input of inverter 4cb Inverter 4cc and external row address strobe signal ext. It includes a transfer gate 4cb formed of a p-channel MOS transistor which conducts when / RAS is at L level and supplies the output signal of inverter 4cb to set input S of set / reset flip-flop 4ab. Here, the input buffer of Embodiment 3 may be provided.

  Refresh control circuit 6 starts timer 18 in response to data holding mode detection signal REF applied from refresh mode detection circuit 4 and refresh operation activation signal ZRAS in response to refresh request signal φref applied from timer 18. Is supplied to the RAS drive circuit 60 as an active state. When the refresh operation is completed, the refresh control circuit 6 increments (decreases) the count value of the refresh counter 10 in response to the rise (inactivation) of the refresh operation activation signal ZRAS.

  In response to the activation of the refresh operation activation signal ZRAS, the RAS drive circuit 60 outputs a latch instruction signal RAL and a buffer activation signal RADE that give a latch timing and an output permission timing in the row address buffer. The RAS drive circuit 60 also generates a control signal for the RAS circuit (operating in response to the signal RAS). FIG. 22 representatively shows a sense amplifier activation signal φSA for activating the sense amplifier. The RAS drive circuit 60 also generates a bit line equalize signal for equalizing the bit lines.

  Control circuit 62 includes an OR circuit 62a that receives data holding mode instruction signal REF and latch instruction signal RAL, and an OR circuit 62b that receives data holding mode instruction signal REF and buffer activation signal RADE. OR circuit 62a generates an H level output signal when one of data holding mode instruction signal REF and latch instruction signal RAL is at H level. OR circuit 62b outputs an H level signal when one of data holding mode instruction signal REF and buffer activation signal RADE is at H level.

  Row address buffer 16 includes a row address buffer circuit provided corresponding to each internal row address signal bit. FIG. 22 representatively shows buffer circuit 16a generating 1-bit internal row address signals RA and / RA. The row address buffer circuit 16a is turned on when the output signal of the OR circuit 62a is at the H level, and is supplied from the transfer gate 16aa formed of an n-channel MOS transistor that passes the signal supplied from the multiplexer 14 and the transfer gate 16aa. Inverter 16ab for inverting the signal, inverter 16ac for inverting the output signal of inverter 16ab and transmitting it to the input of inverter 16ab, inverter 16ab for inverting the output signal of inverter 16ab, output signal of inverter 16ab and OR circuit 62b NAND circuit 16ae that receives the output signal of the inverter, inverter 16af that inverts the output signal of the NAND circuit 16ae and outputs the internal row address signal bit / RA, and the output signal of the inverter 16ad and the OR circuit It includes a NAND circuit 16ag receiving an output signal of 2b, and inverter 16ah to generate internal row address signal bit RA inverts the output signal of the NAND circuit 16ag.

  The multiplexer 14 selectively passes one of the refresh address supplied from the refresh counter 10 and the address signal A supplied from the outside under the control of the control signal supplied from the refresh control circuit 6. Next, the operation of the address system circuit shown in FIG. 22 will be described with reference to FIG.

  FIG. 23A is a signal waveform diagram representing an operation of RAS drive circuit 60 shown in FIG. The RAS drive circuit 60 holds the latch instruction signal RAL at the H level and the buffer activation signal RADE at the L level when the refresh operation activation signal ZRAS is at the inactive H level. In the normal operation mode in which data holding mode instruction signal REF is at L level, in this state, the output signal of OR circuit 62a is at H level and the output signal of OR circuit 62b is at L level. In row address buffer circuit 16a, therefore, transfer gate 16aa is rendered conductive in response to the H level signal from OR circuit 62a, and passes the signal applied from multiplexer 14. On the other hand, the output signal of OR circuit 62b is at L level, the output signals of NAND circuits 16ae and 16ad are at H level, and both row address signal bits / RA and RA are at L level.

  When refresh operation activation signal ZRAS is activated to an L level, latch instruction signal RAL is set to an L level, and then buffer activation signal RADE is set to an H level. As a result, transfer gate 16aa is rendered non-conductive, row address buffer circuit 16a enters the latch state, and NAND circuits 16ae and 16ad operate as inverters in response to the rise of address buffer activation signal RADE. Internal row address signal bits / RA and RA corresponding to the address signal bits latched by the latch circuit formed of inverters 16ab and 16ac are generated.

  Therefore, in the normal operation mode, row address buffer circuit 16a latches an applied address signal bit in accordance with internal RAS signal φRASZ corresponding to refresh operation activation signal ZRAS to generate an internal row address signal bit. Row address buffer circuit 16a is reset in response to inactivation of refresh operation activation signal ZRAS (internal RAS signal φRASZ). That is, signal RAL is set to H level, signal RADE is set to L level, and internal row address signal bits RA and / RA are both set to L level.

  During the data holding mode operation, data holding mode instruction signal REF is at the H level. In this state, the output signals of OR circuits 62a and 62b are always held at the H level. Therefore, in row address buffer circuit 16a, transfer gate 16aa maintains a conductive state, and NAND circuits 16ae and 16ad operate as inverters. That is, row address buffer circuit 16a operates statically and generates signal bits RA and / RA that change according to the signal bits applied from multiplexer 14.

  That is, as shown in FIG. 23B, the external row address strobe signal ext. / RAS and external column address strobe signal ext. When / CAS is applied at the CBR timing and the data holding mode instruction signal REF from the refresh detection circuit 4 is set to H level, the row address buffer 16 starts a static operation. When refresh control circuit 6 activates refresh operation activation signal ZRAS in response to refresh request signal φref given after elapse of time t from timer 18 when data holding mode designating signal REF is activated, refresh counter 6 10 is activated, and the count value is applied to row address buffer 16 via multiplexer 14, and the state of internal row address signal bits RA and / RA changes accordingly. When the refresh operation is completed and the refresh operation activation signal ZRAS is deactivated, the count value of the refresh counter 10 is updated in response to the deactivation. As the count value is updated, the state of the row address signal bits RA and / RA output from the row address buffer circuit 16 that performs the static operation changes. Thereafter, the row address buffer 16 performs a static operation during the data holding mode operation period, and the internal row address is updated every time the count value of the refresh counter 10 is updated in response to the deactivation of the refresh operation activation signal ZRAS. The state of signal bits RA and / RA changes.

  When the data holding mode operation is completed, data holding mode designating signal REF is rendered inactive at L level, row address buffer 16 is reset, and internal row address signal bits RA and / RA are held at L level.

  As described above, when the row address buffer 16 is statically operated during the data holding mode operation, only the row address buffer circuit that outputs the changing row address signal bits among the internal row address signal bits is charged / discharged. I do. Since the row address buffer circuit for the row address signal bit that does not change does not perform the charge / discharge operation, the current consumption during the data holding mode operation can be reduced. At this time, the set / reset (active state / precharge state) of the selected memory array (sub-array) is performed in response to the refresh operation activation signal ZRAS under the control of the RAS drive circuit 60.

  FIG. 24 is a diagram showing a refresh operation sequence in the data holding mode. In the refresh operation sequence, there are a burst refresh mode shown in FIG. 24A and a distributed refresh mode shown in FIG. In the burst refresh mode, the refresh operation is continuously performed a predetermined number of times as shown in FIG. When the predetermined number of refreshes are completed, the DRAM is maintained in a standby state (precharge state) for a relatively long pause time Tp. When this pause time Tp is completed, a predetermined number of refresh operations are performed again. In this burst refresh mode, as shown in FIG. 22, the row address buffer is operated statically, and only the signal line of the changing address signal bit is charged / discharged, thereby reducing the operating current during the refresh operation. Is done.

  In the distributed refresh mode shown in FIG. 24B, the refresh operation is performed every predetermined refresh period Tref. Therefore, compared to this distributed refresh configuration, in the burst refresh mode shown in FIG. 21A, the pause time Tp can be longer than the refresh interval Tref (memory cell data over a plurality of rows is refreshed continuously). For). As a result, the time during which the DRAM is effectively maintained in the standby (precharged state) becomes longer, and the current consumption can be reduced. In the fourth embodiment, this burst refresh mode is used in combination with the configuration of the row address buffer shown in FIG. 22 to perform a refresh operation in units of subarrays or memory blocks.

  FIG. 25 schematically shows a structure of a memory block portion of the DRAM according to the fourth embodiment of the present invention. In FIG. 25, two memory blocks MBL and MBR are shown. A sense amplifier band SAB including a sense amplifier SA for detecting and amplifying memory cell data is arranged between memory blocks MBL and MBR. A configuration in which the sense amplifier SA of the sense amplifier band SAB is shared by the memory blocks MBL and MBR is referred to as “shared sense amplifier arrangement”. The “shared sense amplifier arrangement” may be a configuration of an “alternate arrangement type shared sense amplifier arrangement” in which the sense amplifiers are alternately arranged in each column on both sides of the memory block. In order to simplify the above, a configuration of “shared sense amplifier arrangement” is shown. Memory blocks MBL and MBR may be subarrays MB # j (j = 0 to 7) shown in the first and second embodiments, respectively, and each of memory blocks MBL and MBR includes one subarray. It may be configured.

  As an example, the memory block MBL includes 128 word lines WL0 to WL127, and the memory block MBR also includes 128 word lines WL128 to WL225. An X decoder RDL is provided for the memory block MBL, and an X decoder RDR is provided for the memory block MBR.

  In each of memory blocks MBL and MBR, a bit line pair is arranged corresponding to each column of memory cells. In FIG. 25, memory block MBL shows one bit line pair BLL, / BLL, and memory block MBR representatively shows one bit line pair BLR and / BLR.

  Sense amplifier band SAB includes sense amplifiers SA arranged corresponding to bit line pairs BLL, / BLL and BLR, / BLR in corresponding columns of memory blocks MBL and MBR. Sense amplifier SA is connected to bit lines BLL and / BLL via bit line isolation gate IGL which is selectively turned on in response to bit line isolation control signal BLIL, and in response to isolation control signal BLIR. Are connected to the bit lines BLR and / BLR via the bit line isolation gate IGR which is selectively turned on. Bit line isolation control signals BLIL and BLIR are output from isolation control circuit ICL responding to memory block designating signal BS. The separation control circuit ICL holds the separation control signal BLIL at the H level and the separation control signal BLIR at the L level when the memory block MBL is designated by the block designation signal BS.

  During the operation of the sense amplifier SA, only the bit line pair BLL, / BLL is connected to the sense amplifier SA, so that the load driven by the sense amplifier SA is reduced and the sense operation can be performed at high speed. Further, since the load capacitance (parasitic capacitance) of the sense node of sense amplifier SA (connection node between the sense amplifier and the bit line pair) is reduced, the read voltage from memory cell MC (memory cell memory transmitted to the bit line is stored). The amount of change in the potential of the bit line caused by the data can be increased, and the sensing operation can be performed stably. When memory block designating signal BS designates a memory block other than these memory blocks MBL and MBR, both bit line isolation control signals BLIL and BLIR are set to H level, and sense amplifier SA has isolation control gates IGL and IGR. To the bit line pairs BL, / BLL and BLR, / BLR. In this state, memory blocks MBL and MBR maintain a standby state (precharge state).

  FIG. 26A shows a structure of a portion for generating bit line isolation control signals BLIL and BLIR. In FIG. 26A, the refresh control circuit 6 responds to the refresh control unit 70 that is activated in response to the data holding mode detection signal REF given from the refresh detection circuit, and the activation signal from the refresh control unit 70. Then, a timer 18a that counts a predetermined period, a pause timer 72 that starts under the control of the refresh control unit 70, counts the pause time, and outputs the refresh request signal φPA every time the pause time elapses, and the refresh control unit 70 Includes a counter 74 that counts the refresh operation activation signal ZRAS output from.

  Counter 74 counts the number (128) of word lines included in each of memory blocks MBL and MBR, and sets count-up signal φCNT to, for example, an inactive state of L level after the completion of the counting operation. Under the control of the refresh control unit 70, the timer 18a outputs a signal indicating that a self-refresh operation is started after a predetermined period has elapsed since the data holding mode detection signal REF is activated. Refresh controller 70 repeatedly activates refresh operation activation signal ZRAS in response to the self-refresh mode designating signal from timer 18a while count signal φCNT from counter 74 is at the H level.

  Refresh operation activation signal ZRAS from refresh control unit 70 is applied to block decoder 76 which decodes block address signal bits RABa-RABb. The number of address signal bits applied to the block decoder 76 is determined by the number of memory blocks included in the memory mat. The block decoder 76 is activated when the refresh operation activation signal ZRAS from the refresh control unit 70 is activated, performs a decoding operation, and outputs a block designation signal BS.

  Isolation control circuit ICL receives count control signal φCNT from counter 74, block designation signal BS, and refresh operation activation signal ZRAS, and outputs bit line isolation signals BLIL and BLIR. Isolation control circuit ICL maintains the states of isolation control signals BLIL and BLIR while count control signal φCNT from counter 74 is in an active state of H level, that is, during a period when burst refresh is performed. Next, the operation of the circuit shown in FIG. 26A will be described with reference to FIG.

  When the data holding mode designating signal REF is activated to the H level, the refresh control unit 70 starts the timer 18a. When a time-up signal is applied from timer 18a, refresh control unit 70 activates counter 74 and activates its output signal φCNT at the H level. In parallel with this, the refresh operation activation signal ZRAS is activated. FIG. 26B shows an inverted signal RAS of the refresh operation activation signal ZRAS. In response to activation of refresh operation activation signal ZRAS, block decoder 76 decodes block address signal bits RABa-RABb applied from the row address buffer, and decodes block selection signal BS for the selected memory block. Then, the block selection signal BS for the selected memory block is activated.

  Isolation control circuit ICL sets one of bit line isolation control signals BLIL and BLIR to H level and the other to L level in accordance with a block selection signal (BS0) provided from block decoder 76.

  Now, assume that the memory block MBL is designated first. In this state, isolation control circuit ICL maintains bit line isolation signal BLIL at H level and fixes bit line isolation control signal BLIR at L level. While the count signal φCNT from the counter 74 is at the H level, the isolation control circuit ICL internally considers the refresh operation activation signal ZRAS to be always active. Therefore, even if refresh operation activation signal ZRAS from refresh control unit 70 repeats the active state and the inactive state repeatedly, isolation control signal BLIL remains at H level while count control signal φCNT from counter 74 is at H level. The separation control signal BLIR is maintained at the L level. Thereby, the charge / discharge currents of separation control signals BLIL and BLIR in separation control circuit ICL are reduced, and the current consumption in the data holding mode is reduced.

  When refresh control unit 70 generates refresh operation activation signal ZRAS 128 times, counter 74 resets count control signal φCNT to L level. In response to the reset of the count control signal φCNT from the counter 74, the separation control circuit ICL returns the separation control signal BLIR to the H level. At this time, the refresh controller 70 also starts the pause timer 72 in response to the fall of the count control signal φCNT from the counter 74. Pause timer 72 measures a predetermined pause time, and when this pause time elapses, it outputs refresh request signal φPA again. In response to the refresh request signal φPA, the refresh control unit 70 sets the counter 74 again to the driving state, sets the count control signal φCNT to the H level, and continuously outputs the refresh operation activation signal ZRAS 128 times. In this state, the block selection signal BS from the block decoder 76 designates the memory block MBR. Therefore, isolation control circuit ICL falls isolation control signal BLIL to L level and fixes isolation control signal BLIR to H level.

  The 128 word lines in the memory block MBR are sequentially selected, and the stored data in the memory cells in the memory block MBR is refreshed. When refresh operation activation signal ZRAS is generated 128 times, count control signal φCNT from counter 74 is set to L level, and isolation control circuit ICL is reset, and both of isolation control signals BIL and BIR are set to H level. To do. In response to the fall of the count control signal φCNT from the counter 74, the refresh control unit 70 starts the pause timer 72 again. During this time, the block decoder 76 maintains the state of the block selection signal BS to be output because the refresh operation activation signal ZRAS is inactive. This is because clock designation address signal bits RABa and RABb applied to block decoder 76 are applied from a statically operated row address buffer. However, the block decoder 76 may be configured to be in a reset state during the pause period after completion of the burst refresh operation, as indicated by a broken line in FIG.

  When refresh request signal φPA is applied again from pause timer 72, refresh control unit 70 activates counter 70 again to repeatedly activate refresh operation activation signal ZRAS. Block decoder 76 decodes the address signal bits again and outputs memory block designating signal BS. In this state, a memory block different from memory blocks MBL and MBR is designated. Therefore, separation control circuit ICL holds both separation control signals BIL and BIR at the H level.

  By performing burst refresh for each memory block by the above-described operation, the charge / discharge of the separation control signal for connecting the sense amplifier and the memory block is not performed during this burst refresh operation period. The current consumption in can be reduced.

  FIG. 27 is a diagram showing an example of the configuration of the block decoder 76 shown in FIG. FIG. 27 shows a configuration of a portion that generates one block selection signal BSi. 27, block decoder 76 includes an inverter 76a that receives refresh operation activation signal ZRS, an OR circuit 76b that receives an output signal of inverter 76a and a data holding mode designating signal REF, an output signal of OR circuit 76b, and a block designating address. AND circuit 76c receiving signal bits RABa-RABb is included. A memory block designating signal BSi is output from the AND circuit 76c.

  In the configuration shown in FIG. 27, when data holding mode designating signal REF is at the H level, that is, during the data holding mode operation, the output signal of OR circuit 76b is at the H level. Block designation address signal bits RABa to RABb are applied from an address buffer which operates statically in the data holding mode operation. Therefore, the block designating signal BSi output from the AND circuit 76c changes statically without being reset during the data holding mode operation, as shown in the block designating signal BS0 (BS1) shown in FIG. To change.

[Block decoder change example]
FIG. 28 is a diagram showing a modification of the block decoder 76 shown in FIG. In FIG. 28, block decoder 76 is rendered conductive when count control signal φCNT is at L level, and transfer control circuit 76d that passes block designation address signal bits RABa to RABb and refresh operation activation signal ZRAS, and this transfer It includes an inverter 76e receiving refresh operation activation signal ZRAS applied from control circuit 76d, and an AND circuit 76f receiving block designation address signal bits RABa-RABb applied from transfer control circuit 76d and an output signal of inverter 76e. A block selection signal BSi is output from the AND circuit 76f. Transfer control circuit 76d includes transfer gates formed of p-channel MOS transistors 76da to 76db and 76e provided for signals RABa to RABb and ZRAS and receiving count control signal φCNT at their gates.

  In the configuration shown in FIG. 28, count control signal φCNT is at the H level during the burst refresh operation period, and transfer gates 76da to 76db and 76dc included in transfer control circuit 76a are all non-conductive. Therefore, the state of the input signal of the AND circuit 76f does not change, and the state of the memory block BSi does not change during the burst refresh operation period. When the burst refresh operation period is completed and the pause period is reached, the count control signal φCNT is set to the L level, and the transfer gates 76da to 76db and 76dc of the transfer control circuit 76d are all turned on. In this state, the refresh operation activation signal ZRAS is set to the H level, so that the output signal of the inverter 76e is set to the L level, and the block designation signal BSi output from the AND circuit 76f is reset to the L level. Therefore, according to this configuration, the waveforms of block selection signals BS0 and BS1 indicated by broken lines in FIG.

  FIG. 29 is a diagram illustrating an example of the configuration of the separation control circuit ICL illustrated in FIG. Isolation control circuit ICL receives inverter 81 that receives refresh operation activation signal ZRAS, OR circuit 82 that receives the output signal of inverter 81 and count control signal φCNT, inverter 83 that receives block designation signal BSi, and block designation signal BS0. NAND circuit 85 receiving inverter 84, block designation signal BS0, output signal of inverter 83 and output signal of OR circuit 82, NAND circuit receiving block designation signal BS1, output signal of inverter 84 and output signal of OR circuit 82 86. The NAND circuit 85 outputs a separation control signal BLIR, and the NAND circuit 86 outputs a separation control signal BLIL.

  When count control signal φCNT is at H level, that is, during the burst refresh operation period, the output signal of OR circuit 82 is at H level, and NAND circuits 85 and 86 are enabled. Now, it is assumed that the block selection signal BS0 is at the H level and the block selection signal BS1 is at the L level. In this state, isolation control signal BLIL output from NAND circuit 86 is at H level, and isolation control signal BLIR output from NAND circuit 85 is at L level. Conversely, when block designation signal BS0 is at L level and block designation signal BS1 is at H level, block separation control signal BLIR is at H level and block separation control signal BLIL is at L level. When block selection signals BS0 and BS1 are both at L level, separation control signals BLIR and BLIL are both at H level.

  When count control signal φCNT becomes L level and the burst refresh operation period is completed, refresh operation activation signal ZRAS becomes H level, the output signal of inverter 81 becomes L level, and the output signal of OR circuit 82 becomes L level. . Thereby, isolation control signals BLIR and BLIL output from NAND circuits 85 and 86 are both reset to H level.

  Therefore, by utilizing the configuration of the separation control circuit shown in FIG. 29, the block selection designation signal BSi (BS0 and BS1) output from the block decoder 76 during the burst refresh operation period does not change its state. The states of control signals BSIR and BSIL do not change. Thereby, the charge / discharge current accompanying the set / reset of separation control signals BLIR and BLIL can be reduced.

  In the configuration shown in FIG. 29, a configuration similar to a latch circuit (transfer control circuit 76d shown in FIG. 28) that latches block designation signals BS0 and BS1 may be provided by count control signal φCNT.

  In the fourth embodiment, only refresh operation activation signal ZRAS is shown, but in the normal operation mode, internal RAS signal φRASZ is applied in place of refresh operation activation signal ZRAS.

[Example of change]
FIG. 30 shows a structure of a modification of the fourth embodiment of the present invention. In the configuration shown in FIG. 30, count control signal φCNT from refresh control circuit 6 is applied to control circuit 62 for realizing the static operation of the row address buffer. The refresh counter 10 resets the count value to the initial value when the data holding mode detection signal REF changes (at the time of setting and resetting). Other configurations are the same as those shown in FIG. 22, and corresponding portions are denoted by the same reference numerals. According to the configuration shown in FIG. 30, address buffer 16 performs a static operation during a burst refresh operation period, and the row address buffer maintains a reset state during a pause period. Therefore, even if the configuration shown in FIG. 30 is used, only the internal row address signal bits to be changed (including the clock designation signal) change during the burst refresh operation period. Similarly, the current consumption during the data holding mode operation is reduced. Can be reduced.

  Further, by resetting the refresh counter 10, refreshing can be performed accurately from the first word line of the memory block during burst refresh.

  As described above, according to the fourth embodiment of the present invention, the refresh operation is executed in units of memory blocks, and the burst refresh operation period (refresh operation period in units of blocks) is connected to the sense amplifier and the memory block. Therefore, the charge / discharge current associated with the set / reset of the separation control signal can be reduced, and the current consumption during the data holding mode operation can be reduced.

[Embodiment 5]
FIG. 31A shows a structure of a main portion of the DRAM according to the fifth embodiment of the present invention. FIG. 31A shows the configuration of one memory array portion. This memory array may be a sub-array. In FIG. 31A, main word lines MWL0 to MWLn are arranged corresponding to each row of memory cells in the memory array. The memory array is divided into a plurality of memory sub-blocks MG # 0, MG # 1,. In each memory sub-block MG # 0, MG # 1, sub-word line SWL is arranged corresponding to each row of memory cells. In FIG. 31A, sub word lines SWL00, SWL10 to SWLn0 are shown in memory sub block MG # 0, and sub word lines SWL01, SWL11 to SWLn1 are representatively shown in memory sub block MG # 1. One row of memory cells of a memory sub-block corresponding to these sub-word lines SWLkl (k = 0 to n: l = 0 to m (m is not shown)) is connected.

  For main word lines MWL0 to MWLn, row decode circuit RDx for decoding internal row address signal RA is provided. The number of internal row address signal bits RA applied to row decode circuit RDx is determined according to the number of main word lines MWL0 to MWLn included. The output section of the row decoder RDx drives the corresponding main word line to the selected state when selected (when the output signal of the row decode circuit RDx indicates the selected state) corresponding to each of the main word lines MWL0 to MWLn. Word line drive circuits WD0 to WDn are provided.

  In order to connect sub word line SWLkl to corresponding main word line MWLk, a sub block selection gate GTkl for connecting corresponding main word line MWLk and sub word line SWLkl in response to memory sub block selection signal RGl is provided. Sub-block selection gate GTkl drives corresponding sub-word line SWLkl to the selected state when the corresponding sub-block selection signal RGl and the signal on corresponding main word line MWLk are both set to the H-level selected state.

  The structure shown in FIG. 31A is called a “divided word line (DWL)” structure including a main word line and a sub word line. The number of memory cells connected to the selected word line is small, the load capacity of the word line is small, and the corresponding sub word line can be selected at high speed.

  In the divided word line configuration shown in FIG. 31A, refresh is performed for each memory sub-block during the refresh operation. That is, after the memory cells connected to sub word lines SWL00 to SWLn0 are sequentially refreshed in one memory sub block MG # 0, the refresh operation of the memory cells in the next memory sub block MG # 1 is executed. Memory subblock designating signal RGk is output from block selection circuit SBS that decodes memory block designating signals RAp to RAq.

  Block selection circuit SBS is selectively activated in response to refresh operation activation signal ZRAS and count control signal φCNTa. In the refresh operation, block selection circuit SBS holds the state of sub block designating signal RGk until all sub block word lines are selected in one memory sub block.

  FIG. 31B shows the operation of the DRAM shown in FIG. 31A in the data holding mode. In FIG. 31B, when data holding mode designating signal REF is activated, refresh operation activation signal ZRAS is repeatedly activated. In response to the activation of the refresh operation activation signal ZRAS, the row decode circuit RDx performs a decoding operation to sequentially set the main word lines MWL to a selected state. Assume that the number of main word lines MWL is 128 (n = 127). Block select circuit SBS maintains the state of memory sub-block designating signal RGi while refresh operation activation signal ZRAS is activated 128 times under the control of count control signal φCNTa during the data holding mode operation. . Thus, in the data holding mode, it is not necessary to reset the sub-block designation signal RGi for each refresh operation, and current consumption associated with charging / discharging of the sub-block designation signal can be reduced.

  In the configuration shown in FIGS. 31A and 31B, the refresh operation is performed in burst refresh operation in units of memory sub-blocks, but may be refreshed according to the distributed refresh mode.

  As the configuration of the block selection circuit SBS, the configuration of the block decoder 76 and the separation control circuit ICL described in the fourth embodiment can be used. In this case, regarding count control signal φCNTa, the count value of counter 75 shown in FIG. 26 may be appropriately adjusted according to the number of main word lines included.

  As described above, according to the fifth embodiment of the present invention, in a DRAM having a divided word line configuration including a main word line and a sub word line, when refresh is performed in units of memory sub blocks of sub word lines, one sub The memory sub block selection signal for connecting the sub word line and the main word line is not changed until the refresh operation of the memory cell of the block is completed. The accompanying current consumption can be reduced, and the current consumption during the data holding mode operation can be reduced.

[Embodiment 6]
FIG. 32A schematically shows a structure of a main portion of the DRAM according to the sixth embodiment of the present invention. 32A, switching elements 81a and 81b that are rendered non-conductive in response to pause period designation signal PS are provided between peripheral circuit 82 and memory array 84 and power supply node Vcc. An intermediate voltage generation circuit 86 that generates intermediate voltage Vcc / 2 from power supply voltage Vcc from power supply node Vcc and applies it to memory array 84 is always supplied with power supply voltage Vcc to generate intermediate voltage Vcc / 2. Memory array 84 may include a plurality of memory mats, or may be a single memory mat that is selected during a refresh operation. Peripheral circuit 82 includes a row decoder and sense amplifier activation circuit for driving memory array 84 to a selected state. FIG. 32B is a waveform diagram showing an operation of the DRAM shown in FIG. The operation of the DRAM according to the sixth embodiment of the present invention will be described below with reference to FIG.

  In the data holding mode operation, pause period designation signal PS is set to L level during burst refresh, switching elements 81a and 81b are turned on, and peripheral circuit 82 and memory array 84 are connected to a power supply node. A power supply voltage Vcc from Vcc is supplied. An intermediate voltage Vcc / 2 is always supplied from the intermediate voltage generation circuit 86.

  When the burst refresh operation is completed and the pause period starts, pause period designation signal PS is set to H level, switching elements 81a and 81b are turned off, and supply of power supply voltage Vcc to peripheral circuit 82 and memory array 84 is provided. Is stopped, and the operating power supply voltage in peripheral circuit 82 and memory array 84 drops to the ground potential level as it discharges. During the pause period, the refresh operation is not performed, and the peripheral circuit 82 and the memory array 84 are not operated. Therefore, the current consumption during this pause period can be greatly reduced.

  When the pause time elapses, the burst refresh operation is performed again. In response to the end of the pause period, pause period designation signal PS is set to L level again, switching elements 81a and 81b are rendered conductive, and power supply voltage Vcc is supplied to peripheral circuit 82 and memory array 84. Peripheral circuit 82 and memory array 84 are rendered operable. When the power supply voltage in the peripheral circuit 82 and the memory array 84 is stabilized, the burst refresh operation is executed again.

  FIG. 33 shows an exemplary configuration of memory array 84 and peripheral circuit 82 shown in FIG. FIG. 33 representatively shows a pair of bit lines BL and / BL and word lines WL0 and WL1 in the memory array. A memory cell MC is arranged corresponding to the intersection of the bit line BL and the word line WL, and another memory cell MC is arranged corresponding to the intersection of the bit line / BL and the word line WL. These memory cells MC are connected to a capacitor C that stores information in the form of electric charges and an access transistor T that conducts in response to the potential on the corresponding word line and connects the capacitor to the corresponding bit line BL (or / BL). including.

  When the sense amplifier driving transistor 22a is turned on as a bit line peripheral circuit, the power supply voltage 89 is supplied from the power supply line 89 to operate to drive the high bit line potentials of the bit lines BL and / BL to the power supply voltage Vcc level. A sense amplifier 20 is provided. A control portion for the n-channel MOS transistor of the sense amplifier 20 is not shown.

  A precharge / equalize circuit EP is provided for bit lines BL and / BL, which is activated in response to bit line equalize instruction signal EQ and precharges bit lines BL and / BL to an intermediate potential. . Precharge / equalize circuit EP is turned on in response to equalize instruction signal EQ to electrically short-circuit bit lines BL and / BL, and intermediate voltage Vbl (= Vcc / 2) is applied to bit lines BL and / A MOS transistor for transmitting to BL is included.

  Intermediate voltage generation circuit 86 generates bit line precharge voltage Vbl and cell plate voltage Vcp at intermediate voltage Vcc level from power supply voltage Vcc from power supply node Vcc. This bit line precharge voltage Vbl is supplied to a precharge / equalize circuit EP provided for each bit line pair. Cell plate voltage Vcp is applied to one electrode (cell plate electrode) of capacitor C included in memory cell MC.

  Peripheral circuit 82 outputs equalize control circuit 83 for generating equalize signal EQ, X decoder 85 for driving the word line to the selected state, and sense activation signal φS for activating sense amplifier 20. A sense control circuit 87 is included. Equalize control circuit 83 is always active in order to hold the potentials of bit lines BL and / BL at an intermediate potential level via precharge / equalize circuit EP included in memory array 84. X decoder 85 is coupled to power supply node Vcc through switching transistor 81aa (exemplarily shown as a p-channel MOS transistor). Sense control circuit 87 is supplied with power supply voltage Vcc from power supply node Vcc via switching transistor 81ab. Power supply line 89 is coupled to power supply node Vcc through switching transistor 81ba. Pause period designation signal PS is applied to the gates of switching transistors 81aa, 81ab and 81ba.

  In the refresh operation and the normal operation mode, the pause period designation signal PS is at L level, the switching transistors 81aa, 81ab and 81ba are all in a conductive state, and the X decoder 85 and the sense control circuit 87 are all operable. State. The power supply line 89 is supplied with the power supply voltage Vcc via the switching transistor 81ba. Therefore, in this state, since the operating power supply voltage is supplied, the X decoder 85, the sense control circuit 87, and the sense amplifier 20 operate normally and can perform a refresh operation. Equalize control circuit 83 is always supplied with power supply voltage Vcc from power supply node Vcc. Therefore, bit lines BL and / BL are stably precharged to the intermediate potential level even during the refresh operation.

  In the pause period, pause period designation signal PS is set to H level, and switching transistors 81aa, 81ab and 81ba are all turned off. Therefore, X decoder 85 and sense control circuit 87 are inactivated, and word lines WL0, WL1,... Are held at the ground potential level (because the signal lines are discharged and maintained in the same state as the reset state). In sense control circuit 87, sense activation signal φS is set to the L level. Even in this state, since power supply line 89 is isolated from power supply node Vcc by switching transistor 81ba, power supply line 89 is also in a floating state, the potential is lowered to the ground potential level, and sense amplifier 20 is in an inoperative state. It is said. Even in this state, equalize control circuit 83 is in the operating state, equalize instruction signal EQ is at the H level, precharge / equalize circuit EP operates, and bit lines BL and / BL are precharged at intermediate potential Vbl. Precharge to level and hold. A cell plate voltage Vcp (= Vcc / 2) is supplied from the intermediate voltage generation circuit 86 to the cell plate electrode of the capacitor C of the memory cell MC, and this cell plate voltage maintains a predetermined intermediate voltage level. During the pause period, the operation state of the intermediate voltage generation circuit 86 is maintained to prevent the memory cell data from being destroyed. Hereinafter, prevention of the destruction of the memory cell data will be described.

  FIG. 34A shows a change in the potential of the memory cell when the operation of intermediate voltage generation circuit 86 is stopped during the pause period. As shown in FIG. 34A, when the operation of intermediate voltage generation circuit 86 is stopped, the potential of bit line BL (or / BL) is discharged from intermediate potential Vcc / 2 to 0 V during the pause period. . Cell plate voltage Vcp also drops from intermediate voltage Vcc / 2 to 0V level. The potential of the word line WL is 0 V in the non-selected state. A connection node (storage node) SN between the memory access transistor T and the capacitor C is in a floating state. In this state, when the cell plate voltage Vcp at the intermediate potential level is lowered to 0 V, the potential of the storage node SN is lowered by Vcc / 2 due to the capacitive coupling of the capacitor C. When the capacitor C stores L level data, the potential (−Vcc / 2) of the storage node SN is lower than the potential (0V) of the bit line BL, and the potential of the word line WL is 0V. Access transistor T becomes conductive, electrons flow from storage node SN to bit line BL, and the potential of storage node SN rises. Therefore, the information of L level data (potential 0 V) stored in storage node SN is lost, and the memory cell data is destroyed, or the refresh characteristic (data retention characteristic) of the memory cell is deteriorated.

  In order to prevent the potential drop of the storage node SN due to the capacitive coupling of the capacitor C, it is conceivable to fix the cell plate potential Vcp to the ground potential level (even during normal operation). However, in this case, although the potential drop due to the capacitive coupling of storage node SN does not occur, sense operation is performed by precharging bit lines BL and / BL to intermediate potential Vbl (= Vcc / 2) during normal operation or refresh operation. Can no longer do.

  That is, when bit lines BL and / BL are precharged to intermediate potential Vcc / 2 and cell plate potential Vcp is fixed to 0 V, the amount of change in the potential of the bit line during H level data reading and L level data reading The magnitude of (read voltage) is different.

V ′ (H) −Vcc / 2
= (Vcc / 2) (Cb / (Cb + Cs)),
Vcc / 2−V ′ (L) = (Vcc / 2) · Cs / (Cb + Cs)
It is because it becomes. Here, Cb and Cs indicate the capacity of the bit line and the capacity of the memory cell capacitor C, respectively, and V ′ (L) and V ′ (H) are the bits at the time of L level data reading and H level data reading, respectively. Indicates the potential of the line. Therefore, the operation margin of the sense amplifier differs when H level data and L level data are read (Cb> Cs), and an accurate sense operation cannot be performed.

  Therefore, as shown in FIG. 34B, intermediate voltage generation circuit 86 and equalize control circuit 83 are activated, and bit line BL (or / BL) and cell plate voltage Vcp are set to intermediate voltage Vcc / Held at a potential level of 2. As a result, there is no influence of capacitive coupling by the capacitor C on the storage node SN, and the storage node SN accurately holds charges corresponding to the stored data. Thereby, destruction of stored data is prevented and deterioration of refresh characteristics is prevented.

  As described above, in the pause period, supply of power supply voltage Vcc to memory array 84 and peripheral circuit 82 is stopped, and intermediate voltage generation circuit 86 is always operated, so that bit lines BL and / BL and cell plates and intermediate voltage Vcc / By maintaining the precharge voltages Vbl and Vcp at level 2, current consumption can be reduced without causing deterioration of refresh characteristics and destruction of memory cell storage data.

  FIG. 35A is a diagram showing a configuration of a portion that generates a pause period designation signal PS. In FIG. 32A, a pause period designation signal generation system includes a counter 74a that counts the number of refresh operation activation signals that are activated during a burst refresh operation, a pause timer 72 that defines a pause period, and a counter 74a. Set / reset flip-flop 90 which is set in response to the fall of count control signal φCNT from the timer and reset in response to activation of refresh request signal φPA from pause timer 72, and set / reset flip-flop 90 AND circuit 91 which receives an output signal given from output Q and data holding mode designating signal REF. The AND circuit 91 outputs a pause period designation signal PS. Next, the operation of the circuit shown in FIG. 35A will be described with reference to the waveform diagram shown in FIG.

  When data holding mode designating signal REF is activated to an H level, AND circuit 91 is enabled. In the previous state, pause period specifying signal PS output from AND circuit 91 is at L level, and switching transistors 81aa, 81ab and 81ba are all in a conductive state. When a burst refresh operation is performed in response to the active state of data holding mode designating signal REF, count control signal φCNT from counter 74a is set to H level. When the burst refresh operation is completed, count control signal φCNT falls to L level, flip-flop 90 is set, the signal from its output Q rises to H level, and pause period designation signal PS is set to H level accordingly. . When the pause period is completed, the refresh request signal φPA from the pause timer 72 is set to H level, the flip-flop 90 is reset, the signal from its output Q is set to L level, and the pause period designation signal PS is set to L level. . In response to refresh request signal φPA, the burst refresh operation is performed again, and count control signal φCNT is set to the H level. When this burst refresh operation is completed, flip-flop 90 is set again, and pause period designation signal PS is accordingly set to H level. Thereafter, while the data holding mode designation signal REF is at the H level, the pause period designation signal PS is at the L level during the burst refresh operation period, and the pause period designation signal PS is at the H level during the pause period.

  When the data holding mode is completed, the pause period specifying signal PS is set to the L level in response to the decrease of the data holding mode specifying signal REF to the L level.

  In the configuration shown in FIG. 35A, the pause period designation signal PS is configured to be supplied with the power supply voltage Vcc only in the data holding mode only for the memory mat to be refreshed in combination with the memory mat designation signal. Also good. This uses a configuration in which the pause period designation signal PSi for the memory mat is generated by the logical sum of the inverted signal of the memory mat designation signal MSi and the pause period designation signal PS as shown by the broken line block in FIG. It only has to be done.

  Note that a configuration in which only the cell plate potential Vcp at the intermediate potential level is always applied may be employed.

  As described above, according to the sixth embodiment of the present invention, in the memory array, the supply of the power supply voltage is stopped and the intermediate voltage is always supplied during the pause period. Therefore, current consumption can be reduced without causing data leakage and therefore without causing data destruction and refresh characteristic deterioration.

[Embodiment 7]
FIG. 36A schematically shows a whole structure of the DRAM according to the seventh embodiment of the present invention. 36A, an internal high voltage generation circuit 92 for generating internal high voltage Vpp higher than the internal operating power supply potential is provided in a central region between memory mats MM # 0 to MM # 3. Internal high voltage generation circuit 92 is formed of a charge pump circuit that utilizes a charge pump operation of a capacitor, for example. The internal high voltage Vpp is transmitted onto the selected word line as will be described in detail later.

  Main internal high voltage lines 95a to 95d are arranged corresponding to memory mats MM # 0 to MM # 3, respectively. Main internal high voltage line 95a receives internal high voltage Vpp from internal high voltage generation circuit 92 through switching transistor 94a which is selectively turned on in response to memory mat designation signal / MS0. Main internal high voltage line 95b receives internal high voltage Vpp from internal high voltage generation circuit 92 through switching transistor 94b which is selectively turned on in response to memory mat designation signal / MS1. Main internal high voltage line 95c receives internal high voltage Vpp from internal high voltage generation circuit 92 through switching transistor 94c which is selectively turned on in response to memory mat designation signal / MS2. Main internal high voltage line 95d receives internal high voltage Vpp through switching transistor 94d which is selectively rendered conductive by memory mat designation signal / MS3. Internal high voltage generation circuit 92 includes an internal high voltage generator provided in each of memory mats MM # 0 to MM # 0 (shown by a broken line).

  For memory mats MM # 0-MM # 3, Vpp switches 96a-96d receiving internal high voltage Vpp from corresponding internal high voltage lines 95a-95d are provided. The configuration of the Vpp switch will be described in detail later. In the data holding mode operation, the internal high voltage Vpp given from the corresponding main internal high voltage line is transmitted to the subarray group in which the refresh operation is performed. In the standby state (precharge state), the supply of the internal high voltage to the corresponding subarray group is stopped.

  In the normal operation mode, memory mat designating signals / MS0- / MS3 are all at the L level of the selected state, switching transistors 94a-94d are all in the conductive state, and internal high voltage Vpp from internal high voltage generating circuit 92 is in the conductive state. Is applied to main internal high voltage lines 95a-95d. Vpp switch groups 96a to 96d are in a conductive state in the normal operation mode, and internal high voltage applied from corresponding main internal high voltage lines 95a to 95d is applied to corresponding memory mats MM # 0 to MM # 3. introduce. Therefore, in the normal operation mode, memory mats MM # 0 to MM # 3 are selected and operate in response to internal high voltage Vpp.

  On the other hand, in the data holding mode operation, only one memory mat is designated and the refresh operation is performed. Therefore, only one memory mat designation signal among memory mat designation signals / MS0 to / MS3 is set to the L level selection state, and the remaining memory mat designation signals are set to the H level inactive state. Since the non-selected memory mat maintains the standby state, the internal high voltage Vpp is not consumed, and thus the current consumption in the data holding mode can be reduced.

  FIG. 36B shows in more detail the configuration of the Vpp switch for one memory mat (representing MM # 0 as a representative). In FIG. 36B, memory mat MM # 0 includes eight subarrays MB # 0-MB # 7 as an example. Subarrays MB # 0-MB # 7 are divided into two groups in units of subarrays in which refresh operations are performed simultaneously. Subarrays MB # 0, MB # 2, MB # 4, and MB # 6 constitute one subarray group, and subarrays MB # 1, MB # 3, MB # 5, and MB # 7 constitute another subarray group. . Local internal high voltage lines 95aa are arranged for even-numbered subarrays, and local internal high voltage lines 95ab are arranged in common for odd-numbered subarrays.

  Vpp switch 96a is arranged between main internal high voltage line 95a and local internal high voltage line 95aa, and is a switching transistor 96aa formed of a p-channel MOS transistor that is selectively turned on in response to array group designation signal SAG0. Switching transistor 96ab formed of a p-channel MOS transistor connected between internal high voltage line 95a and local internal high voltage line 95ab and selectively rendered conductive in response to array group designation signal SAG1. Including.

  Subarrays MB # 0-MB # 7 are selected at the time of refreshing according to refresh block selection signals RBS and / RBS that simultaneously designate blocks to be refreshed at the time of refresh operation (decode signals of bits RAa, RAb, RAc). The During normal operation, only one subarray is selected. This configuration is the same as in the first embodiment.

  In the normal operation mode, subarray group designation signals SAG0 and SAG1 are both at L level, switching transistors 96aa and 96ab are in a conductive state, and internal high voltage line 95aa to local internal high voltage lines 95aa and 95ab Supply voltage Vpp. In memory mat MM # 0, one sub-array is selected and access is made to the selected memory cell. Even in the normal operation mode, only the switching transistors of the subarray group including the selected subarray may be made conductive.

  On the other hand, in the data holding mode operation, in the refresh operation, one of array group designation signals SAG0 and SAG1 is selected and the other is not selected (however, memory mat MM # 0 is designated). When). Therefore, in this state, only the switching transistor (96aa or 96ab) provided corresponding to the subarray to be refreshed is rendered conductive, and the local internal high voltage line (provided for the subarray to be refreshed) 95aa or 95ab) is supplied with internal high voltage Vpp from internal high voltage line 95a. The local internal high voltage line (95ab or 95aa) provided for the non-selected subarray is separated from the internal high voltage line 95a. In this state, as will be described later in the non-selected subarray, only the subthreshold current flows, and the current consumption is extremely reduced. As a result, the data holding current during the data holding mode operation (the refresh current consumed during the refresh operation and the standby current during the standby state during the data holding mode) can be greatly reduced. Further, only one switching transistor is provided for a subarray group composed of a plurality of subarrays, and the number of transistors included in a Vpp switch for selectively supplying an internal high voltage can be reduced. The area occupied by the Vpp switch can be reduced.

  FIG. 37 is a diagram showing a configuration of a portion using a high voltage of one subarray. In FIG. 37, memory sub-array MB # (MB # 0-MB # 7) decodes a given internal row address signal (not shown) and outputs a word line designating signal, and word line Word line drivers WD0 to WDn are provided corresponding to WL0 to WLn, respectively, and drive corresponding word lines to a selected state in response to a row designation signal from X decoder RD. The word line drivers WD0 to WDn are turned on in response to the L level signal indicating the selected state from the X decoder RD, and transmit the internal high voltage Vpp to the corresponding word lines WL (WL0 to WLn). Transistor PQ includes an n channel MOS transistor NQ which is turned on in response to a word line non-designating signal (H level) from X decoder RD and discharges corresponding word line WL to the ground potential level.

  One conduction node (source node) of p channel MOS transistor PQ included in each of word line drivers WD0 to WDn is commonly coupled to local internal high voltage line 95 (95a to 95d) via switching transistor 96 (96aa). Is done. Switching transistor 96 is selectively rendered conductive in response to memory subarray group designation signal SAG (SAGi).

  For example, when word line WL0 is selected, p channel MOS transistor PQ included in word line driver WD0 is rendered conductive, and internal high voltage Vpp is transmitted onto word line WL0 (in this state, switching transistor 96 is in conduction). Therefore, since the gate potential of access transistor T included in memory cell MC is set higher than the internal operating power supply potential (Vint: not shown), the threshold voltage loss of access transistor T (n-channel MOS transistor) is reduced. The internal high voltage (Vint level voltage) on the bit line BL can be transmitted to the capacitor C without accompanying. Thereby, even when a low power supply voltage is used, H level data can be stored in the capacitor C without voltage loss.

  The current driving capability (channel width) of switching transistor 96 is approximately the same as the current driving capability (channel width) of p-channel MOS transistor PQ included in each of word line drivers WD0 to WDn. Since only one word line is set to the selected state, only one p-channel MOS transistor PQ is set to the conductive state, and a required drive current is supplied to the word line driver via the switching transistor 96. Can do.

  In the standby state (or in the precharge state; both in the refresh operation and the normal operation), p channel MOS transistor PQ included in word line drivers WD0 to WDn is turned off. Usually, in this case, the gate potential of MOS transistor PQ is set to the internal high voltage Vpp level. In the standby state, array group designation signal SAG is held at the H level (internal high voltage Vpp level). Switching transistor 96 is formed of a p-channel MOS transistor, and sub-threshold current Is flows even when the gate and source potentials are equal. Also in word line drivers WD0 to WDn, a subthreshold current flows in p channel MOS transistor PQ. However, in this case, only the subthreshold current Is is supplied through one switching transistor 96, and the subthreshold current Id of the p-channel MOS transistor PQ included in the word line drivers WD 0 to WDn and the switching transistor 96 are used. Subthreshold current Is flowing in the following manner: Is = n · Id. Due to this subthreshold current Is, the drain node potential of switching transistor 96 becomes lower than internal high voltage Vpp (voltage drop due to the channel resistance of switching transistor 96). Therefore, the source potential of np channel MOS transistor PQ of word line drivers WD0 to WDn becomes lower than its gate potential, the gate-source region of p channel MOS transistor PQ is put in a reverse bias state, and the subthreshold current is further reduced. The Thereby, the subthreshold current in the standby state can be reduced, and the current consumption in the data holding mode can be reduced.

  FIG. 38A shows a structure of a portion that generates array group designation signal SAG. In FIG. 38, the array group designation signal generation unit includes a NAND circuit 99a that receives memory mat designation signal MSi and subarray group designation address signal bits RAi (RAa-RAc), a data holding mode designation signal REF, and an output signal of NAND circuit 99a. Receiving AND circuit 99b. The array group designation signal RAi is a 1-bit row address signal bit (RAc) because the upper array group designation address signal bits (bits RAa and RAb shown in FIG. 4) are degenerated during the data holding mode operation. ) Is used. Needless to say, the number of subarray group designation signal bits RAi is appropriately determined according to the number of subarray groups in the subarray. Next, the operation of the configuration shown in FIG. 38A will be described with reference to the waveform diagram shown in FIG.

  In the data holding mode operation, data holding mode designating signal REF is at the H level, and NAND circuit 99b operates as a buffer. When memory mat designating signal MSi is selected and becomes H level, switching transistor 94 is turned on in FIG. When array group designation signal RAi is selected, the output signal of NAND circuit 99a is at L level, array group designation signal SAGi is at L level, and switching transistor 96 (see FIG. 37) is turned on. . On the other hand, in the non-selected state, the output signal of NAND circuit 99a is at H level, and array group designation signal SAGi output from AND circuit 99b is at H level. Therefore, switching transistor 96 is turned on and internal high voltage Vpp is supplied to the array group to be refreshed, and switching transistor 96 is turned off in the non-selected subarray group (and memory mat). The supply of the internal high voltage Vpp is cut off.

  In the normal operation mode, data holding mode designating signal REF is at L level, and array group designating signal SAGi is always at L level.

  In the configuration shown in FIG. 37A, the memory mat designation signal MSi is valid in the data holding mode operation, and the memory mat designation signal MSi is in the degenerated state in the normal operation mode. Therefore, in the normal operation mode, memory mat designating signal MSi selects all memory mats MM # 0 to MM # 3, and in the data holding mode operation, the memory mat designation signal MSi selects the refreshed memory mat. Only the memory mat designation signal MSi is selected. Therefore, the AND circuit 99b need not be provided.

  In particular, in the waveform diagram shown in FIG. 38B, when burst refresh is performed in which refresh is performed in subarray units (array block units) in the refresh period, current consumption can be further reduced. The signal φCNT may be used instead of the signal REF.

[Modification 1]
FIG. 39 is a diagram showing a configuration of a first modification of the seventh embodiment of the present invention. In FIG. 39A, a switching transistor 94 provided between internal high voltage generation circuit 92a provided corresponding to each memory mat and main internal high voltage line 95 includes an inverted signal / MSi of the memory mat designation signal. This conduction / non-conduction is controlled by the output signal of the OR circuit 100 which takes the logical sum of the internal RAS signal φRASZ. The operation of the configuration of FIG. 39A will be described with reference to FIG. 39B which is an operation waveform diagram thereof.

  Internal RAS signal φRASZ is at the H level in the standby state (precharge state) in both the data holding mode and the normal operation mode, and in the active cycle (a period in which the memory cell is actually selected and the sense amplifier operates). Is at the L level. In the data holding mode operation cycle, the memory mat designation signal / MSi is set to the L level of the selected state only for the memory mat to be refreshed. The memory mat designation signal / MSi for the non-selected memory mat is set to the H level, and the switching transistor 94 is turned off regardless of the operation cycle. In the selected memory mat, output signal φS of OR circuit 100 attains an L level and an H level in accordance with the operation cycle of the active cycle and the standby cycle, and switching transistor 94 is turned on during the active cycle and turned off during the standby cycle. Is done. Therefore, the current consumption during the standby cycle during the data holding mode operation can be further reduced.

  In the normal operation mode, memory mat designating signal / MSi is set to the L level of the selected state in all memory mats. Therefore, switching transistor 94 is selectively turned on / off in response to output signal φS of OR circuit 100 in accordance with the operation cycle. Therefore, the standby current in the normal operation mode can be reduced.

  If the standby cycle period is short during the burst refresh operation (RAS system precharge period), there is no need to selectively turn on / off the transistor 94, and even in the normal operation mode. In order to make transistor 94 conductive / non-conductive in the standby cycle and active cycle, the count control signal φCNT (see the third to fifth embodiments) is used and an inverted signal of the count control signal φCNT is used as the internal RAS. A logical product signal of the signal φRASZ may be supplied to the OR circuit 100 instead of the signal φRASZ (indicated by ()).

[Modification 2]
FIG. 40 shows a structure of a second modification of the seventh embodiment of the present invention. In the configuration shown in FIG. 40, internal high voltage Vpp is directly applied to main internal high voltage line 95 from internal high voltage generation circuit 92a. Internal high voltage line 95 is connected to local internal high voltage lines 95ia and 95ib via Vpp switch 96. Vpp switch 96 includes a switching transistor (p-channel MOS transistor) 96x that is selectively turned on in response to an output signal of NAND circuit 97x that receives memory mat designation signal MSi and array group designation signal RAj, and memory mat designation signal MSi. And a switching transistor (p-channel MOS transistor) 96y that is selectively turned on in response to an output signal of NAND circuit 97y receiving subarray group designation signal RAi. Switching transistor 96x conducts when a sub-array group connected to local internal high voltage line 95ia is designated, and electrically connects main internal high voltage line 95 and local internal high voltage line 95ia. Switching transistor 96y is turned on when a sub-array group connected to local internal high voltage line 95ib is designated, and connects main internal high voltage line 95 and local internal high voltage line 95ib.

  In the structure shown in FIG. 40, when array group designation signals RAj and RAi are generated based on a signal output from a statically operating row address buffer, a subarray group in which refresh is performed during a burst refresh cycle period. The switching transistors 96x or 96y provided corresponding to are connectedly connected. In the pause period, memory mat designation signal MSi and array group designation signals RAi and RAj are reset, so that switching transistors 96x and 96y are turned off.

  In the normal operation mode, the memory mat designation signal MSi is always at the H level in the selected state. In the active cycle, array group designation signal RAi or RAj corresponding to the selected sub-array becomes H level, and corresponding switching transistor 96x or 96y is turned on. In the standby cycle, array group designation signals RAi and RAj are reset to L level, and switching transistors 96x and 96y are both turned off.

  Therefore, with the configuration shown in FIG. 40, internal high voltage Vpp is transmitted to the refreshed subarray group during the burst refresh operation period, and internal high voltage line 95 and local internal high voltage lines 95ia and 95ib are transmitted during the pause period. Can be separated. In the normal operation, the switching transistors corresponding to the subarray group including the operating subarray are turned on in the active cycle, and the switching transistors 96x and 96y are both turned off in the standby cycle. Therefore, current consumption due to the subthreshold current in the array precharge state (pause period or standby cycle in the normal cycle operation mode) can be greatly reduced.

  As described above, according to the seventh embodiment of the present invention, in a plurality of memory mats, a refresh operation is intensively performed in one memory mat, and refresh is performed on the memory mat on which this refresh is performed. Since the internal high voltage is supplied only to the sub-array group, the current consumption can be significantly reduced compared to the configuration in which the internal high voltage is supplied to all the memory mats (leakage current in the word driver). Can be reduced).

  In the seventh embodiment, internal high voltage Vpp is shown to be transmitted only to the word line drive circuit. However, as shown in the fourth embodiment, in the “shared sense amplifier” arrangement in which the sense amplifier is shared by the sub-arrays, this internal control signal BLIL and BLIR are generated to generate the separation control signals BLIL and BLIR that connect the sense amplifiers and the sub-arrays A high voltage Vpp may be used. In this case, the supply of the internal high voltage to the non-selected memory block paired with the selected sub-array (memory block) is stopped. In other non-selected memory blocks, the isolation signal needs to hold the high voltage Vpp level.

[Embodiment 8]
FIG. 41 shows a structure of a main portion of the DRAM according to the eighth embodiment of the present invention. In FIG. 41A, two memory blocks MBAa and MBAb are shown. Each of memory blocks MBAa and MBAb may be one subarray, and memory blocks MBAa and MBAb may be included in one subarray. Further, the number of memory blocks MBAa and MBAb may be greater than two.

  Memory block MBAa includes 64 word lines WL0 to WL63, and memory block MBAb includes 64 word lines WL64 to WL127. Sub-bit line pairs SBL1, / SBL1,... Connected to one column of memory cells of memory block MBAa are arranged so as to cross word lines WL0 to WL63. Similarly, in memory block MBAb, sub bit line pairs SBL2, / SBL2,... Connected to one column of memory cells of memory block MBAb are arranged so as to cross word lines WL64 to WL127. In FIG. 41, memory cell MC arranged corresponding to the intersection of word line WL63 and sub-bit line SBL1, and memory cell MC arranged corresponding to the intersection of word line WL127 and sub-bit line SBL2 are representatively shown. Show.

  Main bit line pairs MBL, / MBL,... Are arranged in common to the memory cell columns of memory blocks MBAa and MBAb. This main bit line pair MBL, / MBL is electrically connected to sub bit line pair SBL1, / SBL1 through block select gates BG0a and BG0b which are turned on in response to block select signal BS0, and to block select signal BS1. It is connected to sub bit line pair SBL2, / SBL2 via block select gates BG1a and BG1b which are turned on in response. These block selection signals BS0 and BS1 are generated by a block selection circuit 102 that operates in accordance with block designation address signal bits RABa,..., RABb and data holding mode designation signal REF. The main bit line pair MBL, / MBL is provided with a sense amplifier 20 for detecting and amplifying data appearing on the main bit lines MBL, / MBL.

  In operation, one memory block is selected, and the sub bit line pair SBL, / SBL of this selected memory block is connected to the corresponding main bit line MBL, / MBL. The number of memory cells connected to the main bit lines MBL and / MBL is small, and the parasitic capacitance of the main bit lines MBL and / MBL is accordingly reduced, so that data can be detected and amplified at high speed. The configuration of the main bit line and the sub bit line is called “hierarchical bit line structure”.

  In the normal operation mode, block selection signals BS0 and BS1 are inactive in the standby state, and in the active cycle, only the block selection signal for the selected memory block is in the active state of H level. In the data holding mode operation, a refresh operation is performed in units of memory blocks. This data holding mode operation will be described with reference to FIG.

  The data holding mode designating signal REF is activated to an H level and the DRAM enters the data holding mode. Now, it is assumed that the word lines WL0 to WL63 included in the memory block MBAa are sequentially refreshed. In this state, the block selection circuit 102 holds the block selection signal BS0 at the H level during a period in which the word lines WL0 to WL63 are sequentially selected (burst refresh period). During this time, the block selection signal BS1 is fixed at the L level. When the refresh operation of the memory cell MC of the memory block MBAa is completed, the block selection circuit 102 then sets the block selection signal BS0 to L level and the block selection signal BS1 to H level. The word lines WL64 to WL127 are sequentially selected and the memory cell data is refreshed. During this period, the block selection signal BS1 is held at the H level of the selected state. When refresh is performed during a burst refresh period, that is, when word lines are sequentially selected in one memory block, the block selection signal is held for each refresh cycle by holding the block selection signal for this memory block in the selected state. Need not be driven to the set / reset state (selected state / non-selected state), the current consumption for driving the block selection signal can be reduced, and the current consumption in the data holding mode can be reduced. it can.

  The configuration of the block selection circuit 102 shown in FIG. 41A can use the configuration of the block selection circuit 76 shown in FIG. 27 or FIG.

  As described above, according to the eighth embodiment of the present invention, in a memory block having a hierarchical bit line structure, when refreshing is performed in units of memory blocks formed by sub-bit lines, the memory block including the selected word line is Since the block selection signal is always held in the selected state and the block selection signal of the non-selected memory block is fixed to the L level in the non-selected state, the block selection signal is changed to the selected state and the non-selected state in the data holding mode operation. There is no need to drive, the current consumption for driving the block selection signal can be reduced, and the current consumption in the data holding mode can be reduced.

  As described above, according to the present invention, in a plurality of memory mats, a refresh operation is intensively performed in one memory mat, and a circuit operation is selectively unnecessary during a refresh period. Since the circuit operation is stopped, the current consumption in the data holding mode can be greatly reduced, and a large capacity DRAM with a reduced data holding current can be realized.

  The present invention can be applied to a semiconductor memory device that internally reduces an external power supply voltage to generate an internal power supply potential. In particular, when applied to a dynamic semiconductor memory device, it can be stably operated with a low current consumption even in the data holding mode.

It is a figure for demonstrating the operation principle of DRAM of Embodiment 1 of this invention. 1 schematically shows a configuration of a main part of a DRAM according to a first embodiment of the invention. FIG. FIG. 7 is a waveform diagram showing an operation of the DRAM in the first embodiment of the present invention. It is a figure which shows assignment of the address signal of the subarray in one memory mat of DRAM in Embodiment 1 of this invention. It is a figure which shows the structure of the address signal generation part at the time of refresh in Embodiment 1 of this invention. FIG. 6 is a diagram illustrating an example of a configuration of a row address buffer illustrated in FIG. 5. FIG. 7 is a diagram for explaining how the address buffer activation signal shown in FIG. 6 is generated. FIG. 6 schematically shows a configuration of an array decoder included in the array control circuit shown in FIG. 5. FIG. 3 schematically shows a configuration of a unit decode circuit included in the row decoder shown in FIG. 2. FIG. 6 is a diagram showing a configuration of a modified example of the first embodiment. It is a figure which shows the structure of the part which implement | achieves the address translation shown in FIG. It is a figure which shows the specific structure of the scrambler of FIG. (A) shows a configuration of a sense amplifier driving portion of the DRAM according to the first embodiment of the present invention, and (B) shows this operation waveform. FIG. 5 schematically shows a configuration of an internal RAS signal generation unit of a DRAM according to the first embodiment of the present invention. It is a figure which shows roughly the principle of operation of DRAM in Embodiment 2 of this invention. (A) shows the configuration of the internal step-down circuit shown in FIG. 15, and (B) is a waveform diagram showing the operation of the internal step-down circuit. It is a figure which shows roughly the structure of the power supply part for the operating speed fall of DRAM in Embodiment 2 of this invention. It is a figure which shows an example of the input buffer circuit used for DRAM according to Embodiment 3 of this invention. (A) shows a configuration of an input buffer circuit according to the third embodiment of the present invention, and (B) shows a logic gate thereof. (A) shows the configuration of the part that generates the power cut designation signal shown in FIG. 19 (A), and (B) shows the operation waveform. (A) shows the structure of the modification of Embodiment 3 of this invention, (B) is a figure which shows the operation | movement waveform. FIG. 14 schematically shows a structure of a main portion of a DRAM according to the fourth embodiment of the invention. (A) shows the timing of the control signal for driving the row address buffer shown in FIG. 22, and (B) is a waveform diagram showing the operation of the fourth embodiment of the present invention. It is a figure for demonstrating the burst refresh operation mode in Embodiment 5 of this invention. It is a figure which shows roughly the structure of the principal part of DRAM in Embodiment 5 of this invention. (A) shows the structure of the part which controls the refresh operation in Embodiment 5 of this invention, (B) is a figure which shows the operation | movement waveform. FIG. 27 is a diagram illustrating an example of a configuration of a block decoder illustrated in FIG. 26. FIG. 27 is a diagram showing a configuration of a modified example of the block decoder shown in FIG. 26. FIG. 27 is a diagram illustrating an example of a configuration of a separation control circuit illustrated in FIG. 26. It is a figure which shows the structure of the example of a change of Embodiment 5 of this invention. (A) shows a configuration of a main part of a DRAM according to the sixth embodiment of the present invention, and (B) shows an operation waveform thereof. (A) shows a configuration of a main part of a DRAM according to the sixth embodiment of the present invention, and (B) is a waveform diagram showing its operation. FIG. 33 is a diagram showing a specific configuration of the DRAM shown in FIG. 32. It is a figure for demonstrating the effect of Embodiment 6 of this invention. (A) is a figure which shows roughly the structure of the part which generate | occur | produces the pause period designation | designated signal used in Embodiment 6 of this invention, (B) is a figure which shows the operation | movement waveform. (A) schematically shows an overall configuration of a DRAM according to the seventh embodiment of the present invention, and (B) schematically shows a configuration of one memory map of the DRAM shown in (A). . FIG. 37 is a diagram schematically showing a configuration of a main part in one subarray shown in FIG. (A) shows a configuration of a portion for generating an array group designation signal used in Embodiment 7 of the present invention, and (B) is a diagram showing an operation waveform thereof. The structure of the modification 1 of Embodiment 7 of this invention is shown, (B) is a figure which shows the operation | movement waveform. It is a figure which shows the structure of the modification 2 of Embodiment 7 of this invention. It is a figure which shows the structure and operating waveform of the principal part of Embodiment 8 of this invention.

Explanation of symbols

  1 DRAM, 4 refresh detection circuit, 6 refresh control circuit, 8 timer, 10 refresh counter, 12 array control circuit, 14 multiplexer, 16 row address buffer, 19 scrambler MM # 0 to MM # 3 memory mat, MA # 0 to MA # 0 MA # 3 memory array, RD0 to RD3 row decoder, MB # 0 to MB # 7 subarray, 20 sense amplifiers, 27a, 27b, 28a, 28b sense amplifier activation transistors, 22a, 22b sense amplifier drive transistors, 24 sense activations Circuit, 26a, 26b AND circuit, VDC internal step-down circuit, 41 internal power supply line, 46a, 46b current control transistor, 50, 50a, 50b, 50c input buffer circuit, 55 buffer circuit, 59 AND circuit, 58 minutes Peripheral unit, 62 row address buffer control circuit, ICL isolation control circuit, MBL, MBR memory block, IGL, IGR bit line isolation control gate, 70 refresh control unit, 72 pause timer, 74 counter, 76 block decoder, SBS block selection circuit RDx row decode circuit, MWL0 to MWLn main word line, SWL00 to SWLn1 sub word line, 82 peripheral circuit, 84 memory array, 86 intermediate voltage generation circuit, 83 equalize control circuit, 85 X decoder, 87 sense control circuit, 81a, 81b Switching element for current control, 92 internal high voltage generation circuit, 94a to 94d, 94 switching element, 95a to 95d, 95 main internal high voltage line, 96a to 96d Vpp switch, 95aa, 95ab, 95 ia, 95ib Local internal high voltage line, WD0 to WDn word line driver, MBL, / MBL main bit line, BSL1, / BSL1, BSL2, / BSL2 sub bit line, 102 block selection circuit.

Claims (2)

A semiconductor memory device including a plurality of memory mats each including a memory cell array having a configuration in which memory cells are arranged in a matrix,
Data access is performed from the outside of the semiconductor memory device, the first operation mode in which the first operating current flows, and data access is not performed from the outside of the semiconductor memory device, the stored data of the memory cell is refreshed, and the first A second operating mode in which a second operating current less than the operating current of 1 flows,
Each of the memory mats is provided with an internal power supply potential obtained by lowering the power supply potential applied from the outside of the semiconductor memory device to the corresponding memory mat, and activated by a memory mat designation signal for designating the memory mat. A semiconductor memory device comprising an internal step-down means for supplying a current by reducing the amount of current flowing from a power supply external to the semiconductor memory device to a corresponding memory mat in the second operation mode as compared to the first operation mode. A plurality of memory mats each including a memory cell array having a configuration in which memory cells are arranged in a matrix;
The normal operation mode in which the data access from the outside of the semiconductor memory device is performed and the first operating current flows, and the data stored in the memory cell is refreshed without the data access from the outside of the semiconductor memory device. A data holding mode in which a second operating current smaller than the operating current of 1 flows.
Provided in each of the memory mats, an internal power supply potential obtained by lowering the power supply potential applied from the outside of the semiconductor memory device is applied to the corresponding memory mat, and activated by a memory mat designating signal designating the memory mat, and the normal operation A dynamic semiconductor memory device comprising an internal step-down means for supplying a current by reducing the amount of current flowing from a power supply external to the semiconductor memory device to a corresponding memory mat in the data holding operation mode as compared to the mode.

Images