JP2005316108A - Flat panel display device and display control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a drive circuit and a flat panel display device which can always display high quality images without decreasing the gradations of the image signals even when lowering the whole luminance of a pattern having large high luminance areas. <P>SOLUTION: The PWM circuit 23 outputs pulse signals of a pulse width following the clock pulses of a clock generater circuit 6 when the ABL circuit 5 is not operating. When the ABL circuit 5 is operating, it outputs the pulse signals of a pulse width following the clock pulses from the variable clock frequency circuit 7 making the frequency high responding to the adjustment. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a flat display device and a display control circuit for a display device such as a field emission display (FED) in which a plurality of display pixels are configured by using, for example, surface conduction electron-emitting devices.

  The FED generally includes a display panel and a drive circuit that drives the display panel. The display panel includes a plurality of scanning lines arranged in the horizontal (horizontal) direction, a plurality of signal lines arranged in the vertical (vertical) direction intersecting with the scanning lines, and intersections of the scanning lines and the signal lines. A plurality of display pixels are arranged. In a display panel for color display, for example, three display pixels adjacent in the horizontal direction are used as color display pixels. Each display pixel includes a surface conduction electron-emitting device and a red (R), green (G), or blue (B) phosphor that emits light by an electron beam emitted from the electron-emitting device.

  The drive circuit includes a Y driver connected to one end of the plurality of scanning lines and an X driver connected to one end of the plurality of signal lines. The Y driver sequentially drives a plurality of scanning lines using the scanning signal, and the X driver drives the plurality of signal lines by a driving signal having a pulse width corresponding to the gradation level of the video signal while each scanning line is driven. To do. Each display pixel emits light with a luminance corresponding to the pixel voltage between the corresponding signal line and the corresponding scanning line.

  The X driver is provided with a line memory for buffering the input video signal and a pulse width corresponding to the gradation level of the video signal buffered and stored in the line memory. A pulse width modulation (PWM) circuit that generates a signal, an output buffer amplifier that amplifies the pulse signal generated by the PWM circuit, and outputs a drive signal (Vref) to the corresponding signal line by the pulse width of the pulse signal; Is provided.

  The video processing circuit for driving and controlling the X driver includes a clock generation circuit that supplies an operation clock to each PWM circuit, an APL detection circuit that detects an average of video signal levels for each frame, and a high luminance portion. An ABL circuit is provided which lowers the video signal input to the PWM circuit in advance according to the output value of the APL detection circuit and reduces the overall luminance for a pattern having a large area.

  One PWM circuit is provided for each pixel in the horizontal line, and the video data input to the line memory is pulse-modulated for each pixel based on the clock signal generated by the clock generation circuit. A signal with a pulse width proportional to the video signal level is output.

  During a period in which pulses corresponding to these video signals are output to each signal line via the output buffer amplifier, a plurality of negative pulses (Vyon) output from the Y driver are arranged in a horizontal row (for example, 3072). The amplitude of Vref + Vyon is added to the surface conduction electron-emitting devices by the length corresponding to the brightness of the image, and light is emitted for that time. As a result, an image for one horizontal scan is displayed.

  The ABL circuit performs luminance adjustment control for lowering the overall luminance by reducing the video signal input to the PWM circuit in advance according to the output value of the APL detection circuit for the pattern having a large area of the high luminance portion.

  Although the video signal can be displayed with brightness in proportion to the pulse width by the above configuration and operation, there has been the following problem in the past.

The ABL circuit performs adjustment (brightness correction) to lower the brightness of the entire screen by processing the video signal and lowering the level in the brightness reduction control. Therefore, when the ABL circuit performs adjustment control for reducing the luminance, there arises a problem that the gradation of the video signal is reduced. This is because the gray level decreases as the luminance adjustment amount of the ABL circuit increases. As a simple specific example, when the resolution of the video signal is, for example, 4 bits (16 gradations) (actually about 8 to 10 bits), when the brightness is adjusted (limited) to half by the ABL circuit, the 0th gradation is obtained. The level of “0” is “0” for the first gradation, the level “1” is “0.5” for the first gradation, the level “2” is “1” for the second gradation, and the third gradation The level of “3” is “1.5”, and the level of the 15th gradation is half the level of “15” to “7.5”. This circuit operation is performed by digital processing. Therefore, the decimal part is rounded down. Therefore, for each gradation, the level of the 0th gradation is “0”, the level of the 1st gradation is “0”, the level of the 2nd gradation is “1”, and the level of the 3rd gradation is also “1”. ,..., The level of the 15th gradation is “7”, and the odd gradation is the same as the level of the even gradation immediately before, and as a result, the gradation is reduced by half ( (Refer FIG.3 (b)). In the above example, the case where the luminance is halved has been described. However, when the luminance is further reduced (limited), the gradation is further reduced. Therefore, for example, when a video signal having a resolution of 10 bits (1024 gradations) is input, the gradation is reduced in the same manner as described above, resulting in a problem that gradation display with the original resolution is impaired.
JP 2002-221933 A

  As described above, conventionally, when adjustment is performed to lower the overall luminance of a pattern having a large area of a high luminance portion, there is a problem that the gradation of the video signal is reduced according to the adjustment.

  The present invention has been made in view of the above circumstances, and even when adjustment is performed to reduce the overall luminance of a pattern having a large area of a high luminance portion, a high quality image is always obtained without reducing the gradation of the video signal. An object is to provide a flat display device and a display control circuit capable of displaying.

  According to the present invention, a plurality of scanning lines, a plurality of signal lines intersecting with the plurality of scanning lines, a plurality of scanning lines and a plurality of signal lines are disposed at intersections of the plurality of scanning lines and the plurality of signal lines, respectively. A plurality of display pixels driven in response to a voltage between the signal lines, a scanning line driver for sequentially driving the plurality of scanning lines, and each of the plurality of scanning lines being driven by the scanning line driver. A signal line driver that drives the plurality of signal lines with a drive signal having a pulse width corresponding to a gradation level of the video signal, a detection circuit that detects an average gradation level of the video signal, and the plurality of signal lines And a control circuit that uniformly adjusts the pulse width of the drive signal obtained from the signal line driver based on the average gray level of the video signal.

  According to the present invention, a plurality of scanning lines, a plurality of signal lines intersecting with the plurality of scanning lines, a plurality of scanning lines and a plurality of signal lines are disposed at intersections of the plurality of scanning lines and the plurality of signal lines, respectively. A plurality of display pixels driven in response to a voltage between the signal lines, a scanning line driver for sequentially driving the plurality of scanning lines, and each of the plurality of scanning lines being driven by the scanning line driver. A display control circuit of a flat panel display device comprising a signal line driver for driving the plurality of signal lines by a drive signal having a pulse width corresponding to a gradation level of a video signal, and detecting an average gradation level of the video signal And a control circuit that uniformly adjusts the pulse width of the drive signal obtained from the signal line driver for the plurality of signal lines based on the average gradation level of the video signal. There is provided.

  Even when adjustment is performed to reduce the overall luminance of a pattern having a large area of high luminance portions, a high quality image can always be displayed without reducing the gradation of the video signal.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows a configuration of a flat display device and a display control circuit thereof according to an embodiment of the present invention. In this embodiment, for example, a field emission display (FED) device having a 720P high-vision XGA resolution in which the number of color display pixels is horizontal: vertical = 1280: 720 is taken as an example of the flat display device.

  In FIG. 1, the flat display device includes a display panel 1, an X driver 2, a Y driver 3, and a control circuit (4 to 7) that controls driving of the X driver 2.

Among these components, the display panel 1 constitutes a flat type display panel in which surface conduction type emission elements are arranged in a matrix, and a plurality of scanning lines 11, 11,. A plurality of signal lines 12, 12,..., 12 arranged in the vertical direction intersecting the scanning lines 11, 11,..., 11 and the scanning lines 11, 11,. .., 13 are arranged at a crossing position with 12, 12,..., 12 (matrix arrangement).

  For example, in the case of XGA resolution in a personal computer, 768 scanning lines 11, 11,. In addition, in the case of the XGA resolution, a total of 3072 signal lines 12, 12,..., 12 of 1024 × 3 times (R, G, B) are required. Here, the scanning lines 11, 11,..., 11 are m, and the signal lines 12, 12,.

  The surface conduction electron-emitting devices 13, 13,... 13 excite phosphors when the potentials applied to the signal lines 12, 12,. And emits light. Color display is possible by arranging red, green, and blue (R, G, B) phosphors alternately. In the figure, i is a discharge current that flows when the surface conduction electron-emitting device 13 is discharged, Vy is an output voltage of the Y driver 3 applied to the surface conduction electron-emitting device 13, and z is a distribution of line capacitance and resistance. It is a constant.

  The X driver 2 includes a line memory 21, PWM circuits 23, 23,... 23 and output buffer amplifiers (AMP) 24, 24,. 24.

  The line memory 21 samples and holds a video signal input from the outside as display information in units of horizontal lines in synchronization with the horizontal synchronization signal HD.

  The PWM circuits 23, 23,..., 23 are gradations of video signals of corresponding pixels held in the line memory 21 based on operation clock pulses input via the clock frequency variable circuit 7 described later. Generate and output a pulse signal with a pulse width according to the level.

  The output buffer amplifiers 24, 24,..., 24 receive the voltage Vref supplied to the drive reference voltage terminal for the period equal to the pulse width of the pulse signal from the corresponding PWM circuit 23, 23,. 12,..., 12 are output as drive signals.

The Y driver 3 includes a shift register 31 and output buffer amplifiers (AMP) 32, 32,.
The shift register 31 shifts the vertical synchronization signal VD every horizontal scanning period, and sequentially outputs scanning signals from one of the m output terminals. The output buffer amplifiers (AMP) 32, 32,..., 32 respond to the negative scanning signal Vy by one horizontal scanning period in response to pulses output as scanning signals from the m output terminals of the shift register 31, respectively. To the scanning line 11 to be output.

  The control circuit that drives and controls the X driver 2 includes an APL detection circuit (average detection circuit) 4, an ABL circuit (adjustment circuit) 5, a clock generation circuit 6, and a clock frequency variable circuit 7.

The APL detection circuit 4 adds up the levels of RGB video signals for one frame, for example, and detects the average level.
The ABL circuit 5 controls the clock frequency variable circuit 7 when the average level detected by the APL detection circuit 4 exceeds a predetermined value, and the pulse of the pulse signal generated by the PWM circuits 23, 23,. The frequency of clock pulses supplied to the PWM circuits 23, 23,..., 23 is controlled so as to narrow the width, and brightness adjustment is performed to uniformly reduce the brightness of an image pattern having a large area of high brightness.

  The clock generation circuit 6 generates an operation clock pulse having a constant frequency that serves as a reference for pulse width control of the PWM circuits 23, 23,. This clock generation circuit 6 is a pulse that allows the PWM circuits 23, 23,..., 23 to express gradation according to a predetermined resolution with a pulse width within a range not exceeding one horizontal period as the maximum value of the video signal level. Generate a constant frequency clock pulse as a PWM operation clock pulse so that a pulse signal with a width (for example, the pulse width of a value obtained by dividing one horizontal display period by 1023 if the maximum value is 1023) is obtained. And output.

  The clock frequency variable circuit 7 follows the luminance adjustment operation of the ABL circuit 5 when the average level exceeds a predetermined value, so as to narrow the pulse width of the pulse signal generated by the PWM circuits 23, 23,. The frequency of the clock pulse output from the generation circuit 6 is converted and supplied to the PWM circuits 23, 23,.

  FIG. 2 is a time chart of each part in one horizontal scanning period for explaining the operations of the clock frequency variable circuit 7 and the PWM circuit 23. FIG. 2A shows the horizontal synchronization signal HD supplied to the line memory 21 of the X driver 2. FIG. 2B shows the operation clock pulse CLK supplied to the PWM circuit 23 and the operation clock pulse when the ABL circuit 5 is not adjusted to reduce the luminance (when the ABL circuit 5 is not operating). The pulse width of the pulse signal at each video signal level output from the PWM circuit 23 based on CLK is shown. Here, a pulse signal having a pulse width corresponding to each CLK when the video signal level is 1, 2, n, 1023 (= maximum value) is shown. FIG. 2C shows an operation clock pulse CLK supplied to the PWM circuit 23 and its operation clock pulse CLK when the ABL circuit 5 performs adjustment to reduce the luminance (when the ABL circuit 5 is operating). The pulse widths of the pulse signals at various video signal levels (1, 2, n, 1023) output from the PWM circuit 23 based on FIG.

The clock frequency variable circuit 7 does not frequency-convert the clock pulse output from the clock generation circuit 6 when the ABL circuit 5 is not adjusted to reduce the brightness (when the ABL circuit 5 is not operating). Output. The operation clock pulse CLK supplied to the PWM circuit 23 at this time is shown in FIG. At this time, the PWM circuit 23 has a pulse width corresponding to one cycle of the operation clock pulse CLK when the video signal level is “1” based on the operation clock pulse CLK shown in FIG. A pulse signal having a Vref potential is output. When the video signal level is “2”, a pulse signal having a Vref potential having a pulse width corresponding to two cycles of the operation clock pulse CLK is output. When the video signal level is “n”, the operation clock pulse is output. When a pulse signal of Vref potential having a pulse width corresponding to n cycles of CLK is output and the video signal level is “1023” (= maximum value), Vref having a pulse width corresponding to 1023 cycles of the operation clock pulse CLK. A potential pulse signal is output.

  The clock frequency variable circuit 7 adjusts the clock pulse output from the clock generation circuit 6 when the ABL circuit 5 performs adjustment to reduce the luminance (when the ABL circuit 5 is operating). Depending on the frequency, the frequency is converted so that the frequency becomes higher and output. The operation clock pulse CLK supplied to the PWM circuit 23 at this time is shown in FIG. At this time, the PWM circuit 23 has a pulse width corresponding to one cycle of the operation clock pulse CLK when the video signal level is “1” based on the operation clock pulse CLK shown in FIG. A pulse signal of Vref potential is output. When the video signal level is “2”, a pulse signal having a Vref potential having a pulse width corresponding to two cycles of the operation clock pulse CLK is output. When the video signal level is “n”, the operation clock pulse is output. When a pulse signal of Vref potential having a pulse width of n cycles of CLK is output and the video signal level is “1023 (= maximum value)”, Vref having a pulse width of 1023 cycles of the operation clock pulse CLK. A potential pulse signal is output.

  As described above, the clock frequency variable circuit 7 does not frequency-convert the clock pulse output from the clock generation circuit 6 when the ABL circuit 5 is not adjusted to reduce the luminance (when the ABL circuit 5 is not operating). When the ABL circuit 5 is performing adjustment to reduce the luminance (when the ABL circuit 5 is operating), the frequency of the clock pulse output from the clock generation circuit 6 is increased according to the adjusted correction amount. The frequency is converted so that As a result, when the ABL circuit 5 is not operating, the PWM circuits 23, 23,..., 23 receive a pulse signal having a pulse width according to the clock pulse of the clock generation circuit 6, as shown in FIG. When output and the ABL circuit 5 is operating, as shown in FIG. 2C, the pulse width according to the clock pulse from the clock frequency variable circuit 7 whose frequency is increased according to the correction amount adjusted by the ABL circuit 5 The pulse signal is output. Therefore, when the ABL circuit 5 is performing adjustment to reduce the luminance (when the luminance is reduced), when the ABL circuit 5 is not performing adjustment to reduce the luminance (when the luminance is not reduced). Similar gradation display can be maintained. Thereby, it is possible to limit the luminance by the ABL circuit 5 while maintaining the gradation display according to the predetermined resolution of the video signal.

  FIG. 3 shows gradation control in the configuration having the clock frequency variable function of the PWM circuit in the above embodiment in contrast to the gradation control in the configuration not having the clock frequency variable function. FIG. 3A shows the output pulse width of the X driver 2 accompanying the change in level (0, 1, 2,...) Of the video signal when the ABL circuit 5 is not operating. FIG. 3B shows the output pulse width of the X driver 2 accompanying the change in level (0, 1, 2,...) Of the video signal during the operation of the ABL circuit 5 when the clock frequency variable function is not provided. Yes. At this time, as described above, the gradation decreases as the correction amount by adjustment of the ABL circuit 5 increases. FIG. 3C shows the output pulse width of the X driver 2 in accordance with the level change (0, 1, 2,...) Of the video signal during the operation of the ABL circuit 5 when the clock frequency variable function is activated. . In this case, the number of gradations does not change only by changing the variable amount at each level with respect to the video signal level shown in FIG. Therefore, the luminance can be lowered by the operation of the ABL circuit 5 without reducing the gradation determined by the resolution, and high-quality screen control is possible.

  In the above-described embodiment, the APL detection circuit 4 detects the average level of the video signal for each frame, the ABL circuit 5 adjusts the video signal level based on the detection level, and the clock frequency variable circuit 7 Although the clock frequency supplied to the PWM circuits 23, 23,..., 23 is variably controlled according to the adjustment, for example, based on the level of the video signal for a plurality of frames, a predetermined line, a predetermined number of pixels, and the like. The configuration may be such that the frequency of the clock pulse supplied to the PWM circuits 23, 23,.

1 is a block diagram illustrating a configuration of a drive circuit of a display device and a flat display device according to an embodiment of the present invention. The time chart for demonstrating operation | movement of the principal part which concerns on embodiment of this invention. The figure which shows the gradation control which concerns on embodiment of this invention in contrast with the gradation control in case it does not have a clock frequency variable function.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Display panel, 2 ... X driver, 3 ... Y driver, 4 ... APL detection circuit (average detection circuit), 5 ... ABL circuit (adjustment circuit), 6 ... Clock generation circuit, 7 ... Clock frequency variable circuit, 11 ... Scan lines, 12 signal lines, 13 surface conduction electron-emitting devices, 21 line memories, 23 PWM circuits, 24 output buffer amplifiers (AMP), 31 shift registers, 32 output buffer amplifiers (AMP).

Claims (10)

  A plurality of scanning lines, a plurality of signal lines intersecting with the plurality of scanning lines, and arranged at positions where the plurality of scanning lines and the plurality of signal lines intersect with each other. A plurality of display pixels that are driven correspondingly, a scanning line driver that sequentially drives the plurality of scanning lines, and a gradation level of a video signal while each of the plurality of scanning lines is driven by the scanning line driver A signal line driver that drives the plurality of signal lines with a drive signal having a pulse width corresponding to the detection signal, a detection circuit that detects an average gradation level of the video signal, and the signal line driver for the plurality of signal lines. A flat display device comprising: a control circuit that uniformly adjusts a pulse width of the obtained drive signal based on an average gradation level of the video signal.   2. The control circuit includes clock frequency variable control means for adjusting a pulse width of the drive signal by converting a frequency of a clock pulse for generating the drive signal based on an average gradation level of the video signal. The flat display device described.   3. The flat display device according to claim 1, wherein the control circuit includes means for narrowing a pulse width of the drive signal at a certain rate when an average gradation level of the video signal exceeds a predetermined value.   4. The flat display device according to claim 1, wherein the detection circuit is configured to detect an average level of a video signal for a predetermined frame.   4. The flat display device according to claim 1, wherein the detection circuit is configured to detect an average level of video signals for a predetermined line.   4. The flat display device according to claim 1, wherein the detection circuit is configured to detect a level of a video signal for a predetermined number of pixels.   4. The flat display device according to claim 1, wherein the detection circuit is configured to detect an average level of a video signal with respect to display pixels corresponding to a predetermined area of the screen. A plurality of scanning lines, a plurality of signal lines intersecting with the plurality of scanning lines, and arranged at positions where the plurality of scanning lines and the plurality of signal lines intersect with each other. A plurality of display pixels that are driven correspondingly, a scanning line driver that sequentially drives the plurality of scanning lines, and a gradation level of a video signal while each of the plurality of scanning lines is driven by the scanning line driver A display control circuit of a flat panel display device including a signal line driver that drives the plurality of signal lines by a drive signal having a pulse width corresponding to the detection circuit, and a detection circuit that detects an average gradation level of the video signal; And a control circuit that uniformly adjusts a pulse width of a drive signal obtained from the signal line driver for a plurality of signal lines based on an average gray level of the video signal. .   9. The display according to claim 8, wherein the control circuit includes a circuit that variably controls a clock pulse for generating the drive signal based on an average gradation level of the video signal to adjust a pulse width of the drive signal. Control circuit.   10. The display control circuit according to claim 8, wherein the control circuit includes means for narrowing a pulse width of the drive signal at a certain rate when an average gradation level of the video signal exceeds a predetermined value.

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