JP2005150877A - Mos type solid state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that reduction in a chip area has a limit in the problem of a pad area and a circuit scale even if an arrangement for externally inputting the driving pulse of a vertical select circuit or an internal generation circuit is mounted. <P>SOLUTION: The MOS type solid state imaging device comprises a dummy counter circuit 5 being driven by a horizontal select circuit driving pulse and beginning to operate upon receiving the final output from the horizontal select circuit 3, and a pulse generation circuit 6 for generating vertical select circuit driving pulse using the output from the dummy counter circuit 5. The dummy counter circuit 5 and the pulse generating circuit 6 can be realized by a small scale circuit and the cost can be reduced by reducing the chip area for the solid state imaging device mounting a conventional internal generation circuit. Since a solid state imaging device having a small number of terminals can be fabricated, it contributes to reduction in size of a camera set. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device using an amplification type MOS sensor that amplifies signal charges in a cell.

  FIG. 4 is a schematic configuration diagram of the MOS type solid-state imaging device of the first conventional example.

  This solid-state imaging device includes a photosensitive region 10 in which pixel units 1 as unit pixels are arranged two-dimensionally in rows and columns, a vertical selection circuit unit 2 that selects a vertical row of the photosensitive region 10, and a horizontal direction. And a horizontal selection circuit unit 3 for selecting the column, and an output amplifier 4 for amplifying or impedance-converting and outputting the signal of the pixel unit 1 selected by the vertical selection circuit unit 2 and the horizontal selection circuit unit 3. is there. In this configuration, as a method of selecting a column and a row in order to read out each pixel signal, first, the vertical selection circuit V1 is selected, and in that state, the horizontal selection circuits H1 to Hn are scanned and selected to complete the selection of one row. . Similarly, all columns and all pixels can be selected by performing scanning selection in the vertical direction from the vertical selection circuits V2 to Vm.

  However, for example, in order to drive the vertical selection circuit unit 2, it is necessary to input a pulse from the outside, and it occupies a wide area including the input terminal. Further, although not shown in FIG. 4, the pixel portion driving pulses include a signal readout pulse, a reset pulse, an electronic shutter vertical selection circuit driving pulse, an electronic shutter signal readout pulse, and an electronic shutter reset pulse. Etc. are required. These also occupy a large area including the input terminals. In addition, an external circuit for generating the pulse group is required, and the combined area of the chips is 1.5 times or more the chip area of the solid-state imaging device.

  FIG. 5 is a schematic configuration diagram of a MOS type solid-state imaging device of a second conventional example.

In this figure, the basic operation is the same as in FIG. 4, but an internal generation circuit 7 is provided to internally generate the pulse group. Usually, to generate these pulses, a logic circuit having a large circuit scale is required. This occupies a large area, and the chip area is about 1.3 times that of a solid-state imaging device with external input.
Japanese Patent Laid-Open No. 9-93498

  As shown in FIG. 4, in the configuration in which a pulse group necessary for scanning the pixel portion is input from the outside or the configuration in which the internal generation circuit 7 is mounted as in FIG. 5, there is a limit to reducing the chip area. there were.

  An object of the present invention is to provide a MOS type solid-state imaging device capable of reducing the chip area.

  A first MOS type solid-state imaging device according to the present invention includes a photosensitive region in which amplification type unit pixels for amplifying an electric signal obtained by photoelectric conversion of incident light are arranged two-dimensionally in rows and columns, and a vertical selection circuit drive. A MOS type solid-state imaging device comprising: a vertical selection circuit unit that selects a row of unit pixels based on a pulse; and a horizontal selection circuit unit that selects a column of unit pixels based on a horizontal selection circuit drive pulse. A dummy counter circuit that is driven by a selection circuit drive pulse and starts to operate with the final output of the horizontal selection circuit unit as an input, and a pulse generation circuit that generates a pulse using the output of the dummy counter circuit are provided.

  The second MOS type solid-state imaging device of the present invention is characterized in that, in the first MOS type solid-state imaging device, the pulse generated by the pulse generation circuit is a vertical selection circuit driving pulse.

  The third MOS type solid-state imaging device of the present invention is characterized in that, in the first MOS type solid-state imaging device, the unit circuit of the dummy counter circuit has the same configuration as the horizontal selection circuit unit.

  According to the configuration of the first to third MOS solid-state imaging devices described above, the output of the dummy counter circuit is synchronized with the horizontal selection circuit drive pulse and is delayed in time with respect to the final output of the horizontal selection circuit unit. It becomes. Since the dummy counter circuit does not limit the number of stages, the output of the dummy counter may be used according to the timing of the pulse desired to be generated by the pulse generation circuit. In this case, it is possible to generate a necessary pixel portion pulse such as a vertical selection circuit drive pulse within the horizontal blanking period. By providing the dummy counter circuit and the pulse generation circuit in this manner, the pulse input terminal can be omitted by internally generating a pulse that has been externally applied. Further, since the dummy counter circuit and the pulse generation circuit do not require a logic circuit that delays in time unlike the conventional internal generation circuit, the circuit scale is small and the chip area can be reduced.

  The fourth MOS type solid-state imaging device of the present invention comprises a photosensitive region in which amplification type unit pixels for amplifying an electric signal obtained by photoelectric conversion of incident light are arranged in a two-dimensional array of rows and columns, and a vertical selection circuit drive. A MOS-type solid-state imaging device including a vertical selection circuit unit that selects a row of unit pixels based on a pulse and a horizontal selection circuit unit that selects a column of unit pixels based on a horizontal selection circuit drive pulse. A dummy counter circuit that is driven by a selection circuit drive pulse and starts to operate with the final output of the vertical selection circuit unit as an input, and a pulse generation circuit that generates a pulse using the output of the dummy counter circuit are provided.

  The fifth MOS type solid-state imaging device of the present invention is characterized in that, in the fourth MOS type solid-state imaging device of the present invention, the unit circuit of the dummy counter circuit has the same configuration as the vertical selection circuit unit.

  According to the configuration of the fourth and fifth MOS type solid-state imaging devices described above, the output of the dummy counter circuit is synchronized with the vertical selection circuit drive pulse and is delayed with respect to the final output of the vertical selection circuit unit. It becomes. Since the dummy counter circuit does not limit the number of stages, the output of the dummy counter may be used according to the timing of the pulse desired to be generated by the pulse generation circuit. In this case, it is possible to generate a necessary pixel portion pulse within the vertical blanking period. By providing the dummy counter circuit and the pulse generation circuit in this manner, the pulse input terminal can be omitted by internally generating a pulse that has been externally applied. Further, since the dummy counter circuit and the pulse generation circuit have a configuration that does not require a logic circuit that delays in time like the conventional internal generation circuit, the circuit scale is small and the chip area can be reduced.

  The sixth MOS type solid-state imaging device of the present invention is a unit based on a photosensitive region in which amplification type unit pixels for amplifying an electric signal obtained by photoelectric conversion of incident light are arranged one-dimensionally, and a selection circuit driving pulse. A MOS type solid-state imaging device including a selection circuit unit for selecting a pixel, which is driven by a selection circuit drive pulse and receives a final output of the selection circuit unit as an input and starts operating, and an output of the dummy counter circuit And a pulse generation circuit for generating a pulse using the same.

  The seventh MOS type solid-state imaging device of the present invention is characterized in that, in the sixth MOS type solid-state imaging device, the unit circuit of the dummy counter circuit has the same configuration as the selection circuit unit.

  According to the configuration of the sixth and seventh MOS type solid-state imaging devices described above, the output of the dummy counter circuit is synchronized with the selection circuit drive pulse and delayed in time with respect to the final output of the selection circuit unit. . Since the dummy counter circuit does not limit the number of stages, the output of the dummy counter may be used according to the timing of the pulse desired to be generated by the pulse generation circuit. By providing the dummy counter circuit and the pulse generation circuit in this manner, the pulse input terminal can be omitted by internally generating a pulse that has been externally applied. Further, since the dummy counter circuit and the pulse generation circuit have a configuration that does not require a logic circuit that delays in time like the conventional internal generation circuit, the circuit scale is small and the chip area can be reduced.

  As described above, according to the present invention, since the dummy counter circuit and the pulse generation circuit can be realized with a small-scale circuit and necessary pulses can be generated internally, the solid-state imaging device equipped with the conventional internal generation circuit can be used. The cost can be reduced by reducing the chip area. In addition, since a solid-state imaging device with a small number of terminals can be manufactured, the connection area can be reduced by flip-chip mounting, which is currently the mainstream, which contributes to miniaturization of the camera set. Furthermore, since an external pulse generation circuit is not required, the size of the timing generation LSI can be reduced to reduce the size of the camera set, which is advantageous in terms of cost and size reduction of the camera set.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a schematic circuit diagram of the MOS type solid-state imaging device according to the present embodiment. As shown in FIG. 1, this solid-state imaging device includes a photosensitive region 10 in which pixel units 1 as unit pixels are arranged in a two-dimensional array of rows and columns on a semiconductor substrate, as in the conventional example. Each pixel unit 1 includes a light receiving unit that receives light and performs photoelectric conversion, a floating diffusion unit that converts a signal charge generated by the light receiving unit as a voltage, and an amplification transistor that amplifies a voltage change of the floating diffusion unit. ing. Then, the vertical selection circuit unit 2 that selects the vertical row of the photosensitive area 10, the horizontal selection circuit unit 3 that selects the horizontal column, the vertical selection circuit unit 2, and the horizontal selection circuit unit 3 select the row. It has a structure having an output amplifier 4 that amplifies or impedance-converts the signal of the pixel unit 1 and outputs it.

  Furthermore, in the present embodiment, the dummy counter circuit 5 is configured by extending the horizontal selection circuit unit 3 by the horizontal blanking period. That is, the circuits D1, D2,..., Dl of the dummy counter circuit 5 have the same configuration as the circuits H1, H2,. The horizontal selection circuit unit 3 and the dummy counter circuit 5 can be composed of only nMOS transistors. Further, in order to generate a pulse necessary for driving the vertical selection circuit unit 2, a pulse generation circuit 6 for vertical selection circuit is provided. The input to the vertical selection circuit pulse generation circuit 6 is realized by extracting the timing necessary for driving the vertical selection circuit unit 2 from the dummy counter circuit 5. The vertical selection circuit unit 2 can be driven by inputting the output from the vertical selection circuit pulse generation circuit 6 to the vertical selection circuit unit 2.

  Next, the operation of this embodiment will be described with reference to FIG. FIG. 2 is a timing chart showing an operation in the embodiment of the present invention.

  The horizontal selection circuit unit 3 performs scanning by sequentially shifting the column selection portion by inputting horizontal selection circuit scanning pulses φHA, φHB, and φHC. In FIG. 2, for simplification, one of φHA, φHB, and φHC is shown. On the other hand, since the dummy counter circuit 5 has the same configuration as that of the horizontal selection circuit unit 3, when the selection of each column of the photosensitive area 10 is completed, the dummy counter is operated as it is and scanning continues at the same timing. However, the dummy counter circuit 5 does not select the photosensitive area 10 and enters the feeding state. This portion is used as a horizontal blanking period (no signal period). The pulses necessary for the operation of the vertical selection circuit unit 2 only have to be input using this period. Therefore, if a pulse can be generated using the outputs D1out to Dlout from the dummy counter circuit 5, it can be used as an operation pulse of the vertical selection circuit unit 2. This is realized by the pulse generator 6 for the vertical selection circuit.

  ΦVA is a start signal for the vertical selection circuit, and φVB and φVC are vertical selection circuit drive pulses.

  Hereinafter, an example of the pulse generation circuit 6 for the vertical selection circuit will be described with reference to FIG. FIG. 3 is a circuit diagram showing a circuit for generating any one pulse of φVA, φVB, φVC,... Input to the vertical selection circuit unit 2 in the vertical selection circuit pulse generation circuit 6.

  In the present embodiment, two outputs of the dummy counter circuit 5 are used for the rising of the pulse, and one output of the dummy counter circuit 5 is used for the falling of the pulse.

  The circuit shown in FIG. 3 includes one capacitor C1 and seven nMOS transistors M1 to M7, and outputs φin1, φin2, and φin3 from the dummy counter circuit 5 are used as inputs. First, the transistor M1 and the transistor M7 are turned ON by φin1. As a result, at the same time as the transistor M3 is turned ON, the source side of the transistor M3 is fixed to GND, and the capacitor C1 is charged. Next, φin2 is input. At this time, since the capacitor C1 is charged even when φin1 becomes LOW, the transistor M3 remains in the ON state. Therefore, the input of φin2 is transmitted to the transistor M5 by the amplitude of φin2 in addition to the voltage charged in the capacitor C1. Here, the maximum voltage is obtained and the rise is completed. Next, when φin3 is input, the transistor M2 and the transistor M4 are turned on, and both ends of the capacitor C1 are set to GND to discharge. Further, the pulse reaches the LOW level by turning on the transistor M6. In the case of FIG. 2, for example, in a circuit that generates the vertical selection circuit drive pulse φVA, the output (D1out) of the dummy counter D1 is used for φin1, the output (D2out) of the dummy counter D2 is used for φin2, and the dummy counter D4 is used for φin3. The output (D4out) is used.

  The pulses generated in the horizontal blanking period by the dummy counter circuit 5 and the vertical selection circuit pulse generation circuit 6 in this way are used in the vertical selection circuit unit 2 in the horizontal blanking period. For example, the vertical selection circuit is a circuit that transmits a pulse to the pixel unit and transmits a signal to the next row (referred to as a master circuit) and a circuit that is used only for shifting to the next row (referred to as a slave circuit). In this example, φVA is given to the master circuit and φVB is given to the slave circuit. φVA and φVB are square waves of divide by two and are in antiphase with each other. The input method of the start pulse differs depending on whether it starts from the master circuit or the slave circuit. If the master circuit is the first, scanning can be started by matching the high period of the start pulse with the high period of the master circuit. If the slave circuit is the first, scanning can be started by matching the high period of the start pulse with the high period of the slave circuit. The start pulse is a pulse that is set to High only when the operation of the vertical scanning circuit is started, and the others are LOW.

  The above flip-flop circuit has a circuit configuration in consideration of drive capability, current consumption, etc. in realizing the present invention. Of course, various circuit configurations can be assumed as long as the circuit can generate a pulse. It is not limited to.

  In the vertical selection circuit pulse generation circuit 6, the necessary number of the circuits shown in FIG. For example, in addition to φVA, φVB, and φVC, when the vertical selection circuit 2 requires 9 inputs, the circuit shown in FIG. 3 is used in the vertical selection circuit pulse generation circuit 6 in addition to generating φVA, φVB, and φVC. Nine are installed. The number of circuits is not limited, and the number of inputs required by the vertical selection circuit unit 2 may be provided. Note that the nine inputs required by the vertical selection circuit unit 2 are pulses transmitted to the pixel unit 1 as they are, and pixels are selected only in the row selected from the vertical selection circuits V1, V2,. Is transmitted to section 1. Each of the vertical selection circuits V1, V2,... Vm is a flip-flop provided corresponding to each row, and constitutes a shift register as a whole. Note that there are AND circuits (for example, multiplexers) in each row of V1, V2,. Then, 9 inputs are transmitted to the pixel portion side only in the rows in the range of V1 to Vm that are at the high level. With this operation, it is possible to drive pixels only in the selected row.

  Here, the circuit scale is compared. In order to realize 9 inputs of the vertical selection circuit unit 2 as described above, the internal generation circuit 7 using the conventional logic circuit as shown in FIG. 5 requires 432 transistors, whereas this embodiment This configuration can be realized with 100 or less. The area occupied by the circuit is 1/3 or less.

  As described above, according to the present embodiment, the drive pulse used for the vertical selection circuit unit 2 can be internally generated with a small circuit scale. As a result, the cost can be reduced by reducing the chip area, and a solid-state imaging device with a small number of terminals can be manufactured, which contributes to miniaturization of the camera set.

  In this embodiment, the vertical selection circuit drive pulse is generated using the output of the dummy counter circuit 5, but in addition to this, the signal readout pulse of the pixel unit is output using the output of the dummy counter circuit 5. There is also a pulse generation circuit that generates necessary pulses such as reset pulse, electronic shutter vertical selection circuit drive pulse, electronic shutter signal readout pulse, electronic shutter reset pulse, vertical selection circuit drive start pulse, etc. Good.

  Further, in this embodiment, the dummy counter circuit 5 is provided which is driven by the horizontal selection circuit drive pulse and starts to operate with the final output of the horizontal selection circuit unit 3 as an input, but is driven by the vertical selection circuit drive pulse. By providing a dummy counter circuit that starts operating with the final output of 2 as an input, and by providing a pulse generation circuit that generates the necessary pulses as described above using the output of the dummy counter circuit within the vertical blanking period, Effects can be obtained.

  In the present embodiment, the MOS type solid-state imaging device having the photosensitive region 10 in which the pixel unit 1 is arranged in a two-dimensional manner has been described. However, the pixel unit 1 has a photosensitive region in which the pixel unit 1 is arranged in a one-dimensional manner. The same applies to the MOS type solid-state imaging device. In this case, a selection circuit unit that selects the pixel units 1 arranged in a one-dimensional form based on the selection circuit driving pulse is provided, and the pixel circuit 1 is driven by the selection circuit driving pulse and the final output of the selection circuit unit is input to start operation. A similar effect can be obtained by providing a dummy counter circuit and a pulse generation circuit that generates a necessary pulse using the output of the dummy counter circuit.

  The MOS type solid-state imaging device according to the present invention can reduce the chip area and is useful as a MOS type solid-state imaging device having a photosensitive region in which pixel portions are arranged two-dimensionally or one-dimensionally. .

1 is a schematic circuit diagram of a MOS type solid-state imaging device according to an embodiment of the present invention. Timing diagram showing operation in the embodiment of the present invention 1 is a circuit diagram of an example of a pulse generation circuit for a vertical selection circuit according to an embodiment of the present invention. Schematic circuit diagram of a MOS type solid-state imaging device of a first conventional example Schematic circuit diagram of a MOS type solid-state imaging device of a second conventional example

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Pixel part 2 Vertical selection circuit part 3 Horizontal selection circuit part 4 Output amplifier 5 Dummy counter circuit 6 Pulse generation circuit 10 for vertical selection circuits Photosensitive area

Claims (7)

A photosensitive region in which amplification unit pixels for amplifying an electric signal obtained by photoelectric conversion of incident light are arranged in a two-dimensional array of rows and columns, and a vertical for selecting a row of the unit pixels based on a vertical selection circuit driving pulse. A MOS type solid-state imaging device including a selection circuit unit and a horizontal selection circuit unit that selects a column of the unit pixels based on a horizontal selection circuit drive pulse,
A dummy counter circuit that is driven by the horizontal selection circuit drive pulse and starts to operate with the final output of the horizontal selection circuit unit as an input, and a pulse generation circuit that generates a pulse using the output of the dummy counter circuit are provided. Characteristic MOS type solid-state imaging device.   2. The MOS solid-state imaging device according to claim 1, wherein the pulse generated by the pulse generation circuit is the vertical selection circuit drive pulse.   2. The MOS type solid-state imaging device according to claim 1, wherein the unit circuit of the dummy counter circuit has the same configuration as that of the horizontal selection circuit section. A photosensitive region in which amplification unit pixels for amplifying an electric signal obtained by photoelectric conversion of incident light are arranged in a two-dimensional array of rows and columns, and a vertical for selecting a row of the unit pixels based on a vertical selection circuit driving pulse. A MOS type solid-state imaging device including a selection circuit unit and a horizontal selection circuit unit that selects a column of the unit pixels based on a horizontal selection circuit drive pulse,
A dummy counter circuit that is driven by the vertical selection circuit drive pulse and starts to operate with a final output of the vertical selection circuit section as an input, and a pulse generation circuit that generates a pulse using the output of the dummy counter circuit are provided. Characteristic MOS type solid-state imaging device.   5. The MOS type solid-state imaging device according to claim 4, wherein the unit circuit of the dummy counter circuit has the same configuration as that of the vertical selection circuit unit. MOS including a photosensitive region in which amplification type unit pixels that amplify an electric signal obtained by photoelectric conversion of incident light are arranged one-dimensionally, and a selection circuit unit that selects the unit pixel based on a selection circuit drive pulse Type solid-state imaging device,
A dummy counter circuit driven by the selection circuit drive pulse and starting to operate with a final output of the selection circuit unit as an input, and a pulse generation circuit for generating a pulse using the output of the dummy counter circuit are provided. MOS type solid-state imaging device.   7. The MOS type solid-state imaging device according to claim 6, wherein the unit circuit of the dummy counter circuit has the same configuration as that of the selection circuit unit.

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