JP2005136444A - Semiconductor device, its manufacturing method, circuit board, and electronic equipment - Google Patents

Semiconductor device, its manufacturing method, circuit board, and electronic equipment Download PDF

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JP2005136444A
JP2005136444A JP2005042340A JP2005042340A JP2005136444A JP 2005136444 A JP2005136444 A JP 2005136444A JP 2005042340 A JP2005042340 A JP 2005042340A JP 2005042340 A JP2005042340 A JP 2005042340A JP 2005136444 A JP2005136444 A JP 2005136444A
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semiconductor device
resin
resin portion
electrodes
semiconductor substrate
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JP4240226B2 (en
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Terunao Hanaoka
輝直 花岡
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Seiko Epson Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device, a method of manufacturing the device, a circuit board, and electronic equipment. <P>SOLUTION: The semiconductor device comprises a semiconductor substrate 10 having electrically connected electrodes 14 inside, a first resin section 20 formed at the central part of the surface of the substrate 10 on which the electrodes 14 are formed, and a plurality of second resin sections 25 formed in the areas of the surface of the substrate 10, on which the electrodes 14 are formed, nearer to the end sections of the substrate 10 than the first resin section 20. The device also comprises a wiring 30 formed on the first resin section 20 from the surfaces of the electrodes 14 and a resin layer 40 formed from the surface of the first resin section 20 to the outside of the second resin sections 25 to cover the wiring 30. The resin layer 40 is formed to expose at least the upper end sections of the second resin sections 25. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体装置及びその製造方法、回路基板並びに電子機器に関する。   The present invention relates to a semiconductor device, a manufacturing method thereof, a circuit board, and an electronic device.

半導体装置のパッケージとして、ＣＳＰ（チップスケール／サイズパッケージ）の普及率が高まってきている。また、パッケージをウエハレベルで製造する技術（ウエハレベルパッケージ）が開発されている。この方法で製造されたパッケージ（例えばウエハレベルＣＳＰ）は、外部寸法が半導体チップ寸法になっているため、従来のパッケージとは構造が異なっているが、従来のパッケージと同等又はそれ以上の信頼性が要求される。
国際公開００／５５８９８号パンフレット 特開２００３−２３００９号公報 The spread rate of CSP (chip scale / size package) is increasing as a package of a semiconductor device. In addition, a technique for manufacturing a package at a wafer level (wafer level package) has been developed. A package manufactured by this method (for example, a wafer level CSP) has a structure different from that of a conventional package because the external dimensions are semiconductor chip dimensions, but the reliability is equal to or higher than that of the conventional package. Is required.
International publication 00/55898 pamphlet Japanese Patent Laid-Open No. 2003-23009

本発明の目的は、信頼性の高い半導体装置及びその製造方法、回路基板並びに電子機器を提供することにある。   An object of the present invention is to provide a highly reliable semiconductor device, a manufacturing method thereof, a circuit board, and an electronic apparatus.

（１）本発明に係る半導体装置は、内部に電気的に接続された電極を有する、集積回路が形成された半導体基板と、
前記半導体基板の前記電極が形成された面の中央部に形成された第１の樹脂部と、
前記半導体基板の前記電極が形成された面の前記第１の樹脂部よりも端部に近い領域に形成された複数の第２の樹脂部と、
前記電極上から前記第１の樹脂部上に形成された配線と、
前記配線を覆うように、前記第１の樹脂部上から前記第２の樹脂部の外側に至るように形成された樹脂層と、
を有し、
前記樹脂層は、前記第２の樹脂部の少なくとも上端部が露出するように形成されてなる。本発明によれば、半導体装置は、第１の樹脂部よりも半導体基板の端部に近い領域に形成された第２の樹脂部を有する。そして、樹脂層は、第２の樹脂部の外側に至るように形成されてなる。これによると、樹脂層が収縮することにより発生する力は、第２の樹脂部に吸収される。そのため、樹脂層の収縮による影響を受けにくい、信頼性の高い半導体装置を提供することができる。
（２）この半導体装置において、
前記第２の樹脂部は、前記半導体基板のすべての辺のそれぞれに沿って形成されていてもよい。
（３）この半導体装置において、
前記第２の樹脂部は、前記電極を避けて形成されていてもよい。これによれば、電気的な信頼性の高い半導体装置を提供することができる。
（４）この半導体装置において、
前記第２の樹脂部は、前記電極の間を通り前記電極の外側の領域から前記電極の内側の領域に至る仕切り部を有してもよい。これによれば、電極間のマイグレーションの発生を防止することが可能な、信頼性の高い半導体装置を提供することができる。
（５）本発明に係る回路基板には、上記半導体装置が実装されてなる。
（６）本発明に係る電子機器は、上記半導体装置を有する。
（７）本発明に係る半導体装置の製造方法は、内部に電気的に接続された電極を有する、集積回路が形成された半導体基板を用意すること、
前記半導体基板の前記電極が形成された面の中央部に、第１の樹脂部を形成すること、
前記半導体基板の前記電極が形成された面の前記第１の樹脂部よりも端部に近い領域に、複数の第２の樹脂部を形成すること、
前記電極上から、前記第１の樹脂部上に配線を形成すること、及び、
前記配線を覆う樹脂層を、前記第１の樹脂部上から前記第２の樹脂部の外側に至るように形成することを含み、
前記樹脂層を、前記第２の樹脂部の少なくとも上端部が露出するように形成する。本発明によれば、半導体装置の製造方法は、半導体基板の第１の樹脂部よりも端部に近い領域に第２の樹脂部を形成することを含む。そして、樹脂層は、第２の樹脂部の外側に至るように形成される。これによると、樹脂層が収縮することにより発生する力を、第２の樹脂部に吸収させることが可能な、信頼性の高い半導体装置を製造することができる。
（８）この半導体装置の製造方法において、
前記第２の樹脂部を、前記半導体基板のすべての辺のそれぞれに沿って形成してもよい。
（９）この半導体装置の製造方法において、
前記第２の樹脂部を、前記電極を避けて形成してもよい。これによれば、電気的な信頼性の高い半導体装置を製造することができる。
（１０）この半導体装置の製造方法において、
前記第１の樹脂部と前記第２の樹脂部とを、一括して形成してもよい。これによれば、半導体装置の製造効率を高めることができる。
（１１）この半導体装置の製造方法において、
前記第２の樹脂部を、前記電極の間を通り前記電極の外側の領域から前記電極の内側の領域に至る仕切り部を有するように形成してもよい。これによれば、電極間のマイグレーションを防止することが可能な、信頼性の高い半導体装置を製造することができる。 (1) A semiconductor device according to the present invention includes a semiconductor substrate on which an integrated circuit is formed, having an electrode electrically connected to the inside;
A first resin portion formed at the center of the surface of the semiconductor substrate on which the electrodes are formed;
A plurality of second resin portions formed in a region closer to the end than the first resin portion of the surface of the semiconductor substrate on which the electrodes are formed;
Wiring formed on the first resin portion from the electrode;
A resin layer formed so as to cover the wiring from the first resin portion to the outside of the second resin portion;
Have
The resin layer is formed so that at least an upper end portion of the second resin portion is exposed. According to the present invention, the semiconductor device has the second resin portion formed in a region closer to the end portion of the semiconductor substrate than the first resin portion. The resin layer is formed so as to reach the outside of the second resin portion. According to this, the force generated when the resin layer contracts is absorbed by the second resin portion. Therefore, it is possible to provide a highly reliable semiconductor device that is not easily affected by the shrinkage of the resin layer.
(2) In this semiconductor device,
The second resin portion may be formed along each of all sides of the semiconductor substrate.
(3) In this semiconductor device,
The second resin portion may be formed avoiding the electrode. According to this, a semiconductor device with high electrical reliability can be provided.
(4) In this semiconductor device,
The second resin portion may include a partition portion that passes between the electrodes and extends from a region outside the electrode to a region inside the electrode. According to this, a highly reliable semiconductor device capable of preventing the occurrence of migration between electrodes can be provided.
(5) The above-described semiconductor device is mounted on the circuit board according to the present invention.
(6) An electronic apparatus according to the present invention includes the semiconductor device.
(7) A method of manufacturing a semiconductor device according to the present invention includes preparing a semiconductor substrate on which an integrated circuit is formed, having an electrode electrically connected to the inside.
Forming a first resin portion at a central portion of the surface of the semiconductor substrate on which the electrodes are formed;
Forming a plurality of second resin portions in a region closer to an end portion than the first resin portion of the surface of the semiconductor substrate on which the electrodes are formed;
Forming a wiring on the first resin part from the electrode; and
Forming a resin layer covering the wiring from the first resin portion to the outside of the second resin portion,
The resin layer is formed so that at least an upper end portion of the second resin portion is exposed. According to the present invention, the method for manufacturing a semiconductor device includes forming the second resin portion in a region closer to the end portion than the first resin portion of the semiconductor substrate. The resin layer is formed so as to reach the outside of the second resin portion. According to this, it is possible to manufacture a highly reliable semiconductor device in which the force generated by the shrinkage of the resin layer can be absorbed by the second resin portion.
(8) In this method of manufacturing a semiconductor device,
The second resin portion may be formed along each of all sides of the semiconductor substrate.
(9) In this method of manufacturing a semiconductor device,
The second resin portion may be formed avoiding the electrode. According to this, a semiconductor device with high electrical reliability can be manufactured.
(10) In this method of manufacturing a semiconductor device,
The first resin portion and the second resin portion may be formed collectively. According to this, the manufacturing efficiency of the semiconductor device can be increased.
(11) In this method of manufacturing a semiconductor device,
The second resin portion may be formed so as to have a partition portion that passes between the electrodes and extends from a region outside the electrode to a region inside the electrode. According to this, a highly reliable semiconductor device that can prevent migration between electrodes can be manufactured.

以下、本発明を適用した実施の形態について図面を参照して説明する。ただし、本発明は、以下の実施の形態に限定されるものではない。図１及び図２は、本発明を適用した実施の形態に係る半導体装置を説明するための図である。ここで、図１は、本発明を適用した実施の形態に係る半導体装置１の断面の一部拡大図である。また、図２は、説明のために配線３０、樹脂層４０及び外部端子５０を取り除いた半導体装置の平面図である。   Embodiments to which the present invention is applied will be described below with reference to the drawings. However, the present invention is not limited to the following embodiments. 1 and 2 are diagrams for explaining a semiconductor device according to an embodiment to which the present invention is applied. Here, FIG. 1 is a partially enlarged view of a cross section of a semiconductor device 1 according to an embodiment to which the present invention is applied. FIG. 2 is a plan view of the semiconductor device from which the wiring 30, the resin layer 40, and the external terminal 50 are removed for explanation.

本実施の形態に係る半導体装置は、半導体基板１０を有する。半導体基板１０の材料は特に限定されないが、例えばシリコンであってもよい。半導体基板１０は、半導体チップであってもよい（図２参照）。半導体チップの平面形状は、矩形であることが一般的であるが、これに限られるものではない。ただし、半導体基板は、半導体ウエハであってもよい。   The semiconductor device according to the present embodiment has a semiconductor substrate 10. The material of the semiconductor substrate 10 is not particularly limited, but may be silicon, for example. The semiconductor substrate 10 may be a semiconductor chip (see FIG. 2). The planar shape of the semiconductor chip is generally rectangular, but is not limited thereto. However, the semiconductor substrate may be a semiconductor wafer.

図１に示すように、半導体基板１０には、１つ又は複数の（半導体チップには１つの、半導体ウエハには複数の）集積回路１２が形成されている。集積回路１２は、半導体基板１０の一方の面側に形成されていてもよい。   As shown in FIG. 1, one or a plurality of integrated circuits 12 (one for a semiconductor chip and a plurality for a semiconductor wafer) are formed on a semiconductor substrate 10. The integrated circuit 12 may be formed on one surface side of the semiconductor substrate 10.

半導体基板１０は、電極１４を有する。電極１４は、半導体基板１０の内部に電気的に接続されていてもよい。電極１４は、集積回路１２に電気的に接続されていてもよい。あるいは、集積回路１２に電気的に接続されていない電極を、電極１４としてもよい。電極１４は、半導体基板１０の平行な２辺に沿って配列されていてもよいし（図３参照）、４辺に沿って配列されていてもよい。電極１４は、半導体基板１０の端部付近に配置されていてもよく、中央部付近に配置されていてもよい。なお、半導体基板１０には、１つの集積回路１２に対して、複数の電極１４が形成されていてもよい。電極１４の材料は特に限定されないが、例えばＡｌであってもよい。   The semiconductor substrate 10 has an electrode 14. The electrode 14 may be electrically connected to the inside of the semiconductor substrate 10. The electrode 14 may be electrically connected to the integrated circuit 12. Alternatively, an electrode that is not electrically connected to the integrated circuit 12 may be used as the electrode 14. The electrodes 14 may be arranged along two parallel sides of the semiconductor substrate 10 (see FIG. 3), or may be arranged along four sides. The electrode 14 may be disposed near the end of the semiconductor substrate 10 or may be disposed near the center. The semiconductor substrate 10 may have a plurality of electrodes 14 for one integrated circuit 12. Although the material of the electrode 14 is not specifically limited, For example, Al may be sufficient.

半導体基板１０は、囲繞部材１６を有してもよい。ここで、囲繞部材１６は、半導体基板１０と後述するパッシベーション膜１８との間に浸入する水分が、半導体基板１０の素子領域に到達することを防止する役割を果たすものである。囲繞部材１６によって、半導体装置の信頼性を高めることができる。囲繞部材１６は、半導体基板１０の電極１４が形成された面の電極１４よりも外側の領域に形成されていてもよい（図１及び図２参照）。囲繞部材１６は、すべての電極１４を囲むように形成されていてもよい。詳しくは、囲繞部材１６は、１つの集積回路１２に対応して形成された一群の電極１４のすべてを囲むように形成されていてもよい（図２参照）。半導体基板として、内部に複数の集積回路を有する半導体ウエハを用意する場合、半導体基板は、各集積回路に対応した複数の囲繞部材１６を有することになる。囲繞部材１６は、一体的に形成されていることが一般的である。囲繞部材１６の材料は特に限定されず、例えばＡｌであってもよい。囲繞部材１６は、電極１４を形成する工程で、これと同時に形成してもよく、このとき、電極１４と同じ材料で形成してもよい。   The semiconductor substrate 10 may have a surrounding member 16. Here, the surrounding member 16 plays a role of preventing moisture that enters between the semiconductor substrate 10 and a passivation film 18 described later from reaching the element region of the semiconductor substrate 10. The surrounding member 16 can improve the reliability of the semiconductor device. The surrounding member 16 may be formed in a region outside the electrode 14 on the surface on which the electrode 14 of the semiconductor substrate 10 is formed (see FIGS. 1 and 2). The surrounding member 16 may be formed so as to surround all the electrodes 14. Specifically, the surrounding member 16 may be formed so as to surround all of the group of electrodes 14 formed corresponding to one integrated circuit 12 (see FIG. 2). When a semiconductor wafer having a plurality of integrated circuits therein is prepared as a semiconductor substrate, the semiconductor substrate has a plurality of surrounding members 16 corresponding to each integrated circuit. The surrounding member 16 is generally formed integrally. The material of the surrounding member 16 is not specifically limited, For example, Al may be sufficient. The surrounding member 16 may be formed simultaneously with the step of forming the electrode 14, and at this time, the surrounding member 16 may be formed of the same material as the electrode 14.

半導体基板１０は、パッシベーション膜１８を有してもよい。パッシベーション膜１８は、半導体基板１０の表面（電極１４が形成された面）を保護するための絶縁保護膜である。パッシベーション膜１８は、半導体基板１０の表面（電極１４が形成された面）に形成されていてもよい。パッシベーション膜１８は、それぞれの電極１４の少なくとも一部を露出させるように、電極１４及び囲繞部材１６を覆っていてもよい。パッシベーション膜１８は、例えば、ＳｉＮ、ＳｉＯ２、ポリイミド樹脂等で形成されていてもよい。 The semiconductor substrate 10 may have a passivation film 18. The passivation film 18 is an insulating protective film for protecting the surface of the semiconductor substrate 10 (the surface on which the electrode 14 is formed). The passivation film 18 may be formed on the surface of the semiconductor substrate 10 (the surface on which the electrode 14 is formed). The passivation film 18 may cover the electrode 14 and the surrounding member 16 so that at least a part of each electrode 14 is exposed. The passivation film 18 may be formed of, for example, SiN, SiO 2 , polyimide resin, or the like.

本実施の形態に係る半導体装置は、第１の樹脂部２０を有する。第１の樹脂部２０は、半導体基板１０の電極１４が形成された面の中央部に形成されてなる。第１の樹脂部２０は、電極１４を避けて形成されていてもよい。第１の樹脂部２０は、図１に示すように、パッシベーション膜１８上に形成されていてもよい。第１の樹脂部２０の材料は特に限定されないが、例えば、ポリイミド樹脂、シリコーン変性ポリイミド樹脂、エポキシ樹脂、シリコーン変性エポキシ樹脂、ベンゾシクロブテン（ＢＣＢ；benzocyclobutene）、ポリベンゾオキサゾール（ＰＢＯ；polybenzoxazole）等の樹脂であってもよい。   The semiconductor device according to the present embodiment has a first resin portion 20. The first resin portion 20 is formed at the center of the surface on which the electrode 14 of the semiconductor substrate 10 is formed. The first resin portion 20 may be formed avoiding the electrode 14. As shown in FIG. 1, the first resin portion 20 may be formed on the passivation film 18. Although the material of the 1st resin part 20 is not specifically limited, For example, a polyimide resin, a silicone modified polyimide resin, an epoxy resin, a silicone modified epoxy resin, benzocyclobutene (BCB; benzocyclobutene), polybenzoxazole (PBO), etc. This resin may be used.

本実施の形態に係る半導体装置は、複数の第２の樹脂部２５を有する。第２の樹脂部２５は、半導体基板１０の電極１４が形成された面の第１の樹脂部２０よりも端部に近い領域に形成されてなる。言い換えると、第２の樹脂部２５は、半導体基板１０の第１の樹脂部２０よりも外側の領域に形成されてなる。図１及び図２に示すように、第２の樹脂部２５は、電極１４よりも外側の領域に形成されていてもよい。第２の樹脂部２５は、電極１４を避けて形成されていてもよい。詳しくは、第２の樹脂部２５は、電極１４におけるパッシベーション膜１８から露出した部分と接触しないように形成されていてもよい。これにより、電極１４上に水分が入り込みにくい、信頼性の高い半導体装置を提供することができる。第２の樹脂部２５は、図２に示すように、半導体基板１０の、すべての辺のそれぞれに沿って形成されていてもよい。第２の樹脂部２５は、第１の樹脂部２０と同じ高さであってもよい。なお、ここでいう「高さ」とは、半導体基板１０の表面（電極１４が形成された面）からの高さを指す。第２の樹脂部２５の材料は特に限定されるものではなく、第１の樹脂部２０の説明で挙げた材料のいずれかを適用してもよい。このとき、第１の樹脂部２０と第２の樹脂部２５とは、同じ材料で形成されていてもよい。   The semiconductor device according to the present embodiment has a plurality of second resin portions 25. The second resin portion 25 is formed in a region closer to the end than the first resin portion 20 on the surface of the semiconductor substrate 10 on which the electrode 14 is formed. In other words, the second resin portion 25 is formed in a region outside the first resin portion 20 of the semiconductor substrate 10. As shown in FIGS. 1 and 2, the second resin portion 25 may be formed in a region outside the electrode 14. The second resin portion 25 may be formed avoiding the electrode 14. Specifically, the second resin portion 25 may be formed so as not to contact a portion of the electrode 14 exposed from the passivation film 18. Thereby, a highly reliable semiconductor device in which moisture hardly enters the electrode 14 can be provided. As shown in FIG. 2, the second resin portion 25 may be formed along each of all sides of the semiconductor substrate 10. The second resin portion 25 may be the same height as the first resin portion 20. The “height” here refers to the height from the surface of the semiconductor substrate 10 (the surface on which the electrode 14 is formed). The material of the second resin part 25 is not particularly limited, and any of the materials mentioned in the description of the first resin part 20 may be applied. At this time, the 1st resin part 20 and the 2nd resin part 25 may be formed with the same material.

図１に示すように、本実施の形態に係る半導体装置は、配線３０を有する。配線３０は、複数本形成されることが一般的である。配線３０は、一層又は複数層で形成されていてもよい。配線３０の材料は特に限定されないが、例えばCuで形成された層を有してもよい。配線３０は、電極１４上から第１の樹脂部２０上に形成されてなる。配線３０は、電極１４におけるパッシベーション膜１８から露出した部分の全てを覆っていてもよい。配線３０は、電極１４から第１の樹脂部２０の上面（パッシベーション膜１８とは反対側の面）に至るように形成されてなる。配線３０は、第１の樹脂部２０上にランド３２を有していてもよい。ランド３２は、配線３０の一部である。すなわち、配線３０は、ランド３２と、ランド３２と電極１４とを電気的に接続するラインとを含む。ランド３２は、配線３０のラインよりも幅が広くなっていてもよい。ランド３２の平面形状は特に限定されないが、例えば円形であってもよい。第１の樹脂部２０の上面には、複数のランド３２が形成されていてもよい。配線３０は、ラインの少なくとも一部が第１の樹脂部２０の上面に至るように形成されていてもよい。   As shown in FIG. 1, the semiconductor device according to the present embodiment has a wiring 30. In general, a plurality of wirings 30 are formed. The wiring 30 may be formed of a single layer or a plurality of layers. Although the material of the wiring 30 is not specifically limited, For example, you may have the layer formed with Cu. The wiring 30 is formed on the first resin portion 20 from the electrode 14. The wiring 30 may cover the entire portion of the electrode 14 exposed from the passivation film 18. The wiring 30 is formed so as to extend from the electrode 14 to the upper surface of the first resin portion 20 (surface opposite to the passivation film 18). The wiring 30 may have a land 32 on the first resin portion 20. The land 32 is a part of the wiring 30. That is, the wiring 30 includes a land 32 and a line that electrically connects the land 32 and the electrode 14. The land 32 may be wider than the line of the wiring 30. The planar shape of the land 32 is not particularly limited, but may be circular, for example. A plurality of lands 32 may be formed on the upper surface of the first resin portion 20. The wiring 30 may be formed so that at least a part of the line reaches the upper surface of the first resin portion 20.

図１に示すように、本実施の形態に係る半導体装置は、樹脂層４０を有する。樹脂層４０を、ソルダーレジストと称してもよい。樹脂層４０は、配線３０を覆うように形成されてなる。また、樹脂層４０は、第１の樹脂部２０上から第２の樹脂部２５の外側に至るように形成されてなる。図１に示すように、樹脂層４０は、第２の樹脂部２５を覆うように形成してもよい。樹脂層４０は、パッシベーション膜１８の形成領域内に形成されていてもよい。あるいは、樹脂層４０は、パッシベーション膜１８の外側に至るように形成されていてもよい。   As shown in FIG. 1, the semiconductor device according to the present embodiment has a resin layer 40. The resin layer 40 may be referred to as a solder resist. The resin layer 40 is formed so as to cover the wiring 30. The resin layer 40 is formed so as to extend from the first resin portion 20 to the outside of the second resin portion 25. As shown in FIG. 1, the resin layer 40 may be formed so as to cover the second resin portion 25. The resin layer 40 may be formed in the formation region of the passivation film 18. Alternatively, the resin layer 40 may be formed so as to reach the outside of the passivation film 18.

樹脂層４０は、開口４２を有してもよい。開口４２は、それぞれのランド３２の少なくとも一部を露出させる。開口４２からランド３２を露出させることで、後述する外部端子５０とランド３２との電気的な接続を図ることができる。例えば、ランド３２の中央部を開口４２から露出させ、ランド３２の周縁部を覆うように、樹脂層４０を形成してもよい。   The resin layer 40 may have an opening 42. The opening 42 exposes at least a part of each land 32. By exposing the land 32 from the opening 42, an electrical connection between an external terminal 50 and a land 32 described later can be achieved. For example, the resin layer 40 may be formed so that the center portion of the land 32 is exposed from the opening 42 and the peripheral portion of the land 32 is covered.

図１に示すように、本実施の形態に係る半導体装置は、外部端子５０を有してもよい。外部端子５０は、ランド３２に設けられてなる。外部端子５０は、樹脂層４０の開口４２の内側を通るように形成される。このとき、外部端子５０における開口４２内に配置される部分を、根元部５２と称してもよい。外部端子５０は、導電性を有する金属（例えば合金）であって、溶融させて電気的な接続を図るもの（例えばハンダ）である。外部端子５０は、軟ろう（soft solder）又は硬ろう（hard solder）のいずれで形成されてもよい。外部端子５０は、球状をなしてもよく、例えばハンダボールであってもよい。   As shown in FIG. 1, the semiconductor device according to the present embodiment may have an external terminal 50. The external terminal 50 is provided on the land 32. The external terminal 50 is formed so as to pass inside the opening 42 of the resin layer 40. At this time, a portion arranged in the opening 42 in the external terminal 50 may be referred to as a root portion 52. The external terminal 50 is a metal having conductivity (for example, an alloy) and is melted to achieve electrical connection (for example, solder). The external terminal 50 may be formed of either soft solder or hard solder. The external terminal 50 may have a spherical shape, for example, a solder ball.

本発明を適用した実施の形態に係る半導体装置１は、以上のように構成されてなる。通常、半導体装置の製造工程や、半導体装置をマザーボード等に実装する工程において、半導体装置には熱が加えられる。この影響で、樹脂層（ソルダーレジスト）が収縮し、パッシベーション膜や、半導体基板に力がかかることがあった。ところで、本発明を適用した実施の形態に係る半導体装置１は、第２の樹脂部２５を有する。そして、樹脂層４０（ソルダーレジスト）は、第２の樹脂部２５の外側に至るように形成されてなる。これにより、樹脂層４０の収縮により発生する応力を、第２の樹脂部２５によって吸収させることが可能となる。そのため、樹脂層４０の収縮応力の影響を受けにくい、信頼性の高い半導体装置を提供することができる。なお、図３には、本発明を適用した実施の形態に係る半導体装置１が実装された回路基板１０００を示す。また、本発明を適用した実施の形態に係る半導体装置を有する電子機器として、図４にはノート型パーソナルコンピュータが、図５には、携帯電話が、それぞれ示されている。   The semiconductor device 1 according to the embodiment to which the present invention is applied is configured as described above. Usually, heat is applied to a semiconductor device in a manufacturing process of the semiconductor device or a process of mounting the semiconductor device on a motherboard or the like. As a result, the resin layer (solder resist) contracts, and force may be applied to the passivation film and the semiconductor substrate. Incidentally, the semiconductor device 1 according to the embodiment to which the present invention is applied has a second resin portion 25. The resin layer 40 (solder resist) is formed so as to reach the outside of the second resin portion 25. As a result, the stress generated by the contraction of the resin layer 40 can be absorbed by the second resin portion 25. Therefore, it is possible to provide a highly reliable semiconductor device that is not easily affected by the shrinkage stress of the resin layer 40. FIG. 3 shows a circuit board 1000 on which the semiconductor device 1 according to the embodiment to which the present invention is applied is mounted. Further, as an electronic device having the semiconductor device according to the embodiment to which the present invention is applied, FIG. 4 shows a notebook personal computer and FIG. 5 shows a mobile phone.

以下、本発明を適用した実施の形態に係る半導体装置１の製造方法を説明する。半導体装置１の製造方法は、半導体基板１０を用意することを含む。半導体基板１０は、既に説明した内容のいずれかを適用してもよい。例えば、半導体基板１０は、電極１４を有し、集積回路１２が形成されてなる。半導体基板１０は、囲繞部材１６とパッシベーション膜１８とを有してもよい。   Hereinafter, a method for manufacturing the semiconductor device 1 according to the embodiment to which the present invention is applied will be described. The method for manufacturing the semiconductor device 1 includes preparing the semiconductor substrate 10. Any of the contents already described may be applied to the semiconductor substrate 10. For example, the semiconductor substrate 10 includes an electrode 14 and an integrated circuit 12 is formed. The semiconductor substrate 10 may have a surrounding member 16 and a passivation film 18.

半導体装置１の製造方法は、半導体基板１０の電極１４が形成された面の中央部に、第１の樹脂部２０を形成することを含む。半導体装置１の製造方法は、半導体基板１０の電極１４が形成された面の第１の樹脂部２０よりも端部に近い領域に、第２の樹脂部２５を形成することを含む。ここで、第１の樹脂部２０及び第２の樹脂部２５は、既に公知となっているいずれかの方法によって形成してもよい。これらは、異なる工程で形成してもよく、あるいは、一括して形成してもよい。第１の樹脂部２０及び第２の樹脂部２５を一括して形成することで、半導体基板の製造効率を高めることができる。第１の樹脂部２０及び第２の樹脂部２５は、例えば、半導体基板１０の表面（電極１４が形成された面）の全面に樹脂の層を形成し、その後、露光及び現像する工程を経て形成してもよい。マスクのパターンを調整することで、第１の樹脂部２０と第２の樹脂部２５とを一括して形成してもよい。ただし、これとは別に、例えばスクリーン印刷法を用いて、第１の樹脂部２０及び第２の樹脂部２５を形成してもよい。   The method for manufacturing the semiconductor device 1 includes forming the first resin portion 20 at the center of the surface of the semiconductor substrate 10 on which the electrode 14 is formed. The method for manufacturing the semiconductor device 1 includes forming the second resin portion 25 in a region closer to the end portion than the first resin portion 20 on the surface of the semiconductor substrate 10 on which the electrode 14 is formed. Here, the first resin portion 20 and the second resin portion 25 may be formed by any of the methods already known. These may be formed in different steps, or may be formed in a lump. By forming the 1st resin part 20 and the 2nd resin part 25 collectively, the manufacturing efficiency of a semiconductor substrate can be improved. For example, the first resin portion 20 and the second resin portion 25 are formed by forming a resin layer on the entire surface of the semiconductor substrate 10 (the surface on which the electrode 14 is formed), and then performing exposure and development. It may be formed. The first resin portion 20 and the second resin portion 25 may be collectively formed by adjusting the mask pattern. However, separately from this, for example, the first resin portion 20 and the second resin portion 25 may be formed by using a screen printing method.

半導体装置１の製造方法は、電極１４上から、第１の樹脂部２０上に配線３０を形成することを含む。配線３０は、既に公知となっているいずれかの方法を適用して形成してもよい。   The manufacturing method of the semiconductor device 1 includes forming the wiring 30 on the first resin portion 20 from the electrode 14. The wiring 30 may be formed by applying any known method.

半導体装置１の製造方法は、配線３０を覆う樹脂層４０を、第１の樹脂部２０上から第２の樹脂部２５の外側に至るように形成することを含む。   The manufacturing method of the semiconductor device 1 includes forming the resin layer 40 covering the wiring 30 so as to extend from the first resin part 20 to the outside of the second resin part 25.

半導体装置１の製造方法は、外部端子５０を形成することを含んでもよい。そして、図示しない根元補強材を形成する工程や、半導体基板を半導体ウエハで用意した場合には、これを個片に切り出す工程を経て、半導体装置１を製造してもよい。なお、半導体装置の製造方法として、半導体装置１の構成の説明で記載した内容から導き出せるいずれかの事項を適用してもよい。   The method for manufacturing the semiconductor device 1 may include forming the external terminal 50. The semiconductor device 1 may be manufactured through a step of forming a base reinforcing material (not shown) and a step of cutting the semiconductor substrate into individual pieces when the semiconductor substrate is prepared as a semiconductor wafer. As a method for manufacturing a semiconductor device, any matter that can be derived from the contents described in the description of the configuration of the semiconductor device 1 may be applied.

（変形例）
本発明は以上の実施の形態に限られず、種々の変形例が可能である。図６に示す例では、第２の樹脂部２５は、電極１４の半導体基板１０の周縁側の端部１５よりも内側の領域に形成されている。本実施の形態に係る半導体装置では、樹脂層（ソルダーレジスト）は、配線３０を覆うように形成される。そのため、第２の樹脂部２５が電極１４の端部１５よりも内側の領域に形成されている場合、配線３０を覆うように樹脂層を形成することによって、樹脂層は第２の樹脂部２５の外側に至るように形成される。すなわち、配線３０を覆う領域に樹脂層を形成することで発明の効果を発揮することができる。そのため、樹脂層の形成領域を小さくすることができ、樹脂層を半導体基板１０の端部から離して形成することが可能となる。これにより、樹脂層の収縮応力が半導体基板１０の端面にかからないようにすることができ、半導体装置の信頼性を高めることができる。また、第２の樹脂部２５を集積回路１２に近い位置に形成することによって、集積回路１２に応力がかかる事を防止することができる。特に、第２の樹脂部２５を、集積回路１２を構成する特定の素子の近傍に形成すれば、特定の素子を応力から保護することが可能となり、さらに信頼性の高い半導体装置を提供することができる。なお、図６に示すように、第２の樹脂部２５を、電極１４よりも内側の領域に形成してもよい。このとき、図６に示すように、配線３０を形成する領域を避けて、第２の樹脂部２５を形成してもよい。 (Modification)
The present invention is not limited to the above embodiment, and various modifications are possible. In the example shown in FIG. 6, the second resin portion 25 is formed in a region inside the end portion 15 on the peripheral side of the semiconductor substrate 10 of the electrode 14. In the semiconductor device according to the present embodiment, the resin layer (solder resist) is formed so as to cover the wiring 30. Therefore, when the second resin portion 25 is formed in a region inside the end portion 15 of the electrode 14, the resin layer is formed so as to cover the wiring 30, so that the resin layer becomes the second resin portion 25. It is formed so as to reach the outside. That is, the effect of the invention can be exhibited by forming the resin layer in the region covering the wiring 30. Therefore, the formation region of the resin layer can be reduced, and the resin layer can be formed away from the end portion of the semiconductor substrate 10. Thereby, the shrinkage stress of the resin layer can be prevented from being applied to the end surface of the semiconductor substrate 10, and the reliability of the semiconductor device can be improved. Further, by forming the second resin portion 25 at a position close to the integrated circuit 12, it is possible to prevent stress from being applied to the integrated circuit 12. In particular, if the second resin portion 25 is formed in the vicinity of a specific element constituting the integrated circuit 12, the specific element can be protected from stress, and a highly reliable semiconductor device is provided. Can do. Note that, as shown in FIG. 6, the second resin portion 25 may be formed in a region inside the electrode 14. At this time, as shown in FIG. 6, the second resin portion 25 may be formed avoiding the region where the wiring 30 is formed.

図７に示す例では、第２の樹脂部２５は、半導体基板１０の、互いに向かい合う一組の対辺のそれぞれのみに沿って形成されている。例えば、図７に示すように、半導体基板１０の、互いに向かい合う一組の対辺のそれぞれのみに沿って電極１４が形成されている場合、該対辺のそれぞれのみに沿って、第２の樹脂部２５が形成されていてもよい。これによっても、上記実施の形態と同様の効果を達成することができる。ただしこれとは別に、電極１４が形成されていない辺のみに沿って、第２の樹脂部が形成されてもよい（図示せず）。   In the example shown in FIG. 7, the second resin portion 25 is formed along each of a pair of opposite sides of the semiconductor substrate 10 facing each other. For example, as shown in FIG. 7, when the electrodes 14 are formed along only a pair of opposite sides of the semiconductor substrate 10 facing each other, the second resin portion 25 is formed along only the opposite sides. May be formed. Also by this, the same effect as the above embodiment can be achieved. However, separately from this, the second resin portion may be formed only along the side where the electrode 14 is not formed (not shown).

図８及び図９に示す例では、樹脂層４０は、第２の樹脂部２５の少なくとも上端部が露出するように形成されてなる。本発明を適用した実施の形態では、樹脂層４０（ソルダーレジスト）は、第２の樹脂部２５よりも外側に至るように形成される。そのため、第２の樹脂部２５の上端部が露出するように樹脂層４０が形成されていても、第２の樹脂部２５によって樹脂層４０の収縮応力を吸収することができ、上記実施の形態と同様の効果を達成することができる。なお、図９は、図８のIX−IX線断面の一部拡大図である。   8 and 9, the resin layer 40 is formed so that at least the upper end portion of the second resin portion 25 is exposed. In the embodiment to which the present invention is applied, the resin layer 40 (solder resist) is formed so as to reach the outer side than the second resin portion 25. Therefore, even if the resin layer 40 is formed so that the upper end portion of the second resin portion 25 is exposed, the contraction stress of the resin layer 40 can be absorbed by the second resin portion 25, and the above embodiment is described. The same effect can be achieved. 9 is a partially enlarged view of a cross section taken along line IX-IX in FIG.

図１０に示す例では、半導体装置は、第２の樹脂部２７を有する。第２の樹脂部２７は、電極１４の間を通り電極１４の外側の領域から電極１４の内側の領域に至る仕切り部２８を有する。すなわち、電極１４の間には仕切り部２８が形成される。本変形例では、仕切り部２８が障壁の役割を果たすため、電極１４間のマイグレーションを防止することが可能となり、さらに信頼性の高い半導体装置を提供することができる。なお、すべての電極１４の間に仕切り部２８が配置されるように、樹脂部２７を形成してもよい。あるいは、特定の電極１４間のみに仕切り部２８が配置されるように、選択的に樹脂部２７を形成してもよい。選択的に樹脂部２７を形成する場合、例えば、高電圧を印加する電極１４の両側に仕切り部２８が配置されるように、樹脂部２７を形成してもよい。あるいは、距離が近い位置に配置された２つの電極１４の間に仕切り部２８が配置されるように、樹脂部２７を形成してもよい。本変形例では、樹脂層（ソルダーレジスト）は、第２の樹脂部２７を覆うように形成されていてもよい（図示せず）。これによれば、半導体装置内に水分が浸入しにくくなるため、半導体装置の信頼性をさらに高めることができる。   In the example shown in FIG. 10, the semiconductor device has a second resin portion 27. The second resin portion 27 has a partition portion 28 that passes between the electrodes 14 and extends from a region outside the electrode 14 to a region inside the electrode 14. That is, a partition portion 28 is formed between the electrodes 14. In this modification, since the partition portion 28 serves as a barrier, migration between the electrodes 14 can be prevented, and a more reliable semiconductor device can be provided. Note that the resin portion 27 may be formed so that the partition portion 28 is disposed between all the electrodes 14. Alternatively, the resin portion 27 may be selectively formed so that the partition portion 28 is disposed only between the specific electrodes 14. When the resin portion 27 is selectively formed, for example, the resin portion 27 may be formed such that the partition portions 28 are disposed on both sides of the electrode 14 to which a high voltage is applied. Or you may form the resin part 27 so that the partition part 28 may be arrange | positioned between the two electrodes 14 arrange | positioned in the position with a short distance. In this modification, the resin layer (solder resist) may be formed so as to cover the second resin portion 27 (not shown). According to this, since it becomes difficult for moisture to enter the semiconductor device, the reliability of the semiconductor device can be further improved.

これらの変形例では、特に説明した事項以外の構成及び製造方法については、上記実施の形態で説明した内容を適用することができる。また、本発明を適用した実施の形態に係る半導体装置の構成は、以上に挙げたいずれかの内容を組み合わせたものであってもよい。   In these modified examples, the contents described in the above embodiment can be applied to configurations and manufacturing methods other than the matters specifically described. Further, the configuration of the semiconductor device according to the embodiment to which the present invention is applied may be a combination of any of the above-described contents.

なお、本発明は、上述した実施の形態に限定されるものではなく、種々の変形が可能である。例えば、本発明は、実施の形態で説明した構成と実質的に同一の構成（例えば、機能、方法及び結果が同一の構成、あるいは目的及び効果が同一の構成）を含む。また、本発明は、実施の形態で説明した構成の本質的でない部分を置き換えた構成を含む。また、本発明は、実施の形態で説明した構成と同一の作用効果を奏する構成又は同一の目的を達成することができる構成を含む。また、本発明は、実施の形態で説明した構成に公知技術を付加した構成を含む。   In addition, this invention is not limited to embodiment mentioned above, A various deformation | transformation is possible. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

図１は、本発明を適用した実施の形態に係る半導体装置を説明するための図である。FIG. 1 is a diagram for explaining a semiconductor device according to an embodiment to which the present invention is applied. 図２は、本発明を適用した実施の形態に係る半導体装置を説明するためのである。FIG. 2 is a view for explaining a semiconductor device according to an embodiment to which the present invention is applied. 図３は、本発明を適用した実施の形態に係る半導体装置が実装された回路基板を示す図である。FIG. 3 is a diagram showing a circuit board on which a semiconductor device according to an embodiment to which the present invention is applied is mounted. 図４は、本発明を適用した実施の形態に係る半導体装置を有する電子機器を示す図である。FIG. 4 is a diagram showing an electronic apparatus having a semiconductor device according to an embodiment to which the present invention is applied. 図５は、本発明を適用した実施の形態に係る半導体装置を有する電子機器を示す図である。FIG. 5 is a diagram showing an electronic apparatus having a semiconductor device according to an embodiment to which the present invention is applied. 図６は、本発明を適用した実施の形態に係る半導体装置の変形例を説明するための図である。FIG. 6 is a diagram for explaining a modification of the semiconductor device according to the embodiment to which the present invention is applied. 図７は、本発明を適用した実施の形態に係る半導体装置の変形例を説明するための図である。FIG. 7 is a diagram for explaining a modification of the semiconductor device according to the embodiment to which the present invention is applied. 図８は、本発明を適用した実施の形態に係る半導体装置の変形例を説明するための図である。FIG. 8 is a diagram for explaining a modification of the semiconductor device according to the embodiment to which the present invention is applied. 図９は、本発明を適用した実施の形態に係る半導体装置の変形例を説明するための図である。FIG. 9 is a diagram for explaining a modification of the semiconductor device according to the embodiment to which the present invention is applied. 図１０は、本発明を適用した実施の形態に係る半導体装置の変形例を説明するための図である。FIG. 10 is a diagram for explaining a modification of the semiconductor device according to the embodiment to which the present invention is applied.

符号の説明Explanation of symbols

１０ 半導体基板、 １２ 集積回路、 １４ 電極、 １６ 囲繞部材、
１８ パッシベーション膜、 ２０ 第１の樹脂部、 ２５ 第２の樹脂部、
３０ 配線、 ３２ ランド、 ４０ 樹脂層、 ５０ 外部端子 10 semiconductor substrate, 12 integrated circuit, 14 electrode, 16 surrounding member,
18 passivation film, 20 first resin part, 25 second resin part,
30 wirings, 32 lands, 40 resin layers, 50 external terminals

Claims (11)

内部に電気的に接続された電極を有する、集積回路が形成された半導体基板と、
前記半導体基板の前記電極が形成された面の中央部に形成された第１の樹脂部と、
前記半導体基板の前記電極が形成された面の前記第１の樹脂部よりも端部に近い領域に形成された複数の第２の樹脂部と、
前記電極上から前記第１の樹脂部上に形成された配線と、
前記配線を覆うように、前記第１の樹脂部上から前記第２の樹脂部の外側に至るように形成された樹脂層と、
を有し、
前記樹脂層は、前記第２の樹脂部の少なくとも上端部が露出するように形成されてなる半導体装置。 A semiconductor substrate on which an integrated circuit is formed having an electrode electrically connected to the inside;
A first resin portion formed at the center of the surface of the semiconductor substrate on which the electrodes are formed;
A plurality of second resin portions formed in a region closer to the end than the first resin portion of the surface of the semiconductor substrate on which the electrodes are formed;
Wiring formed on the first resin portion from the electrode;
A resin layer formed so as to cover the wiring from the first resin portion to the outside of the second resin portion;
Have
The resin layer is a semiconductor device formed such that at least an upper end portion of the second resin portion is exposed. 請求項１記載の半導体装置において、
前記第２の樹脂部は、前記半導体基板のすべての辺のそれぞれに沿って形成されてなる半導体装置。 The semiconductor device according to claim 1,
The second resin portion is a semiconductor device formed along each of all sides of the semiconductor substrate. 請求項１又は請求項２記載の半導体装置において、
前記第２の樹脂部は、前記電極を避けて形成されてなる半導体装置。 The semiconductor device according to claim 1 or 2,
The second resin portion is a semiconductor device formed so as to avoid the electrode. 請求項１から請求項３のいずれかに記載の半導体装置において、
前記第２の樹脂部は、前記電極の間を通り前記電極の外側の領域から前記電極の内側の領域に至る仕切り部を有する半導体装置。 The semiconductor device according to any one of claims 1 to 3,
The second resin portion is a semiconductor device having a partition portion that passes between the electrodes and extends from a region outside the electrodes to a region inside the electrodes. 請求項１から請求項４のいずれかに記載の半導体装置が実装された回路基板。   A circuit board on which the semiconductor device according to claim 1 is mounted. 請求項１から請求項４のいずれかに記載の半導体装置を有する電子機器。   An electronic apparatus comprising the semiconductor device according to claim 1. 内部に電気的に接続された電極を有する、集積回路が形成された半導体基板を用意すること、
前記半導体基板の前記電極が形成された面の中央部に、第１の樹脂部を形成すること、
前記半導体基板の前記電極が形成された面の前記第１の樹脂部よりも端部に近い領域に、複数の第２の樹脂部を形成すること、
前記電極上から、前記第１の樹脂部上に配線を形成すること、及び、
前記配線を覆う樹脂層を、前記第１の樹脂部上から前記第２の樹脂部の外側に至るように形成することを含み、
前記樹脂層を、前記第２の樹脂部の少なくとも上端部が露出するように形成する半導体装置の製造方法。 Providing a semiconductor substrate on which an integrated circuit is formed having an electrode electrically connected to the inside;
Forming a first resin portion at a central portion of the surface of the semiconductor substrate on which the electrodes are formed;
Forming a plurality of second resin portions in a region closer to an end portion than the first resin portion of the surface of the semiconductor substrate on which the electrodes are formed;
Forming a wiring on the first resin part from the electrode; and
Forming a resin layer covering the wiring from the first resin portion to the outside of the second resin portion,
A method of manufacturing a semiconductor device, wherein the resin layer is formed so that at least an upper end portion of the second resin portion is exposed. 請求項７記載の半導体装置の製造方法において、
前記第２の樹脂部を、前記半導体基板のすべての辺のそれぞれに沿って形成する半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 7.
A method of manufacturing a semiconductor device, wherein the second resin portion is formed along each of all sides of the semiconductor substrate. 請求項７又は請求項８記載の半導体装置の製造方法において、
前記第２の樹脂部を、前記電極を避けて形成する半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 7 or claim 8,
A method of manufacturing a semiconductor device, wherein the second resin portion is formed avoiding the electrode. 請求項７から請求項９のいずれかに記載の半導体装置の製造方法において、
前記第１の樹脂部と前記第２の樹脂部とを、一括して形成する半導体装置の製造方法。 In the manufacturing method of the semiconductor device in any one of Claims 7-9,
A method of manufacturing a semiconductor device, wherein the first resin portion and the second resin portion are formed in a lump. 請求項７から請求項１０のいずれかに記載の半導体装置の製造方法において、
前記第２の樹脂部を、前記電極の間を通り前記電極の外側の領域から前記電極の内側の領域に至る仕切り部を有するように形成する半導体装置の製造方法。 In the manufacturing method of the semiconductor device in any one of Claims 7-10,
A method of manufacturing a semiconductor device, wherein the second resin portion is formed so as to have a partition portion that passes between the electrodes and extends from a region outside the electrodes to a region inside the electrodes.
JP2005042340A 2005-02-18 2005-02-18 Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus Expired - Fee Related JP4240226B2 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998025297A1 (en) * 1996-12-04 1998-06-11 Seiko Epson Corporation Electronic component and semiconductor device, method for manufacturing and mounting thereof, and circuit board and electronic equipment
JP2001077237A (en) * 1999-09-07 2001-03-23 Matsushita Electronics Industry Corp Semiconductor device and manufacture thereof
JP2001144217A (en) * 1999-11-17 2001-05-25 Seiko Epson Corp Semiconductor device and method of manufacture, circuit board and electronic apparatus
JP2003023009A (en) * 2001-07-10 2003-01-24 Toppan Printing Co Ltd Semiconductor device and method of manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998025297A1 (en) * 1996-12-04 1998-06-11 Seiko Epson Corporation Electronic component and semiconductor device, method for manufacturing and mounting thereof, and circuit board and electronic equipment
JP2001077237A (en) * 1999-09-07 2001-03-23 Matsushita Electronics Industry Corp Semiconductor device and manufacture thereof
JP2001144217A (en) * 1999-11-17 2001-05-25 Seiko Epson Corp Semiconductor device and method of manufacture, circuit board and electronic apparatus
JP2003023009A (en) * 2001-07-10 2003-01-24 Toppan Printing Co Ltd Semiconductor device and method of manufacturing the same

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