JP2005116957A - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- JP2005116957A JP2005116957A JP2003352442A JP2003352442A JP2005116957A JP 2005116957 A JP2005116957 A JP 2005116957A JP 2003352442 A JP2003352442 A JP 2003352442A JP 2003352442 A JP2003352442 A JP 2003352442A JP 2005116957 A JP2005116957 A JP 2005116957A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 116
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- 239000002313 adhesive film Substances 0.000 claims abstract description 104
- 238000000034 method Methods 0.000 claims abstract description 104
- 239000000758 substrate Substances 0.000 claims abstract description 66
- 238000005520 cutting process Methods 0.000 claims abstract description 18
- 230000001681 protective effect Effects 0.000 claims description 82
- 238000007789 sealing Methods 0.000 abstract description 19
- 238000011049 filling Methods 0.000 abstract description 2
- 238000004026 adhesive bonding Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 149
- 239000010410 layer Substances 0.000 description 143
- 235000012431 wafers Nutrition 0.000 description 49
- 229920005989 resin Polymers 0.000 description 38
- 239000011347 resin Substances 0.000 description 38
- 230000001070 adhesive effect Effects 0.000 description 35
- 239000000853 adhesive Substances 0.000 description 34
- 229920001187 thermosetting polymer Polymers 0.000 description 20
- 239000011230 binding agent Substances 0.000 description 19
- 238000000227 grinding Methods 0.000 description 13
- 229920001169 thermoplastic Polymers 0.000 description 12
- 239000004416 thermosoftening plastic Substances 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 10
- 239000002390 adhesive tape Substances 0.000 description 9
- 238000010438 heat treatment Methods 0.000 description 8
- 239000000203 mixture Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 239000000945 filler Substances 0.000 description 5
- 239000002245 particle Substances 0.000 description 5
- -1 polyethylene Polymers 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 229920001225 polyester resin Polymers 0.000 description 4
- 239000004645 polyester resin Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000000843 powder Substances 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 229920000178 Acrylic resin Polymers 0.000 description 3
- 239000004925 Acrylic resin Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 238000002156 mixing Methods 0.000 description 3
- 239000005011 phenolic resin Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 239000009719 polyimide resin Substances 0.000 description 3
- 229920002803 thermoplastic polyurethane Polymers 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- VGGSQFUCUMXWEO-UHFFFAOYSA-N Ethene Chemical compound C=C VGGSQFUCUMXWEO-UHFFFAOYSA-N 0.000 description 2
- 239000005977 Ethylene Substances 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- PPBRXRYQALVLMV-UHFFFAOYSA-N Styrene Chemical compound C=CC1=CC=CC=C1 PPBRXRYQALVLMV-UHFFFAOYSA-N 0.000 description 2
- 150000001252 acrylic acid derivatives Chemical class 0.000 description 2
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 239000002216 antistatic agent Substances 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229920001577 copolymer Polymers 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000007822 coupling agent Substances 0.000 description 2
- 239000003431 cross linking reagent Substances 0.000 description 2
- 239000000975 dye Substances 0.000 description 2
- 229920001971 elastomer Polymers 0.000 description 2
- 239000003063 flame retardant Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000011256 inorganic filler Substances 0.000 description 2
- 229910003475 inorganic filler Inorganic materials 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000000049 pigment Substances 0.000 description 2
- 239000004800 polyvinyl chloride Substances 0.000 description 2
- 229920000915 polyvinyl chloride Polymers 0.000 description 2
- GHMLBKRAJCXXBS-UHFFFAOYSA-N resorcinol Chemical compound OC1=CC=CC(O)=C1 GHMLBKRAJCXXBS-UHFFFAOYSA-N 0.000 description 2
- 230000002441 reversible effect Effects 0.000 description 2
- 239000005060 rubber Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- MYWOJODOMFBVCB-UHFFFAOYSA-N 1,2,6-trimethylphenanthrene Chemical compound CC1=CC=C2C3=CC(C)=CC=C3C=CC2=C1C MYWOJODOMFBVCB-UHFFFAOYSA-N 0.000 description 1
- CMLFRMDBDNHMRA-UHFFFAOYSA-N 2h-1,2-benzoxazine Chemical compound C1=CC=C2C=CNOC2=C1 CMLFRMDBDNHMRA-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-M Acrylate Chemical compound [O-]C(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-M 0.000 description 1
- 229920002126 Acrylic acid copolymer Polymers 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 239000004831 Hot glue Substances 0.000 description 1
- 239000004640 Melamine resin Substances 0.000 description 1
- 229920000877 Melamine resin Polymers 0.000 description 1
- CERQOIWHTDAKMF-UHFFFAOYSA-N Methacrylic acid Chemical compound CC(=C)C(O)=O CERQOIWHTDAKMF-UHFFFAOYSA-N 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- 239000005062 Polybutadiene Substances 0.000 description 1
- 239000004698 Polyethylene Substances 0.000 description 1
- 239000004743 Polypropylene Substances 0.000 description 1
- 239000004793 Polystyrene Substances 0.000 description 1
- 239000004820 Pressure-sensitive adhesive Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- DAKWPKUUDNSNPN-UHFFFAOYSA-N Trimethylolpropane triacrylate Chemical compound C=CC(=O)OCC(CC)(COC(=O)C=C)COC(=O)C=C DAKWPKUUDNSNPN-UHFFFAOYSA-N 0.000 description 1
- 229920001807 Urea-formaldehyde Polymers 0.000 description 1
- MPIAGWXWVAHQBB-UHFFFAOYSA-N [3-prop-2-enoyloxy-2-[[3-prop-2-enoyloxy-2,2-bis(prop-2-enoyloxymethyl)propoxy]methyl]-2-(prop-2-enoyloxymethyl)propyl] prop-2-enoate Chemical compound C=CC(=O)OCC(COC(=O)C=C)(COC(=O)C=C)COCC(COC(=O)C=C)(COC(=O)C=C)COC(=O)C=C MPIAGWXWVAHQBB-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- DQXBYHZEEUGOBF-UHFFFAOYSA-N but-3-enoic acid;ethene Chemical compound C=C.OC(=O)CC=C DQXBYHZEEUGOBF-UHFFFAOYSA-N 0.000 description 1
- QHIWVLPBUQWDMQ-UHFFFAOYSA-N butyl prop-2-enoate;methyl 2-methylprop-2-enoate;prop-2-enoic acid Chemical compound OC(=O)C=C.COC(=O)C(C)=C.CCCCOC(=O)C=C QHIWVLPBUQWDMQ-UHFFFAOYSA-N 0.000 description 1
- 239000006229 carbon black Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229920001940 conductive polymer Polymers 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 229910002026 crystalline silica Inorganic materials 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- UHESRSKEBRADOO-UHFFFAOYSA-N ethyl carbamate;prop-2-enoic acid Chemical compound OC(=O)C=C.CCOC(N)=O UHESRSKEBRADOO-UHFFFAOYSA-N 0.000 description 1
- 239000005038 ethylene vinyl acetate Substances 0.000 description 1
- 239000013538 functional additive Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003999 initiator Substances 0.000 description 1
- 229920000554 ionomer Polymers 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229920002601 oligoester Polymers 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920001200 poly(ethylene-vinyl acetate) Polymers 0.000 description 1
- 229920002037 poly(vinyl butyral) polymer Polymers 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229920006122 polyamide resin Polymers 0.000 description 1
- 229920000767 polyaniline Polymers 0.000 description 1
- 229920002857 polybutadiene Polymers 0.000 description 1
- 229920001083 polybutene Polymers 0.000 description 1
- 229920001707 polybutylene terephthalate Polymers 0.000 description 1
- 229920006289 polycarbonate film Polymers 0.000 description 1
- 229920000573 polyethylene Polymers 0.000 description 1
- 229920006290 polyethylene naphthalate film Polymers 0.000 description 1
- 229920000139 polyethylene terephthalate Polymers 0.000 description 1
- 239000005020 polyethylene terephthalate Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 229920000306 polymethylpentene Polymers 0.000 description 1
- 239000011116 polymethylpentene Substances 0.000 description 1
- 229920001155 polypropylene Polymers 0.000 description 1
- 229920000128 polypyrrole Polymers 0.000 description 1
- 229920002223 polystyrene Polymers 0.000 description 1
- 229920005990 polystyrene resin Polymers 0.000 description 1
- 229920006264 polyurethane film Polymers 0.000 description 1
- 229920002689 polyvinyl acetate Polymers 0.000 description 1
- 239000011118 polyvinyl acetate Substances 0.000 description 1
- 229920001289 polyvinyl ether Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68313—Auxiliary support including a cavity for storing a finished device, e.g. IC package, or a partly finished device, e.g. die, during manufacturing or mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
- H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
本発明は、半導体チップの固着に用いられる接着剤層を回路面に簡便に形成でき、かつ均一性の高い保護膜を、チップ裏面および側面に簡便に形成でき、しかも機械研削によってチップ裏面に微小な傷が形成されたとしても、かかる傷に起因する悪影響を解消できる半導体装置の製造方法に関する。 In the present invention, an adhesive layer used for fixing a semiconductor chip can be easily formed on the circuit surface, and a highly uniform protective film can be easily formed on the back surface and side surface of the chip. The present invention relates to a method for manufacturing a semiconductor device capable of eliminating the adverse effects caused by such scratches even if such scratches are formed.
近年、ICチップの実装方法が多様化しており、ICチップ回路面が下側に配置されるパッケージング方法がある。このようなパッケージング方法はフェースダウン(face down)方式あるいはフリップチップボンディングとも呼ばれている。このパッケージング方法
では、凸状の電極素子が回路表面より突出して形成されており、その高低差は30μm以上となり、また場合によっては100μmを超えるものも現れている。このような半導体ウエハの表面に形成される凸状部分はバンプと呼ばれている。フリップチップボンディングでは、このバンプを介して、リードフレーム等のチップ搭載用基板とチップとの導通が確保される。
In recent years, IC chip mounting methods have been diversified, and there is a packaging method in which an IC chip circuit surface is disposed on the lower side. Such a packaging method is also called a face down method or flip chip bonding. In this packaging method, convex electrode elements are formed so as to protrude from the circuit surface, and the height difference thereof is 30 μm or more, and in some cases, some of them exceed 100 μm. Such convex portions formed on the surface of the semiconductor wafer are called bumps. In flip chip bonding, conduction between a chip mounting substrate such as a lead frame and the chip is ensured through the bumps.
また、一般に半導体装置においては、回路面を保護するために、樹脂により封止されている。上記のような高バンプチップを用いた半導体装置においても同様であり、具体的には、次の手法により樹脂封止が行われている。
(1)バンプが形成されているチップをチップ搭載用基板に載置し、バンプを介してチップとチップ搭載用基板とを接続し、その後樹脂封止する。
(2)異方導電性ペーストを介して高バンプチップとチップ搭載用基板とを接続し、その後樹脂封止する。
In general, a semiconductor device is sealed with resin in order to protect the circuit surface. The same applies to the semiconductor device using the high bump chip as described above. Specifically, resin sealing is performed by the following method.
(1) The chip on which the bump is formed is placed on the chip mounting substrate, the chip and the chip mounting substrate are connected via the bump, and then resin-sealed.
(2) The high bump chip and the chip mounting substrate are connected through an anisotropic conductive paste, and then resin-sealed.
しかし、上記(1)の方法においては、バンプの高さの分だけ、チップとチップ搭載用基板との間に空間があり、樹脂封止を行っても、この空間に封止用の樹脂が充分に侵入せず、ボイドが発生することがある。このため、樹脂封止の前に、チップとチップ搭載用基板との間に絶縁性樹脂(アンダーフィル)を充填する必要があった。 However, in the method (1), there is a space between the chip and the chip mounting substrate by the height of the bump, and even if resin sealing is performed, the sealing resin is in this space. Insufficient penetration may cause voids. For this reason, it is necessary to fill an insulating resin (underfill) between the chip and the chip mounting substrate before resin sealing.
また上記(2)の方法では、微小なチップに、異方導電性ペーストを塗布する必要があり、やはり作業工程上煩雑である。特に異方導電性ペーストは、一定量を塗布することが困難であり、製品毎にペーストの量が異なり、製品特性にバラツキがでる虞もある。 In the method (2), it is necessary to apply an anisotropic conductive paste to a minute chip, which is also complicated in terms of work steps. In particular, it is difficult to apply a certain amount of anisotropic conductive paste, and the amount of paste differs from product to product, which may cause variations in product characteristics.
このような課題を解決するため、特許文献1においては、「表面に回路が形成された半導体ウエハの回路面に、接着性薄膜層を形成し、
該半導体ウエハを、回路毎に個別のチップに切断分離し、
該個別のチップを該接着性薄膜層を介して、チップ搭載用基板の所定位置に載置し、
該個別のチップと該チップ搭載用基板との導通を確保しながら該個別のチップを該チップ搭載用基板に接着固定することを特徴とする半導体装置の製造方法。」が開示されている。
In order to solve such a problem, in Patent Document 1, “an adhesive thin film layer is formed on a circuit surface of a semiconductor wafer on which a circuit is formed on the surface,
The semiconductor wafer is cut and separated into individual chips for each circuit,
The individual chip is placed at a predetermined position of the chip mounting substrate through the adhesive thin film layer,
A method for manufacturing a semiconductor device, comprising: bonding and fixing the individual chip to the chip mounting substrate while ensuring conduction between the individual chip and the chip mounting substrate. Is disclosed.
このような特許文献1に記載の製法によれば、接着性薄膜層をウエハ回路面に形成し、ダイシングを行い、チップを得ている。得られるチップの回路面には接着性薄膜層が密着しているため、樹脂封止時のボイド発生を防止でき、また均一性、信頼性の高い製品が得られる。 According to such a manufacturing method described in Patent Document 1, an adhesive thin film layer is formed on a wafer circuit surface, and dicing is performed to obtain a chip. Since the adhesive thin film layer is in close contact with the circuit surface of the resulting chip, voids can be prevented during resin sealing, and a product with high uniformity and reliability can be obtained.
また、半導体ウエハは、一般にウエハプロセスの終了後、厚みを均一にし、酸化被膜を
除去するために、裏面研削が行われる。裏面研削では、機械研削によってチップ裏面に微小な筋状の傷が形成される。この微小な傷は、パッケージングの後に、クラック発生の原因となることがある。このため、従来は、機械研削後に、微小な傷を除くためのケミカルエッチングが必要になる場合があった。しかし、ケミカルエッチングには、もとより設備費、運転費が必要になり、コスト増の原因となる。
Further, the semiconductor wafer is generally subjected to back surface grinding after the completion of the wafer process in order to make the thickness uniform and remove the oxide film. In back surface grinding, minute streak-like scratches are formed on the back surface of the chip by mechanical grinding. This minute scratch may cause cracking after packaging. For this reason, conventionally, chemical etching for removing minute scratches may be necessary after mechanical grinding. However, chemical etching necessitates equipment and operation costs as well as the cost increase.
したがって、機械研削によってチップ裏面に微小な傷が形成されたとしても、かかる傷に起因する悪影響を解消する技術の開発が要望されている。 Therefore, even if a minute scratch is formed on the back surface of the chip by mechanical grinding, there is a demand for the development of a technique that eliminates the adverse effects caused by the scratch.
このような技術としては、既に本願出願人により、「剥離シートと、該剥離シートの剥離面上に形成された、熱硬化性成分および/またはエネルギー線硬化性成分とバインダーポリマー成分とからなる保護膜形成層とを有するチップ用保護膜形成用シート」が開示されている(特許文献2参照)。また特許文献2には、上記チップ用保護膜形成用シートを半導体ウエハの裏面側に貼付し、これをウエハとともにダイシングする工程を含む、保護膜付きチップの製造方法が開示されている。 As such a technique, the applicant of the present application has already said, "Protection comprising a release sheet, a thermosetting component and / or an energy ray curable component and a binder polymer component formed on the release surface of the release sheet. A "protective film forming sheet for chips having a film forming layer" is disclosed (see Patent Document 2). Patent Document 2 discloses a method for manufacturing a chip with a protective film, which includes a step of pasting the protective film forming sheet for a chip on the back side of a semiconductor wafer and dicing the sheet together with the wafer.
しかし、いずれの特許文献の方法においても、チップの一面のみを保護するにとどまり、その他の面も完全に保護するには従来採用されている封止方法の一部を別途採用しなければならない。また、特許文献1及び特許文献2の方法を両方採用したとしても、チップの側面が開放されているため、充分な保護がなされていない。これらの特許文献の方法と従来の封止方法との併用は、簡易な方法で封止が可能となるという、その発明の効果が得られない。
本発明は、上記のような問題に鑑みてなされたものであり、フリップチップボンディングを行う半導体装置の封止方法(アンダーフィルの充填工程を含む)を、従来の封止方法と併用することなく簡便方法のみで完成させられ、かつ、従来の封止方法と同様チップの全ての面を充分に保護できる半導体装置の製造方法を提供することを目的としている。 The present invention has been made in view of the above problems, and a semiconductor device sealing method (including an underfill filling step) for performing flip chip bonding is not used in combination with a conventional sealing method. An object of the present invention is to provide a method of manufacturing a semiconductor device which can be completed only by a simple method and can sufficiently protect all surfaces of a chip as in a conventional sealing method.
本発明に係る半導体装置の第1の製造方法は、
表面に回路が形成された半導体ウエハの回路面に、接着膜形成層を形成する工程、
該半導体ウエハおよび接着膜形成層を、フルカットダイシングしてチップ化する工程、
各半導体チップの裏面および側面に、保護膜形成層を貼着する工程、
個々の半導体チップ毎に分割されるように保護膜形成層を切断する工程、および
個別のチップを、該接着膜形成層を介して、チップ搭載用基板の所定位置に載置し、該個別のチップと該チップ搭載用基板との導通を確保しながら該個別のチップを該チップ搭載用基板に接着固定する工程を含む。
A first manufacturing method of a semiconductor device according to the present invention includes:
Forming an adhesive film forming layer on a circuit surface of a semiconductor wafer having a circuit formed on the surface;
A step of full-cut dicing the semiconductor wafer and the adhesive film forming layer into chips;
A process of attaching a protective film forming layer to the back and side surfaces of each semiconductor chip;
A step of cutting the protective film forming layer so as to be divided into individual semiconductor chips, and placing the individual chips at predetermined positions on the chip mounting substrate via the adhesive film forming layer. A step of bonding and fixing the individual chip to the chip mounting substrate while ensuring conduction between the chip and the chip mounting substrate.
本発明に係る半導体装置の第2の製造方法は、
表面に回路が形成された半導体ウエハをダイシングしてチップ化する工程、
各半導体チップの回路面に、接着膜形成層を形成する工程、
各半導体チップの裏面および側面に、保護膜形成層を貼着する工程、
個々の半導体チップ毎に分割されるように保護膜形成層を切断する工程、および
個別のチップを、該接着膜形成層を介して、チップ搭載用基板の所定位置に載置し、該個別のチップと該チップ搭載用基板との導通を確保しながら該個別のチップを該チップ搭載用基板に接着固定する工程を含む。
A second method for manufacturing a semiconductor device according to the present invention is as follows.
A step of dicing a semiconductor wafer having a circuit formed on its surface into chips,
Forming an adhesive film forming layer on the circuit surface of each semiconductor chip;
A process of attaching a protective film forming layer to the back and side surfaces of each semiconductor chip;
A step of cutting the protective film forming layer so as to be divided into individual semiconductor chips, and placing the individual chips at predetermined positions on the chip mounting substrate via the adhesive film forming layer. A step of bonding and fixing the individual chip to the chip mounting substrate while ensuring conduction between the chip and the chip mounting substrate.
本発明に係る半導体装置の第3の製造方法は、
表面に回路が形成された半導体ウエハをダイシングしてチップ化する工程、
各半導体チップの裏面および側面に、保護膜形成層を貼着する工程、
個々の半導体チップ毎に分割されるように保護膜形成層を切断する工程、
各半導体チップの回路面に、接着膜形成層を形成する工程、
および
個別のチップを、該接着膜形成層を介して、チップ搭載用基板の所定位置に載置し、該個別のチップと該チップ搭載用基板との導通を確保しながら該個別のチップを該チップ搭載用基板に接着固定する工程を含む。
A third manufacturing method of a semiconductor device according to the present invention is as follows:
A step of dicing a semiconductor wafer having a circuit formed on its surface into chips,
A process of attaching a protective film forming layer to the back and side surfaces of each semiconductor chip;
Cutting the protective film forming layer so as to be divided into individual semiconductor chips,
Forming an adhesive film forming layer on the circuit surface of each semiconductor chip;
And an individual chip is placed at a predetermined position on the chip mounting substrate via the adhesive film forming layer, and the individual chip is mounted on the chip mounting substrate while ensuring conduction between the individual chip and the chip mounting substrate. A step of bonding and fixing to the chip mounting substrate.
このような本発明に係わる半導体装置の製造方法によれば、フリップチップボンディングを行う半導体装置を、従来の封止方法を併用することなく簡便な方法のみでチップの全面に対し封止が行うことができ、しかも、従来の方法と同様の保護が施されているので充分な信頼性を有する半導体装置を製造できる。 According to such a method for manufacturing a semiconductor device according to the present invention, a semiconductor device for performing flip chip bonding can be sealed on the entire surface of the chip only by a simple method without using a conventional sealing method. In addition, since the same protection as that of the conventional method is performed, a semiconductor device having sufficient reliability can be manufactured.
以下、本発明について図面を参照しながらさらに具体的に説明する。 Hereinafter, the present invention will be described more specifically with reference to the drawings.
本発明に係る製造方法の各工程を説明する前に、まず第1〜第3の製法における共通の要素である半導体ウエハ1、接着膜形成層を形成するための接着膜形成用シート10、保護膜形成層を形成するための保護膜形成用シート20について説明する。 Before explaining each step of the manufacturing method according to the present invention, first, a semiconductor wafer 1 which is a common element in the first to third manufacturing methods, an adhesive film forming sheet 10 for forming an adhesive film forming layer, protection The protective film forming sheet 20 for forming the film forming layer will be described.
「半導体ウエハ1」
半導体ウエハ1としては、従来より用いられているシリコン半導体ウエハ、ガリウム・ヒ素半導体ウエハなどが挙げられるが、これらに限定されず、種々の半導体ウエハを用いることができる。ウエハ表面への回路の形成は、エッチング法、リフトオフ法などの従来より汎用されている方法を含む、様々な方法により行うことができる。半導体ウエハの回路形成工程において、所定の回路が形成される。また回路面には、チップ搭載用基板との導通に用いられる導通用突起物(バンプ)2が形成されていることが望ましい。バンプ2の高さ、径は、半導体装置の設計に応じ様々だが、一般的には、高さは10〜100μm程度であり、径は20〜100μm程度である。このようなバンプ2は、金、銅、ハンダ等の金属から形成されることが多い。
"Semiconductor wafer 1"
Examples of the semiconductor wafer 1 include conventionally used silicon semiconductor wafers and gallium / arsenic semiconductor wafers, but are not limited thereto, and various semiconductor wafers can be used. Formation of a circuit on the wafer surface can be performed by various methods including conventionally used methods such as an etching method and a lift-off method. In the semiconductor wafer circuit forming step, a predetermined circuit is formed. Further, it is desirable that conductive protrusions (bumps) 2 used for electrical connection with the chip mounting substrate are formed on the circuit surface. The height and diameter of the bump 2 vary depending on the design of the semiconductor device, but generally the height is about 10 to 100 μm and the diameter is about 20 to 100 μm. Such bumps 2 are often formed from a metal such as gold, copper, or solder.
「接着膜形成用シート10」
接着膜形成用シート10は、支持フィルム11と支持フィルム11の片面に形成された接着膜形成層12の積層体よりなる。支持フィルム11は、接着膜形成層12が転写可能なように、接着膜形成層12に面した側が剥離性を有する。
"Adhesive film forming sheet 10"
The adhesive film forming sheet 10 is composed of a laminate of a support film 11 and an adhesive film forming layer 12 formed on one side of the support film 11. The side of the support film 11 facing the adhesive film forming layer 12 is peelable so that the adhesive film forming layer 12 can be transferred.
支持フィルム11としては、接着膜形成用シート10がバンプが形成された面に着実に密着させられるように、可撓性、追従性に優れたフィルムが好ましく、たとえばポリエチレンフィルム、ポリプロピレンフィルム、ポリブテンフィルム、ポリブタジエンフィルム、ポリメチルペンテンフィルム、ポリ塩化ビニルフィルム、塩化ビニル共重合体フィルム、ポリウレタンフィルム、エチレン酢ビフィルム、アイオノマー樹脂フィルム、エチレン・(メタ)アクリル酸共重合体フィルム、エチレン・(メタ)アクリル酸エステル共重合体フィルム等が用いられる。またこれらの架橋フィルムも用いられる。さらにこれらの積層フィルムであってもよい。 The support film 11 is preferably a film excellent in flexibility and followability so that the adhesive film forming sheet 10 can be steadily adhered to the surface on which the bumps are formed. For example, a polyethylene film, a polypropylene film, a polybutene film is preferable. , Polybutadiene film, polymethylpentene film, polyvinyl chloride film, vinyl chloride copolymer film, polyurethane film, ethylene vinyl acetate film, ionomer resin film, ethylene / (meth) acrylic acid copolymer film, ethylene / (meth) acrylic An acid ester copolymer film or the like is used. These crosslinked films are also used. Furthermore, these laminated films may be sufficient.
さらに支持フィルム11の表面張力は、好ましくは40mN/m以下、さらに好ましく
は37mN/m以下、特に好ましくは35mN/m以下であることが望ましい。このような表面張力の低い支持フィルム11は、材質を適宜に選択して得ることが可能であるし、またフィルムの表面にシリコーン樹脂等を塗布して離型処理を施すことで得ることもできる。
Furthermore, the surface tension of the support film 11 is preferably 40 mN / m or less, more preferably 37 mN / m or less, and particularly preferably 35 mN / m or less. Such a support film 11 having a low surface tension can be obtained by appropriately selecting the material, and can also be obtained by applying a silicone resin or the like to the surface of the film and performing a release treatment. .
支持フィルム11の膜厚は、通常は5〜300μm、好ましくは10〜200μm、特に好ましくは20〜150μm程度である。 The film thickness of the support film 11 is usually about 5 to 300 μm, preferably about 10 to 200 μm, and particularly preferably about 20 to 150 μm.
接着膜形成層12は、従来の封止方法におけるアンダーフィルと同等の役割をなす層であり、半導体チップ3とチップ搭載用基板30とを接着するとともに、接着膜形成層12を介して双方の導通が行われる。接着膜形成層12は、絶縁性接着剤または異方導電性接着剤からなる。 The adhesive film forming layer 12 is a layer having a role equivalent to that of the underfill in the conventional sealing method. The adhesive film forming layer 12 adheres the semiconductor chip 3 and the chip mounting substrate 30 and both of them through the adhesive film forming layer 12. Conduction is performed. The adhesive film forming layer 12 is made of an insulating adhesive or an anisotropic conductive adhesive.
絶縁性の接着膜形成層12は、熱可塑性、熱硬化性あるいは粘接着性であってもよい。粘接着性とは、常温時で感圧接着性を示し加熱により硬化し強固な接着性を示す接着剤をいう。 The insulating adhesive film forming layer 12 may be thermoplastic, thermosetting, or adhesive. The adhesiveness refers to an adhesive that exhibits pressure-sensitive adhesiveness at room temperature, cures by heating, and exhibits strong adhesiveness.
熱可塑性の接着膜形成層は、熱可塑性のバインダー樹脂を主成分とするものよりなる。熱可塑性のバインダー樹脂としては、たとえばポリエステル樹脂、ポリ酢酸ビニル樹脂、ポリビニルブチラール樹脂、ポリ塩化ビニル樹脂、アクリル樹脂、ポリスチレン樹脂、ウレタン樹脂、ポリアミド樹脂、ポリイミド樹脂、各種のホットメルト系接着剤が用いられ、好ましくはポリエステル樹脂、ポリイミド樹脂が用いられる。 The thermoplastic adhesive film forming layer is composed of a material mainly composed of a thermoplastic binder resin. Examples of thermoplastic binder resins include polyester resins, polyvinyl acetate resins, polyvinyl butyral resins, polyvinyl chloride resins, acrylic resins, polystyrene resins, urethane resins, polyamide resins, polyimide resins, and various hot melt adhesives. Preferably, a polyester resin or a polyimide resin is used.
熱硬化性の接着膜形成層は、熱硬化性のバインダー樹脂を主成分とするものよりなる。熱硬化性のバインダー樹脂としては、たとえばエポキシ樹脂、アクリル樹脂、ポリイミド樹脂、フェノール樹脂、尿素樹脂、メラミン樹脂、レゾルシノール樹脂、ウレタン樹脂、ポリエステル樹脂、ベンゾオキサジン樹脂等が用いられ、好ましくはエポキシ樹脂、フェノール樹脂、エポキシ樹脂とフェノール樹脂の混合系が用いられる。 The thermosetting adhesive film forming layer is composed of a thermosetting binder resin as a main component. As the thermosetting binder resin, for example, epoxy resin, acrylic resin, polyimide resin, phenol resin, urea resin, melamine resin, resorcinol resin, urethane resin, polyester resin, benzoxazine resin, etc. are used, preferably epoxy resin, A phenol resin or a mixed system of an epoxy resin and a phenol resin is used.
粘接着性の接着膜形成層は、たとえば常温で粘着性を有するバインダー樹脂と熱硬化性樹脂との混合物が挙げられる。常温で感圧接着性を有するバインダー樹脂としては、たとえばアクリル樹脂、ポリエステル樹脂、ポリビニルエーテル、ウレタン樹脂、ポリアミド等が挙げられる。熱硬化性樹脂としては、前述の熱硬化性のバインダー樹脂と同種の樹脂があげられ、バインダー樹脂よりも比較的低分子量のものが使用できる。 Examples of the adhesive film-forming layer that is adhesive include a mixture of a binder resin and a thermosetting resin that are adhesive at room temperature. Examples of the binder resin having pressure-sensitive adhesive properties at room temperature include acrylic resins, polyester resins, polyvinyl ethers, urethane resins, and polyamides. Examples of the thermosetting resin include the same type of resin as the above-described thermosetting binder resin, and those having a relatively low molecular weight than the binder resin can be used.
また異方導電性の接着膜形成層も同様に、熱可塑性、熱硬化性あるいは粘接着性のものが使用できる。異方導電性の接着膜形成層は、通常、前述の絶縁性の接着膜形成層に導電性粒子が分散されたものであり、使用前では、接着膜形成層中の導電性粒子は互いに接触しない範囲でバインダー樹脂中に存在し、フリップチップボンディングの際、チップとチップ搭載用基板との間で圧着されると、電極としての導電性突起物が接着膜形成層を圧縮し、接着膜形成層の厚さ方向のみに導電性粒子が接触し、平面方向では絶縁であり厚み方向のみに導通する、異方導電性を発現するものである。 Similarly, an anisotropic conductive adhesive film-forming layer can be used which is thermoplastic, thermosetting or adhesive. An anisotropic conductive adhesive film forming layer is usually a conductive particle dispersed in the above-mentioned insulating adhesive film forming layer, and before use, the conductive particles in the adhesive film forming layer are in contact with each other. It exists in the binder resin to the extent that it does not, and when flip-chip bonding is performed, the conductive projection as an electrode compresses the adhesive film forming layer when pressed between the chip and the chip mounting substrate, forming an adhesive film Conductive particles are in contact only in the thickness direction of the layer, are anisotropic in the planar direction, and exhibit anisotropic conductivity that conducts only in the thickness direction.
導電性粒子として用いられる材料は、金、銀、銅、ニッケル、アルミニウム等の金属あるいは合金の粉体や繊維状体やカーボンブラックあるいはポリアニリン、ポリピロール等の導電性高分子粉体や繊維状体が用いられる。これらの材料は、それぞれ単独で用いてもよく、また複数種を組み合わせて用いてもよい。また、粉体等の形状についても、導電性材料単独で用いても形成されているものであってもよく、またスチレン、アクリル等の樹脂にコーティングあるいはメッキしたものであってもよい。粉体あるいは繊維状体の大きさは、1〜20μm程度が好ましい。このような導電性粒子は、上記バインダー樹脂10
0重量部に対して、1〜500重量部程度の割合で用いられる。
Materials used as conductive particles include powders and fibrous bodies of metal or alloys such as gold, silver, copper, nickel, and aluminum, and conductive polymer powders and fibrous bodies such as carbon black, polyaniline, and polypyrrole. Used. These materials may be used alone or in combination of two or more. Also, the shape of the powder or the like may be formed by using a conductive material alone, or may be a coating or plating on a resin such as styrene or acrylic. The size of the powder or fibrous body is preferably about 1 to 20 μm. Such conductive particles include the binder resin 10 described above.
It is used at a ratio of about 1 to 500 parts by weight with respect to 0 part by weight.
また、接着膜形成層12は、フィラーが配合されていてもよい。フィラーとしては、結晶シリカ、合成シリカ等のシリカや、アルミナ、ガラスバルーン等の無機フィラーがあげられる。接着膜形成層12に無機フィラーを添加することにより、硬化後の層の熱膨張係数をチップの熱膨張係数に近づけることができ、これによってチップに負荷される応力を低減することができるようになる。 The adhesive film forming layer 12 may contain a filler. Examples of the filler include silica such as crystalline silica and synthetic silica, and inorganic filler such as alumina and glass balloon. By adding an inorganic filler to the adhesive film forming layer 12, the thermal expansion coefficient of the cured layer can be brought close to the thermal expansion coefficient of the chip, thereby reducing the stress applied to the chip. Become.
さらに、接着膜形成層12にはカップリング剤、顔料、染料、架橋剤、帯電防止剤、難燃剤など種々の機能性を有する添加剤を、その半導体装置の要求する性能に応じて配合することができる。 Further, additives having various functionalities such as coupling agents, pigments, dyes, crosslinking agents, antistatic agents, and flame retardants are blended in the adhesive film forming layer 12 in accordance with the performance required by the semiconductor device. Can do.
接着膜形成層12は、支持フィルム11の剥離面上に上記成分からなる組成物をロールナイフコーター、グラビアコーター、ダイコーター、リバースコーターなど一般に公知の方法にしたがって直接または転写によって塗工し、乾燥させて接着膜形成層12を形成することによって得ることができる。なお、上記の組成物は、必要に応じ、溶剤に溶解し、若しくは分散させて塗布することができる。 The adhesive film forming layer 12 is formed by coating the composition comprising the above components on the release surface of the support film 11 directly or by transfer according to a generally known method such as a roll knife coater, gravure coater, die coater, reverse coater, and the like. And forming the adhesive film forming layer 12. In addition, said composition can be apply | coated after making it melt | dissolve or disperse | distribute to a solvent as needed.
このような接着膜形成層12の膜厚は、半導体チップ3側あるいはチップ搭載用基板30側に設けられる導電性突起物2の高さにもよるが、好ましくは1〜1000μm程度で
あり、より好ましくは5〜200μm程度であり、特に好ましくは10〜100μm程度
である。
The film thickness of the adhesive film forming layer 12 is preferably about 1 to 1000 μm, although it depends on the height of the conductive protrusion 2 provided on the semiconductor chip 3 side or the chip mounting substrate 30 side. Preferably it is about 5-200 micrometers, Most preferably, it is about 10-100 micrometers.
接着膜形成層12の支持フィルム側でない面には、他の剥離フィルム(図示せず)が設けられていてもよい。接着膜形成層12は、支持フィルム11と他の剥離フィルムとで積層されることにより、保管中や貼付作業において張力や圧力で接着膜形成層12が変形しなくなり、さらに表面に塵芥等の付着が無くなる。 Another release film (not shown) may be provided on the surface of the adhesive film forming layer 12 that is not on the support film side. The adhesive film forming layer 12 is laminated with the support film 11 and another release film, so that the adhesive film forming layer 12 is not deformed by tension or pressure during storage or pasting work, and dust or the like adheres to the surface. Disappears.
他の剥離フィルムとしては、ポリエチレンテレフタレートフィルム、ポリブチレンテレフタレートフィルム、ポリエチレンナフタレートフィルム、ポリカーボネートフィルム、ポリスチレンフィルム、ポリイミドフィルム等の剛直性のあるフィルムの片面に剥離処理を施したものが使用できる。また、支持フィルム11に採用される可撓性、追従性に優れたフィルムを使用してもよい。 As the other release film, one obtained by subjecting one side of a rigid film such as a polyethylene terephthalate film, a polybutylene terephthalate film, a polyethylene naphthalate film, a polycarbonate film, a polystyrene film, or a polyimide film to a release treatment can be used. Moreover, you may use the film excellent in the flexibility and followable | trackability employ | adopted as the support film 11. FIG.
接着膜形成用シート10の半導体ウエハ1または半導体チップ3への貼付は、貼付装置によって行なわれる。貼付の際の圧力は、貼付装置の貼付方法(ゴムローラー式、真空密着式)により適宜に設定されるが、加圧条件が弱過ぎるとウエハあるいはチップに接着膜形成用シート10が密着しないことがあり、また強過ぎるとウエハ、チップを破損することがある。 The adhesive film forming sheet 10 is attached to the semiconductor wafer 1 or the semiconductor chip 3 by an attaching device. The pressure at the time of sticking is appropriately set according to the sticking method (rubber roller type, vacuum contact type) of the sticking device, but if the pressurization condition is too weak, the adhesive film forming sheet 10 does not stick to the wafer or chip. If it is too strong, the wafer and chip may be damaged.
さらに、半導体チップ3に接着膜形成用シート10を貼付する場合には、予め接着膜形成層12にチップと同形状の切込みを設けておいてもよい。 Further, when the adhesive film forming sheet 10 is affixed to the semiconductor chip 3, a cut having the same shape as the chip may be provided in the adhesive film forming layer 12 in advance.
貼付温度は、使用する接着膜形成用シートの性質による。通常は、バインダー樹脂の可塑化温度以上180℃以下の温度が好ましい。なお、粘接着剤を使用した場合は、常温で貼付できる。貼付温度が高過ぎると、ウエハの研削後、ウエハに反りを発生させるおそれがある。またウエハの回路面に設けられるバンプ2の高さが50μm以上となるようなウエハの回路面の凹凸が大きい場合は、標準の加圧条件よりも強い条件または高い貼付温度で貼付を行ない、ウエハ回路面に密着させることが好ましい。 The application temperature depends on the properties of the adhesive film forming sheet to be used. Usually, a temperature not lower than the plasticization temperature of the binder resin and not higher than 180 ° C. is preferred. In addition, when an adhesive is used, it can be stuck at room temperature. If the sticking temperature is too high, the wafer may be warped after grinding. If the bump 2 provided on the circuit surface of the wafer has a large unevenness on the circuit surface of the wafer, the wafer 2 is applied under conditions higher than the standard pressure condition or at a higher application temperature. It is preferable to adhere to the circuit surface.
「保護膜形成用シート20」
保護膜形成用シート20は、支持フィルム21と支持フィルム21の片面に形成された保護膜形成層22の積層体よりなる。
"Protective film forming sheet 20"
The protective film forming sheet 20 is composed of a laminate of a support film 21 and a protective film forming layer 22 formed on one side of the support film 21.
保護膜形成層用シート20に使用される支持フィルム21は、保護膜形成層22がチップの裏面とともに側面にも確実に密着させるため、可撓性、追従性に優れたフィルムが好ましく、接着膜形成用シート10の支持フィルム11と同様の種類、厚さのフィルムが使用できる。 The support film 21 used for the protective film-forming layer sheet 20 is preferably a film having excellent flexibility and followability because the protective film-forming layer 22 is securely adhered to the side surface as well as the back surface of the chip. A film of the same kind and thickness as the support film 11 of the forming sheet 10 can be used.
保護膜形成層22は、半導体チップ3の裏面および側面に転写され、従来の封止方法におけるモールド樹脂の役割をなす。保護膜形成層22は、バインダー樹脂に熱硬化性成分および/またはエネルギー線硬化性成分を配合した組成が好ましい。保護膜形成層22は、絶縁性となるよう構成される。 The protective film forming layer 22 is transferred to the back surface and side surface of the semiconductor chip 3 and serves as a mold resin in the conventional sealing method. The protective film forming layer 22 preferably has a composition in which a thermosetting component and / or an energy ray curable component is blended with a binder resin. The protective film forming layer 22 is configured to be insulating.
保護膜形成層22のバインダー樹脂は、接着膜形成層12に採用される熱可塑性のバインダー樹脂、熱硬化性のバインダー樹脂、常温で粘着性のバインダー樹脂のいずれもが使用できる。熱硬化性成分としては、前述した接着膜形成層12に使用される熱硬化性バインダー樹脂または熱硬化性樹脂が使用できる。 As the binder resin of the protective film forming layer 22, any of a thermoplastic binder resin, a thermosetting binder resin, and a binder resin that is adhesive at room temperature can be used. As a thermosetting component, the thermosetting binder resin or thermosetting resin used for the adhesive film formation layer 12 mentioned above can be used.
エネルギー線硬化性成分は、紫外線、電子線等のエネルギー線の照射を受けると重合硬化する化合物からなる。具体的には、トリメチロールプロパントリアクリレート、ペンタエリスリトールテトラアクリレート、ジペンタエリスリトールヘキサアクリレートなどの低分子多価(メタ)アクリレートや、オリゴエステルアクリレート、ウレタンアクリレート、エポキシ変性アクリレートなどのオリゴマー等を用いることができる。 The energy ray curable component is composed of a compound that is polymerized and cured when irradiated with energy rays such as ultraviolet rays and electron beams. Specifically, low-molecular polyvalent (meth) acrylates such as trimethylolpropane triacrylate, pentaerythritol tetraacrylate, dipentaerythritol hexaacrylate, oligomers such as oligoester acrylate, urethane acrylate, and epoxy-modified acrylate are used. Can do.
エネルギー線硬化性成分を使用する場合は、光重合開始剤を混在させることにより、重合硬化時間ならびに光線照射量を少なくすることができる。 When an energy ray curable component is used, the polymerization curing time and the amount of light irradiation can be reduced by mixing a photopolymerization initiator.
保護膜形成層22も、接着膜形成層12と同様にフィラー、カップリング剤、顔料、染料、架橋剤、帯電防止剤、難燃剤等の機能性の添加剤を配合してもよい。 The protective film forming layer 22 may also contain functional additives such as fillers, coupling agents, pigments, dyes, cross-linking agents, antistatic agents, and flame retardants, like the adhesive film forming layer 12.
保護膜形成用シート20は、支持シート21または他の剥離フィルム(図示せず)の剥離面上に上記成分からなる組成物をロールナイフコーター、グラビアコーター、ダイコーター、リバースコーターなど一般に公知の方法にしたがって直接または転写によって塗工し、乾燥させて保護膜形成層22を形成することによって得ることができる。なお、上記の組成物は、必要に応じ、溶剤に溶解し、若しくは分散させて塗布することができる。 The protective film forming sheet 20 is a generally known method such as a roll knife coater, a gravure coater, a die coater, a reverse coater, or the like, on the release surface of a support sheet 21 or other release film (not shown). Thus, the protective film forming layer 22 can be obtained by coating directly or by transfer and drying. In addition, said composition can be apply | coated after making it melt | dissolve or disperse | distribute to a solvent as needed.
このようにして形成される保護膜形成層22の厚さは、通常は、3〜100μm、好ましくは10〜60μmであることが望ましい。 The thickness of the protective film forming layer 22 thus formed is usually 3 to 100 μm, preferably 10 to 60 μm.
また、保護膜形成層22は、2層以上の構成層を有していてもよい。この場合、チップに密着する側の層(すなわち図示しない他の剥離フィルムと接触する層)には、チップとの密着性に優れた層を設けることが好ましい。具体的には、バインダー樹脂成分の配合量を多めにすることで、チップとの優れた密着性が得られる。また、この場合、最外層となる層(すなわち支持シート21と接触する層)には、比較的硬質の硬化被膜を形成する層を設けておくことが好ましい。具体的には、フィラー成分や、熱硬化性成分および/またはエネルギー線硬化性成分の配合割合を多めにすることで、硬質の硬化被膜が得られる。また、最上層となる層には、印字適性を与えるために、凹凸を形成するようにしてもよい。具体的には、フィラーを添加したり、あるいは支持シート21としてエンボス処理した剥離処理面を有する支持フィルムを用い、この支持シート21のエンボス模様を最上層に
転写することで、印字適性を制御することができる。
Further, the protective film forming layer 22 may have two or more constituent layers. In this case, it is preferable to provide a layer having excellent adhesion to the chip on the layer that is in close contact with the chip (that is, the layer that is in contact with another release film not shown). Specifically, excellent adhesion to the chip can be obtained by increasing the blending amount of the binder resin component. In this case, it is preferable to provide a layer that forms a relatively hard cured film as the outermost layer (that is, the layer in contact with the support sheet 21). Specifically, a hard cured film can be obtained by increasing the blending ratio of the filler component, the thermosetting component and / or the energy ray curable component. The uppermost layer may be provided with irregularities in order to provide printability. Specifically, the printability is controlled by adding a filler or using a support film having an embossed release surface as the support sheet 21 and transferring the embossed pattern of the support sheet 21 to the uppermost layer. be able to.
「第1の製造方法」
本発明に係る半導体装置の第1の製造方法は、
上述した半導体ウエハ1の回路面に、接着膜形成層12を形成する工程(以下「A1工程」)、
該半導体ウエハ1および接着膜形成層12を、フルカットダイシングしてチップ化する工程(以下「A2工程」)、
各半導体チップ3の裏面および側面に、保護膜形成層22を貼着する工程(以下「A3工程」)、
個々の半導体チップ3毎に分割されるように保護膜形成層22を切断する工程(以下「A4工程」)、および
個別のチップ3を、該接着膜形成層12を介して、チップ搭載用基板30の所定位置に載置し、該個別のチップ3と該チップ搭載用基板30との導通を確保しながら該個別のチップ3を該チップ搭載用基板30に接着固定する工程(以下「A5工程」)を含む。
"First manufacturing method"
A first manufacturing method of a semiconductor device according to the present invention includes:
A step of forming the adhesive film forming layer 12 on the circuit surface of the semiconductor wafer 1 described above (hereinafter referred to as “A1 step”);
A step of cutting the semiconductor wafer 1 and the adhesive film forming layer 12 into chips by full-cut dicing (hereinafter referred to as “A2 step”);
A step of attaching a protective film forming layer 22 to the back and side surfaces of each semiconductor chip 3 (hereinafter referred to as “A3 step”);
A step of cutting the protective film forming layer 22 so as to be divided into individual semiconductor chips 3 (hereinafter referred to as “A4 step”), and the individual chip 3 through the adhesive film forming layer 12; 30 and a step of adhering and fixing the individual chip 3 to the chip mounting substrate 30 (hereinafter referred to as “step A5”) while ensuring conduction between the individual chip 3 and the chip mounting substrate 30. ")including.
以下、各工程の詳細を説明する。
(A1工程)
半導体ウエハ1の回路面への接着膜形成層12の形成(A1工程)は、前述したように、通常の貼付装置を用いた接着膜形成用シート10の貼付によって行なわれる。貼付の際の圧力は、貼付装置の貼付方法(ゴムローラー式、真空密着式)により適宜に設定されるが、加圧条件が弱過ぎるとウエハに接着膜形成用シート10が密着しないことがあり、また強過ぎるとウエハを破損することがある。
Hereinafter, details of each process will be described.
(Step A1)
As described above, the formation of the adhesive film forming layer 12 on the circuit surface of the semiconductor wafer 1 (A1 step) is performed by attaching the adhesive film forming sheet 10 using a normal attaching device. The pressure at the time of sticking is appropriately set by the sticking method (rubber roller type, vacuum contact type) of the sticking device. However, if the pressurization condition is too weak, the adhesive film forming sheet 10 may not stick to the wafer. If it is too strong, the wafer may be damaged.
その後、半導体ウエハのダイシング(A2工程)を行うが、ダイシングに先立ち、必要に応じ、半導体ウエハ1の裏面研削を行なってもよい。半導体ウエハ1の裏面研削工程は、回路形成時においてウエハ裏面に形成される酸化物被膜を除去し、ウエハの厚さを所定の厚さまで研削する工程である。裏面研削は、たとえば研削装置等の従来公知の方法により行いうる。本発明においては、接着膜形成用シート10を裏面研削の前にウエハ回路面に貼付することにより、ウエハ裏面研削用の保護シートとしての機能も発現できる。
(A2工程)
次に、図1または図2に示すように、ウエハのダイシング(A2工程)を行う。ウエハのダイシングは、通常のダイシング装置を用いて行なわれる。図1に示す態様では、ウエハの裏面にダイシングテープ4を貼着し、これを介して円形のフレーム5に固定してダイシングが行なわれる。図2に示す態様では、支持フィルム11の背面にダイシングテープ4を貼着し、これを介して円形のフレーム5に固定してダイシングが行なわれる。ダイシングに際しては、接着膜形成層12もウエハとともに切断される。また、接着膜形成層12に支持フィルム11が積層されている場合には、支持フィルム11も同時に切断される。ダイシングテープ4としては、従来よりこの種の用途に用いられてきた各種粘着テープが特に制限されることなく用いられる。
Thereafter, dicing of the semiconductor wafer (step A2) is performed, but the backside grinding of the semiconductor wafer 1 may be performed as necessary prior to dicing. The back surface grinding step of the semiconductor wafer 1 is a step of removing the oxide film formed on the back surface of the wafer during circuit formation and grinding the wafer to a predetermined thickness. The back surface grinding can be performed by a conventionally known method such as a grinding apparatus. In the present invention, by sticking the adhesive film forming sheet 10 to the wafer circuit surface before the back surface grinding, a function as a protective sheet for wafer back surface grinding can be expressed.
(Step A2)
Next, as shown in FIG. 1 or FIG. 2, the wafer is diced (step A2). The dicing of the wafer is performed using a normal dicing apparatus. In the embodiment shown in FIG. 1, dicing is performed by attaching a dicing tape 4 to the back surface of the wafer and fixing the dicing tape 4 to the circular frame 5 via the dicing tape 4. In the embodiment shown in FIG. 2, dicing tape 4 is attached to the back surface of the support film 11, and the dicing is performed by fixing the dicing tape 4 to the circular frame 5. When dicing, the adhesive film forming layer 12 is also cut together with the wafer. Moreover, when the support film 11 is laminated | stacked on the adhesive film formation layer 12, the support film 11 is also cut | disconnected simultaneously. As the dicing tape 4, various adhesive tapes conventionally used for this type of application are used without any particular limitation.
なお、図1および2では、接着膜形成層12に支持フィルム11が積層されている態様を示したが、支持フィルム11は、ダイシングされた個別のチップ3を、チップ搭載用基板に載置する工程(A5工程)前に、接着膜形成層12から剥離されていればよい。すなわち、A1工程後A5工程前の何れかの段階で支持フィルム11は接着膜形成層12から剥離されていればよい。支持フィルム11を接着膜形成層12から剥離する方法としては、幅広の粘着シートを支持フィルム11の全面に貼り付けた後に鋭角で引き剥がすことなどにより行なわれる。支持フィルム11の剥離はダイシングの後に行なうことが好ましいが、ダイシングの前であってもよい。以下、図面では、ダイシング後に支持フィルム11を剥離した態様を示す。
(A3工程)
次いで、各半導体チップ3の裏面および側面に、保護膜形成用シート20を貼着するすることで、保護膜形成層22を形成する(A3工程)。
1 and 2 show a mode in which the support film 11 is laminated on the adhesive film forming layer 12, the support film 11 places the individual chips 3 diced on the chip mounting substrate. It may be peeled off from the adhesive film forming layer 12 before the step (A5 step). That is, the support film 11 may be peeled off from the adhesive film forming layer 12 at any stage after the A1 process and before the A5 process. A method of peeling the support film 11 from the adhesive film forming layer 12 is performed by attaching a wide adhesive sheet to the entire surface of the support film 11 and then peeling it off at an acute angle. The support film 11 is preferably peeled after dicing, but may be before dicing. Hereinafter, the drawings show an embodiment in which the support film 11 is peeled after dicing.
(Step A3)
Next, the protective film forming layer 22 is formed by sticking the protective film forming sheet 20 to the back and side surfaces of each semiconductor chip 3 (step A3).
ダイシング工程を図1の態様で行った場合には、次の3つの方法の何れかによりA3工程を実施することができる。
(A3a法)
ダイシング工程を図1の態様で行った場合には、チップの裏面が露出していないため、まずチップ3を他の粘着テープ6に転写する(図3)。他の粘着テープ6としては、被着体の再剥離が可能であり、エキスパンド性を有するテープが用いられる。他の粘着テープ6としては、前述のダイシングテープが一般的に再剥離性を有し、エキスパンド性に優れるものがあるので、市販されているものの中より適宜選択することができる。
When the dicing process is performed in the mode of FIG. 1, the A3 process can be performed by any of the following three methods.
(A3a method)
When the dicing process is performed in the form of FIG. 1, since the back surface of the chip is not exposed, the chip 3 is first transferred to another adhesive tape 6 (FIG. 3). As the other adhesive tape 6, an adherend can be peeled again, and a tape having expandability is used. As the other adhesive tape 6, since the above-mentioned dicing tape generally has removability and excellent expandability, it can be appropriately selected from commercially available ones.
次いで、粘着テープ6をエキスパンドして隣接するチップ同士の間隔を広げる(図4)。エキスパンド工程は、公知の手法により行うことができる。チップ間隔は、保護膜形成用シート20の貼付が行える程度であれば十分であり、一般的には、0.1〜3mm、好ましくは0.2〜2mm程度である。 Next, the adhesive tape 6 is expanded to widen the interval between adjacent chips (FIG. 4). The expanding step can be performed by a known method. The interval between the chips is sufficient as long as the protective film-forming sheet 20 can be attached, and is generally 0.1 to 3 mm, preferably about 0.2 to 2 mm.
その後、図5に示すように、保護膜形成用シート20を、各半導体チップ3の裏面および側面に密着するように貼付する。この際、必要に応じ、半導体チップが破壊されない程度の圧力を加え、保護膜形成用シート20を各チップに密着させてもよい。 Thereafter, as shown in FIG. 5, the protective film forming sheet 20 is stuck so as to be in close contact with the back surface and the side surface of each semiconductor chip 3. At this time, if necessary, the protective film forming sheet 20 may be brought into close contact with each chip by applying a pressure that does not destroy the semiconductor chip.
上記のようにして、各半導体チップ2の裏面および側面に保護膜形成用シート20が貼着される。
(A3b法)
この方法では、ダイシング工程(A2工程)後、チップ3のピックアップを行う。なお、図面では、ダイシング後に支持フィルム11を剥離した態様を示している。
As described above, the protective film forming sheet 20 is adhered to the back surface and the side surface of each semiconductor chip 2.
(A3b method)
In this method, the chip 3 is picked up after the dicing step (step A2). In the drawings, the support film 11 is peeled off after dicing.
ピックアップされた半導体チップ3は、各チップ3が一定の間隔をおいて離間する配列で、各チップ3の裏面側が面するように保護膜形成用シート20に貼着され、該保護膜形成用シート20の離間部分を各チップの側面に密着させることで、各半導体チップ3の裏面および側面に保護膜形成用シート20が貼着される。 The picked-up semiconductor chips 3 are attached to the protective film forming sheet 20 so that the respective chips 3 are spaced apart from each other at a predetermined interval so that the back surface side of each chip 3 faces. The protective film forming sheet 20 is adhered to the back surface and the side surface of each semiconductor chip 3 by bringing the 20 spaced portions into close contact with the side surface of each chip.
A3b法は、たとえば図6に示すように、チップ3よりもやや大きなキャビティー41を所定の間隔で有する治具40を用いて行うことができる。キャビティー41の大きさは、チップ3と、保護膜形成用シート20の厚みを勘案して、適宜に決められる。 For example, as shown in FIG. 6, the A3b method can be performed using a jig 40 having cavities 41 slightly larger than the chip 3 at predetermined intervals. The size of the cavity 41 is appropriately determined in consideration of the thickness of the chip 3 and the protective film forming sheet 20.
治具40の上に、保護膜形成用シート20を、保護膜形成層22が上方に位置するように、載置する。 The protective film forming sheet 20 is placed on the jig 40 so that the protective film forming layer 22 is positioned above.
ついで、チップ3を、チップ裏面が保護膜形成層22に面するように載置し、チップ3をキャビティー41内に押し込むように圧力を加えると、チップ3の裏面および側面が保護膜形成層40に密着する。 Next, when the chip 3 is placed so that the back surface of the chip faces the protective film forming layer 22 and pressure is applied so as to push the chip 3 into the cavity 41, the back surface and the side surface of the chip 3 are protected by the protective film forming layer. Adhere to 40.
また、キャビティー41の内部から真空吸引することにより、チップ3をキャビティー内に誘導し、チップ3の裏面および側面を保護膜形成用シート20に密着させてもよい。 Further, the chip 3 may be guided into the cavity by vacuum suction from the inside of the cavity 41, and the back surface and the side surface of the chip 3 may be brought into close contact with the protective film forming sheet 20.
さらに、保護膜形成用シート20の支持フィルム21として、収縮性フィルムを用いても良い。収縮性フィルムを収縮させると、保護膜形成用シート20がチップ3を包み込むように収縮し、チップ3の裏面および側面が保護膜形成用シート20に密着する。ここで
、収縮性フィルムとしては、一軸または二軸延伸した各種の樹脂フィルムが用いられる。(A3c法)
この方法では、ダイシング工程(A2工程)後、チップ3のピックアップを行う。なお、図面では、ダイシング後に支持フィルム11を剥離した態様を示している。
Furthermore, a shrinkable film may be used as the support film 21 of the protective film forming sheet 20. When the shrinkable film is shrunk, the protective film forming sheet 20 is shrunk so as to wrap the chip 3, and the back surface and side surfaces of the chip 3 are in close contact with the protective film forming sheet 20. Here, various resin films uniaxially or biaxially stretched are used as the shrinkable film. (A3c method)
In this method, the chip 3 is picked up after the dicing step (step A2). In the drawings, the support film 11 is peeled off after dicing.
ピックアップされた半導体チップ3は、各チップ3が一定の間隔をおいて離間する配列で、各チップ3の裏面側が表出するようにテーブル50上に載置し、該半導体チップ群の裏面および側面に保護膜形成用シート20を貼着する(図7)。 The picked-up semiconductor chips 3 are placed on the table 50 so that the back surfaces of the chips 3 are exposed in an arrangement in which the chips 3 are spaced apart from each other at a predetermined interval. A protective film forming sheet 20 is adhered to the substrate (FIG. 7).
テーブル50としては、チップ3を保持できる機能を有するものが用いられ、真空吸引型の吸着テーブルが好ましく用いられる。テーブル50上に、チップの表面(回路面)側を載置、保持し、チップの裏面側が表出するようにする。その後、図7に示すように、保護膜形成用シート20の保護膜形成層22側をチップ裏面に貼着する。その後、前述した圧着、真空吸引、あるいは収縮性支持フィルムを用いる等の手段により、チップ3の裏面および側面が保護膜形成用シート20に密着する。 As the table 50, a table having a function of holding the chip 3 is used, and a vacuum suction type suction table is preferably used. The front surface (circuit surface) side of the chip is placed and held on the table 50 so that the back surface side of the chip is exposed. Thereafter, as shown in FIG. 7, the protective film forming layer 22 side of the protective film forming sheet 20 is attached to the back surface of the chip. Thereafter, the back surface and side surfaces of the chip 3 are brought into close contact with the protective film forming sheet 20 by means such as the above-described pressure bonding, vacuum suction, or using a shrinkable support film.
また、ダイシング工程を図2の態様で行った場合には、チップの裏面側が既に露出しているため、チップを他の粘着テープ6に転写することなく、チップがダイシングテープ4に貼着されている状態で、ダイシングテープ4をエキスパンドして隣接するチップ同士の間隔を広げ、その後A3a法と同様にして、保護膜形成用シート20を貼着すればよい。またこの場合、上記A3b法、A3c法を採用することもできる。 In addition, when the dicing process is performed in the form of FIG. 2, since the back side of the chip is already exposed, the chip is attached to the dicing tape 4 without transferring the chip to another adhesive tape 6. In such a state, the dicing tape 4 is expanded to widen the interval between adjacent chips, and then the protective film forming sheet 20 may be attached in the same manner as in the A3a method. In this case, the above A3b method and A3c method can also be employed.
上記のようなA3a法、A3b法、A3c法により、チップ3の裏面および側面に保護膜形成用シート20が貼着される。この状態では、各チップ3は保護膜形成用シート20を介して相互に連結されている。
(A4工程)
したがって、本発明では、必要に応じ支持フィルム21を剥離した後、該保護膜形成用シート20を切断し、個々のチップ毎に切断分割する(A4工程)。この切断工程は、前記したダイシング工程と同様に、公知の手法により行うことができる。
The protective film forming sheet 20 is attached to the back surface and the side surface of the chip 3 by the A3a method, A3b method, and A3c method as described above. In this state, the chips 3 are connected to each other via the protective film forming sheet 20.
(Step A4)
Therefore, in this invention, after peeling off the support film 21 as needed, this sheet | seat 20 for protective film formation is cut | disconnected, and it cut-divides for every chip | tip (A4 process). This cutting step can be performed by a known method in the same manner as the dicing step described above.
次いで、加熱および/またはエネルギー線照射により保護膜形成層22を硬化させ(硬化工程)、半導体チップの裏面および側面に硬化被膜(保護膜)を形成する。加熱および/またはエネルギー線照射の条件は、保護膜形成層22の組成により適宜に設定される。硬化性成分として、熱硬化性成分とエネルギー線硬化性成分を併用した場合は、保護膜形成層の硬化工程は加熱およびエネルギー線照射を同時に行ってもよく、また逐次行ってもよい。特にチップ上に保護膜形成層を設けてからエネルギー線照射を行い、保護膜形成層を半硬化させ、その後加熱により保護膜形成層を完全に硬化させ、保護膜とすることが好ましい。 Next, the protective film forming layer 22 is cured by heating and / or energy ray irradiation (curing step), and a cured film (protective film) is formed on the back surface and side surfaces of the semiconductor chip. The conditions for heating and / or energy beam irradiation are appropriately set depending on the composition of the protective film forming layer 22. When a thermosetting component and an energy beam curable component are used in combination as the curable component, the curing step of the protective film forming layer may be performed simultaneously with heating and energy beam irradiation or sequentially. In particular, it is preferable to provide a protective film forming layer on the chip and then irradiate energy rays to semi-cure the protective film forming layer, and then completely cure the protective film forming layer by heating to form a protective film.
なお、本発明の第1の製法においては、上述した支持フィルム21の剥離、保護膜形成用シート20の切断およびその硬化の実施は、この順に限定されない。たとえば、剥離工程の後、硬化、切断の工程を行ってもよく、切断、硬化、剥離の順、切断、剥離、硬化の順、硬化、剥離、切断の順、あるいは硬化、切断、剥離の順で行ってもよい。さらに、保護膜形成層22の硬化は、後述するA5工程において行ってもよい。 In addition, in the 1st manufacturing method of this invention, peeling of the support film 21 mentioned above, cutting | disconnection of the sheet | seat 20 for protective film formation, and implementation of the hardening are not limited to this order. For example, after the peeling process, the curing and cutting processes may be performed, and the order of cutting, curing, peeling, cutting, peeling, curing order, curing, peeling, cutting order, or curing, cutting, peeling order. You may go on. Furthermore, you may perform hardening of the protective film formation layer 22 in A5 process mentioned later.
このような工程A1〜A4を経て、回路面に接着膜形成層12を有し、裏面および側面に保護膜形成層22またはその硬化被膜を有するチップ3が得られる。
(A5工程)
次いで、本発明では、該チップをフリップチップボンディングによりチップ搭載用基板30に実装する。
Through such steps A1 to A4, the chip 3 having the adhesive film forming layer 12 on the circuit surface and the protective film forming layer 22 or a cured film thereof on the back surface and the side surface is obtained.
(Step A5)
Next, in the present invention, the chip is mounted on the chip mounting substrate 30 by flip chip bonding.
具体的には、個別のチップ3を、該接着膜形成層12を介して、チップ搭載用基板30の所定位置に載置し、該個別のチップ3と該チップ搭載用基板30との導通を確保しながら該個別のチップ3を該チップ搭載用基板30に接着固定する。 Specifically, the individual chip 3 is placed at a predetermined position on the chip mounting substrate 30 via the adhesive film forming layer 12, and electrical connection between the individual chip 3 and the chip mounting substrate 30 is established. The individual chips 3 are bonded and fixed to the chip mounting substrate 30 while securing.
また、前記接着膜形成層12が絶縁性接着剤からなる場合には、チップ3として、回路上に導通用突起物2を有するチップを用いるか、あるいは導通用突起物2'を有するチッ
プ搭載用基板30を用いる。もちろんこれらを併用してもよい。図8に示したものは、導通用突起物2を有するチップ3および導通用突起物2'を有するチップ搭載用基板30を
併用した例である。
When the adhesive film forming layer 12 is made of an insulating adhesive, a chip having a conductive protrusion 2 on the circuit is used as the chip 3, or a chip mounting having a conductive protrusion 2 'is used. A substrate 30 is used. Of course, you may use these together. FIG. 8 shows an example in which a chip 3 having a conductive protrusion 2 and a chip mounting substrate 30 having a conductive protrusion 2 ′ are used in combination.
この場合には、回路面に絶縁性接着膜形成層12が転写されたチップ3を、該絶縁性接着膜形成層12を介して、バンプ2、2'を有するチップ搭載用基板30上に載置する。
この時点では、チップ3とチップ搭載用基板30との導通はとれていないので、絶縁性接着剤12を流動化させてバンプ2、2'を介してチップ3とチップ搭載用基板30とを接
続し、導通を確保した後、チップ3の固着を行う。
In this case, the chip 3 having the insulating adhesive film forming layer 12 transferred to the circuit surface is mounted on the chip mounting substrate 30 having the bumps 2 and 2 ′ via the insulating adhesive film forming layer 12. Put.
At this time, since the chip 3 and the chip mounting substrate 30 are not electrically connected, the insulating adhesive 12 is fluidized to connect the chip 3 and the chip mounting substrate 30 via the bumps 2 and 2 ′. After securing the conduction, the chip 3 is fixed.
上記絶縁性接着膜形成層12が、熱硬化性絶縁性接着剤または粘接着剤型絶縁性接着剤からなる場合には、チップ3を該絶縁性接着膜形成層12を介してチップ搭載用基板上30に載置した後、該絶縁性接着剤を硬化しないように加熱して、流動化させ、該バンプ2、2'を介してチップ3とチップ搭載用基板30との間の導通を確保した後、絶縁性接着
剤の硬化温度以上に加熱して、チップの固着を行う。なお、接着膜形成層12と保護膜形成層22は、双方ともに熱硬化性でない方が好ましい。しかし、接着膜形成層12と保護膜形成層22が双方とも、熱硬化性または粘接着性のものが選択された場合は、始めに硬化される保護膜形成層22の硬化温度を低温とし、次に硬化される接着膜形成層12の硬化温度を高温とすることにより、保護膜形成層12の硬化の際に接着膜形成層12が硬化してしまわないようにすることができる。
When the insulating adhesive film forming layer 12 is made of a thermosetting insulating adhesive or an adhesive adhesive adhesive, the chip 3 is mounted on the chip via the insulating adhesive film forming layer 12. After mounting on the substrate 30, the insulating adhesive is heated and fluidized so as not to be cured, and conduction between the chip 3 and the chip mounting substrate 30 is achieved via the bumps 2, 2 ′. After securing, the chip is fixed by heating above the curing temperature of the insulating adhesive. It is preferable that both the adhesive film forming layer 12 and the protective film forming layer 22 are not thermosetting. However, when both of the adhesive film forming layer 12 and the protective film forming layer 22 are selected to be thermosetting or adhesive, the curing temperature of the protective film forming layer 22 that is cured first is set to a low temperature. Then, by setting the curing temperature of the adhesive film forming layer 12 to be cured next to a high temperature, it is possible to prevent the adhesive film forming layer 12 from being cured when the protective film forming layer 12 is cured.
また、上記絶縁性接着膜形成層12が、熱可塑性絶縁性接着剤からなる場合には、チップ3を該熱可塑性絶縁性接着剤を介してチップ搭載用基板30上に載置した後、該熱可塑性絶縁性接着剤を加熱して、流動化させ、該バンプ2、2'を介してチップ3とチップ搭
載用基板30との間の導通を確保した後、該熱可塑性絶縁性接着剤の可塑化温度未満に冷却して、チップの固着を行う。
Further, when the insulating adhesive film forming layer 12 is made of a thermoplastic insulating adhesive, after the chip 3 is placed on the chip mounting substrate 30 via the thermoplastic insulating adhesive, After the thermoplastic insulating adhesive is heated and fluidized to ensure electrical conduction between the chip 3 and the chip mounting substrate 30 via the bumps 2 and 2 ′, the thermoplastic insulating adhesive The chip is fixed by cooling below the plasticizing temperature.
接着膜形成用シートが異方導電性接着剤からなる場合には、チップ3をチップ搭載用基板30に載置後、圧着することで、異方導電性接着膜形成層12の厚さ方向への導電性が発現し、チップ2とチップ搭載用基板30との導通が確保される。この場合、チップ3およびチップ搭載用基板30は、バンプ2を及び2'の両方を有するものであってもよく、
またどちらか一方のみ有するものであってもよい。図9に示したものは、バンプ2を有するチップ3を用いた例である。
In the case where the adhesive film forming sheet is made of an anisotropic conductive adhesive, the chip 3 is placed on the chip mounting substrate 30 and then subjected to pressure bonding, thereby moving the anisotropic conductive adhesive film forming layer 12 in the thickness direction. Thus, the electrical connection between the chip 2 and the chip mounting substrate 30 is ensured. In this case, the chip 3 and the chip mounting substrate 30 may have both the bumps 2 and 2 ′.
Moreover, you may have only either one. FIG. 9 shows an example in which a chip 3 having bumps 2 is used.
なお、異方導電性接着膜形成層12が、熱硬化性異方導電性接着剤または粘接着剤型異方導電性接着剤からなる場合には、チップ3を該異方導電性接着膜形成層12を介してチップ搭載用基板30上に載置した後、該異方導電性接着剤の硬化温度以上に加熱して、チップ3の固着を行う。また、異方導電性接着膜形成層12が、熱可塑性異方導電性接着剤からなる場合には、チップ3を該熱可塑性異方導電性接着膜形成層12を介してチップ搭載用基板30上に載置した後、熱圧着を行って、チップの固着を行う。 When the anisotropic conductive adhesive film forming layer 12 is made of a thermosetting anisotropic conductive adhesive or an adhesive-type anisotropic conductive adhesive, the chip 3 is attached to the anisotropic conductive adhesive film. After mounting on the chip mounting substrate 30 via the formation layer 12, the chip 3 is fixed by heating to a temperature equal to or higher than the curing temperature of the anisotropic conductive adhesive. Further, when the anisotropic conductive adhesive film forming layer 12 is made of a thermoplastic anisotropic conductive adhesive, the chip mounting substrate 30 is inserted into the chip 3 via the thermoplastic anisotropic conductive adhesive film forming layer 12. After mounting on the chip, thermocompression bonding is performed to fix the chip.
チップ3とチップ搭載用基板30との接着固定は、フリップチップボンダー等により行うことができる。フリップチップボンダーは、加熱条件、加圧条件を精度良く設定できる
ものが好ましい。このような本発明に係る半導体装置の製造方法によれば、チップ3とチップ搭載用基板30とを、空間を生じることなく、密着した状態で固着できる。また、チップ3の裏面および側面にも保護膜形成層22の硬化被膜が形成されるので、別途樹脂封止を行う必要もなく、ボイドのない、信頼性の高い、半導体装置を得ることができる。
「第2の製造方法」
本発明に係る半導体装置の第2の製造方法は、
表面に回路が形成された半導体ウエハをダイシングしてチップ化する工程(以下「B1工程」)、
各半導体チップ3の回路面に、接着膜形成層12を形成する工程(以下「B2工程」)、
各半導体チップ3の裏面および側面に、保護膜形成層22を貼着する工程(以下「B3工程」)、
個々の半導体チップ毎に分割されるように保護膜形成層22を切断する工程(以下「B4工程」)、および
個別のチップ3を、該接着膜形成層12を介して、チップ搭載用基板30の所定位置に載置し、該個別のチップ3と該チップ搭載用基板30との導通を確保しながら該個別のチップ3を該チップ搭載用基板30に接着固定する工程(以下「B5工程」)を含む。
(B1工程)
ウエハのダイシングは、通常のダイシング装置を用いて行なわれる。すなわち、前記A2工程の説明において述べたように、ウエハの裏面にダイシングテープ4を貼着し、これを介して円形のフレーム5に固定してダイシングが行なわれる。ダイシングテープ4としては、従来よりこの種の用途に用いられてきた各種粘着テープが特に制限されることなく用いられる。
(B2工程)
B1工程によって、ダイシングテープ4上にチップがウエハ形状を保ちつつ整列固着された状態となる。次いで、各半導体チップ3の回路面に、接着膜形成層12を形成する。接着膜形成層12の形成は、次の方法により行うことができる。
(B2a法)
チップの露出面全体を覆うように、接着膜形成用シート10を形成(図10)し、その後、接着膜形成層12を各チップ形状に切断する(図11)。接着膜形成層12の切断は、カッターやダイシングブレードを用いて行ってもよく、また、ダイシングテープ4をエキスパンドして、接着膜形成層12を引きちぎるように切断してもよい。この場合、チップ上に貼着されている接着膜形成層12は延伸されず、チップ間の空隙部に存在する接着膜形成層12のみが延伸されるため、接着膜形成層12の破断伸び以上にチップ間の空隙部が延伸されると、この部分で接着膜形成層12が切断される。
Bonding and fixing of the chip 3 and the chip mounting substrate 30 can be performed by a flip chip bonder or the like. The flip chip bonder is preferably one that can accurately set the heating condition and the pressing condition. According to such a method for manufacturing a semiconductor device according to the present invention, the chip 3 and the chip mounting substrate 30 can be fixed in close contact with each other without generating a space. Further, since the cured film of the protective film forming layer 22 is also formed on the back surface and the side surface of the chip 3, it is not necessary to perform resin sealing separately, and a highly reliable semiconductor device without voids can be obtained. .
"Second manufacturing method"
A second method for manufacturing a semiconductor device according to the present invention is as follows.
A step of dicing a semiconductor wafer having a circuit formed on its surface into chips (hereinafter referred to as “B1 step”),
A step of forming an adhesive film forming layer 12 on the circuit surface of each semiconductor chip 3 (hereinafter referred to as “B2 step”);
A step of attaching a protective film forming layer 22 to the back and side surfaces of each semiconductor chip 3 (hereinafter referred to as “B3 step”);
A step of cutting the protective film forming layer 22 so as to be divided into individual semiconductor chips (hereinafter referred to as “B4 step”), and the individual chip 3 through the adhesive film forming layer 12; A step of adhering and fixing the individual chip 3 to the chip mounting substrate 30 while ensuring electrical continuity between the individual chip 3 and the chip mounting substrate 30 (hereinafter referred to as “step B5”). )including.
(Step B1)
The dicing of the wafer is performed using a normal dicing apparatus. That is, as described in the description of the A2 step, the dicing tape 4 is attached to the back surface of the wafer, and the dicing is performed by fixing the dicing tape 4 to the circular frame 5 via the dicing tape 4. As the dicing tape 4, various adhesive tapes conventionally used for this type of application are used without any particular limitation.
(Step B2)
By the B1 process, the chips are aligned and fixed on the dicing tape 4 while maintaining the wafer shape. Next, an adhesive film forming layer 12 is formed on the circuit surface of each semiconductor chip 3. The adhesive film forming layer 12 can be formed by the following method.
(B2a method)
The adhesive film forming sheet 10 is formed so as to cover the entire exposed surface of the chip (FIG. 10), and then the adhesive film forming layer 12 is cut into each chip shape (FIG. 11). The adhesive film forming layer 12 may be cut using a cutter or a dicing blade, or the dicing tape 4 may be expanded to cut the adhesive film forming layer 12. In this case, the adhesive film forming layer 12 stuck on the chip is not stretched, and only the adhesive film forming layer 12 existing in the gap between the chips is stretched. When the gap between the chips is stretched, the adhesive film forming layer 12 is cut at this portion.
また、後記B3工程を、前記A3a法により行う場合、粘着テープ6の延伸と同時に、接着膜形成層12が切断される態様であってもよい。
(B2b法)
また、図12に示すように、支持フィルム11上の接着膜形成層12にチップと同形状の切込みを設けておき、接着膜形成層12の切断片を各チップ3に接着するようにしてもよい。
(B3工程)、(B4工程)、(B5工程)
これらの工程は、前記(A3工程)、(A4工程)、(A5工程)と同様にして行われる。
Moreover, when performing postscript B3 process by said A3a method, the aspect by which the adhesive film formation layer 12 is cut | disconnected simultaneously with the extending | stretching of the adhesive tape 6 may be sufficient.
(B2b method)
Further, as shown in FIG. 12, the adhesive film forming layer 12 on the support film 11 is provided with a cut having the same shape as the chip, and the cut piece of the adhesive film forming layer 12 is bonded to each chip 3. Good.
(Step B3), (Step B4), (Step B5)
These steps are performed in the same manner as the above-mentioned (A3 step), (A4 step), and (A5 step).
本発明に係る半導体装置の第3の製造方法は、
表面に回路が形成された半導体ウエハ1をダイシングしてチップ化する工程(以下「C1工程」)、
各半導体チップ3の裏面および側面に、保護膜形成層22を貼着する工程(以下「C2
工程」)、
個々の半導体チップ毎に分割されるように保護膜形成層22を切断する工程(以下「C3工程」)、
各半導体チップ3の回路面に、接着膜形成層12を形成する工程(以下「C4工程」)、
および
個別のチップ3を、該接着膜形成層12を介して、チップ搭載用基板30の所定位置に載置し、該個別のチップ3と該チップ搭載用基板30との導通を確保しながら該個別のチップ3を該チップ搭載用基板30に接着固定する工程(以下「C5工程」)を含む。
A third manufacturing method of a semiconductor device according to the present invention is as follows:
A process of dicing the semiconductor wafer 1 having a circuit formed on its surface into chips (hereinafter referred to as “C1 process”),
A step of attaching a protective film forming layer 22 to the back and side surfaces of each semiconductor chip 3 (hereinafter referred to as “C2
Process "),
A step of cutting the protective film forming layer 22 so as to be divided into individual semiconductor chips (hereinafter referred to as “C3 step”),
A step of forming an adhesive film forming layer 12 on the circuit surface of each semiconductor chip 3 (hereinafter referred to as “C4 step”);
The individual chip 3 is placed at a predetermined position on the chip mounting substrate 30 via the adhesive film forming layer 12, and the electrical connection between the individual chip 3 and the chip mounting substrate 30 is ensured. This includes a step of bonding and fixing individual chips 3 to the chip mounting substrate 30 (hereinafter referred to as “C5 step”).
C1工程は、前記B1工程と同様である。 Step C1 is the same as step B1.
C2、C3工程は、回路面側に接着膜形成層12が形成されていない点を除き、前記A3、A4工程と同様にして行われる。 Steps C2 and C3 are performed in the same manner as steps A3 and A4, except that the adhesive film forming layer 12 is not formed on the circuit surface side.
この結果、裏面および側面に保護膜形成層22を有するチップが得られる。C4工程においては、この個別のチップの回路面側に接着膜形成層12を形成する。この場合、接着膜形成層12を予め回路面と同形状に切断しておき、これをチップの回路面に貼着することが好ましい。 As a result, a chip having the protective film forming layer 22 on the back surface and side surfaces is obtained. In step C4, the adhesive film forming layer 12 is formed on the circuit surface side of the individual chip. In this case, it is preferable to cut the adhesive film forming layer 12 in the same shape as the circuit surface in advance and attach this to the circuit surface of the chip.
その後、A5工程と同様にして半導体装置が得られる。 Thereafter, a semiconductor device is obtained in the same manner as in step A5.
本発明に係わる半導体装置の製造方法によれば、フリップチップボンディングを行う半導体装置を、従来の封止方法を併用することなく簡便な方法のみでチップの全面に対し封止が行うことができ、しかも、従来の方法と同様の保護が施されているので充分な信頼性を有する半導体装置を製造できる。 According to the method for manufacturing a semiconductor device according to the present invention, a semiconductor device for performing flip chip bonding can be sealed on the entire surface of the chip by a simple method without using a conventional sealing method. In addition, since the same protection as the conventional method is applied, a semiconductor device having sufficient reliability can be manufactured.
1…半導体ウエハ
2,2'…バンプ(導電性突起物)
3…半導体チップ
4…ダイシングテープ
5…リングフレーム
6…粘着テープ
10…接着膜形成用シート
11…支持フィルム
12…接着膜形成層
13…剥離性シート
20…保護膜形成用シート
21…支持フィルム
22…保護膜形成層
30…チップ搭載用基板
40…治具
41…キャビティー
50…吸着テーブル
1 ... Semiconductor wafer 2, 2 '... Bump (conductive protrusion)
DESCRIPTION OF SYMBOLS 3 ... Semiconductor chip 4 ... Dicing tape 5 ... Ring frame 6 ... Adhesive tape 10 ... Adhesive film forming sheet 11 ... Support film 12 ... Adhesive film forming layer 13 ... Release sheet 20 ... Protective film forming sheet 21 ... Support film 22 ... Protective film forming layer 30 ... Chip mounting substrate 40 ... Jig 41 ... Cavity 50 ... Suction table
Claims (3)
該半導体ウエハおよび接着膜形成層を、フルカットダイシングしてチップ化する工程、
各半導体チップの裏面および側面に、保護膜形成層を貼着する工程、
個々の半導体チップ毎に分割されるように保護膜形成層を切断する工程、および
個別のチップを、該接着膜形成層を介して、チップ搭載用基板の所定位置に載置し、該個別のチップと該チップ搭載用基板との導通を確保しながら該個別のチップを該チップ搭載用基板に接着固定する工程を含む半導体装置の製造方法。 Forming an adhesive film forming layer on a circuit surface of a semiconductor wafer having a circuit formed on the surface;
A step of full-cut dicing the semiconductor wafer and the adhesive film forming layer into chips;
A process of attaching a protective film forming layer to the back and side surfaces of each semiconductor chip;
A step of cutting the protective film forming layer so as to be divided into individual semiconductor chips, and placing the individual chips at predetermined positions on the chip mounting substrate via the adhesive film forming layer. A method for manufacturing a semiconductor device, comprising a step of bonding and fixing the individual chip to the chip mounting substrate while ensuring conduction between the chip and the chip mounting substrate.
各半導体チップの回路面に、接着膜形成層を形成する工程、
各半導体チップの裏面および側面に、保護膜形成層を貼着する工程、
個々の半導体チップ毎に分割されるように保護膜形成層を切断する工程、および
個別のチップを、該接着膜形成層を介して、チップ搭載用基板の所定位置に載置し、該個別のチップと該チップ搭載用基板との導通を確保しながら該個別のチップを該チップ搭載用基板に接着固定する工程を含む半導体装置の製造方法。 A step of dicing a semiconductor wafer having a circuit formed on its surface into chips,
Forming an adhesive film forming layer on the circuit surface of each semiconductor chip;
A process of attaching a protective film forming layer to the back and side surfaces of each semiconductor chip;
A step of cutting the protective film forming layer so as to be divided into individual semiconductor chips, and placing the individual chips at predetermined positions on the chip mounting substrate via the adhesive film forming layer. A method for manufacturing a semiconductor device, comprising a step of bonding and fixing the individual chip to the chip mounting substrate while ensuring conduction between the chip and the chip mounting substrate.
各半導体チップの裏面および側面に、保護膜形成層を貼着する工程、
個々の半導体チップ毎に分割されるように保護膜形成層を切断する工程、
各半導体チップの回路面に、接着膜形成層を形成する工程、
および
個別のチップを、該接着膜形成層を介して、チップ搭載用基板の所定位置に載置し、該個別のチップと該チップ搭載用基板との導通を確保しながら該個別のチップを該チップ搭載用基板に接着固定する工程を含む半導体装置の製造方法。 A step of dicing a semiconductor wafer having a circuit formed on its surface into chips,
A process of attaching a protective film forming layer to the back and side surfaces of each semiconductor chip;
Cutting the protective film forming layer so as to be divided into individual semiconductor chips,
Forming an adhesive film forming layer on the circuit surface of each semiconductor chip;
And an individual chip is placed at a predetermined position on the chip mounting substrate via the adhesive film forming layer, and the individual chip is mounted on the chip mounting substrate while ensuring conduction between the individual chip and the chip mounting substrate. A method for manufacturing a semiconductor device, comprising a step of bonding and fixing to a chip mounting substrate.
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