JP2006261529A - Underfill tape for flip chip mount and manufacturing method of semiconductor device - Google Patents

Underfill tape for flip chip mount and manufacturing method of semiconductor device Download PDF

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Publication number
JP2006261529A
JP2006261529A JP2005079293A JP2005079293A JP2006261529A JP 2006261529 A JP2006261529 A JP 2006261529A JP 2005079293 A JP2005079293 A JP 2005079293A JP 2005079293 A JP2005079293 A JP 2005079293A JP 2006261529 A JP2006261529 A JP 2006261529A
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adhesive layer
chip mounting
bumps
bump
underfill
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Akinori Sato
明徳 佐藤
Osamu Yamazaki
修 山崎
Kazuhiro Takahashi
和弘 高橋
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Lintec Corp
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Lintec Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/274Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2743Manufacturing methods by blanket deposition of the material of the layer connector in solid form
    • H01L2224/27436Lamination of a preform, e.g. foil, sheet or layer
    • H01L2224/2744Lamination of a preform, e.g. foil, sheet or layer by transfer printing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731Location prior to the connecting process
    • H01L2224/73101Location prior to the connecting process on the same surface
    • H01L2224/73103Bump and layer connectors
    • H01L2224/73104Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

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  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide an underfill tape for flip chip mounting which adheres to a semiconductor wafer with bumps without exerting a high tension to the semiconductor wafer at room temperature and forms underfill without void, and also to provide a manufacturing method of a semiconductor device utilizing the underfill tape. <P>SOLUTION: The underfill tape for flip chip mount comprises a base, and a viscoadhesive layer formed thereon in an exfoliable way. The tape is used for the manufacturing method of the semiconductor device including a process wherein at the same time when the viscoadhesive layer adheres to a circuit face with the bumps of a semiconductor wafer, the bumps are penetrated through the viscoadhesive layer, and the bump tops are penetrated into the base. A ratio (H<SB>B</SB>/T<SB>A</SB>) of an average height (H<SB>B</SB>) of the bumps to the thickness (T<SB>A</SB>) of the viscoadhesive layer is selected to be within a range of 1.0/0.3 to 1.0/0.95, and a ratio (T<SB>S</SB>/T<SB>A</SB>) of the thickness (T<SB>S</SB>) of the base to the thickness (T<SB>A</SB>) of the viscoadhesive layer is selected to be 0.5 or over. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、フリップチップ実装用アンダーフィルテープおよびこのテープを用いた半導体装置の製造方法に関する。   The present invention relates to an underfill tape for flip chip mounting and a method of manufacturing a semiconductor device using the tape.

従来、MPUやゲートアレー等に用いる多ピンのLSIパッケージをプリント配線基板に実装する場合には、半導体チップの接続パッド部に共晶ハンダ、高温ハンダ、金等から成る凸状電極(バンプ)を形成し、所謂フェースダウン方式により、それらのバンプ電極をチップ搭載用基板上の相対応する端子部に対面、接触させ、溶融/拡散接合するフリップチップ実装方法が採用されてきた。しかし、この方法によるときは、温度の周期的変動を受けたとき、半導体チップとチップ搭載用基板の熱膨張係数の違いにより接合部が破断する恐れがあるため、フェースダウンで接続された半導体チップのバンプ電極が設けられた面全体と、相対向するプリント配線基板の間の間隙に液状の熱硬化性樹脂(アンダーフィル材)を注入、硬化させ、バンプ接合部全面をチップ搭載用基板に接合してバンプ電極に集中する熱応力を分散させ、破断を防止する方法が提案されている。しかしながら、フリップチップ実装における半導体チップとチップ搭載用基板の間の空隙は40〜200μmと小さく、そのためアンダーフィル材をボイドなく含浸させる工程には相当の時間が掛ること、および、アンダーフィル材のロット間の粘度管理が煩雑なこと等の問題がある。   Conventionally, when a multi-pin LSI package used for an MPU, a gate array, or the like is mounted on a printed wiring board, a convex electrode (bump) made of eutectic solder, high-temperature solder, gold or the like is provided on a connection pad portion of a semiconductor chip. A flip chip mounting method has been adopted in which the bump electrodes are formed in a so-called face-down manner so that the bump electrodes face and come into contact with corresponding terminal portions on the chip mounting substrate, and are melted / diffusion bonded. However, when this method is used, the semiconductor chip connected face-down may be broken due to the difference in thermal expansion coefficient between the semiconductor chip and the chip mounting substrate when subjected to periodic temperature fluctuations. A liquid thermosetting resin (underfill material) is injected and cured in the gap between the entire surface where the bump electrodes are provided and the printed wiring board facing each other, and the entire bump joint is bonded to the chip mounting substrate. Thus, a method has been proposed in which thermal stress concentrated on the bump electrode is dispersed to prevent breakage. However, the gap between the semiconductor chip and the chip mounting substrate in flip chip mounting is as small as 40 to 200 μm, so that the process of impregnating the underfill material without voids takes a considerable amount of time, and the lot of underfill material There are problems such as complicated viscosity management.

この問題の解決方法としてシート状の熱硬化性樹脂あるいは熱可塑性樹脂を半導体チップとチップ搭載用基板の間に挟み、熱圧着する技術が、例えば、特開平9−213741号、特開平10−242208号、特開平10−270497号などにより提案されている。しかしながら、特開平9−213741号の技術は、別途封止材によりバンプ部を囲むように封止部を設ける工程が必要であり、工程が煩雑になると同時にボイドの発生を完全に回避することができないという問題がある。また、特開平10−242208号の提案では、アンダーフィル樹脂の位置合わせが必要であり、場所によりアンダーフィル樹脂量の過不足が発生したり、逃げ穴によるボイド発生の可能性があることが否めない。また、特開平10−270497号では、絶縁接着フィルムに半導体チップのバンプ電極を食い込ませてチップ搭載用基板の端子部に接続させているため、バンプ電極先端には絶縁接着フィルムの被膜が残存し、接続の信頼性を損ねることがあるなど、工程の面、信頼性の面より問題がある。また、近年、半導体パッケージの薄型化の要求拡大により、半導体チップも薄く研削されることが通常に行われている。その目的のため、従来、回路が形成されたウエハのバンプ電極面にバックグラインドテープを圧着し、ウエハの裏面を研削した後、該テープを剥がし、ダイシングにより個片化し接合を行うという煩雑な工程を経て加工されている。さらに研削された薄板化ウエハの搬送やハンドリングの際に破損することが多いという問題も生じている。   As a method for solving this problem, a technique in which a sheet-like thermosetting resin or thermoplastic resin is sandwiched between a semiconductor chip and a chip mounting substrate and thermocompression bonded is disclosed in, for example, JP-A-9-213741 and JP-A-10-242208. And JP-A-10-270497. However, the technique of Japanese Patent Laid-Open No. 9-213741 requires a step of providing a sealing portion so as to separately surround the bump portion with a sealing material, and the process becomes complicated and at the same time, the generation of voids can be completely avoided. There is a problem that you can not. Further, in the proposal of Japanese Patent Laid-Open No. 10-242208, it is necessary to align the underfill resin, and it is denied that the amount of the underfill resin may be excessive or insufficient depending on the location, or voids may be generated due to escape holes. Absent. Further, in JP-A-10-270497, a bump electrode of a semiconductor chip is bitten into an insulating adhesive film and connected to a terminal portion of a chip mounting substrate, so that an insulating adhesive film film remains on the tip of the bump electrode. There are problems in terms of process and reliability, such as the reliability of connection being impaired. In recent years, semiconductor chips have also been usually ground thinly due to increasing demands for thinning semiconductor packages. For that purpose, conventionally, a complicated process of pressing a back grind tape on the bump electrode surface of a wafer on which a circuit is formed, grinding the back surface of the wafer, peeling off the tape, and separating and joining by dicing. It is processed through. Further, there is a problem that the ground thin wafer is often damaged during transportation and handling.

これらの問題を解決するため、特許文献1には、装着すべき半導体チップのバンプ高さと同一程度の厚みを有する熱硬化性樹脂層を、合成樹脂フィルムの片面に設けてなる半導体チップ装着用シートが提案されている。この半導体チップ装着用シートのウエハへの貼り合わせは、硬化前の熱硬化性樹脂層の軟化温度以上、硬化温度以下の温度で熱圧着することで行われる。
特開2002−118147号公報
In order to solve these problems, Patent Document 1 discloses a semiconductor chip mounting sheet in which a thermosetting resin layer having the same thickness as the bump height of a semiconductor chip to be mounted is provided on one surface of a synthetic resin film. Has been proposed. The semiconductor chip mounting sheet is bonded to the wafer by thermocompression bonding at a temperature not lower than the softening temperature of the thermosetting resin layer before curing and not higher than the curing temperature.
JP 2002-118147 A

ところで、近年、上記のバンプの形状として、スタッドバンプと呼ばれる先端が鋭利な
ものが採用されつつある。特許文献1のような半導体チップ装着用シートを加熱下で熱圧着を行うと、熱硬化性樹脂層および基材が軟化した状態で熱圧着を行うため、熱圧着の過程でバンプの先端部において熱硬化性樹脂層が引き伸ばされ、ちぎれてしまうことがある。熱硬化性樹脂層がちぎれた場合、ボイド発生の原因となる。
By the way, in recent years, as the shape of the above-mentioned bump, a stud bump having a sharp tip is being adopted. When a semiconductor chip mounting sheet as in Patent Document 1 is subjected to thermocompression bonding under heating, thermocompression bonding is performed in a state where the thermosetting resin layer and the base material are softened. The thermosetting resin layer may be stretched and broken. When the thermosetting resin layer is torn off, voids are generated.

本発明は、バンプを有する半導体ウエハに対して、常温において大きなテンションをかけることなく貼付可能であり、ボイドのないアンダーフィルを形成できるフリップチップ実装用アンダーフィルテープおよびこれを利用した半導体装置の製造方法を提供することを目的としている。   The present invention relates to a flip-chip mounting underfill tape that can be applied to a semiconductor wafer having bumps without applying a large tension at room temperature and can form a void-free underfill, and a semiconductor device using the same It aims to provide a method.

上記の課題を解決する本発明は、以下の事項を要旨としている。
(1)基材と、その上に剥離可能に形成された粘接着剤層とからなり、
回路面にバンプを有する半導体ウエハの回路面に、粘接着剤層を貼付すると同時に、該バンプが粘接着剤層を貫通し、バンプ頂部を基材内に貫入する工程を含む半導体装置の製造方法に使用されるフリップチップ実装用アンダーフィルテープであって、
該バンプの平均高さ(HB)と、粘接着剤層の厚み(TA)との比(HB/TA)が1.0/0.3〜1.0/0.95の範囲にあり、基材の厚み(TS)と、粘接着剤層の厚み(
A)との比(TS/TA)が0.5以上であるフリップチップ実装用アンダーフィルテー
プ。
(2)回路面にバンプを有する半導体ウエハの回路面に、(1)に記載のフリップチップ実装用アンダーフィルテープの粘接着剤層を貼付すると同時に、該バンプが粘接着剤層を貫通し、バンプ頂部を基材内に貫入する工程、
該半導体ウエハを回路毎に個別のチップに切断分離する工程、
粘接着剤層面から基材を剥離し、バンプ頂部を露出させる工程、
チップ搭載用基板の所定位置に、チップのバンプ形成面を載置し、チップとチップ搭載用基板との導通を確保しながら、粘接着剤層を介してチップをチップ搭載用基板に接着固定する工程からなる半導体装置の製造方法。
The gist of the present invention for solving the above problems is as follows.
(1) It consists of a base material and an adhesive layer formed so as to be peelable thereon,
A semiconductor device comprising a step of attaching an adhesive layer to a circuit surface of a semiconductor wafer having bumps on a circuit surface, and simultaneously, the bump penetrates the adhesive layer and penetrates the top of the bump into a substrate. An underfill tape for flip chip mounting used in a manufacturing method,
The ratio (H B / T A ) between the average height (H B ) of the bumps and the thickness (T A ) of the adhesive layer is 1.0 / 0.3 to 1.0 / 0.95 The thickness of the base material (T S ) and the thickness of the adhesive layer (
T A) and the ratio (T S / T A) underfill tape for flip-chip mounting is 0.5 or more.
(2) Attach the adhesive layer of the flip chip mounting underfill tape described in (1) to the circuit surface of a semiconductor wafer having bumps on the circuit surface, and at the same time, the bumps penetrate the adhesive layer. And a step of penetrating the bump top portion into the base material,
Cutting and separating the semiconductor wafer into individual chips for each circuit;
Peeling the substrate from the adhesive layer surface to expose the bump top,
Place the bump formation surface of the chip at a predetermined position on the chip mounting board, and secure the conduction between the chip and the chip mounting board, and adhere and fix the chip to the chip mounting board through the adhesive layer A method for manufacturing a semiconductor device comprising the steps of:

本発明に係るフリップチップ実装用アンダーフィルテープによれば、バンプを有する半導体ウエハに対して、常温において大きなテンションをかけることなく貼付可能であり、ボイドのないアンダーフィルを簡便に形成できる。   The flip chip mounting underfill tape according to the present invention can be applied to a semiconductor wafer having bumps without applying a large tension at room temperature, and an underfill without voids can be easily formed.

以下、本発明について図面を参照しながらさらに具体的に説明する。
図1に示すように、本発明のフリップチップ実装用アンダーフィルテープ4は、基材1と、その片面に形成された粘接着剤層2とからなり、その使用前には粘接着剤層2を保護するための剥離フィルム3が粘接着剤層2上に仮着されている。
Hereinafter, the present invention will be described more specifically with reference to the drawings.
As shown in FIG. 1, the underfill tape 4 for flip-chip mounting of this invention consists of the base material 1 and the adhesive layer 2 formed in the single side | surface, and before that use, an adhesive agent is used. A release film 3 for protecting the layer 2 is temporarily attached on the adhesive layer 2.

基材1としては、たとえば、ポリエチレンフィルム、ポリプロピレンフィルム、ポリブテンフィルム、ポリブタジエンフィルム、ポリメチルペンテンフィルム、ポリ塩化ビニル
フィルム、塩化ビニル共重合体フィルム、ポリウレタンフィルム、エチレン酢ビフィルム、アイオノマー樹脂フィルム、エチレン・(メタ)アクリル酸共重合体フィルム、エチレン・(メタ)アクリル酸エステル共重合体フィルム、フッ素樹脂フィルム等のフィルムが用いられる。またこれらの架橋フィルムも用いられる。さらにこれらの積層フィルムであってもよい。さらにこれらのフィルムは、透明フィルム、着色フィルムあるいは不透明フィルムであってもよい。
Examples of the substrate 1 include polyethylene film, polypropylene film, polybutene film, polybutadiene film, polymethylpentene film, polyvinyl chloride film, vinyl chloride copolymer film, polyurethane film, ethylene vinyl acetate film, ionomer resin film, ethylene A film such as a (meth) acrylic acid copolymer film, an ethylene / (meth) acrylic acid ester copolymer film, or a fluororesin film is used. These crosslinked films are also used. Furthermore, these laminated films may be sufficient. Furthermore, these films may be transparent films, colored films or opaque films.

本発明に係る半導体装置の製造方法においては、後述するように、基材1上の粘接着剤
層2を、回路基板のチップ搭載面に転写するため、基材1と粘接着剤層2とは剥離可能なように積層されている。このため、基材1の粘接着剤層2に接する面の表面張力は、好ましくは40mN/m 以下、さらに好ましくは37mN/m 以下、特に好ましくは35mN/m 以下
であることが望ましい。このような表面張力が低いフィルムは、材質を適宜に選択して得ることが可能であるし、またフィルムの表面に、シリコーン樹脂やアルキッド樹脂などの剥離剤を塗布して剥離処理を施すことで得ることもできる。
In the method for manufacturing a semiconductor device according to the present invention, as will be described later, in order to transfer the adhesive layer 2 on the substrate 1 to the chip mounting surface of the circuit board, the substrate 1 and the adhesive layer 2 are laminated so as to be peelable. For this reason, the surface tension of the surface of the substrate 1 in contact with the adhesive layer 2 is preferably 40 mN / m or less, more preferably 37 mN / m or less, and particularly preferably 35 mN / m or less. Such a film having a low surface tension can be obtained by appropriately selecting the material, and by applying a release agent such as a silicone resin or an alkyd resin to the surface of the film and performing a release treatment. It can also be obtained.

このような基材1の膜厚は、通常は5〜250μm、好ましくは8〜175μm、特に好ましくは10〜125μm程度である。
粘接着剤層2を形成する粘接着剤とは、初期状態において常温で粘着性を示し、加熱のようなトリガーにより硬化し強固な接着性を示す接着剤をいう。
The film thickness of such a base material 1 is usually 5 to 250 μm, preferably 8 to 175 μm, and particularly preferably about 10 to 125 μm.
The adhesive that forms the adhesive layer 2 refers to an adhesive that exhibits adhesiveness at room temperature in the initial state and is cured by a trigger such as heating and exhibits strong adhesiveness.

このような粘接着剤としては、従来公知の粘接着剤が特に制限されることなく用いられる。 粘接着剤としては、たとえば常温で感圧接着性を有するバインダー樹脂と熱硬化性樹脂との混合物が挙げられる。常温で感圧接着性を有するバインダー樹脂としては、たとえばアクリル樹脂、ポリエステル樹脂、ポリビニルエーテル樹脂、ウレタン樹脂、ポリアミド樹脂等が挙げられ、特にアクリル樹脂が好ましい。熱硬化性樹脂は、一般的にはエポキシ樹脂、フェノキシ樹脂、フェノール樹脂、レゾルシノール樹脂、ユリア樹脂、メラミン樹脂、フラン樹脂、不飽和ポリエステル樹脂、シリコーン樹脂等であり、適当な硬化促進剤と組み合わせて用いられる。このような熱硬化性樹脂は種々知られており、本発明においては特に制限されることなく公知の様々な熱硬化性樹脂を用いることができるが特にエポキシ樹脂、フェノール樹脂が好ましい。また、基材1表面からの剥離を容易にするために、粘接着剤層2は、エネルギー線硬化性成分を有することが好ましい。エネルギー線硬化性成分を硬化させることで、粘着力が減少するため、基材1表面からの剥離を容易に行えるようになる。エネルギー線硬化性成分としてはウレタン系アクリレートオリゴマー、ジペンタエリスリトールヘキサアクリレートなどの紫外線硬化性樹脂を配合することが好ましい。紫外線硬化性樹脂を配合すると、紫外線照射前は基材1とよく密着し、紫外線照射後は基材1から剥離しやすくなる。   As such an adhesive, a conventionally known adhesive is used without any particular limitation. Examples of the adhesive include a mixture of a binder resin having a pressure-sensitive adhesive property at room temperature and a thermosetting resin. Examples of the binder resin having pressure-sensitive adhesive properties at room temperature include acrylic resins, polyester resins, polyvinyl ether resins, urethane resins, polyamide resins, and the like, and acrylic resins are particularly preferable. Thermosetting resins are generally epoxy resins, phenoxy resins, phenol resins, resorcinol resins, urea resins, melamine resins, furan resins, unsaturated polyester resins, silicone resins, etc., in combination with an appropriate curing accelerator. Used. Various such thermosetting resins are known, and various known thermosetting resins can be used without particular limitation in the present invention, but epoxy resins and phenol resins are particularly preferable. Moreover, in order to make peeling from the base material 1 surface easy, it is preferable that the adhesive layer 2 has an energy-beam curable component. By curing the energy ray-curable component, the adhesive force is reduced, so that the substrate 1 can be easily peeled from the surface. As the energy ray curable component, an ultraviolet curable resin such as urethane acrylate oligomer or dipentaerythritol hexaacrylate is preferably blended. When an ultraviolet curable resin is blended, it adheres well to the base material 1 before the ultraviolet irradiation, and is easily peeled off from the base material 1 after the ultraviolet irradiation.

また、粘接着剤層2には、光重合開始剤、熱活性型潜在性硬化剤、架橋剤が配合されていてもよい。
エネルギー線として紫外線を用いる場合には、光重合開始剤を添加することにより、重合硬化時間および照射量を少なくすることができる。光重合開始剤としてはベンゾフェノン、アセトフェノン、ベンゾイン等が好ましい。
The adhesive layer 2 may contain a photopolymerization initiator, a thermally activated latent curing agent, and a crosslinking agent.
When ultraviolet rays are used as energy rays, the polymerization curing time and irradiation amount can be reduced by adding a photopolymerization initiator. As the photopolymerization initiator, benzophenone, acetophenone, benzoin and the like are preferable.

熱活性型潜在性硬化剤は、室温ではエポキシ樹脂と反応せず、ある温度以上の加熱により活性化し、エポキシ樹脂と反応する硬化剤で、加熱硬化前は、室温付近でウエハに貼付可能であり、チップ搭載用基板へ載置後、加熱硬化することでチップ搭載用基板に強固に接着する。   Thermally activated latent curing agent is a curing agent that does not react with epoxy resin at room temperature but is activated by heating above a certain temperature and reacts with epoxy resin, and can be applied to wafers near room temperature before heat curing. After being placed on the chip mounting substrate, it is firmly bonded to the chip mounting substrate by heat curing.

これら熱活性型潜在性硬化剤は、1種単独で、または2種以上を組み合わせて用いることができ、特にジシアンジアミド、イミダゾール化合物あるいはこれらの混合物が好ましい。   These thermally activated latent curing agents can be used singly or in combination of two or more, and dicyandiamide, an imidazole compound or a mixture thereof is particularly preferable.

エネルギー線照射前の初期接着力および凝集力を調節するために架橋剤を添加することができる。架橋剤としては有機多価イソシアナート化合物、有機多価イミン化合物等が挙げられる。   A cross-linking agent can be added to adjust the initial adhesive force and cohesive force before irradiation with energy rays. Examples of the crosslinking agent include organic polyvalent isocyanate compounds and organic polyvalent imine compounds.

上記のような各成分からなる粘接着剤は、エネルギー線硬化性と加熱硬化性とを有し、常温においてテンションをかけることなく、基材1に密着してウエハの固定に寄与し、マ
ウントの際にはチップとチップ搭載用基板とを接着する接着剤として使用することができる。そして熱硬化を経て最終的には耐衝撃性の高い硬化物を与えることができ、しかも剪断強度と剥離強度とのバランスにも優れ、厳しい熱湿条件下においても充分な接着物性を保持しうる。
Adhesives composed of the above components have energy ray curability and heat curability, contribute to fixing the wafer by adhering to the substrate 1 without applying tension at room temperature, and mounting In this case, it can be used as an adhesive for bonding the chip and the chip mounting substrate. Finally, a cured product with high impact resistance can be obtained through thermal curing, and it has an excellent balance between shear strength and peel strength, and can maintain sufficient adhesive properties even under severe heat and humidity conditions. .

このような粘接着剤層2の膜厚は、通常は10〜500μm、好ましくは15〜350μm、特に好ましくは20〜250μm程度である。
上記のようなフリップチップ実装用アンダーフィルテープ4は、回路面にバンプを有する半導体ウエハの回路面に、貼付すると同時に、該バンプが粘接着剤層2を貫通し、バンプ頂部を基材内に貫入する工程を含む半導体装置の製造方法、特に後述する本発明に係る半導体装置の製造方法において好ましく使用される。
The film thickness of such an adhesive layer 2 is usually 10 to 500 μm, preferably 15 to 350 μm, and particularly preferably about 20 to 250 μm.
The underfill tape 4 for flip chip mounting as described above is applied to the circuit surface of a semiconductor wafer having bumps on the circuit surface, and at the same time, the bumps penetrate the adhesive layer 2 and the bump tops are in the substrate. It is preferably used in a method for manufacturing a semiconductor device including a step of penetrating into a semiconductor device, particularly a method for manufacturing a semiconductor device according to the present invention described later.

この際、ボイドの発生なく回路面を覆い、かつバンプが粘接着剤層2を貫通するため、バンプの平均高さ(HB)と、粘接着剤層の厚み(TA)との比(HB/TA)が1.0/0.3〜1.0/0.95、好ましくは1.0/0.5〜1.0/0.9、さらに好ましくは1.0/0.6〜1.0/0.85、特に好ましくは1.0/0.7〜1.0/0.8の範囲にある。バンプの平均高さ(HB)は、図2に示しように、チップ表面(バンプを
除く回路面)からバンプ頂部までの高さであり、バンプが複数ある場合には、これらの算術平均による。
At this time, the circuit surface is covered without generation of voids, and the bump penetrates the adhesive layer 2, so that the average height of the bump (H B ) and the thickness of the adhesive layer (T A ) The ratio (H B / T A ) is 1.0 / 0.3 to 1.0 / 0.95, preferably 1.0 / 0.5 to 1.0 / 0.9, more preferably 1.0 / It is in the range of 0.6 to 1.0 / 0.85, particularly preferably 1.0 / 0.7 to 1.0 / 0.8. As shown in FIG. 2, the average height (H B ) of the bumps is the height from the chip surface (circuit surface excluding the bumps) to the top of the bumps. .

粘接着剤層の厚みに対して、バンプ高さが高すぎると、チップ表面(バンプを除く回路面)とチップ搭載用基板との間隔があき、ボイド発生の原因となる。一方、粘接着剤層2が厚すぎると、バンプが粘接着剤層2を貫通しないため、導通不良の原因となる。   If the bump height is too high with respect to the thickness of the adhesive layer, there is a gap between the chip surface (circuit surface excluding the bump) and the chip mounting substrate, which causes voids. On the other hand, if the adhesive layer 2 is too thick, bumps do not penetrate the adhesive layer 2, which causes poor conduction.

また、フリップチップ実装用アンダーフィルテープ4における 基材の厚み(TS)と
、粘接着剤層の厚み(TA)との比(TS/TA)は、好ましくは0.5以上、さらに好ま
しくは1.0以上、特に好ましくは2.0以上の範囲にある。
Further, the ratio (T S / T A ) of the base material thickness (T S ) and the adhesive layer thickness (T A ) in the flip-chip mounting underfill tape 4 is preferably 0.5 or more. More preferably, it is 1.0 or more, and particularly preferably 2.0 or more.

粘接着剤層の厚みに対して、基材の厚みが薄過ぎると、バンプが粘接着剤層2を貫通せずに導通不良の原因となることがある。これは、基材がある程度厚いと、クッション的な役割を果たし、貫通したバンプ先端が基材内にめりこむためバンプが貫通しやすくなるのに対し、基材が薄過ぎるとかかるクッション作用を期待しがたいためと考えられる。   If the thickness of the substrate is too thin relative to the thickness of the adhesive layer, the bumps may not penetrate the adhesive layer 2 and cause conduction failure. This is because if the base material is thick to some extent, it plays a cushioning role, and the bump tip penetrates into the base material, making it easier for the bumps to penetrate. This is thought to be due to the difficulty.

本発明のフリップチップ実装用アンダーフィルテープ4の使用前には、前述したように、粘接着剤層2を保護するために、剥離フィルム3が仮着されていてもよい。このような剥離フィルムとしては、従来から粘着テープ類に使用されてきた種々の剥離フィルムが特に制限されることなく使用できる。具体的には紙、金属箔や基材1として例示したフィルムのほかに、ポリエチレンテレフタレートフィルム、ポリエチレンナフタレートフィルム、ポリブチレンテレフタレートフィルムなどの合成樹脂フィルムの表面に、シリコーン樹脂やアルキッド樹脂などの剥離剤を塗布して得ることができる。   Before using the underfill tape 4 for flip chip mounting of the present invention, as described above, the release film 3 may be temporarily attached to protect the adhesive layer 2. As such a release film, various release films conventionally used for adhesive tapes can be used without any particular limitation. Specifically, in addition to the film exemplified as paper, metal foil, and substrate 1, the surface of a synthetic resin film such as a polyethylene terephthalate film, a polyethylene naphthalate film, or a polybutylene terephthalate film is peeled off such as a silicone resin or an alkyd resin. It can be obtained by applying an agent.

次に本発明のフリップチップ実装用アンダーフィルテープを利用した半導体装置の製造方法について説明する。
まず、図2に示すように、回路面にバンプ5を有する半導体ウエハ6を準備する。回路やバンプの形成は、常法により行われる。
Next, a method for manufacturing a semiconductor device using the flip-chip mounting underfill tape of the present invention will be described.
First, as shown in FIG. 2, a semiconductor wafer 6 having bumps 5 on a circuit surface is prepared. Circuits and bumps are formed by conventional methods.

次に、半導体ウエハ6の回路面に、上述した本発明に係るフリップチップ実装用アンダーフィルテープ4の粘接着剤層2を貼付する。この際、粘接着剤層2が常温粘着性を有するため、フリップチップ実装用アンダーフィルテープ4の貼付に際しては、バンプ5が粘接着剤層2を貫通するように、加圧が必要であるが、加熱やテンションの付加を行う必要
は必ずしもない。このようにして、フリップチップ実装用アンダーフィルテープ4を貼付すると、バンプ5が粘接着剤層2を貫通し、またバンプ頂部が基材内に貫入する。
Next, the adhesive layer 2 of the flip-chip mounting underfill tape 4 according to the present invention described above is attached to the circuit surface of the semiconductor wafer 6. At this time, since the adhesive layer 2 has room temperature adhesiveness, when applying the flip-chip mounting underfill tape 4, it is necessary to apply pressure so that the bumps 5 penetrate the adhesive layer 2. However, it is not always necessary to apply heating or tension. In this way, when the flip-chip mounting underfill tape 4 is applied, the bumps 5 penetrate the adhesive layer 2 and the bump tops penetrate into the substrate.

この結果、図3に示すように、半導体ウエハ6の回路面およびバンプがフリップチップ実装用アンダーフィルテープ4に保護された状態となる。この状態で、半導体ウエハ6の裏面研削や、その他の裏面加工を行ってもよい。   As a result, as shown in FIG. 3, the circuit surface and bumps of the semiconductor wafer 6 are protected by the flip-chip mounting underfill tape 4. In this state, the backside grinding of the semiconductor wafer 6 or other backside processing may be performed.

次いで、半導体ウエハ6を回路毎に個別のチップに切断分離する。ウエハ6の切断分離法は、特に限定されず、従来より公知の種々の方法により行われる。たとえば、ウエハ6の裏面側に通常のダイシングテープを圧着し、これを介してリングフレームに固定して、ダイシング装置を用いてウエハを切断分離し、チップを得ることができる。また、レーザーダイシング等の種々のダイシング法を採用することもできる。   Next, the semiconductor wafer 6 is cut and separated into individual chips for each circuit. The method for cutting and separating the wafer 6 is not particularly limited, and is performed by various conventionally known methods. For example, a normal dicing tape can be pressure-bonded to the back side of the wafer 6 and fixed to a ring frame through this, and the wafer can be cut and separated using a dicing apparatus to obtain a chip. Various dicing methods such as laser dicing can also be employed.

また、ウエハの表面側から所定深さの溝を形成した後、この裏面側から研削し、溝の底部を除去することで、ウエハをチップ化することもできる。この方法は、「先ダイシング法」とも呼ばれ、極薄チップを得る上で有効な手段となっている。さらに半導体ウエハに切断起点となる脆弱部を形成しておき、ウエハに熱的あるいは機械的衝撃を与えることで、切断起点から割断を起こさせて、ウエハをチップ化してもよい。切断起点は、たとえば、レーザー光をウエハ内部に集光し、ウエハ内部に部分的に改質部を形成したり、あるいは溝を削成することで形成できる。   Further, after forming a groove having a predetermined depth from the front surface side of the wafer, the wafer can be chipped by grinding from the back surface side and removing the bottom of the groove. This method is also called a “first dicing method” and is an effective means for obtaining an ultrathin chip. Further, a brittle portion serving as a cutting start point may be formed on the semiconductor wafer, and the wafer may be cut into chips by cleaving from the cutting start point by applying a thermal or mechanical shock to the wafer. The cutting starting point can be formed, for example, by condensing laser light inside the wafer and partially forming a modified portion inside the wafer or by cutting a groove.

次いで、粘接着剤層2面から基材1を剥離し、バンプ頂部を露出させる。なお、基材1の剥離は、上述したチップ化工程後でもよく、またチップ化工程の前であってもよい。また、粘接着剤層2が紫外線硬化性を有する場合には、基材1の剥離に先立ち、粘接着剤層に紫外線照射を行い、粘着力を低下させた後に基材1を剥離することが好ましい。   Next, the base material 1 is peeled off from the surface of the adhesive layer 2 to expose the bump tops. In addition, peeling of the base material 1 may be after the chip formation process mentioned above, and may be before the chip formation process. Moreover, when the adhesive layer 2 has ultraviolet curable properties, the adhesive layer is irradiated with ultraviolet rays prior to the peeling of the base material 1, and the base material 1 is peeled after the adhesive force is reduced. It is preferable.

このような工程を経ることで、図4に示すように、回路面が粘接着剤層で覆われ、かつバンプ頂部が粘接着剤層を貫通し、バンプ頂部が粘接着剤層2から突出したチップ7が得られる。   Through such a process, as shown in FIG. 4, the circuit surface is covered with the adhesive layer, the bump top part penetrates the adhesive layer, and the bump top part is the adhesive layer 2. A chip 7 protruding from is obtained.

次いで、チップ7のバンプが、チップ搭載用基板の電極部に相対するように位置合わせをし、チップとチップ搭載用基板との導通を確保するように、チップをチップ搭載用基板に載置する。その後、粘接着剤層2を熱硬化することで、チップとチップ搭載用基板とを強固に接着できる。   Next, the chip 7 is placed on the chip mounting substrate so that the bumps of the chip 7 are aligned so as to face the electrode portions of the chip mounting substrate, and the conduction between the chip and the chip mounting substrate is ensured. . Then, the chip | tip and the board | substrate for chip | tip mounting can be adhere | attached firmly by thermosetting the adhesive agent layer 2. FIG.

その後、樹脂封止などの公知の工程を経ることで半導体装置が得られる。   Thereafter, the semiconductor device is obtained through a known process such as resin sealing.

本発明に係るフリップチップ実装用アンダーフィルテープによれば、バンプを有する半導体ウエハに対して、常温において大きなテンションをかけることなく貼付可能であり、ボイドのないアンダーフィルを簡便に形成できる。このためプロセスが簡略化され、高信頼性の半導体装置を得ることができ、半導体装置の製造コストの削減に寄与できる。
(実施例)
以下、本発明を実施例により説明するが、本発明はこれら実施例に限定されるものではない。
The flip chip mounting underfill tape according to the present invention can be applied to a semiconductor wafer having bumps without applying a large tension at room temperature, and an underfill without voids can be easily formed. For this reason, the process is simplified, a highly reliable semiconductor device can be obtained, and the manufacturing cost of the semiconductor device can be reduced.
(Example)
EXAMPLES Hereinafter, although an Example demonstrates this invention, this invention is not limited to these Examples.

なお、以下の実施例および比較例において、「バンプ貫通量」は次のように評価した。「バンプ貫通量」
ウエハ上の所定位置にバンプボンダー(SBB4 (株) 新川製)を用い金ボールハンダを
形成し、これを溶融、引き伸ばし、所定高さのバンプを形成した。
In the following examples and comparative examples, the “bump penetration amount” was evaluated as follows. "Bump penetration"
A gold ball solder was formed at a predetermined position on the wafer by using a bump bonder (SBB4 manufactured by Shinkawa Co., Ltd.), which was melted and stretched to form a bump having a predetermined height.

貼付装置(RAD-3500 m/8(リンテック(株)製))を用いて、貼付速度3mm/秒、荷重0.3MPa、ラミネートローラー硬度50、ラミネートローラー温度25℃、テーブル温度25℃で
、バンプを形成したウエハに、実施例および比較例で調整したアンダーフィルテープを貼付した。貼付後、紫外線照射装置(RAD-2000 m/8(リンテック(株)製))を用い、光量110mJ/cm2、照度150mW/cm2で粘接着剤層を紫外線硬化し、基材を剥離後、下記の評価を行った。
(1)電子顕微鏡((株)日立製作所製、日立走査電子顕微鏡S-2360)を用いて、粘接着剤層の表面を観察し、バンプ頂部が粘接着剤層を貫通し、導通が可能であることを視覚的に確認した。
(2)広視野コンフォーカル顕微鏡(HD100D(レーザーテック(株)社製))を用いて、粘接着剤層表面側に貫通したバンプの高さ(μm、粘接着剤層表面からバンプ頂点までの距離)を計測(n=10)した。
Using a sticking device (RAD-3500 m / 8 (manufactured by Lintec Corporation)), with a sticking speed of 3 mm / second, a load of 0.3 MPa, a laminating roller hardness of 50, a laminating roller temperature of 25 ° C, and a table temperature of 25 ° C, The underfill tape prepared in Examples and Comparative Examples was attached to the formed wafer. After pasting, the adhesive layer is UV-cured with an ultraviolet irradiation device (RAD-2000 m / 8 (Lintec Co., Ltd.)) with a light intensity of 110 mJ / cm 2 and an illuminance of 150 mW / cm 2 , and the substrate is peeled off. Then, the following evaluation was performed.
(1) Using an electron microscope (manufactured by Hitachi, Ltd., Hitachi Scanning Electron Microscope S-2360), observe the surface of the adhesive layer, the top of the bump penetrates the adhesive layer, Visually confirmed that it was possible.
(2) Using a wide-field confocal microscope (HD100D (Lasertec Corp.)), the height of the bump penetrating the adhesive layer surface side (μm, from the adhesive layer surface to the bump apex) ) Was measured (n = 10).

また、実施例および比較例において、バインダー樹脂(A)、熱硬化性樹脂(B)、熱活性型潜在性硬化剤(C)、紫外線硬化性樹脂(D)、光重合開始剤(E)および架橋剤(F)として以下のものを用いた。
(A)バインダー樹脂(アクリル樹脂)
ブチルアクリレート55重量部、メチルメタクリレート10重量部、グリシジルメタクリレート20重量部と2−ヒドロキシエチルアクリレート15重量部とを共重合してなる重量平均分子量30万の共重合体を有機溶媒(トルエン/酢酸エチル=6/4)に溶解した溶液(固形濃度50%)
(B)熱硬化性樹脂(エポキシ樹脂)
ビスフェノールA型エポキシ樹脂(ジャパンエポキシレジン(株)社製、エピコート828
、エポキシ当量180〜200eq/g)22重量部と、固形ビスフェノールA型エポキシ樹脂(ジャパンエポキシレジン(株)製、エピコート1055、エポキシ当量800〜900eq/g)を有機溶媒(メチルエチルケトン)に溶解した溶液(固形濃度が60%)44重量部(固形比)と、o-クレゾールノボラック型エポキシ樹脂(日本化薬(株)社製、EOCN-104S、エポキシ当量210〜230g/eq)を有機溶媒(メチルエチルケトン)に溶解した溶
液(固形濃度が70%)14重量部(固形比)との混合物
(C)熱活性型潜在性硬化剤
ジシアンジアミド(旭電化工業(株)製、ハードナー3636AS)1重量部と、2-フェニル-4,5-ヒドロキシメチルイミダゾール(四国化成工業(株)製、キュアゾール2PHZ)1重量
部の混合物を有機溶媒(メチルエチルケトン)に溶解した溶液(固形濃度が30%)
(D)紫外線硬化性樹脂
ジペンタエリスリトールヘキサアクリレート
(E)ベンゾフェノン系光重合開始剤
イルガキュア184(チバスペシャルティケミカルズ(株)製)30重量部を有機溶媒(トルエン)100重量部に溶解した溶液(固形濃度が30%)
(F)イソシナネート系架橋剤
コロネートL(日本ポリウレタン工業(株)製 固形濃度75%)100重量部を有機溶媒(トルエン)172重量部に溶解した溶液(固形濃度が38%)
(実施例1)
上記成分を固形重量比で、(A)20重量部、(B)80重量部、(C)2重量部、(D)10重量部、(E)0.3重量部、(F)0.3重量部を混合し、メチルエチルケトンを固形濃度が55%になるように混合して粘接着剤層を得た。ポリエチレンテレフタレートフィルムにシリコーン樹脂を塗布した剥離フィルム(リンテック(株)製、商品名SP−PET3811)の剥離処理面にこの粘接着剤層を、乾燥後の塗布厚が35μmになるように塗布し、100℃で1分間乾燥した。次に低密度ポリエチレンフィルム(厚さ110μm、表面張力31mN/m)に貼合し、アンダーフィルテープを得た。
In the examples and comparative examples, the binder resin (A), the thermosetting resin (B), the thermally activated latent curing agent (C), the ultraviolet curable resin (D), the photopolymerization initiator (E), and The following were used as a crosslinking agent (F).
(A) Binder resin (acrylic resin)
A copolymer having a weight average molecular weight of 300,000 obtained by copolymerization of 55 parts by weight of butyl acrylate, 10 parts by weight of methyl methacrylate, 20 parts by weight of glycidyl methacrylate and 15 parts by weight of 2-hydroxyethyl acrylate was converted into an organic solvent (toluene / ethyl acetate). = 6/4) dissolved solution (solid concentration 50%)
(B) Thermosetting resin (epoxy resin)
Bisphenol A type epoxy resin (Japan Epoxy Resin Co., Ltd., Epicoat 828
, Epoxy equivalent 180-200 eq / g) 22 parts by weight and solid bisphenol A type epoxy resin (Japan Epoxy Resin Co., Ltd., Epicoat 1055, epoxy equivalent 800-900 eq / g) dissolved in organic solvent (methyl ethyl ketone) (Solid concentration is 60%) 44 parts by weight (solid ratio) and o-cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., EOCN-104S, epoxy equivalent 210-230 g / eq) in an organic solvent (methyl ethyl ketone) (C) 1 part by weight of a heat-activatable latent curing agent dicyandiamide (manufactured by Asahi Denka Kogyo Co., Ltd., Hardener 3636AS) A mixture of 1 part by weight of 2-phenyl-4,5-hydroxymethylimidazole (manufactured by Shikoku Kasei Kogyo Co., Ltd., Curesol 2PHZ) in an organic solvent (methyl ethyl ketone) Solution solution (solid concentration 30%)
(D) Ultraviolet curable resin dipentaerythritol hexaacrylate (E) Benzophenone photopolymerization initiator Irgacure 184 (Ciba Specialty Chemicals Co., Ltd.) 30 parts by weight in an organic solvent (toluene) 100 parts by weight (solid) (Concentration is 30%)
(F) Isocyanate-based crosslinking agent Coronate L (manufactured by Nippon Polyurethane Industry Co., Ltd., solid concentration 75%) 100 parts by weight of an organic solvent (toluene) 172 parts by weight (solid concentration 38%)
Example 1
(A) 20 parts by weight, (B) 80 parts by weight, (C) 2 parts by weight, (D) 10 parts by weight, (E) 0.3 parts by weight, (F) 0. 3 parts by weight was mixed, and methyl ethyl ketone was mixed so that the solid concentration was 55% to obtain an adhesive layer. This adhesive layer was applied to the release surface of a release film (trade name SP-PET3811, manufactured by Lintec Co., Ltd.) in which a silicone resin was applied to a polyethylene terephthalate film so that the applied thickness after drying was 35 μm. And dried at 100 ° C. for 1 minute. Next, it was bonded to a low density polyethylene film (thickness 110 μm, surface tension 31 mN / m) to obtain an underfill tape.

(実施例2)
乾燥後の粘接着剤層の塗布厚が45μmになるように塗布したほかは実施例1と同様にアンダーフィルテープを得た。
(Example 2)
An underfill tape was obtained in the same manner as in Example 1 except that the coating thickness of the adhesive layer after drying was 45 μm.

(実施例3)
乾燥後の粘接着剤層の塗布厚が50μmになるように塗布したほかは実施例1と同様にアンダーフィルテープを得た。
(Example 3)
An underfill tape was obtained in the same manner as in Example 1 except that the coating thickness of the adhesive layer after drying was 50 μm.

(実施例4)
乾燥後の粘接着剤層の塗布厚が60μmになるように塗布したほかは実施例1と同様にアンダーフィルテープを得た。
Example 4
An underfill tape was obtained in the same manner as in Example 1 except that the coating thickness of the adhesive layer after drying was 60 μm.

(実施例5)
実施例1で得られた粘接着剤組成物を、剥離フィルム(リンテック(株)製、商品名SP−PET3811)の剥離処理面に、乾燥後の粘接着剤層の塗布厚が50μmになるように塗布し、100℃で1分間乾燥した。次に低密度ポリエチレンフィルム(厚さ50μm、表面張力32mN/m)に貼合し、アンダーフィルテープを得た。
(Example 5)
The adhesive thickness obtained in Example 1 was applied to the release-treated surface of a release film (trade name SP-PET3811, manufactured by Lintec Corporation), and the coating thickness of the adhesive layer after drying was 50 μm. It was applied so that it was dried at 100 ° C. for 1 minute. Next, it was bonded to a low density polyethylene film (thickness 50 μm, surface tension 32 mN / m) to obtain an underfill tape.

(実施例6)
実施例1で得られた粘接着剤組成物を、剥離フィルム(リンテック(株)製、商品名SP−PET3811)の剥離処理面に、乾燥後の粘接着剤層の塗布厚が50μmになるように塗布し、100℃で1分間乾燥した。次に低密度ポリエチレンフィルム(厚さ160μm、表面張力31mN/m)に貼合し、アンダーフィルテープを得た。
(Example 6)
The adhesive thickness obtained in Example 1 was applied to the release-treated surface of a release film (trade name SP-PET3811, manufactured by Lintec Corporation), and the coating thickness of the adhesive layer after drying was 50 μm. It was applied so that it was dried at 100 ° C. for 1 minute. Next, it was bonded to a low density polyethylene film (thickness 160 μm, surface tension 31 mN / m) to obtain an underfill tape.

(実施例7)
所定の回路パターンを形成した半導体ウエハ(6インチ、厚さ300μm、バンプ高さ
55μm)の回路面に実施例1のアンダーフィルテープを貼付し、バンプ頂部を基材内に
貫入させた。(テープ貼付装置:Adwill RAD−2500m/8;リンテック(株)社製)。ついでアンダーフィルテープの基材側より紫外線照射(紫外線照射装置:Adwill RAD−2000m/8;リンテック(株)社製)を行った。
(Example 7)
The underfill tape of Example 1 was applied to the circuit surface of a semiconductor wafer (6 inches, thickness 300 μm, bump height 55 μm) on which a predetermined circuit pattern was formed, and the bump tops were penetrated into the substrate. (Tape sticking device: Adwill RAD-2500m / 8; manufactured by Lintec Corporation). Subsequently, ultraviolet irradiation (ultraviolet irradiation device: Adwill RAD-2000m / 8; manufactured by Lintec Corporation) was performed from the substrate side of the underfill tape.

ダイシング装置(DFG−2H/6T;(株)ディスコ社製)を使用して、ウエハ回路
面のダイシングラインに沿ってウエハ裏面に印を付け、これを元に回路パターン毎に切断分離し、チップを得た。次いで基材を剥離し、チップ回路面に粘接着剤層を残存させた状態で、チップをピックアップし、チップトレーに収納した。
Using a dicing machine (DFG-2H / 6T; manufactured by DISCO Corporation), the wafer back surface is marked along the dicing line on the wafer circuit surface, and the circuit pattern is cut and separated on the basis of this. Got. Next, the substrate was peeled off, and the chip was picked up and stored in a chip tray with the adhesive layer remaining on the chip circuit surface.

次いでフリップチップボンダー(FB30T−M 九州松下電器産業(株)社製)を用い、バンプの位置に対応する配線パターンを有する評価用のチップ搭載用基板に実装した。実装の際の、ステージ温度は60℃、ヘッド温度は130℃、荷重は20N、時間は60秒とした。   Next, using a flip chip bonder (FB30T-M manufactured by Kyushu Matsushita Electric Industrial Co., Ltd.), it was mounted on an evaluation chip mounting substrate having a wiring pattern corresponding to the position of the bump. During mounting, the stage temperature was 60 ° C., the head temperature was 130 ° C., the load was 20 N, and the time was 60 seconds.

実装後、150℃のオーブン中で60分保持し、粘接着剤層を完全に硬化させ半導体装置を得た。得られた半導体装置の各端子間の抵抗値を低抵抗率計(Loresta−GPMCP−T600;三菱化学社製)を用いて測定し、導通すべき端子間の導通と、その他の端子間の絶縁を確認した。
(比較例1)
乾燥後の粘接着剤層の塗布厚が10μmになるように塗布したほかは実施例5と同様にアンダーフィルテープを得た。
(比較例2)
乾燥後の粘接着剤層の塗布厚が65μmになるように塗布したほかは実施例1と同様にアンダーフィルテープを得た。
After mounting, it was kept in an oven at 150 ° C. for 60 minutes, and the adhesive layer was completely cured to obtain a semiconductor device. The resistance value between each terminal of the obtained semiconductor device is measured using a low resistivity meter (Loresta-GPMCP-T600; manufactured by Mitsubishi Chemical Corporation), and conduction between terminals to be conducted and insulation between other terminals are measured. It was confirmed.
(Comparative Example 1)
An underfill tape was obtained in the same manner as in Example 5 except that the coating thickness of the adhesive layer after drying was 10 μm.
(Comparative Example 2)
An underfill tape was obtained in the same manner as in Example 1 except that the adhesive layer was dried so that the thickness of the adhesive layer after drying was 65 μm.

以上の結果を表1にまとめる。
(比較例3)
実施例1で得られた粘接着剤組成物を、剥離フィルム(リンテック(株)製、商品名SP−PET3811)の剥離処理面に、乾燥後の粘接着剤層の塗布厚が50μmになるように塗布し、100℃で1分間乾燥した。次にポリプロピレンフィルム(厚さ20μm、表面張力31mN/m)に貼合し、アンダーフィルテープを得た。
The results are summarized in Table 1.
(Comparative Example 3)
The adhesive thickness obtained in Example 1 was applied to the release-treated surface of a release film (trade name SP-PET3811, manufactured by Lintec Corporation), and the coating thickness of the adhesive layer after drying was 50 μm. It was applied so that it was dried at 100 ° C. for 1 minute. Next, it was bonded to a polypropylene film (thickness 20 μm, surface tension 31 mN / m) to obtain an underfill tape.

Figure 2006261529
Figure 2006261529

本発明に係るフリップチップ実装用アンダーフィルテープの断面図である。It is sectional drawing of the underfill tape for flip chip mounting which concerns on this invention. バンプを形成した半導体ウエハの断面図である。It is sectional drawing of the semiconductor wafer in which bump was formed. ウエハにフリップチップ実装用アンダーフィルテープを貼付した状態を示す。The state which affixed the underfill tape for flip chip mounting to the wafer is shown. 粘接着剤層をバンプが貫通した状態を示す。The state which the bump penetrated the adhesive layer is shown.

符号の説明Explanation of symbols

1…基材
2…粘接着剤層
3…剥離フィルム
4…フリップチップ実装用アンダーフィルテープ
5…バンプ
6…半導体ウエハ
7…半導体チップ
DESCRIPTION OF SYMBOLS 1 ... Base material 2 ... Adhesive layer 3 ... Release film 4 ... Underfill tape 5 for flip chip mounting ... Bump 6 ... Semiconductor wafer 7 ... Semiconductor chip

Claims (2)

基材と、その上に剥離可能に形成された粘接着剤層とからなり、
回路面にバンプを有する半導体ウエハの回路面に、粘接着剤層を貼付すると同時に、該バンプが粘接着剤層を貫通し、バンプ頂部を基材内に貫入する工程を含む半導体装置の製造方法に使用されるフリップチップ実装用アンダーフィルテープであって、
該バンプの平均高さ(HB)と、粘接着剤層の厚み(TA)との比(HB/TA)が1.0/0.3〜1.0/0.95の範囲にあり、基材の厚み(TS)と、粘接着剤層の厚み(
A)との比(TS/TA)が0.5以上であるフリップチップ実装用アンダーフィルテー
プ。
It consists of a base material and an adhesive layer formed so as to be peelable thereon,
A semiconductor device comprising a step of attaching an adhesive layer to a circuit surface of a semiconductor wafer having bumps on a circuit surface, and simultaneously, the bump penetrates the adhesive layer and penetrates the top of the bump into a substrate. An underfill tape for flip chip mounting used in a manufacturing method,
The ratio (H B / T A ) between the average height (H B ) of the bumps and the thickness (T A ) of the adhesive layer is 1.0 / 0.3 to 1.0 / 0.95 The thickness of the base material (T S ) and the thickness of the adhesive layer (
T A) and the ratio (T S / T A) underfill tape for flip-chip mounting is 0.5 or more.
回路面にバンプを有する半導体ウエハの回路面に、請求項1に記載のフリップチップ実装用アンダーフィルテープの粘接着剤層を貼付すると同時に、該バンプが粘接着剤層を貫通し、バンプ頂部を基材内に貫入する工程、
該半導体ウエハを回路毎に個別のチップに切断分離する工程、
粘接着剤層面から基材を剥離し、バンプ頂部を露出させる工程、
チップ搭載用基板の所定位置に、チップのバンプ形成面を載置し、チップとチップ搭載用基板との導通を確保しながら、粘接着剤層を介してチップをチップ搭載用基板に接着固定する工程からなる半導体装置の製造方法。
The adhesive layer of the underfill tape for flip chip mounting according to claim 1 is applied to the circuit surface of a semiconductor wafer having bumps on the circuit surface, and at the same time, the bumps penetrate the adhesive layer, A step of penetrating the top portion into the base material,
Cutting and separating the semiconductor wafer into individual chips for each circuit;
Peeling the substrate from the adhesive layer surface to expose the bump top,
Place the bump formation surface of the chip at a predetermined position on the chip mounting board, and secure the conduction between the chip and the chip mounting board, and adhere and fix the chip to the chip mounting board through the adhesive layer A method for manufacturing a semiconductor device comprising the steps of:
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