JP2005106881A - Liquid crystal display device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve such a problem that in the conventional manufacturing method wherein the number of manufacturing steps is reduced, when a channel length is shortened, a manufacturing margin is small and a yield is lowered. <P>SOLUTION: A four sheet mask process and a three sheet mask process of TN type and IPS type liquid crystal display devices are constructed by combining technologies of a novel technology which first forms an etch stop layer and then rationalizes a scanning line forming step and a contact forming step by introducing a halftone exposure technology, a new technology which rationalizes a step for forming a protective layer of an electrode terminal by introducing a halftone exposure technology to an anodization step of a source/drain wiring which is a well-known technology, and a rationalization technology simultaneously forming a pixel electrode and a scanning line which is a well-known technology. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

The present invention relates to a liquid crystal display device having a color image display function, and more particularly to an active liquid crystal display device.

With recent advances in microfabrication technology, liquid crystal material technology, high-density packaging technology, and the like, television images and various image display devices are provided in large quantities on a commercial basis in 5 to 50 cm diagonal liquid crystal display devices. Further, color display is easily realized by forming an RGB colored layer on one of the two glass substrates constituting the liquid crystal panel. In particular, so-called active liquid crystal panels in which switching elements are built in for each picture element have little crosstalk, fast response speed, and an image having a high contrast ratio.

 These liquid crystal display devices (liquid crystal panels) generally have a matrix organization of 200 to 1200 scanning lines and 300 to 1600 signal lines, but recently, a large screen is required to cope with an increase in display capacity. And high definition are progressing simultaneously.

FIG. 23 shows a mounting state on the liquid crystal panel, and a semiconductor integrated circuit that supplies a drive signal to the electrode terminal group 5 of the scanning line formed on one transparent insulating substrate, for example, the glass substrate 2 constituting the liquid crystal panel 1. A COG (Chip-On-Glass) system in which the chip 3 is connected using a conductive adhesive, or a copper foil terminal (not shown) based on, for example, a polyimide resin thin film and plated with gold or solder. An electrical signal is supplied to the image display unit by a mounting means such as a TCP (Tape-Carrier-Package) system in which the TCP film 4 is fixed to the electrode terminal group 6 of the signal line by pressing with an appropriate adhesive containing a conductive medium. The Here, for convenience, two mounting methods are shown at the same time, but in actuality, either method is appropriately selected.

Wiring paths 7 and 8 connect the pixels in the image display unit located almost at the center of the liquid crystal panel 1 to the electrode terminals 5 and 6 of the scanning lines and signal lines, and are not necessarily the same as the electrode terminal groups 5 and 6. It is not necessary to be made of a conductive material. Reference numeral 9 denotes a counter glass substrate or color filter which is another transparent insulating substrate having a transparent conductive counter electrode common to all liquid crystal cells on the counter surface.

  FIG. 24 shows an equivalent circuit diagram of an active liquid crystal display device in which insulated gate transistors 10 are arranged for each picture element as a switching element, 11 (7 in FIG. 23) is a scanning line, and 12 (8 in FIG. 23) is a signal. A line 13 is a liquid crystal cell, and the liquid crystal cell 13 is electrically treated as a capacitive element. The elements drawn with solid lines are formed on one glass substrate 2 constituting the liquid crystal panel, and the counter electrode 14 common to all liquid crystal cells 13 drawn with dotted lines is the main electrode facing the other glass substrate 9. It is formed on the surface. When the OFF resistance of the insulated gate transistor 10 or the resistance of the liquid crystal cell 13 is low, or when importance is attached to the gradation of the display image, an auxiliary storage capacitor 15 for increasing the time constant of the liquid crystal cell 13 as a load. Is added to the liquid crystal cell 13 in parallel. Reference numeral 16 denotes a common bus of the storage capacitor 15.

  FIG. 25 is a cross-sectional view of the main part of the image display portion of the liquid crystal display device. The two glass substrates 2 and 9 constituting the liquid crystal panel 1 are columnar spacers formed on resinous fibers, beads or color filters 9. Are formed at a predetermined distance of about several μm by a spacer material (not shown) such as a sealing material made of an organic resin and a sealing material (both shown in the figure) at the peripheral edge of the glass substrate 9. The liquid crystal 17 is filled in this closed space.

  In the case of realizing color display, an organic thin film having a thickness of about 1 to 2 μm containing either or both of a dye and a pigment called a colored layer 18 is deposited on the closed space side of the glass substrate 9 to provide a color display function. In this case, the glass substrate 9 is also called a color filter (color filter abbreviation is CF). Depending on the properties of the liquid crystal material 17, a polarizing plate 19 is attached to either or both of the upper surface of the glass substrate 9 and the lower surface of the glass substrate 2, and the liquid crystal panel 1 functions as an electro-optical element. Currently, most liquid crystal panels on the market use a TN (twisted nematic) type liquid crystal material, and two polarizing plates 19 are usually required. Although not shown, in the transmissive liquid crystal panel, a back light source is disposed as a light source, and white light is irradiated from below.

The polyimide resin thin film 20 having a thickness of, for example, about 0.1 μm formed on the two glass substrates 2 and 9 in contact with the liquid crystal 17 is an alignment film for aligning liquid crystal molecules in a predetermined direction. Reference numeral 21 denotes a drain electrode (wiring) that connects the drain of the insulated gate transistor 10 and the transparent conductive pixel electrode 22, and is often formed simultaneously with the signal line (source line) 12. The semiconductor layer 23 is located between the signal line 12 and the drain electrode 21 and will be described in detail later. The Cr thin film layer 24 having a thickness of about 0.1 μm formed at the boundary between the adjacent colored layers 18 on the color filter 9 prevents external light from entering the semiconductor layer 23, the scanning line 11, and the signal line 12. It is a technology that is fixed as a so-called black matrix (Black Matrix abbreviation is BM).

Here, a structure and a manufacturing method of an insulated gate transistor as a switching element will be described. Two types of insulated gate transistors are currently widely used, and one of them called etch stop type is introduced as a conventional example. With the introduction of the dry etch technology, the number of photomasks that were originally required to be about eight is reduced to five at the present time, greatly contributing to the reduction of process costs. FIG. 26 is a plan view of unit picture elements of an active substrate (semiconductor device for display device) that constitutes a conventional liquid crystal panel, on the lines AA ′, BB ′, and CC ′ of FIG. FIG. 27 shows a cross-sectional view of this, and the manufacturing process will be briefly described below.

First, as shown in FIGS. 26 (a) and 27 (a), a glass substrate 2 having a thickness of about 0.5 to 1.1 mm as an insulating substrate having high heat resistance, chemical resistance, and transparency, for example, Corning. A first metal layer having a film thickness of about 0.1 to 0.3 μm is deposited on one main surface of a product name 1737 manufactured by the company using a vacuum film-forming apparatus such as SPT (sputtering), and fine processing technology is used. The scanning line 11 that also serves as the gate electrode 11A and the storage capacitor line 16 are selectively formed. The scanning line material is selected by comprehensively considering heat resistance, chemical resistance, hydrofluoric acid resistance, and conductivity, but generally a metal or alloy having high heat resistance such as Cr, Ta, MoW alloy is used. Is done.

  It is reasonable to use AL (aluminum) as the material of the scanning line in order to reduce the resistance value of the scanning line in response to the increase in the screen size and resolution of the liquid crystal panel, but AL alone has heat resistance. Since it is low, it is a common technique to stack with Cr, Ta, Mo or their silicides as mentioned above, or to add an oxide layer (Al2O3) by anodic oxidation on the surface of AL. That is, the scanning line 11 is composed of one or more metal layers.

Next, a first SiNx (silicon nitride) layer 30 serving as a gate insulating layer is formed on the entire surface of the glass substrate 2 by using a PCVD (plasma sieve fluid) apparatus, and a first serving as a channel of an insulated gate transistor containing almost no impurities. The amorphous silicon (a-Si) layer 31, the second SiNx layer 32 serving as an insulating layer for protecting the channel, and three kinds of thin film layers are, for example, about 0.3 to 0.05 μm. Sequentially deposited by the film thickness, the second SiNx layer on the gate electrode 11A is selectively left narrower than the gate electrode 11A by microfabrication technology as shown in FIGS. 26 (b) and 27 (b). Thus, the first amorphous silicon layer 31 is exposed as the channel protective layer 32D.

Subsequently, a second amorphous silicon layer 33 containing, for example, phosphorus as an impurity is deposited on the entire surface using a PCVD apparatus in a thickness of about 0.05 μm, for example, and then FIG. 26 (c) and FIG. ) Using a vacuum film-forming apparatus such as SPT, a heat-resistant metal thin film layer 34 of, for example, Ti, Cr, Mo or the like as a heat-resistant metal layer having a film thickness of about 0.1 μm, and a film thickness of 0 as a low-resistance wiring layer. Then, an AL thin film layer 35 having a thickness of about 3 μm and a Ti thin film layer 36, for example, are sequentially deposited as an intermediate conductive layer having a thickness of about 0.1 μm. , 35A and 36A, the drain electrode 21 of the insulated gate transistor and the signal line 12 also serving as the source electrode are selectively formed. In this selective pattern formation, the Ti thin film layer 36, the AL thin film layer 35, and the Ti thin film layer 34 are sequentially etched using the photosensitive resin pattern used for forming the source / drain wiring as a mask, and then the source / drain electrodes 12, The second amorphous silicon layer 33 between the two regions 21 is removed to expose the second SiNx layer 32D, and the first amorphous silicon layer 31 is also removed in other regions to form the gate insulating layer 30. Made by exposing. As described above, since the second SiNx layer 32D serving as a channel protective layer exists and the etching of the second amorphous silicon layer 33 is automatically terminated, this manufacturing method is called an etch stop.

  The source / drain electrodes 12 and 21 are formed to partially overlap (several μm) in plan with the etch stop layer 32D so that the insulated gate transistor does not have an offset structure. Since this overlap is electrically acting as a parasitic capacitance, the smaller the better, the better. However, it is determined by the alignment accuracy of the exposure machine, the accuracy of the photomask, the expansion coefficient of the glass substrate, and the glass substrate temperature at the time of exposure. It is about 2 μm.

Further, after removing the photosensitive resin pattern, a SiNx layer having a thickness of about 0.3 μm is deposited on the entire surface of the glass substrate 2 as a transparent insulating layer using a PCVD apparatus in the same manner as the gate insulating layer. As the insulating layer 37, as shown in FIGS. 26D and 27D, the passivation insulating layer 37 is selectively removed by a microfabrication technique, an opening 62 is formed on the drain electrode 21, and an image display unit. In the outer region, an opening 63 is formed on the position where the electrode terminal 5 of the scanning line 11 is formed, and an opening 64 is formed on the position where the electrode terminal 6 of the signal line 12 is formed, so that the drain electrode 21 and the scanning line are formed. 11 and a part of the signal line 12 are exposed. An opening 65 is formed on the storage capacitor line 16 (electrode pattern in which the storage capacitor lines are bundled in parallel) to expose a part of the storage capacitor line 16.

Finally, for example, ITO (Indium-Tin-Oxide) or IZO (Indium-Zinc-Oxide) is applied as a transparent conductive layer having a film thickness of about 0.1 to 0.2 μm using a vacuum film forming apparatus such as SPT. As shown in FIGS. 26 (e) and 27 (e), the pixel electrode 22 is selectively formed on the passivation insulating layer 37 including the opening 62 by a microfabrication technique, and the active substrate 2 is completed. A part of the exposed scanning line 11 in the opening 63 may be used as the electrode terminal 5 and a part of the exposed signal line 12 in the opening 64 may be used as the electrode terminal 6. As shown in FIG. The electrode terminals 5A and 6A made of ITO may be selectively formed on the passivation insulating layer 37 including 63 and 64, but normally the transparent conductive short-circuit line 40 connecting the electrode terminals 5A and 6A is also provided. Formed simultaneously. The reason is that although not shown, the resistance between the electrode terminals 5A and 6A and the short-circuit line 40 can be increased in resistance by increasing the resistance by forming an elongated stripe. Similarly, an electrode terminal to the storage capacitor line 16 is formed including the opening 65.

When the wiring resistance of the signal line 12 does not become a problem, the low resistance wiring layer 35 made of AL is not necessarily required. In this case, the source / drain wiring 12 can be selected by selecting a heat-resistant metal material such as Cr, Ta, and Mo. , 21 can be simplified by forming a single layer. As described above, it is important that the source / drain wiring is a refractory metal layer to ensure electrical connection with the second amorphous silicon layer. The heat resistance of the insulated gate transistor is described in detail in Japanese Patent Application Laid-Open No. 7-74368, which is a prior example. In FIG. 27 (c), the storage capacitor 15 is formed by a region 50 (shaded portion to the right) where the storage capacitor line 16 and the drain electrode 21 overlap with each other via the gate insulating layer 30. Detailed description is omitted.
JP-A-7-74368

Although the detailed process of the five-mask process described above is omitted, it was obtained as a result of streamlining the semiconductor layer islanding process and reducing the contact formation process once. The photomask, which has been reduced to 5 at the present time due to the introduction of dry etching technology, has greatly contributed to the reduction of process costs. In order to reduce the production cost of the liquid crystal display device, it is a well-known development target that it is effective to reduce the process cost in the manufacturing process of the active substrate and the member cost in the panel assembly process and the module mounting process. In order to lower the process cost, there are a process reduction that shortens the process and a cheap process development or replacement with a process. Here, the process is reduced to a four-mask process where an active substrate can be obtained with four photomasks. An example will be described. The four-mask process is to reduce the photolithography process by introducing halftone exposure technology. FIG. 28 is a plan view of unit picture elements of an active substrate corresponding to the four-mask process. FIG. FIG. 29 is a cross-sectional view taken along the lines AA ′, BB ′, and CC ′ of FIG. As already described, two types of insulated gate transistors are currently widely used. Here, a channel-etched insulated gate transistor is used.

First, a first metal layer having a film thickness of about 0.1 to 0.3 μm is deposited on one main surface of the glass substrate 2 using a vacuum film forming apparatus such as SPT, as in the five-mask process. As shown in FIG. 28A and FIG. 29A, the scanning line 11 that also serves as the gate electrode 11A and the storage capacitor line 16 are selectively formed by a fine processing technique.

Next, a SiNx layer 30 that becomes a gate insulating layer using a PCVD apparatus on the entire surface of the glass substrate 2, a first amorphous silicon layer 31 that contains almost no impurities and becomes a channel of an insulated gate transistor, and contains impurities. The second amorphous silicon layer 33 that becomes the source / drain of the insulated gate transistor and the three kinds of thin film layers are sequentially deposited with a film thickness of, for example, about 0.3-0.2-0.05 μm. Subsequently, using a vacuum film forming apparatus such as SPT, for example, a Ti thin film layer 34 as a heat resistant metal layer having a thickness of about 0.1 μm, and an AL thin film layer 35 as a low resistance wiring layer having a thickness of about 0.3 μm, For example, a Ti thin film layer 36, that is, a source / drain wiring material is sequentially deposited as an intermediate conductive layer of about 0.1 μm, and the drain electrode 21 of the insulated gate transistor and the signal line 12 also serving as the source electrode are selected by microfabrication technology. In this selective pattern formation, the film of the channel formation region 80B (shaded portion) between the source and drain is formed by the halftone exposure technique as shown in FIGS. 28 (b) and 29 (b). For example, photosensitive resin patterns 80A and 80B having a thickness of 1.5 μm and thinner than the film thickness of 3 μm of the source / drain wiring formation regions 80A (12) and 80A (21) are formed. The point of formation is a major feature.

Since the photosensitive resin patterns 80A and 80B usually use a positive photosensitive resin for the production of a substrate for a liquid crystal display device, the source / drain wiring formation region 80A is black, that is, a Cr thin film is formed. The channel region 80B is gray, for example, a line and space Cr pattern having a width of about 0.5 to 1 μm is formed, and the other region may be white, that is, a photomask from which the Cr thin film is removed may be used. . In the gray area, the line-and-space is not resolved because the resolving power of the exposure machine is insufficient, and it is possible to transmit about half of the photomask irradiation light from the lamp light source. According to the remaining film characteristics, photosensitive resin patterns 80A and 80B having a cross-sectional shape as shown in FIG. 29B can be obtained.

With the photosensitive resin patterns 80A and 80B as masks, as shown in FIG. 29B, the Ti thin film layer 36, the AL thin film layer 35, the Ti thin film layer 34, the second amorphous silicon layer 33, and the first non-crystalline layer 33 are used. After sequentially etching the crystalline silicon layer 31 to expose the gate insulating layer 30, as shown in FIGS. 28C and 29C, the photosensitive resin pattern 80A, When the film thickness of 80B is reduced from 3 μm to 1.5 μm or more, for example, the photosensitive resin pattern 80B disappears and the channel region is exposed, and 80C (12) and 80C (21) are formed only on the source / drain wiring formation region. Can leave. Therefore, the Ti thin film layer, the AL thin film layer, the Ti thin film layer, and the second amorphous film between the source and drain wirings (channel formation region) are again formed using the photosensitive resin patterns 80C (12) and 80C (21) whose thickness has been reduced. The porous silicon layer 33A and the first amorphous silicon layer 31A are sequentially etched, and the first amorphous silicon layer 31A is etched leaving about 0.05 to 0.1 μm. Since the source / drain wiring is formed by etching the metal layer and etching the first amorphous silicon layer 31A leaving about 0.05 to 0.1 μm, an insulated gate type obtained by such a manufacturing method is used. The transistor is called channel etch. In the oxygen plasma treatment, it is desirable to increase the anisotropy in order to suppress the change in pattern dimension, and the reason will be described later.

Further, after the photosensitive resin patterns 80C (12) and 80C (21) are removed, the entire surface of the glass substrate 2 is formed as shown in FIGS. 28 (d) and 29 (d) as in the five-mask process. A SiNx layer having a thickness of about 0.3 μm is deposited as a transparent insulating layer to form a passivation insulating layer 37, and openings are formed in regions where the electrode terminals of the drain electrode 21, the scanning line 11, and the signal line 12 are formed. 62, 63, 64 are formed, the passivation insulating layer 37 and the gate insulating layer 30 in the opening 63 are removed to expose a part of the scanning line, and the passivation insulating layer 37 in the openings 62, 64 is exposed. By removing, a part of the drain electrode 21 and a part of the signal line are exposed.

Finally, for example, ITO or IZO is deposited as a transparent conductive layer having a film thickness of about 0.1 to 0.2 μm using a vacuum film forming apparatus such as SPT, as shown in FIGS. 28 (e) and 29 (e). As described above, the transparent conductive picture element electrode 22 including the opening 62 is selectively formed on the passivation insulating layer 37 by the fine processing technique to complete the active substrate 2. In this case, transparent conductive electrode terminals 5A and 6A made of ITO are selectively formed on the passivation insulating layer 37 including the openings 63 and 64.

  In this way, in the five-mask process and the four-mask process, the contact formation process to the drain electrode 21 and the scanning line 11 is performed at the same time. Therefore, the thickness of the insulating layer in the openings 62 and 63 corresponding to them is determined. The types are different. The passivation insulating layer 37 has a lower film forming temperature and inferior film quality compared to the gate insulating layer 30, and the etching rate with a hydrofluoric acid-based etching solution is several thousand liters / minute and several hundreds liters / minute, which is one digit. In contrast, the cross-sectional shape of the opening 62 on the drain electrode 21 employs dry etching using a fluorine-based gas for the reason that too much etching occurs at the top and the hole diameter cannot be controlled.

Even if dry etching is employed, since the opening 62 on the drain electrode 21 is only the passivation insulating layer 37, over-etching is unavoidable as compared with the opening 63 on the scanning line 11. Depending on the material, The intermediate conductive layer 36A may be reduced in thickness by the etching gas. In removing the photosensitive resin pattern after the etching, the surface of the photosensitive resin pattern is first scraped by about 0.1 to 0.3 μm by oxygen plasma ashing in order to remove the polymer on the fluorinated surface. In general, chemical treatment using an organic stripping solution such as Tokyo Ohka stripping solution 106 is performed, but the intermediate conductive layer 36A is reduced in thickness and the underlying aluminum layer 35A is exposed. If so, AL2O3, which is an insulator, is formed on the surface of the aluminum layer 35A by the oxygen plasma ashing treatment, and ohmic contact with the pixel electrode 22 cannot be obtained. Thus, the thickness of the intermediate conductive layer 36A is set to be as thick as, for example, 0.2 μm so that the film can be reduced. Alternatively, when the openings 62 to 65 are formed, it is possible to avoid the formation of the pixel electrode 22 after removing the aluminum layer 35A and exposing the thin film layer 34A which is the underlying heat-resistant metal layer. There is also an advantage that the intermediate conductive layer 36A is unnecessary from the beginning.

However, if the in-plane uniformity of the film thickness of these thin films is not good in the former measure, this approach does not necessarily work effectively, and the same is true when the in-plane uniformity of the etching speed is not good. is there. The latter measure eliminates the need for the intermediate conductive layer 36A, but the number of steps for removing the aluminum layer 35A increases, and if the cross section control of the opening 62 is insufficient, the pixel electrode 22 may be disconnected. .

In addition, in the channel-etched insulated gate transistor, the first amorphous silicon layer 31 that does not contain impurities in the channel region must be deposited thickly (usually 0.2 μm or more). The transistor characteristics, particularly the OFF current, tend to be uneven due to the great influence of the uniformity inside. This greatly affects the operating rate of PCVD and the state of particle generation, and is very important from the viewpoint of production cost.

In addition, the channel forming process applied in the four-mask process selectively removes the source / drain wiring material between the source / drain wirings 12 and 21 and the semiconductor layer containing impurities, so that the insulated gate transistor is turned on. This is a step of determining the length of the channel (4 to 6 μm in the current mass-produced product) that greatly affects the characteristics. This variation in the channel length greatly changes the ON current value of the insulated gate transistor, and therefore, strict manufacturing control is usually required. Strength and pattern accuracy of photomask (especially line & space dimensions), photosensitive resin coating thickness, photosensitive resin phenomenon treatment, and the amount of photosensitive resin film reduction in the etching process, etc. In combination with the in-plane uniformity of these quantities, it is not always possible to produce products stably at a high yield, and even more stringent manufacturing management is required than conventional manufacturing management, and it can be said that it is at a highly completed level. There is no current situation. In particular, when the channel length is 6 μm or less, the influence of the pattern size generated with a decrease in the film thickness of the resist pattern is large, and this tendency becomes remarkable.

The present invention has been made in view of the current situation, and not only avoids the troubles in forming contacts common to the conventional 5-mask process and 4-mask process, but also adopts a halftone exposure technique with a large manufacturing margin. Thus, the manufacturing process can be reduced. In addition, it is clear that there is a need to pursue further reductions in the number of manufacturing processes in order to reduce the price of liquid crystal panels and respond to the increase in demand. The value of the present invention is further enhanced by providing a technique for simplifying the process or reducing the cost.

In the present invention, the etch stop layer is first formed, and then the halftone exposure technique is applied to the scanning line forming process for easy pattern accuracy management and the contact forming process for electrical connection to the scanning line. This reduces the number of manufacturing processes. Then, in order to effectively passivate only the source / drain wiring, it is combined with an anodic oxidation technique for forming an insulating layer on the surface of the source / drain wiring made of aluminum disclosed in Japanese Patent Laid-Open No. 2-216129 which is a prior art. The aim is to achieve rationalization of processes and low temperatures. Furthermore, a streamlined pixel electrode forming process disclosed in Japanese Patent Application Laid-Open No. 8-136951, which is a prior art, is adopted in conformity with the present invention. In order to further reduce the process, the halftone exposure technique is applied to the formation of the anodic oxide layer of the source / drain wiring, thereby rationalizing the electrode terminal protective layer forming process.
JP-A-2-216129 JP-A-8-136951

The liquid crystal display device according to claim 1 is connected to at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a drain wiring on one main surface. A first transparent insulating substrate in which unit pixel elements each having a pixel electrode are arranged in a two-dimensional matrix; and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In a liquid crystal display device in which liquid crystal is filled in between,
A scanning line comprising at least one first metal layer on one main surface of the first transparent insulating substrate and having an insulating layer on its side surface is formed,
One or more gate insulating layers are formed on the scanning lines;
A first semiconductor layer containing no impurities is formed in an island shape on the gate insulating layer over the gate electrode;
A protective insulating layer is formed on the first semiconductor layer so as to be narrower than the gate electrode;
A second semiconductor layer including a pair of impurities is formed on a part of the protective insulating layer and on the first semiconductor layer;
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display part, and a part of the scanning line is exposed,
Source (signal line) / drain wiring comprising at least one anodizable metal layer including a refractory metal layer on the second semiconductor layer and the first transparent insulating substrate, and the opening and opening The electrode terminal of the scanning line is also formed including the first and second semiconductor layers around the part,
A transparent conductive pixel electrode is formed on a part of the drain wiring and the first transparent insulating substrate, and a transparent conductive electrode terminal is formed on the signal line in a region outside the image display unit,
An anodic oxide layer is formed on the surface of the source / drain wiring except for a region overlapping the pixel electrode of the drain wiring and an electrode terminal region of the signal line.

With this configuration, the gate insulating layer is formed with the same pattern width as the scanning line, and an insulating layer different from the gate insulating layer is provided on the side surface of the scanning line, so that the scanning line and the signal line can intersect. . This is a structural feature common to the liquid crystal display device of the present invention. The transparent conductive pixel electrode is formed on a glass substrate, and a protective insulating layer is formed on the channel between the source and drain to protect the channel, and an insulating anode is formed on the surface of the signal line and drain wiring. Since a tantalum pentoxide (Ta 2 O 5) or aluminum oxide (Al 2 O 3) that is an oxide layer is formed to provide a passivation function, it is not necessary to deposit the passivation insulating layer on the entire surface of the glass substrate, and the heat resistance of the insulated gate transistor No longer becomes a problem. Thus, a TN liquid crystal display device having a transparent conductive electrode terminal is obtained.

The liquid crystal display device according to claim 2 is also provided with a scanning line comprising at least one first metal layer on one main surface of the first transparent insulating substrate and having an insulating layer on its side surface, and transparent conductive material. Pixel electrodes and signal line electrode terminals are formed,
One or more gate insulating layers are formed on the scanning lines;
A first semiconductor layer containing no impurities is formed in an island shape on the gate insulating layer over the gate electrode;
A protective insulating layer is formed on the first semiconductor layer so as to be narrower than the gate electrode;
A second semiconductor layer including a pair of impurities is formed on a part of the protective insulating layer and on the first semiconductor layer;
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display part, and a part of the scanning line is exposed,
An electrode terminal of a transparent conductive scanning line is formed including the opening and the first and second semiconductor layers around the opening,
A source wiring (signal line) including one or more second metal layers including a refractory metal layer on the second semiconductor layer, the first transparent insulating substrate, and a part of the electrode terminal of the signal line. ), Drain wiring is also formed on the second semiconductor layer, the first transparent insulating substrate, and a part of the pixel electrode,
A photosensitive organic insulating layer is formed on the source / drain wiring.

With this configuration, a transparent conductive pixel electrode is formed on a glass substrate, and a protective insulating layer is formed on the channel between the source and drain to protect the channel and the surface of the source / drain wiring is photosensitive organic. Since the insulating layer is formed to provide a passivation function, it is not necessary to deposit the passivation insulating layer on the entire surface of the glass substrate, and the heat resistance of the insulated gate transistor does not become a problem. Thus, a TN liquid crystal display device having a transparent conductive electrode terminal is obtained.

The liquid crystal display device according to claim 3 is similarly
A scanning line comprising a laminate of a transparent conductive layer and a first metal layer on at least one main surface of the first transparent insulating substrate and having an insulating layer on its side surface; a transparent conductive pixel electrode; and a signal line Electrode terminals are formed,
One or more gate insulating layers are formed on the scanning lines;
A first semiconductor layer containing no impurities is formed in an island shape on the gate insulating layer over the gate electrode;
A protective insulating layer is formed on the first semiconductor layer so as to be narrower than the gate electrode;
A second semiconductor layer including a pair of impurities is formed on a part of the protective insulating layer and on the first semiconductor layer;
The gate insulating layer and the first metal layer on the scanning line are removed in a region outside the image display unit to expose a transparent conductive layer serving as an electrode terminal of the scanning line,
A source wiring (signal line) including one or more second metal layers including a refractory metal layer on the second semiconductor layer, the first transparent insulating substrate, and a part of the electrode terminal of the signal line. ), Drain wiring is also formed on the second semiconductor layer, the first transparent insulating substrate, and a part of the pixel electrode,
A photosensitive organic insulating layer is formed on the source / drain wiring.

With this configuration, the transparent conductive pixel electrode is formed simultaneously with the scanning line, so it is automatically formed on the glass substrate, and a protective insulating layer is formed on the channel between the source and drain to protect the channel. 3. The liquid crystal display device according to claim 2, wherein a photosensitive organic insulating layer is formed on the surface of the source / drain wiring to provide a passivation function, so that it is not necessary to deposit the passivation insulating layer on the entire surface of the glass substrate. Similar effects can be obtained.

5. The liquid crystal display device according to claim 4, wherein the scanning line is formed of a laminate of a transparent conductive layer and a first metal layer on at least one main surface of the first transparent insulating substrate, and has an insulating layer on its side surface. A transparent conductive pixel electrode is formed,
One or more gate insulating layers are formed on the scanning lines;
A first semiconductor layer containing no impurities is formed in an island shape on the gate insulating layer over the gate electrode;
A protective insulating layer is formed on the first semiconductor layer so as to be narrower than the gate electrode;
A second semiconductor layer including a pair of impurities is formed on a part of the protective insulating layer and on the first semiconductor layer;
The gate insulating layer and the first metal layer on the scanning line are removed in a region outside the image display unit to expose a transparent conductive layer that is a part of the scanning line,
A source wiring (signal line) including one or more second metal layers including a refractory metal layer on the second semiconductor layer, the first transparent insulating substrate, and a part of the electrode terminal of the signal line. And a drain wiring on the second semiconductor layer, the first transparent insulating substrate, and a part of the pixel electrode, and an electrode terminal of the scanning line, including a part of the scanning line, The electrode terminal of the signal line consisting of a part of the signal line is formed in a region outside the image display unit,
A photosensitive organic insulating layer is formed on the signal line except on the electrode terminal of the signal line.

With this configuration, the transparent conductive pixel electrode is formed simultaneously with the scanning line, so it is automatically formed on the glass substrate, and a protective insulating layer is formed on the channel between the source and drain to protect the channel. A photosensitive organic insulating layer is formed on the surface of the signal line (source line) to provide the minimum necessary passivation function, and the same effect as the liquid crystal display device according to claim 2 can be obtained. Thus, a TN type liquid crystal display device having the same metallic electrode terminal as the signal line is obtained.

The liquid crystal display device according to claim 5 is a scanning line that is formed of a laminate of a transparent conductive layer and a first metal layer on at least one main surface of the first transparent insulating substrate, and has an insulating layer on its side surface. A transparent conductive pixel electrode is formed,
One or more gate insulating layers are formed on the scanning lines;
A first semiconductor layer containing no impurities is formed in an island shape on the gate insulating layer over the gate electrode;
A protective insulating layer is formed on the first semiconductor layer so as to be narrower than the gate electrode;
A second semiconductor layer including a pair of impurities is formed on a part of the protective insulating layer and on the first semiconductor layer;
The gate insulating layer and the first metal layer on the scanning line are removed in a region outside the image display unit to expose a transparent conductive layer that is a part of the scanning line,
A source wiring (signal line) made of one or more anodizable metal layers including a refractory metal layer on the second semiconductor layer and the first transparent insulating substrate, and a part of the protective insulating layer The drain wiring on the top, the first semiconductor layer, the first transparent insulating substrate, and a part of the pixel electrode, the electrode terminal of the scanning line including a part of the scanning line, and an image A signal line electrode terminal formed of a part of the signal line is formed in a region outside the display unit,
An anodized layer is formed on the source / drain wiring except for the electrode terminal of the signal line.

With this configuration, the transparent conductive pixel electrode is formed simultaneously with the scanning line, so it is automatically formed on the glass substrate, and a protective insulating layer is formed on the channel between the source and drain to protect the channel. 2. The liquid crystal display device according to claim 1, wherein tantalum pentoxide (Ta2O5) or aluminum oxide (Al2O3), which is an insulating anodic oxide layer, is formed on the surfaces of the signal line and the drain wiring to provide a passivation function. The same effect can be obtained. Thus, a TN type liquid crystal display device having the same metallic electrode terminal as the signal line is obtained.

The liquid crystal display device according to claim 6, wherein at least one insulated gate transistor, a scanning line that also serves as a gate electrode of the insulated gate transistor, and a signal line that also serves as a source line are provided on one main surface; A first transparent insulating substrate in which unit picture elements each having a picture element electrode connected to a drain and a counter electrode formed at a predetermined distance from the picture element electrode are arranged in a two-dimensional matrix; In a liquid crystal display device in which liquid crystal is filled between the second transparent insulating substrate or the color filter facing the first transparent insulating substrate,
A scanning line and a counter electrode, which are composed of at least one first metal layer on one main surface of the first transparent insulating substrate and have an insulating layer on its side surface, are formed,
One or more gate insulating layers are formed on the scanning line and the counter electrode,
A first semiconductor layer containing no impurities is formed in an island shape on the gate insulating layer over the gate electrode;
A protective insulating layer is formed on the first semiconductor layer so as to be narrower than the gate electrode;
A second semiconductor layer including a pair of impurities is formed on a part of the protective insulating layer and on the first semiconductor layer;
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display part, and a part of the scanning line is exposed,
A source wiring (signal line) / drain wiring (picture element electrode) composed of one or more second metal layers including a refractory metal layer on the second semiconductor layer and the first transparent insulating substrate; Similarly, the scanning line electrode terminal including the opening and the first and second semiconductor layers around the opening, and the signal line electrode terminal formed of a part of the signal line in the region outside the image display unit,
A photosensitive organic insulating layer is formed on the signal line except on the electrode terminal of the signal line.

With this configuration, the pixel electrode and the counter electrode are formed on a glass substrate, and a protective insulating layer is formed on the channel between the source and drain to protect the channel and a photosensitive organic insulating layer is formed on the surface of the signal line. The minimum necessary passivation function is provided. Further, since the gate insulating layer is formed on the counter electrode, the same effect as the liquid crystal display device according to claim 2 can be obtained. Thus, an IPS liquid crystal display device having the same metallic electrode terminal as the signal line can be obtained.

The liquid crystal display device according to claim 7 is provided with a scanning line and a counter electrode, each having at least one first metal layer on one main surface of the first transparent insulating substrate and having an insulating layer on its side surface. Formed,
One or more gate insulating layers are formed on the scanning line and the counter electrode,
A first semiconductor layer containing no impurities is formed in an island shape on the gate insulating layer over the gate electrode;
A protective insulating layer is formed on the first semiconductor layer so as to be narrower than the gate electrode;
A second semiconductor layer including a pair of impurities is formed on a part of the protective insulating layer and on the first semiconductor layer;
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display part, and a part of the scanning line is exposed,
A source wiring (signal line) / drain wiring (picture element electrode) made of one or more anodizable metal layers including a refractory metal layer on the second semiconductor layer and the first transparent insulating substrate; The electrode terminal of the scanning line is also formed including the first and second semiconductor layers around the opening and the opening, and the electrode terminal of the signal line made up of a part of the signal line is formed in a region outside the image display unit. ,
An anodized layer is formed on the source / drain wiring except for the electrode terminal of the signal line.

With this configuration, the pixel electrode and the counter electrode are formed on the glass substrate, and a protective insulating layer is formed on the channel between the source and drain to protect the channel and the surface of the signal line and drain wiring is insulative. An anodized layer, tantalum pentoxide (Ta2O5) or aluminum oxide (Al2O3), is formed to provide a passivation function. Further, since the gate insulating layer is formed on the counter electrode, the same effect as the liquid crystal display device according to claim 1 can be obtained. Thus, an IPS liquid crystal display device having the same metallic electrode terminal as the signal line can be obtained.

The liquid crystal image display device according to claim 8, wherein the insulating layer formed on the side surface of the scanning line is an organic insulating layer. 4. A liquid crystal display device according to claim 5, claim 6, claim 6 and claim 7. With this configuration, an organic insulating layer can be formed on the side surface of the scanning line by electrodeposition regardless of the material and configuration of the scanning line, and the scanning line forming process and the contact forming process can be performed using halftone exposure technology. It is possible to process continuously with one photomask.

The liquid crystal image display device according to claim 9, wherein the first metal layer is made of an anodizable metal layer, and the insulating layer formed on the side surface of the scanning line is an anodized layer. A liquid crystal display device according to claim 2, claim 6, and claim 7. With this configuration, an anodized layer can be formed by anodic oxidation on the side surface of the scanning line, and the scanning line forming process and the contact forming process are successively processed with a single photomask using a halftone exposure technique. It becomes possible to do.

A method of manufacturing a liquid crystal display device according to claim 1, wherein the step of forming the etch stop layer, the formation of the scanning line, and the formation of the contact are performed using the same photomask by a halftone exposure technique. And a step of forming a source / drain wiring, and a step of anodizing the source / drain wiring simultaneously with the formation of a transparent conductive pixel electrode.

With this configuration, the scanning line forming process and the contact forming process necessary for electrical connection to the scanning line can be processed using a single photomask, and the number of photolithography steps can be reduced. Moreover, the contact is formed in a self-aligned manner with the scanning line, and an insulating layer different from the gate insulating layer is provided on the side surface of the scanning line, so that the scanning line and the signal line can intersect. This is a manufacturing characteristic common to the liquid crystal display device of the present invention except for the fifteenth and sixteenth aspects. In addition, a protective insulating layer is formed on the channel between the source and drain to protect the channel and anodize the source / drain wiring when forming the pixel electrode, thereby eliminating the need for forming a passivation insulating layer. As a result of the reduction, a TN liquid crystal display device can be manufactured using four photomasks.

A method of manufacturing a liquid crystal display device according to a second aspect of the present invention is the method of manufacturing the liquid crystal display device according to the second aspect, wherein the step of forming the etch stop layer, the formation of the scanning line, and the contact are formed using the same photomask by a halftone exposure technique. And a step of forming a transparent conductive pixel electrode, and a step of forming a source / drain wiring using a photosensitive organic insulating layer.

With this configuration, it is possible to simultaneously reduce the number of photo-etching processes in which the scanning line forming process and the contact forming process are performed using a single photomask. In addition, a protective insulating layer is formed on the channel between the source and drain to protect the channel, and at the time of forming the source / drain wiring, the photosensitive organic insulating layer is selectively left only on the source / drain wiring for passivation insulation. As a result of reducing the number of manufacturing steps that do not require formation of layers, a TN liquid crystal display device can be manufactured using four photomasks.

According to a twelfth aspect of the present invention, there is provided a method of manufacturing the liquid crystal display device according to the third aspect, wherein a step of forming an etch stop layer, formation of a scanning line comprising a laminate of a transparent conductive layer and a first metal layer, and contact Process using half-tone exposure technology with the same photomask, removing the first metal layer in the contact when forming the contact, and forming the source / drain wiring using the photosensitive organic insulating layer It has the process to perform.

With this configuration, the number of photo-etching steps in which the pixel electrodes and the scanning lines are processed using one photomask is reduced, and the scanning line forming step and the contact forming step are processed using one photomask. Simultaneously reduce the number of photo-etching processes. In addition, a protective insulating layer is formed on the channel between the source and drain to protect the channel, and at the time of forming the source / drain wiring, the photosensitive organic insulating layer is selectively left only on the source / drain wiring for passivation insulation. As a result of reducing the number of manufacturing steps that do not require layer formation, a TN liquid crystal display device can be manufactured using three photomasks.

According to a thirteenth aspect of the present invention, there is provided a method of manufacturing the liquid crystal display device according to the fourth aspect, wherein the step of forming an etch stop layer, the formation of a scanning line comprising a laminate of the transparent conductive layer and the first metal layer, and the contact Processing using the same photomask with halftone exposure technology, removing the first metal layer in the contact during contact formation, and using a photosensitive organic insulating layer with halftone exposure technology A step of forming a drain wiring and leaving a photosensitive organic insulating layer only on the signal line.

With this configuration, the number of photo-etching steps in which the pixel electrodes and the scanning lines are processed using one photomask is reduced, and the scanning line forming step and the contact forming step are processed using one photomask. Simultaneously reduce the number of photo-etching processes. Further, a protective insulating layer is formed on the channel between the source and drain to protect the channel, and at the time of forming the source / drain wiring, a photosensitive organic insulating layer is selectively left only on the signal line using a halftone exposure technique. As a result, the number of manufacturing steps that do not require the formation of a passivation insulating layer is reduced. As a result, a TN liquid crystal display device can be manufactured using three photomasks.

14. A method of manufacturing a liquid crystal display device according to claim 5, wherein a step of forming an etch stop layer, formation of a scanning line composed of a laminate of a transparent conductive layer and a first metal layer, and contact formation A process of forming the contact using the same photomask by a halftone exposure technique, a process of removing the first metal layer in the contact when forming the contact, and forming a source / drain wiring using the halftone exposure technique And a step of anodizing only the source / drain wiring.

With this configuration, the number of photo-etching steps in which the pixel electrodes and the scanning lines are processed using one photomask is reduced, and the scanning line forming step and the contact forming step are processed using one photomask. Simultaneously reduce the number of photo-etching processes. A protective insulating layer is formed on the channel between the source and drain to protect the channel, and a half-tone exposure technique is used to selectively form an anodized layer on the source and drain wiring when forming the source and drain wiring. As a result, the number of manufacturing steps that do not require the formation of a passivation insulating layer is reduced. As a result, a TN liquid crystal display device can be manufactured using three photomasks.

According to a fifteenth aspect of the present invention, there is provided a method of manufacturing the liquid crystal display device according to the sixth aspect, wherein a step of forming an etch stop layer, a step of forming a multilayer film pattern corresponding to the scanning lines and the counter electrode, and a contact are formed. And a step of forming a source / drain wiring using a photosensitive organic insulating layer by a halftone exposure technique and leaving a photosensitive organic insulating layer only on a signal line.

With this configuration, a protective insulating layer is formed on the channel between the source and the drain to protect the channel, and at the time of forming the source / drain wiring, a photosensitive organic insulating layer is selectively formed only on the signal line using a halftone exposure technique. As a result, the number of manufacturing steps that do not require the formation of a passivation insulating layer is reduced, so that an IPS liquid crystal display device can be manufactured using four photomasks.

A sixteenth aspect of the present invention is the method of manufacturing the liquid crystal display device according to the seventh aspect, wherein the step of forming an etch stop layer, the step of forming a multilayer film pattern corresponding to the scanning line and the counter electrode, and the contact are formed. And a step of forming a source / drain wiring using a halftone exposure technique and anodizing only the source / drain wiring.

With this configuration, a protective insulating layer is formed on the channel between the source and drain to protect the channel, and at the time of forming the source / drain wiring, an anodized layer is selectively formed on the source / drain wiring using a halftone exposure technique. As a result of the reduction in the number of manufacturing steps that do not require the formation of a passivation insulating layer, an IPS liquid crystal display device can be manufactured using four photomasks.

A liquid crystal display device manufacturing method according to a sixteenth aspect is the method of manufacturing the liquid crystal display device according to the sixth aspect, wherein the step of forming the etch stop layer, the formation of the scanning line and the counter electrode, and the formation of the contact are the same photomask by a halftone exposure technique. And a step of forming a source / drain wiring using a photosensitive organic insulating layer by a halftone exposure technique and leaving a photosensitive organic insulating layer only on a signal line.

With this configuration, it is possible to reduce the number of photo-etching processes in which the scanning line and counter electrode forming process and the contact forming process are performed using a single photomask. Also, a protective insulating layer is formed on the channel between the source and drain to protect the channel, and at the time of forming the source / drain wiring, a photosensitive organic insulating layer is selectively left only on the signal line using a halftone exposure technique. As a result, the number of manufacturing steps that do not require the formation of a passivation insulating layer is reduced. As a result, an IPS liquid crystal display device can be manufactured using three photomasks.

Claim 18 is also a method of manufacturing a liquid crystal display device according to claim 7, wherein the step of forming the etch stop layer, the formation of the scanning line and the counter electrode, and the contact are formed by the same photomask by a halftone exposure technique. And a step of forming source / drain wirings using a halftone exposure technique and anodizing only the source / drain wirings.

With this configuration, it is possible to reduce the number of photo-etching processes in which the scanning line and counter electrode forming process and the contact forming process are performed using a single photomask. A protective insulating layer is formed on the channel between the source and drain to protect the channel, and a half-tone exposure technique is used to selectively form an anodic oxide layer on the source and drain wiring when forming the source and drain wiring. As a result, the number of manufacturing steps that do not require the formation of a passivation insulating layer is reduced. As a result, an IPS liquid crystal display device can be manufactured using three photomasks.

A nineteenth aspect is the method for manufacturing a liquid crystal display device according to the tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, sixteenth, seventeenth, and eighteenth aspects. The insulating layer formed on the side surface of the scanning line is an organic insulating layer and is formed by electrodeposition. With this configuration, an organic insulating layer can be formed on the side surface of the scanning line by electrodeposition regardless of the material and configuration of the scanning line, and the scanning line forming process and the contact forming process can be performed using halftone exposure technology. It is possible to process continuously with one photomask.

A twentieth aspect is the method of manufacturing a liquid crystal display device according to the tenth, eleventh, fifteenth, sixteenth, seventeenth and eighteenth aspects, wherein the first metal layer can be anodized. An insulating layer is formed of a metal layer and formed on the side surface of the scanning line by anodization. With this configuration, an anodized layer can be formed by anodic oxidation on the side surface of the scanning line, and the scanning line forming process and the contact forming process are successively processed with a single photomask using a halftone exposure technique. It becomes possible to do.

In the liquid crystal display device according to the present invention, since the insulated gate transistor has a protective insulating layer on the channel, the photosensitive organic insulating layer is selected only on the source / drain wiring in the image display section or only on the signal line. The active substrate is provided with a passivation function by forming the insulating layer on the surface by forming the insulating layer on the surface by forming the insulating layer on the surface. Therefore, no special heating step is involved in the production of the active substrate constituting the liquid crystal display device, and the insulated gate transistor having the amorphous silicon layer as the semiconductor layer does not require excessive heat resistance. In other words, an effect of not causing deterioration of electrical performance by forming a passivation is added. In addition, when anodizing the source / drain wiring, it is possible to selectively protect the scanning line and signal line electrode terminals by introducing a halftone exposure technique, and the effect of preventing an increase in the number of photolithography steps can be obtained. It is done.

An etch stop layer is formed first, and then a scanning line forming process and a contact forming process for electrical connection to the scanning line are processed with a single photomask by introducing a halftone exposure technique. The reduction in the number of processes that can be achieved is the main point of the present invention. By forming an organic insulating layer or an anodized layer on the side surface of the exposed scanning line, it is possible to cross the scanning line and the signal line. Features are born.

  In addition, the introduction of pseudo-picture element electrodes, combined with rationalization such as processing of picture element electrodes and scanning lines with one photomask, can further reduce the number of photo-etching steps from the conventional five times to four or three. A liquid crystal display device can be manufactured using a single photomask, and the industrial value is extremely large from the viewpoint of cost reduction of the liquid crystal display device. Moreover, since the pattern accuracy of these processes is not so high, the production control is also facilitated by not greatly affecting the yield and quality.

Further, in the IPS type liquid crystal display device according to the sixth and seventh embodiments, the electric field generated between the counter electrode and the pixel electrode is applied only to the gate insulating layer and the liquid crystal layer on the counter electrode. In the IPS type liquid crystal display device according to Example 9, since it is also applied to the gate insulating layer on the counter electrode, the liquid crystal layer, and the anodic oxidation layer of the pixel electrode, all of the conventional passivation insulating layers with many defects are interposed. In addition, the advantage that the display image is not easily burned out cannot be overlooked. This is because the anodic oxide layer of the drain wiring (picture element electrode) functions as a high resistance layer rather than an insulating layer, so that charge accumulation does not occur.

As is clear from the above description, the requirement of the present invention is that the etch stop layer is first formed in the production of the active substrate, and then the scanning line (and counter electrode) forming step and the contact forming step are halftone. With the introduction of exposure technology, it is possible to process with a single photomask and an organic insulating layer or an anodized layer as an insulating layer is formed on the side surface of the exposed scanning line (and the counter electrode). As for other configurations, it is obvious that the difference in the material of the pixel electrode, the gate insulating layer, etc., the display device semiconductor device or the manufacturing method thereof also belongs to the category of the present invention. The usefulness of the present invention is not changed in a liquid crystal display device using liquid crystal or a reflective liquid crystal display device, and the semiconductor layer of the insulated gate transistor is limited to amorphous silicon. It is not intended is also clear.

An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a plan view of a semiconductor device for display device (active substrate) according to Embodiment 1 of the present invention, and FIG. 2 is on the AA ′ line, the BB ′ line, and the CC ′ line in FIG. Sectional drawing of a manufacturing process is shown. Similarly, Example 2 is shown in FIGS. 3 and 4, Example 3 is shown in FIGS. 5 and 6, Example 4 is shown in FIGS. 7 and 8, Example 5 is shown in FIGS. 9 and 10, and Example 6 is shown in FIGS. 12, FIG. 13 is a plan view of an active substrate and FIG. 17 is a cross-sectional view of a manufacturing process, respectively. In addition, about the site | part same as a prior art example, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.

In Example 1, as in the conventional example, first, a first metal layer having a film thickness of about 0.1 to 0.3 μm is formed on one main surface of the glass substrate 2 by using a vacuum film forming apparatus such as SPT, for example, Cr, Ta. , Mo, etc. or their alloys and silicides are deposited. As will be clarified in the following description, in the present invention, when an organic insulating layer is selected as the insulating layer formed on the side surface of the scanning line, there is almost no restriction caused by the scanning line material, but it is formed on the side surface of the scanning line. When an anodic oxide layer is selected as an insulating layer, it is necessary that the anodic oxide layer has an insulating property. In that case, considering that Ta alone has high resistance and AL alone has poor heat resistance. In order to reduce the resistance of the scanning line, the scanning line is composed of a single layer structure such as AL (Zr, Ta, Nd) alloy having high heat resistance or AL / Ta, Ta / AL / Ta, AL / AL (Ta , Zr, Nd) and other laminated structures can be selected. AL (Ta, Zr, Nd) means an AL alloy having high heat resistance to which Ta, Zr, Nd or the like of several percent or less is added.

Next, a first SiNx layer 30 that becomes a gate insulating layer using a PCVD apparatus on the entire surface of the glass substrate 2, a first amorphous silicon layer 31 that hardly contains impurities and becomes a channel of an insulated gate transistor, and a channel For example, a second SiNx layer 32 serving as an insulating layer for protecting the film and three kinds of thin film layers are sequentially deposited with a film thickness of, for example, about 0.3-0.05-0.1 μm, and FIG. As shown in FIG. 2A, the uppermost second SiNx layer 32 is selectively etched by a microfabrication technique to form a protective insulating layer (or etch stop layer or channel protective layer) of an insulated gate transistor. The second SiNx layer 32D is formed, and the first amorphous silicon layer 31 is exposed.

Then, after depositing a second amorphous silicon layer 33 containing, for example, phosphorus as an impurity on the entire surface of the glass substrate 2 by using a PCVD apparatus with a film thickness of, for example, about 0.05 μm, FIGS. As shown in FIG. 6B, the photosensitive resin in which the thickness of the openings 63A and 65A as the contact formation region 81B is 1 μm and is thinner than 2 μm on the region 81A corresponding to the scanning line 11 and the storage capacitor line 16, for example. Patterns 81A and 81B are formed by a halftone exposure technique, and the second amorphous silicon layer layer 33, the first amorphous silicon layer 31, the gate insulating layer 30 and the first insulating layer 30 are formed using the photosensitive resin patterns 81A and 81B as a mask. The glass substrate 2 is exposed by selectively removing one metal layer. Since the size of the contact is usually 10 μm or more, which is comparable to that of the electrode terminal, it is easy to produce a photomask for forming 81B (halftone region) and to control the accuracy of the finished dimensions.

Subsequently, when the photosensitive resin patterns 81A and 81B are reduced by 1 μm or more by ashing means such as oxygen plasma, the photosensitive resin pattern 81B disappears as shown in FIGS. 1 (c) and 2 (c). The second amorphous silicon layers 33A and 33B in the openings 63A and 65A are exposed, and the photosensitive resin pattern 81C reduced in thickness on the scanning line 11 and the storage capacitor line 16 can be left as it is. The photosensitive resin pattern 81C (black region), that is, the pattern width of the gate electrode 11A is obtained by adding the mask alignment accuracy to the dimensions of the protective insulating layer. Therefore, when the protective insulating layer is 10 to 12 μm and the alignment accuracy is ± 3 μm. The minimum is 16 to 18 μm, and the dimensional accuracy is not severe. Also, the pattern width of the scanning line 11 and the counter electrode 16 is usually set to 10 μm or more because of the resistance value. However, in the present invention, there is no semiconductor layer forming step as in the conventional example, and the semiconductor layer is formed with the same width as the gate electrode. Therefore, the resist pattern isotropically becomes a 1 μm film during conversion from the resist pattern 81A to 81C. If it is reduced, not only the size is reduced by 2 μm, but also the mask alignment accuracy at the time of subsequent source / drain wiring formation is reduced by 1 μm to ± 2 μm, and the influence of the latter is more severe in the process than the former. Therefore, in the oxygen plasma treatment, it is desirable to increase the anisotropy in order to suppress the change in pattern dimension. Specifically, an RIE (Reactive Ion Etching) method, an ICP (Inductively Coupled Plasma) method having a high density plasma source, and a TCP (Transfer Coupled Plasma) method oxygen plasma treatment are more desirable. Alternatively, it is desirable to take a process measure by designing a large pattern dimension of the resist pattern 81A in advance in consideration of the dimensional change amount of the resist pattern.

Thereafter, as shown in FIG. 2C, an insulating layer 76 is formed on the side surface of the gate electrode 11A. For this purpose, as shown in FIG. 19, electrodeposition or anodization is performed on the outer periphery of the glass substrate 2 and the wiring 77 that bundles the scanning lines 11 (the storage capacitor line 16 is the same but is not shown here) in parallel. A connection pattern 78 for applying a potential is sometimes required, and a film forming region 79 using an appropriate mask means for the amorphous silicon layers 31 and 33 and the silicon nitride layers 30 and 32 by plasma CVD is formed from the connection pattern 78. It is limited to the inside, and at least the connection pattern 78 needs to be exposed. Using connection means such as a hook clip having a sharp cutting edge in the connection pattern 78, the photosensitive resin pattern 81C (78) on the connection pattern 78 is pierced, and a + (plus) potential is applied to the scanning line 11 so that ethylene glycol is the main component. When the glass substrate 2 is infiltrated into the chemical conversion solution to be anodized, if the scanning line 11 is an AL-based alloy, for example, alumina (AL2O3) having a film thickness of 0.3 μm at a chemical conversion voltage of 200 V is formed. The In the case of electrodeposition, as shown in the literature, Monthly “Polymer Processing” November 2002 issue, a pendant carboxyl group-containing polyimide electrodeposition solution is used and the electrodeposition voltage number is 0.3 μm. A polyimide resin layer having a film thickness is formed. It should be noted that when the insulating layer is formed on the side surfaces of the exposed scanning line 11 and storage capacitor line 16, the electrical connection of the active substrate 2 must be performed at least when the serial line of the scanning line 11 is released at some point in the subsequent manufacturing process. It goes without saying that not only the inspection but also the actual operation as a liquid crystal display device is hindered. As the releasing means, transpiration by laser light irradiation or mechanical excision by scribing is simple, but a detailed description is omitted.
Monthly “Polymer Processing” November 2002 issue

After the formation of the insulating layer 76, the second crystalline silicon layer 33A in the openings 63A and 65A is used with the photosensitive resin pattern 81C reduced in thickness as shown in FIGS. 1 (d) and 2 (d) as a mask. 33B, the first amorphous silicon layers 31A and 31B, and the gate insulating layers 30A and 30B are selectively etched to expose a portion 73 of the scanning line 11 and a portion 75 of the storage capacitor line 16, respectively.

  After removing the photosensitive resin pattern 81C, in the source / drain wiring forming process, an anodic refractory metal layer having a film thickness of about 0.1 μm is formed by using a vacuum film forming apparatus such as SPT. The thin film layer 34, the AL thin film layer 35 as a low resistance wiring layer having a thickness of about 0.3 μm and also anodizable, and the thin film layer such as Ta as an intermediate conductive layer that can also be anodized in a thickness of about 0.1 μm 36 are sequentially applied. Then, the source / drain wiring material composed of these three thin films, the second amorphous silicon layer 33, and the first amorphous silicon layers 31A and 31B are sequentially etched using a photosensitive resin pattern by a microfabrication technique. Then, the gate insulating layers 30A and 30B are exposed, and also serve as the drain electrode 21 and the source electrode of the insulated gate transistor formed by stacking 34A, 35A and 36A as shown in FIGS. 1 (e) and 2 (e). The signal line 12 is selectively formed. It goes without saying that the source / drain wirings 12 and 21 are formed so as to partially overlap the channel protection layer 32D because they do not become inoperable due to offset. Usually, in order to avoid the side effects associated with the battery action, the electrode terminal 5 of the scanning line is formed at the same time as the formation of the source / drain wirings 12 and 21 including the part 73 of the scanning line. However, the transparent conductive electrode terminal 5A may be directly formed in the subsequent process. As the configuration of the source / drain wirings 12 and 21, it is reasonable to simplify the Ta / single layer if the restriction of the resistance value is loose, and the AL alloy to which Nd is added reduces the chemical potential and reduces the alkaline solution. In this case, the intermediate conductive layer 36 is not required, and the stacked structure of the source / drain wirings 12 and 21 can be made into a two-layer structure. The configuration of the wirings 12 and 21 is slightly simplified. This is the same even when IZO is used instead of ITO which is a transparent conductive layer.

After the formation of the source / drain wirings 12 and 21, for example, ITO is deposited on the entire surface of the glass substrate 2 as a transparent conductive layer having a film thickness of about 0.1 to 0.2 μm using a vacuum film forming apparatus such as SPT. As shown in FIG. 1 (f) and FIG. 2 (f), the pixel electrode 22 is selectively formed on the glass substrate 2 including a part of the intermediate conductive layer 36A of the drain electrode 21 by a fine processing technique. At this time, a transparent conductive layer pattern is also formed on the electrode terminal 5 of the scanning line and the electrode terminal 6 which is a part of the signal line in a region outside the image display unit to form the transparent conductive electrode terminals 5A and 6A. . As described above, the electrode terminal 5 may not be formed, and at this time, the electrode terminal 5A may be formed directly including the opening 63A. Here, as in the conventional example, a transparent conductive short-circuit line 40 is provided on the outer periphery of the active substrate 2, and the electrode terminals 5A, 6A and the short-circuit line 40 are formed in an elongated stripe shape, thereby increasing the resistance and static electricity. High resistance for countermeasures.

Subsequently, as shown in FIGS. 1 (g) and 2 (g), the source / drain wirings 12, while irradiating light with the photosensitive resin pattern 83A used for selective pattern formation of the picture element electrode 22 as a mask, 21 is anodized to form an oxide layer on the surface. At this time, the electrode terminals 5A and 6A are protected by the photosensitive resin patterns 83B and 83C. Ta is formed on the upper surface of the source / drain wirings 12 and 21, and a stacked layer of Ta, AL, Ti and the second amorphous silicon layer 33A is exposed on one side surface on the channel side, and on the opposite side to the channel. A stack of Ta, AL, and Ti is exposed on the other side surface, and the second amorphous silicon layer 33A is formed into an impurity-containing silicon oxide layer (SiO2) 66 (not shown) by anodic oxidation. The semiconductor is transformed into titanium oxide (TiO2) 68, which is a semiconductor, AL is transformed into alumina (AL2O3) 69, which is an insulating layer, and Ta is transformed into tantalum pentoxide (Ta2O5) 70, which is an insulating layer. Although the titanium oxide layer 68 is not an insulating layer, the film thickness is extremely thin and the exposed area is small, so that there is no problem in terms of passivation. However, it is desirable that the refractory metal thin film layer 34A is also selected from Ta. However, it is necessary to pay attention to the characteristic that Ta, unlike Ti, lacks the function of absorbing the underlying surface oxide layer and facilitating ohmic contact.

It has also been disclosed in the previous example that anodization while irradiating light is an important point in the anodization process in order to form an anodized layer with good film quality on the drain wiring 21 as well. . More specifically, when a sufficiently strong light of about 10,000 lux is irradiated and the leakage current of the insulated gate transistor exceeds μA, a good film quality is obtained by anodization of about 10 mA / cm 2 calculated from the area of the drain electrode 21. The current density to obtain is obtained. However, even if the film quality of the anodic oxide layer 70 on the drain wiring 21 is insufficient, the reason why sufficient reliability is usually obtained is that the drive signal applied to the liquid crystal cell is basically alternating current, and the color filter The voltage of the counter electrode 14 is adjusted during image inspection so that the DC voltage component is reduced between the counter electrode 14 and the pixel electrode 22 (drain electrode 21) formed on the counter surface (flicker reduction). This is because, in principle, it is only necessary to form an insulating layer so that a direct current component does not flow only on the signal line 12.

The film thickness of each of the tantalum pentoxide 70, alumina 69, titanium oxide 68, and silicon oxide layer 66 formed by anodization is sufficient to be about 0.1 to 0.2 μm for wiring passivation. The applied voltage is also realized at over 100 V using a chemical conversion liquid such as Although not shown, all signal lines 12 need to be formed electrically in parallel or in series, although not shown in the drawings, in some of the subsequent manufacturing steps. Needless to say, if this series-parallel is not canceled, not only the electrical inspection of the active substrate 2 but also the actual operation as a liquid crystal display device is hindered. As the releasing means, transpiration by laser light irradiation or mechanical excision by scribing is simple, but a detailed description is omitted.

Covering the pixel electrode 22 with the photosensitive resin pattern 83A not only does not require the anodization of the pixel electrode 22, but also causes an excessive formation current to flow to the drain electrode 21 via the insulated gate transistor. This is because it is not necessary to secure a large amount.

Finally, the photosensitive resin patterns 83A to 83D are removed to complete the active substrate 2 (display device semiconductor device) as shown in FIGS. 1 (h) and 2 (h). The active substrate 2 and the color filter thus obtained are bonded to form a liquid crystal panel, and Example 1 of the present invention is completed. With respect to the configuration of the storage capacitor 15, the storage capacitor line 16 and the pixel electrode 22 are planarly overlapped via the gate insulating layer 30B as shown in FIG. However, the configuration of the storage capacitor 15 is not limited to this, and an insulating layer including the gate insulating layer 30A is interposed between the pixel electrode 22 and the preceding scanning line 11. It may be configured. Although other configurations are possible, detailed description thereof is omitted. Similarly, since there is a step of forming a contact (opening) to the scanning line 11, it is easy to take countermeasures against static electricity using a conductive material or a semiconductor layer other than the transparent conductive layer.

In Example 1, first, a protective insulating layer of an insulated gate transistor is formed, and then a half of a layer with low pattern accuracy is formed, which is a scanning line forming step and a contact (opening) forming step for electrical connection to the scanning line. Applying tone exposure technology to reduce the photolithography process, forming transparent conductive pixel electrodes, and simultaneously forming an passivation layer by anodizing the source / drain wiring and providing an insulating layer on the surface. Although an active substrate is manufactured using four photomasks, an active substrate can be manufactured by another passivation forming method, which will be described as a second embodiment.

In the second embodiment, as shown in FIGS. 3D and 4D, the contact forming process, that is, the second crystalline silicon layers 33A and 33B in the openings 63A and 65A and the first amorphous silicon are formed. The layers 31A and 31B and the gate insulating layers 30A and 30B are selectively etched, and the same manufacturing process as in the first embodiment is performed until a part 73 of the scanning line 11 and a part 75 of the storage capacitor line 16 are exposed. proceed.

Subsequently, for example, ITO is deposited on the entire surface of the glass substrate 2 as a transparent conductive layer having a film thickness of about 0.1 to 0.2 μm using a vacuum film forming apparatus such as SPT, and FIGS. As shown in e), the pixel electrodes 22 are selectively formed on the glass substrate 2 by a fine processing technique. At this time, the electrode terminal 5 and the signal line electrode terminal 6 of the scanning line including the part 73 of the scanning line in the region outside the image display portion are formed at the same time. Also here, as in the conventional example, a transparent conductive short-circuit line 40 is provided, and between the electrode terminals 5A, 6A and the short-circuit line 40 is formed in an elongated stripe shape, so that the resistance is increased and the resistance against static electricity is increased. .

Subsequently, in the source / drain wiring formation process, a thin film layer 34 of, for example, Ti or Ta and a low resistance of about 0.3 μm are formed as a heat-resistant metal layer having a thickness of about 0.1 μm using a vacuum film forming apparatus such as SPT. The AL thin film layer 35 is sequentially deposited as a wiring layer. Then, the source / drain wiring material composed of these two thin films, the second amorphous silicon layers 33A and 33B, and the first amorphous silicon layers 31A and 31B are formed using a photosensitive resin pattern 85 by a fine processing technique. Sequential etching exposes the gate insulating layers 30A and 30B, and an insulating layer comprising a stack of 34A and 35A including part of the picture element electrode 22 as shown in FIGS. 3 (f) and 4 (f). A signal line 12 including a drain electrode 21 of the gate transistor and a part of the electrode terminal 6A of the signal line and also serving as a source electrode is selectively formed. It will be understood that the scanning line electrode terminal 5A and the signal line electrode terminal 6A are exposed on the glass substrate 2 after the source / drain wirings 12 and 21 are etched. The configuration of the source / drain wirings 12 and 21 can be simplified to a single layer of Ta, Cr, MoW or the like if the resistance value is loosely restricted.

The active substrate 2 and the color filter thus obtained are bonded to form a liquid crystal panel, and Example 2 of the present invention is completed. In Example 2, since the photosensitive resin pattern 85 is in contact with the liquid crystal, the photosensitive resin pattern 85 is not a normal photosensitive resin mainly composed of a novolac resin, but has a high purity and is mainly composed of acrylic resin or polyimide. It is important to use a highly heat-resistant photosensitive organic insulating layer containing resin, and depending on the material, it can be fluidized by heating to cover the side surfaces of the source / drain wirings 12 and 21. In this case, the reliability of the liquid crystal panel is further improved. With respect to the configuration of the storage capacitor 15, as shown in FIG. 3F, the pixel electrode 22 and the storage capacitor line 16 are connected to the gate insulating layer 30B, the first amorphous silicon layer 31B (not shown), and the first electrode. In the example shown in FIG. 2, the storage capacitor 15 is not limited to this configuration. As in the subsequent third embodiment, an insulating layer including the gate insulating layer 30A may be interposed between the scanning line 11 and the pixel electrode 21 in the previous stage. The static electricity countermeasure line 40 is composed of a transparent conductive layer connected to the electrode terminals 5A and 6A. However, since an opening forming process is applied to the gate insulating layers 30A and 30B, other static electricity countermeasures are possible. .

In Example 1 and Example 2, the process of forming transparent conductive picture element electrodes is independent, and an active substrate is manufactured with four photomasks. However, one picture element electrode and one scanning line are formed. Since the active substrate can be manufactured with three photomasks by further promoting the process reduction by processing with the photomask, this will be described as Example 3 to Example 5.

In Example 3, first, as a transparent conductive layer 91 having a film thickness of about 0.1 to 0.2 μm on one main surface of the glass substrate 2 using a vacuum film forming apparatus such as SPT, for example, ITO and a film thickness of 0.1 to A first metal layer 92 of about 0.3 μm is deposited. As will be clear from the following description, in Examples 3 to 5, since the scanning line is a laminate of a transparent conductive layer and a metal layer, it is impossible to form an insulating layer on the side surface of the scanning line by anodic oxidation. It is. Therefore, since an organic insulating layer is formed by electrodeposition on the insulating layer, a high melting point such as Cr, Ta, Mo or the like is used as the first metal layer that does not cause a battery reaction with the transparent conductive layer ITO as the scanning line material. A metal or an alloy or silicide thereof is selected. If AL is used to reduce resistance, a single layer of heat-resistant AL (Nd) alloy is the simplest, and then Ta / AL (Zr, Hf) and Ta / Al / The Ta stack and configuration are complicated.

Next, a first SiNx layer 30 that becomes a gate insulating layer using a PCVD apparatus on the entire surface of the glass substrate 2, a first amorphous silicon layer 31 that hardly contains impurities and becomes a channel of an insulated gate transistor, and a channel For example, a second SiNx layer 32 and three thin film layers as an insulating layer for protecting the film are sequentially deposited with a film thickness of, for example, about 0.3-0.05-0.1 μm, and FIG. As shown in FIG. 6A, the uppermost second SiNx layer 32 is selectively etched by a microfabrication technique to form a protective insulating layer (or etch stop layer or channel protective layer) of the insulated gate transistor. The second SiNx layer 32D is formed, and the first amorphous silicon layer 31 is exposed.

Then, a second amorphous silicon layer 33 containing, for example, phosphorus as an impurity is deposited on the entire surface of the glass substrate 2 by using a PCVD apparatus with a film thickness of, for example, about 0.05 μm, and then FIG. As shown in (b), the film thickness of the region 82A on the scanning line 11 that also serves as the gate electrode 11A is 2 μm, for example, and is a pseudo pixel electrode (consisting of a laminate of the transparent conductive layer 91B and the first metal layer 92B). 93 and pseudo electrode terminal 94 (consisting of a laminate of transparent conductive layer 91A and first metal layer 92A) and pseudo electrode terminal 95 (consisting of a laminate of transparent conductive layer 91C and first metal layer 92C). A photosensitive resin pattern 82A, 82B thicker than 1 μm thick is formed by a halftone exposure technique, and the second amorphous silicon layer 33 is formed using the photosensitive resin patterns 82A, 82B as a mask. Amorphous silicon layer 31 of 1, the transparent conductive layer 91 in addition to the gate insulating layer 30 and the first metal layer 92 be sequentially removed to expose the glass substrate 2.

Thus, after obtaining a multilayer film pattern corresponding to the scanning line 11, which also serves as the gate electrode 11A, the pseudo picture element electrode 93, and the pseudo electrode terminals 94, 95, the photosensitive resin is subsequently applied by ashing means such as oxygen plasma. When the patterns 82A and 82B are reduced by 1 μm or more, the photosensitive resin pattern 82B disappears as shown in FIGS. 5C and 6C, and the second amorphous silicon layers 33A to 33C are exposed. At the same time, the photosensitive resin pattern 82 </ b> C whose film is reduced only on the scanning line 11 can be left as it is. As described above, in the oxygen plasma treatment, it is desirable to increase the anisotropy and suppress the change in the pattern dimension so that the mask alignment accuracy in the subsequent source / drain wiring forming process is not lowered. Alternatively, the pattern dimension of the resist pattern 82A may be designed to be large in advance in consideration of the dimensional change amount of the resist pattern.

Subsequently, as shown in FIG. 6C, an organic insulating layer 76 is formed on the side surface of the gate electrode 11A. For this purpose, the connection pattern 78 shown in FIG. 20 is cut through the photosensitive resin pattern 82C (78) on the connection pattern 78 using connection means such as a hook clip having a sharp cutting edge, and a + (plus) potential is applied to the scanning line 11. However, depending on the composition of the electrodeposition liquid, a-(minus) potential may be applied. For example, a polyimide resin layer having a film thickness of 0.3 μm at an electrodeposition voltage number V is formed as the organic insulating layer. Since the pseudo picture element electrode 93 is electrically isolated, the organic insulating layer 76 is not formed around the pseudo picture element electrode 93.

Subsequently, as shown in FIGS. 5D and 6D, the second amorphous silicon layers 33A to 33C and the first amorphous silicon layer 31A are formed using the photosensitive resin pattern 82C whose thickness is reduced as a mask. ˜31C, gate insulating layers 30A-30C and first metal layers 92A-92C are sequentially removed to expose transparent conductive layers 91A-91C, respectively. An electrode terminal 6A of the signal line is obtained.

After removing the photosensitive resin pattern 82C, in the source / drain wiring formation process, a thin film layer 34 such as Ti or Ta is formed as a heat-resistant metal layer having a thickness of about 0.1 μm using a vacuum film forming apparatus such as SPT. The AL thin film layer 35 is sequentially deposited as a low resistance wiring layer having a thickness of about 0.3 μm. Then, the source / drain wiring material composed of these two thin films, the second amorphous silicon layer 33A, and the first amorphous silicon layer 31A are sequentially etched using the photosensitive resin pattern 85 by a fine processing technique. The gate insulating layer 30A is exposed, and the drain electrode of an insulated gate transistor comprising a part of the pixel electrode 22 and a stack of 34A and 35A as shown in FIGS. 5 (e) and 6 (e). 21 and the signal line 12 including part of the electrode terminal 6A of the signal line and also serving as the source electrode are selectively formed. It will be understood that the scanning line electrode terminal 5A and the signal line electrode terminal 6A are exposed on the glass substrate 2 after the source / drain wirings 12 and 21 are etched. The configuration of the source / drain wirings 12 and 21 can be simplified to a single layer of Ta, Cr, MoW or the like if the resistance value is loosely restricted.

The active substrate 2 and the color filter thus obtained are bonded to form a liquid crystal panel, and Example 3 of the present invention is completed. Since the photosensitive resin pattern 85 is also in contact with the liquid crystal in Example 3, the photosensitive resin pattern 85 is not a normal photosensitive resin mainly composed of a novolac resin, but has a high purity and is mainly composed of acrylic resin or polyimide. It is important to use a photosensitive organic insulating layer having high heat resistance and containing resin. Regarding the configuration of the storage capacitor 15, as shown in FIG. 5E, the storage electrode 72 formed including a part of the pixel electrode 22 simultaneously with the source / drain wirings 12 and 21 and the scanning line 11 in the previous stage. An example in which the protrusions provided are configured to overlap in a plan view via the gate insulating layer 30A, the first amorphous silicon layer 31A, and the second amorphous silicon layer 33A (lower right oblique line) However, the configuration of the storage capacitor 15 is not limited to this, and the storage capacitor line 16 and the pixel electrode 21 formed simultaneously with the scanning line 11 as in the first embodiment are not limited thereto. An insulating layer including the gate insulating layer 30B may be interposed therebetween. The static electricity countermeasure wire 40 is the same as in the first and second embodiments.

In the first to third embodiments, there are restrictions on the device configuration in which the electrode terminals of the scanning lines and the electrode terminals of the signal lines are both transparent conductive layers as described above, but a device process that removes the restrictions is also possible. This will be described as Example 4 and Example 5.

In the fourth embodiment, the second amorphous silicon layers 33A to 33C and the first amorphous silicon layer 33A to 33C are masked by using the photosensitive resin pattern 82C whose thickness is reduced as shown in FIGS. 7D and 8D. The silicon layers 31A to 31C, the gate insulating layers 30A to 30C, and the first metal layers 92A to 92C are sequentially removed to expose the transparent conductive layers 91A to 91C. Until the element electrode 22 and the electrode terminal 6A of the signal line are obtained, the manufacturing process proceeds in substantially the same manner as in the third embodiment. However, the pseudo electrode terminal 95 is not always necessary for the reason described later.

Subsequently, in the step of forming the source / drain wiring, a heat-resistant metal layer having a film thickness of about 0.1 μm, for example, a thin film layer 34 such as Ti or Ta, and a film thickness of about 0.3 μm, using a vacuum film forming apparatus such as SPT. The AL thin film layer 35 is sequentially deposited as a low resistance wiring layer. Then, the source / drain wiring material composed of these two thin films, the second amorphous silicon layer 33A, and the first amorphous silicon layer 31A are sequentially etched using the photosensitive resin pattern 86 by a fine processing technique. Then, the gate insulating layer 30A is exposed, and the drain electrode of the insulating gate type transistor including a part of the pixel electrode 22 and a stack of 34A and 35A as shown in FIGS. 7 (e) and 8 (e). 21 and the signal line 12 which also serves as the source wiring are selectively formed, and the scanning line electrode terminal 5 and the signal line including the part 5A of the scanning line exposed simultaneously with the formation of the source / drain wirings 12 and 21 A part of the electrode terminal 6 is also formed at the same time. That is, unlike the third embodiment, the pseudo electrode terminal 95 is not always necessary. At this time, the film thickness of the region 86A (black region) on the signal line 12 is 3 μm, for example, and the film thickness of the region 86B (halftone region) on the drain electrode 21, the electrode terminals 5 and 6, and the storage electrode 72 is 1.5 μm. It is an important feature of the fourth embodiment that the thicker photosensitive resin patterns 86A and 86B are formed by the halftone exposure technique. The minimum dimension of 86B corresponding to the electrode terminals 5 and 6 is as large as several tens of μm, and photomask fabrication and finished dimension management are extremely easy. However, the minimum dimension of the area 86A corresponding to the signal line 12 is 4 to 8 μm. Since the dimensional accuracy is relatively high, a thin pattern is required as the black region. However, as described in the conventional example, the source / drain wirings 12 and 21 of the present invention are compared with the single exposure processing and the etching processing twice as compared with the source / drain wirings 12 and 21 formed by one exposure processing. Since it is formed by a single etching process, there are few factors that cause fluctuations in the pattern width, and the dimension management of the source / drain wirings 12 and 21 and the dimension management of the channel length between the source / drain wirings 12 and 21, that is, the channel length are conventional. Pattern accuracy is easier to manage than halftone exposure technology. Compared with the channel etch type insulated gate transistor, the ON current of the etch stop type insulated gate transistor is determined by the dimension of the channel protective insulating layer 32D and not the dimension between the source / drain wirings 12 and 21. Therefore, it should be understood that process management becomes easier.

After the source / drain wirings 12 and 21 are formed, if the photosensitive resin patterns 86A and 86B are reduced by 1.5 μm or more by ashing means such as oxygen plasma, the photosensitive resin pattern 86B disappears, and FIG. 8 (f), the drain electrode 21, the electrode terminals 5 and 6, and the storage electrode 72 are exposed, and the photosensitive resin pattern 86C can be selectively formed only on the signal line 12. When the pattern width of the photosensitive resin pattern 86C is narrowed by the oxygen plasma treatment, the upper surface of the signal line 12 is exposed and the reliability is lowered. Therefore, it is desirable to increase the anisotropy and suppress the change in the pattern dimension. The configuration of the source / drain wirings 12 and 21 can be simplified to a single layer of Ta, Cr, Mo or the like if the resistance value is loosely restricted.

The active substrate 2 and the color filter thus obtained are bonded to form a liquid crystal panel, and Example 4 of the present invention is completed. The electrode terminals 5 and 6 are made of the same metal material as the signal line 12, but the pseudo electrode terminal 95 is introduced as in the third embodiment, and the photosensitive resin patterns 86B (5) and 86B (6) are eliminated. If the line 12 is formed so as to include a part of the pseudo electrode terminal 95, it is easy to provide the transparent conductive electrode terminals 5A and 6A. Also in Example 4, since the photosensitive resin pattern 86C is in contact with the liquid crystal, the photosensitive resin pattern 86C is not a normal photosensitive resin mainly composed of a novolac resin, but has a high purity and is mainly composed of an acrylic resin or a polyimide resin. It is important to use a photosensitive organic insulating layer having high heat resistance including The configuration of the storage capacitor 15 is the same as that of the third embodiment. The transparent conductive layer pattern connecting the transparent conductive pattern 6A (91C) formed under the part 5A of the scanning line and the signal line 12 and the short-circuit line 40 is formed into an elongated linear shape, thereby generating static electricity. High resistance wiring can be used as a countermeasure, but of course, countermeasures against static electricity using other conductive members are possible.

In Example 4 of the present invention, an organic insulating layer is formed only on the signal line 12 and the drain electrode 21 is exposed while maintaining conductivity. The reason why sufficient reliability can be obtained in this case is the liquid crystal cell. The applied drive signal is basically alternating current, and the voltage of the counter electrode 14 is such that the DC voltage component is reduced between the counter electrode 14 and the pixel electrode 22 formed on the counter surface of the color filter. This is because adjustment is performed at the time of image inspection (flicker reduction adjustment). Therefore, it is only necessary to form an insulating layer so that a direct current component does not flow only on the signal line 12. From the viewpoint of reliability, there is no problem even if an organic insulating layer is formed on the drain electrode 21 as in the second and third embodiments. However, in the TN liquid crystal display device, on the drain electrode 21. It is desirable not to avoid the non-orientation caused by the step and to increase the aperture ratio as much as possible.

In the second embodiment, the third embodiment, and the fourth embodiment of the present invention, the organic insulating layer is selectively formed only on the source / drain wiring and the signal line, respectively. Since the thickness of the layer is usually 1 μm or more, if the pixel is small in a high-definition panel, the alignment step using the rubbing cloth causes the step to be non-aligned or hinders ensuring the gap accuracy of the liquid crystal cell. There is also a risk of getting out. Therefore, in the fifth embodiment, a passivation technique for changing to an organic insulating layer with the addition of the minimum number of steps is provided.

In Example 5, the second amorphous silicon layers 33A to 33C and the first amorphous silicon layer 33A to 33C and the first amorphous silicon layer 82C are used as a mask, as shown in FIGS. 9D and 10D. The silicon layers 31A to 31C, the gate insulating layers 30A to 30C, and the first metal layers 92A to 92C are sequentially removed to expose the transparent conductive layers 91A to 91C. The manufacturing process proceeds in substantially the same manner as in Example 4 until the element electrode 22 and the static electricity countermeasure wire 40 (91C) are obtained.

Thereafter, in the source / drain wiring formation process, a thin film layer 34 of Ti, Ta or the like as a heat resistant metal layer having a thickness of about 0.1 μm and a film thickness of 0.3 μm using a vacuum film forming apparatus such as SPT. The AL thin film layer 35 is sequentially deposited as a low-resistance wiring layer that can be anodized to the same extent. Then, the source / drain wiring material composed of these two thin films, the second amorphous silicon layer 33A, and the first amorphous silicon layer 31A are sequentially etched using the photosensitive resin pattern 87 by a fine processing technique. Then, the gate insulating layer 30A is exposed, and the drain electrode 21 of the insulated gate transistor including a part of the picture element electrode 22 and a stack of 34A and 35A as shown in FIGS. 9 (e) and 10 (e). And a signal line 12 which also serves as a source wiring are selectively formed, and a portion of the scanning line 5A exposed at the same time as the formation of the source / drain wirings 12 and 21 is included. An electrode terminal 6 composed of a portion is also formed. At this time, the film thickness of the region 87A (black region) on the electrode terminals 5 and 6 is 3 μm, for example, and the film thickness of the region 87B (halftone region) on the source / drain wirings 12 and 21 and the storage electrode 72 is 1.5 μm. It is an important feature of Example 5 that the thick photosensitive resin patterns 87A and 87B are formed by the halftone exposure technique.

  After the formation of the source / drain wirings 12, 21, when the photosensitive resin patterns 87A, 87B are reduced by 1.5 μm or more by ashing means such as oxygen plasma, the photosensitive resin pattern 87B disappears and the source / drain wirings 12 are removed. , 21 and the storage electrode 72 are exposed, and the photosensitive resin pattern 87C whose film is reduced only on the electrode terminals 5 and 6 can be left as it is. Even if the pattern width of the photosensitive resin pattern 87C is reduced by the oxygen plasma treatment, only an anodic oxide layer is formed around the electrode terminals 5 and 6 having a large pattern size, so that the electrical characteristics and yield of the liquid crystal display device are obtained. It is a remarkable feature that it has almost no influence on quality. Then, while irradiating light using the photosensitive resin pattern 87C as a mask, the source / drain wirings 12 and 21 are anodized to form oxide layers 68 and 69 as shown in FIGS. 9 (f) and 10 (f). .

When the photosensitive resin pattern 87C is removed after the anodic oxidation is finished, as shown in FIGS. 9 (g) and 10 (g), the electrode terminal 5 made of the low resistance thin film layer 35A having the anodic oxide layer formed on the side surface thereof is shown. 6 is exposed. The side surface of the electrode terminal 5 of the scanning line has a thickness of the anodized layer formed on the side surface as compared with the electrode terminal 6 of the signal line because an anodizing current flows through the high resistance short circuit line 40 (91C) for static electricity countermeasures. Please understand that is thin. It should be noted that the source / drain wirings 12 and 21 can be simplified and formed into a Ta single layer that can be anodized if the restriction on the resistance value is loose. The active substrate 2 and the color filter thus obtained are bonded to form a liquid crystal panel, and Example 5 of the present invention is completed. The configuration of the storage capacitor 15 is the same as in the third and fourth embodiments.

In the fifth embodiment, since the source / drain wirings 12 and 21 and the second amorphous silicon layer 33A are anodized as described above, the pixel electrode 22 electrically connected to the drain electrode 21 is also exposed. The point that the pixel electrode 22 is also anodized at the same time is greatly different from the first embodiment. For this reason, depending on the film quality of the transparent conductive layer constituting the pixel electrode 22, the resistance value may be increased by anodic oxidation. In this case, the film forming conditions of the transparent conductive layer are changed as appropriate to obtain a film quality lacking oxygen. Although necessary, the transparency of the transparent conductive layer does not decrease due to anodic oxidation. In addition, a current for anodizing the drain electrode 21, the pixel electrode 22, and the storage electrode 72 is also supplied through the channel of the insulated gate transistor. However, since the area of the pixel electrode 22 is large, a large formation current or Anodization layer 69 having a film quality and a film thickness equivalent to those on signal line 12 is formed on drain electrode 21 and storage electrode 72 on the drain electrode 21 and storage electrode 72, regardless of how much external light is irradiated. It is difficult to cope with the formation of only by extending the formation time. However, even if the anodic oxide layer 69 formed on the drain wiring 21 is somewhat incomplete, reliability that does not hinder practical use is often obtained. This is because it is only necessary to form an insulating layer so that a direct current component does not flow only on the signal line 12 as described above.

The liquid crystal display device described above uses a TN type liquid crystal cell. However, a horizontal electric field is generated between a pair of counter electrodes and a pixel electrode formed at a predetermined distance from the pixel electrode. The process reduction proposed in the present invention is also useful in a liquid crystal display device of an IPS (In-Plain-Switting) system to be controlled, and will be described in the following examples.

In the sixth embodiment, as in the first embodiment, first, as shown in FIGS. 11A and 12A, the second SiNx layer 32, which is the uppermost layer, is selectively etched and insulated by a fine processing technique. A second SiNx layer 32D that serves as a protective insulating layer (or an etch stop layer or a channel protective layer) of the gate type transistor is formed, and the first amorphous silicon layer 31 is exposed.

Next, after depositing a second amorphous silicon layer 33 containing, for example, phosphorus as an impurity on the entire surface of the glass substrate 2 by using a PCVD apparatus with a film thickness of, for example, about 0.05 μm, FIG. As shown in FIG. 12B, the second amorphous silicon layer 33, the first amorphous silicon layer 31, corresponding to the counter electrode 16 serving both as the scanning line 11 and the storage capacitor line by a microfabrication technique, The glass substrate 2 is exposed by selectively removing the gate insulating layer 30 and the first metal layer 92.

Subsequently, as shown in FIG. 12B, the insulating layer 76 is formed on the side surfaces of the gate electrode 11 </ b> A and the counter electrode 16. For this purpose, as shown in FIG. 21, the potential of the electrode 77 during electrodeposition or anodic oxidation at the outer periphery of the glass substrate 2 and the wiring 77 that bundles the scanning lines 11 (the counter electrode 16 is the same but is not shown here) in parallel. A connection pattern 78 is required to provide the film, and a film-forming region 79 using an appropriate mask means of the amorphous silicon layers 31 and 33 and the silicon nitride layers 30 and 32 by plasma CVD is located inside the connection pattern 78. It is limited, and at least the connection pattern 78 needs to be exposed. The connecting pattern 78 is subjected to electrodeposition or anodic oxidation by applying a potential to the scanning line 11 via the connecting pattern 78 by using connecting means such as a hook clip having a sharp edge, and the insulating layer 76 has an organic insulating layer or an anode. One of the oxide layers is formed.

Subsequently, as shown in FIGS. 11 (c) and 12 (c), openings 63A and 65A are selectively formed on the scanning line 11 and the counter electrode 16 in a region outside the image display portion by a fine processing technique. The second amorphous silicon layers 33A and 33B, the first amorphous silicon layers 31A and 31B, and the gate insulating layers 30A and 30B in the openings 63A and 65A are sequentially etched to form the scanning lines 11 respectively. The part 73 and the part 75 of the counter electrode 16 are exposed.

Further, in the source / drain wiring formation process, a thin film layer 34 of, for example, Ti or Ta as a heat-resistant metal layer having a film thickness of about 0.1 μm and a low resistance of about 0.3 μm are formed using a vacuum film forming apparatus such as SPT. The AL thin film layer 35 is sequentially deposited as a wiring layer. Then, the source / drain wiring material composed of these two thin films, the second amorphous silicon layer 33A, and the first amorphous silicon layers 31A and 31B are sequentially eaten using the photosensitive resin pattern 86 by a fine processing technique. The gate insulating layers 30A and 30B are exposed, and as shown in FIGS. 11D and 12E, the drain electrode 21 of the insulated gate transistor that is formed of a stack of 34A and 35A and becomes a pixel electrode. And a signal line 12 that also serves as a source wiring are selectively formed, and a portion 73 of the scanning line exposed at the same time as the formation of the source / drain wirings 12 and 21 is included. The electrode terminal 6 composed of a portion is also formed at the same time. At this time, the photosensitive resin patterns 86A and 86B having a thickness of 86A on the signal line 12 are, for example, 3 μm and thicker than the thickness of 1.5 μm of 86B on the drain electrode 21 and the electrode terminals 5 and 6 are formed by the halftone exposure technique. This is an important feature of the sixth embodiment.

After the source / drain wirings 12 and 21 are formed, if the photosensitive resin patterns 86A and 86B are reduced by 1.5 μm or more by ashing means such as oxygen plasma, the photosensitive resin pattern 86B disappears, and FIG. As shown in FIG. 12E, the drain electrode 21 and the electrode terminals 5 and 6 are exposed and the photosensitive resin pattern 86C whose thickness is reduced only on the signal line 12 can be left as it is. Since the upper surface of the signal line 12 is exposed and the reliability is lowered when the pattern width of the photosensitive resin pattern 86C is reduced, it is desirable in Example 4 to increase the anisotropy and suppress the change in the pattern size. As stated. The configuration of the source / drain wirings 12 and 21 can be simplified to a single layer of Ta, Cr, MoW alloy or the like if the resistance value is loosely restricted.

The active substrate 2 and the color filter thus obtained are bonded to form a liquid crystal panel, and Example 6 of the present invention is completed. As is apparent from the above description, the IPS liquid crystal display device does not require the transparent conductive pixel electrode 22 on the acti substrate 2, and the transparent conductive counter electrode 14 is also formed on the opposing surface of the color filter. Is unnecessary. Therefore, an intermediate conductive layer on the source / drain wirings 12 and 21 is also unnecessary. Also in Example 6, since the photosensitive resin pattern 86C is in contact with the liquid crystal, the photosensitive resin pattern 86C is not a normal photosensitive resin mainly composed of a novolac resin, but has a high purity and is mainly composed of an acrylic resin or a polyimide resin. It is important to use a photosensitive organic insulating layer having high heat resistance including As for the configuration of the storage capacitor 15, as shown in FIG. 11E, a part of the pixel electrode (drain wiring) 21 and the counter electrode 16 that also serves as the storage capacitor line are formed by the gate insulating layer 30B and the first amorphous layer. The example (the downward sloping line part 50) comprised by having overlapped planarly through the quality silicon layer 31B and the 2nd amorphous silicon layer 33B is illustrated. Although the description of the countermeasure against static electricity is omitted, the countermeasure against static electricity is easy because the step of providing the opening 63A and exposing a part 73 of the scanning line 11 is provided.

In Example 6 of the present invention, the reduction of the manufacturing process is promoted by forming the organic insulating layer only on the signal line. However, when the pixel is small in the high-definition panel because the thickness of the organic insulating layer is usually 1 μm or more. In some cases, the alignment step of the alignment film using a rubbing cloth may cause the step to be non-aligned, or may hinder the gap accuracy of the liquid crystal cell. Therefore, in the seventh embodiment, a passivation technique that replaces the organic insulating layer is provided by adding the minimum number of steps.

In the seventh embodiment, as shown in FIGS. 13C and 14C, openings 63A and 65A are selectively formed on the scanning line 11 and the counter electrode 16 in a region outside the image display portion by a fine processing technique. The second amorphous silicon layers 33A and 33B, the first amorphous silicon layers 31A and 31B, and the gate insulating layers 30A and 30B in the openings 63A and 65A are sequentially etched and scanned, respectively. The process proceeds in substantially the same manufacturing steps as in the sixth embodiment until a part 73 of the line 11 and a part 75 of the counter electrode 16 are exposed.

Subsequently, in the source / drain wiring forming step, a thin film layer 34 of, for example, Ti or Ta as an anodizable heat-resistant metal layer having a film thickness of about 0.1 μm using a vacuum film forming apparatus such as SPT, and a film thickness of 0 The AL thin film layer 35 is sequentially deposited as a low resistance wiring layer of about 3 μm which can also be anodized. Then, the source / drain wiring material composed of these two thin films, the second amorphous silicon layers 33A and 33B, and the first amorphous silicon layers 31A and 31B are formed using a photosensitive resin pattern 87 by a fine processing technique. The gate insulating layers 30A and 30B are exposed by sequentially etching, and as shown in FIGS. 13D and 14D, the drains of the insulated gate transistors that are formed by stacking 34A and 35A and serve as pixel electrodes. The signal line 12 which also serves as the electrode 21 and the source wiring is selectively formed, and the scanning line electrode terminal 5 and the signal line including the part 73 of the scanning line exposed at the same time as the formation of the source / drain wirings 12 and 21 are formed. An electrode terminal 6 made of a part of is also formed. At this time, photosensitive resin patterns 87A and 87B having a film thickness of 87A on the electrode terminals 5 and 6 and 3 μm thicker than the film thickness of 1.5 μm on the source / drain wirings 12 and 21 are formed by the halftone exposure technique. This is an important feature of the seventh embodiment.

  After the source / drain wirings 12 and 21 are formed, if the photosensitive resin patterns 87A and 87B are reduced by 1.5 μm or more by ashing means such as oxygen plasma, the photosensitive resin pattern 87B disappears and the source / drain wirings 12 are removed. , 21 is exposed, and the photosensitive resin pattern 87C having a reduced thickness only on the electrode terminals 5 and 6 can be left as it is. Accordingly, the source / drain wirings 12 and 21 are anodized to form oxide layers 68 and 69 as shown in FIGS. 13E and 14E while irradiating light using the photosensitive resin pattern 87C as a mask. .

When the photosensitive resin pattern 87C is removed after the anodic oxidation is completed, the electrode terminals 5 and 6 having the low resistance thin film layer 35A on the surface thereof are exposed as shown in FIGS. 13 (f) and 14 (f). However, in both figures, the antistatic measures for connecting the electrode terminal 5 of the scanning line and the electrode terminal 6 of the signal line with a high resistance member are not shown in particular, so that an anodized layer is formed on the side surface of the electrode terminal 5 of the scanning line However, since an opening 63A is provided and a step of exposing a part 73 of the scanning line 11 is provided, countermeasures against static electricity are easy. It should be noted that the source / drain wirings 12 and 21 can be simplified and formed into a Ta single layer that can be anodized if the restriction on the resistance value is loose. The active substrate 2 and the color filter thus obtained are bonded to form a liquid crystal panel, and Example 7 of the present invention is completed. The configuration of the storage capacitor 15 is the same as that of the sixth embodiment.

In Example 6 and Example 7 of the present invention, the active substrate is manufactured using four photomasks by independently forming the scanning line and counter electrode forming step and the contact forming step. As in Example 5, an active substrate is manufactured using three photomasks by rationalizing the scan line forming process and the contact forming process for electrical connection to the scan line using the halftone exposure technique. This is described as Example 8 and Example 9.

In the eighth embodiment, as in the other embodiments, first, as shown in FIGS. 15A and 16A, the second SiNx layer 32, which is the uppermost layer, is selectively etched by microfabrication technology. The second SiNx layer 32D that serves as a protective insulating layer (or etch stop layer or channel protective layer) of the insulated gate transistor is formed, and the first amorphous silicon layer 31 is exposed.

Next, after depositing a second amorphous silicon layer 33 containing, for example, phosphorus as an impurity on the entire surface of the glass substrate 2 with a PCVD apparatus to a thickness of, for example, about 0.05 μm, FIG. As shown in FIG. 16B, the thickness of the openings 63A and 65A, which are the contact formation regions 84B, is 1 μm, for example, and the thickness on the region 84A corresponding to the counter electrode 16 that also serves as the scanning line 11 and the storage capacitor line. The photosensitive resin patterns 84A and 84B thinner than 2 μm are formed by the halftone exposure technique, and the second amorphous silicon layer 33, the first amorphous silicon layer 31 and the gate are formed using the photosensitive resin patterns 84A and 84B as a mask. The insulating layer 30 and the first metal layer 92 are sequentially removed to expose the glass substrate 2.

Subsequently, when the photosensitive resin patterns 84A and 84B are reduced by 1 μm or more by ashing means such as oxygen plasma, the photosensitive resin pattern 84B disappears as shown in FIGS. 15 (c) and 16 (c). Thus, the second amorphous silicon layer 33A is exposed in the opening 63A, the second amorphous silicon layer 33B is exposed in the opening 65A, and the film thickness is reduced on the scanning line 11 and the counter electrode 16. The photosensitive resin pattern 84C thus made can be left as it is.

Subsequently, as shown in FIG. 16C, an insulating layer 76 is formed on the side surfaces of the gate electrode 11 </ b> A and the counter electrode 16. For this purpose, as shown in FIG. 22, the potential of the electrode 77 during electrodeposition or anodic oxidation at the outer periphery of the glass substrate 2 and the wiring 77 that bundles the scanning lines 11 (the counter electrode 16 is the same but is not shown here) in parallel. A connection pattern 78 is required to provide the film, and a film-forming region 79 using an appropriate mask means of the amorphous silicon layers 31 and 33 and the silicon nitride layers 30 and 32 by plasma CVD is located inside the connection pattern 78. It is limited and at least the connection pattern 78 needs to be exposed. The connecting pattern 78 is cut through the photosensitive resin pattern 84C (78) on the connecting pattern 78 using connecting means such as a hook clip having a sharp edge, and an electric potential is applied to the scanning line 11 to perform electrodeposition or anodic oxidation, and an insulating layer In 76, either an organic insulating layer or an anodized layer is formed.

Further, as shown in FIGS. 15D and 16D, the second amorphous silicon layers 33A and 33B in the openings 63A and 65A and the first amorphous resin layers 84C in the openings 63A and 65A are used as a mask. The amorphous silicon layers 31A and 31B and the gate insulating layers 30A and 30B are sequentially etched to expose a part 73 of the scanning line 11 and a part 75 of the counter electrode 16 respectively.

After the removal of the photosensitive resin pattern 84C, a source / drain wiring forming process is performed using a vacuum film forming apparatus such as SPT as a heat-resistant metal layer having a film thickness of about 0.1 μm, for example, a thin film layer 34 such as Ti or Ta. The AL thin film layer 35 is sequentially deposited as a low resistance wiring layer having a thickness of about 0.3 μm. Then, the source / drain wiring material composed of these two thin films, the second amorphous silicon layers 33A and 33B, and the first amorphous silicon layers 31A and 31B are formed by using a photosensitive resin pattern 86 by a fine processing technique. The gate insulating layers 30A and 30B are exposed by sequentially etching, and as shown in FIGS. 15E and 16E, the drains of the insulated gate transistors which are formed by stacking 34A and 35A and become pixel electrodes. The signal line 12 which also serves as the electrode 21 and the source wiring is selectively formed, and the scanning line electrode terminal 5 and the signal line including the part 73 of the scanning line exposed at the same time as the formation of the source / drain wirings 12 and 21 are formed. The electrode terminal 6 made of a part of the electrode is also formed at the same time. At this time, the photosensitive resin patterns 86A and 86B having a thickness of 86A on the signal line 12 are, for example, 3 μm and thicker than the thickness of 1.5 μm of 86B on the drain electrode 21 and the electrode terminals 5 and 6 are formed by the halftone exposure technique. This is an important feature of the eighth embodiment.

After the source / drain wirings 12 and 21 are formed, if the photosensitive resin patterns 86A and 86B are reduced by 1.5 μm or more by ashing means such as oxygen plasma, the photosensitive resin pattern 86B disappears, and FIG. As shown in FIG. 16F, the drain electrode 21 and the electrode terminals 5 and 6 are exposed and the photosensitive resin pattern 86C whose thickness is reduced only on the signal line 12 can be left as it is. As described above, as the pattern width of the photosensitive resin pattern 86C becomes narrower, the upper surface of the signal line 12 is exposed and the reliability is lowered. Therefore, it is desirable to increase the anisotropy and suppress the change in the pattern dimension. is there. The configuration of the source / drain wirings 12 and 21 can be simplified to a single layer of Ta, Cr, MoW alloy or the like if the resistance value is loosely restricted.

The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel, and Example 8 of the present invention is completed. Also in Example 8, since the photosensitive resin pattern 86C is in contact with the liquid crystal, the photosensitive resin pattern 86C is not a normal photosensitive resin mainly composed of a novolac resin, but has a high purity and an acrylic resin or polyimide resin as a main component. It is important to use a photosensitive organic insulating layer having high heat resistance including With respect to the configuration of the storage capacitor 15, as shown in FIG. 15F, a part of the pixel electrode (drain wiring) 21 and the counter electrode 16 also serving as the storage capacitor line are formed by the gate insulating layer 30B and the first amorphous layer. The example (the downward slanting oblique line part 50) comprised by having overlapped planarly through the quality silicon layer 31B and the 2nd amorphous silicon layer 33B is illustrated. Although the description of the countermeasure against static electricity is omitted, the countermeasure against static electricity is easy because the step of providing the opening 63A and exposing a part 73 of the scanning line 11 is provided.

The active substrate 2 obtained by the sixth embodiment and the eighth embodiment has almost no structural difference, and the required number of photomasks is four and three, respectively. Can be considered advanced.

In Example 8 of the present invention, the reduction of the manufacturing process is promoted by forming the organic insulating layer only on the signal line. However, when the pixel is small in the high-definition panel because the thickness of the organic insulating layer is usually 1 μm or more. In some cases, the alignment step of the alignment film using a rubbing cloth may cause the step to be non-aligned, or may hinder the gap accuracy of the liquid crystal cell. Therefore, in the ninth embodiment, a passivation technique replacing the organic insulating layer is provided by adding the minimum number of steps.

In Example 9, as shown in FIGS. 17D and 18D, the second amorphous silicon layers 33A and 33B in the openings 63A and 65A are formed using the photosensitive resin pattern 84C with a reduced thickness as a mask. And the first amorphous silicon layers 31A and 31B and the gate insulating layers 30A and 30B are sequentially etched to expose the portion 73 of the scanning line 11 and the portion 75 of the counter electrode 16, respectively. It proceeds in almost the same manufacturing process.

Thereafter, in the step of forming the source / drain wiring, a thin film layer 34 of Ti, Ta or the like as a heat-resistant metal layer having a thickness of about 0.1 μm, for example, using a vacuum film forming apparatus such as SPT, The AL thin film layer 35 is sequentially deposited as a low resistance wiring layer of about 3 μm, which can also be anodized. Then, the source / drain wiring material composed of these two thin films, the second amorphous silicon layers 33A and 33B, and the first amorphous silicon layers 31A and 31B are formed using a photosensitive resin pattern 87 by a fine processing technique. The gate insulating layers 30A and 30B are exposed by sequential etching, and as shown in FIGS. 17E and 18E, the drains of the insulated gate transistors which are formed by stacking 34A and 35A and become pixel electrodes. The signal line 12 which also serves as the electrode 21 and the source wiring is selectively formed, and the scanning line electrode terminal 5 and the signal line including the part 73 of the scanning line exposed at the same time as the formation of the source / drain wirings 12 and 21 are formed. An electrode terminal 6 made of a part of is also formed. At this time, photosensitive resin patterns 87A and 87B having a film thickness of 87A on the electrode terminals 5 and 6 and 3 μm thicker than the film thickness of 1.5 μm on the source / drain wirings 12 and 21 are formed by the halftone exposure technique. This is an important feature of the ninth embodiment.

  After the source / drain wirings 12 and 21 are formed, if the photosensitive resin patterns 87A and 87B are reduced by 1.5 μm or more by ashing means such as oxygen plasma, the photosensitive resin pattern 87B disappears and the source / drain wirings 12 are removed. , 21 is exposed, and the photosensitive resin pattern 87C having a reduced thickness only on the electrode terminals 5 and 6 can be left as it is. Therefore, the source / drain wirings 12 and 21 are anodized to form oxide layers 68 and 69 as shown in FIGS. 17 (f) and 18 (f) while irradiating light using the photosensitive resin pattern 87C as a mask. .

When the photosensitive resin pattern 87C is removed after the anodic oxidation, the electrode terminals 5 and 6 having the low resistance thin film layer 35A on the surface thereof are exposed as shown in FIGS. 17 (g) and 18 (g). However, in both figures, the antistatic measures for connecting the electrode terminal 5 of the scanning line and the electrode terminal 6 of the signal line with a high resistance member are not shown in particular, so that an anodized layer is formed on the side surface of the electrode terminal 5 of the scanning line However, since an opening 63A is provided and a step of exposing a part 73 of the scanning line 11 is provided, countermeasures against static electricity are easy. It should be noted that the source / drain wirings 12 and 21 can be simplified and formed into a Ta single layer that can be anodized if the restriction on the resistance value is loose. The active substrate 2 and the color filter thus obtained are bonded to form a liquid crystal panel, and Example 9 of the present invention is completed. The configuration of the storage capacitor 15 is the same as that of the eighth embodiment.

The active substrate 2 obtained by the seventh embodiment and the ninth embodiment has almost no structural difference, and the required number of photomasks is four and three, respectively, so that the ninth embodiment is more manufactured than the seventh embodiment. Can be considered advanced.

Plan view of a semiconductor device for a display device according to Example 1 of the invention. Manufacturing process sectional drawing of the semiconductor device for display apparatuses concerning Example 1 of this invention. The top view of the semiconductor device for display apparatuses concerning Example 2 of this invention. Manufacturing process sectional drawing of the semiconductor device for display apparatuses concerning Example 2 of this invention. The top view of the semiconductor device for display apparatuses concerning Example 3 of this invention. Manufacturing process sectional drawing of the semiconductor device for display apparatuses concerning Example 3 of this invention. The top view of the semiconductor device for display apparatuses concerning Example 4 of this invention. Manufacturing process sectional drawing of the semiconductor device for display apparatuses concerning Example 4 of this invention. Plan view of display device semiconductor device according to embodiment 5 of the present invention. Manufacturing process sectional drawing of the semiconductor device for display apparatuses concerning Example 5 of this invention. Plan view of a semiconductor device for a display device according to Example 6 of the invention. Manufacturing process sectional drawing of the semiconductor device for display apparatuses concerning Example 6 of this invention. Plan view of a semiconductor device for a display device according to Example 7 of the invention. Manufacturing process sectional drawing of the semiconductor device for display apparatuses concerning Example 7 of this invention. Plan view of a semiconductor device for a display device according to Example 8 of the invention. Manufacturing process sectional drawing of the semiconductor device for display apparatuses concerning Example 8 of this invention. Plan view of semiconductor device for display device according to Embodiment 9 of the present invention. Manufacturing process sectional drawing of the semiconductor device for display apparatuses concerning Example 9 of this invention. Arrangement of connection pattern for forming insulating layer in Example 1 and Example 2 Arrangement of connection pattern for forming insulating layer in Example 3, Example 4 and Example 5 Arrangement diagram of connection pattern for insulating layer formation in Example 6 and Example 7 Arrangement diagram of connection pattern for insulating layer formation in Example 8 and Example 9 The perspective view which shows the mounting state of a liquid crystal panel Equivalent circuit diagram of LCD panel Cross section of the main part of the liquid crystal panel Plan view of conventional active substrate Cross-sectional view of manufacturing process of conventional active substrate Plan view of streamlined active substrate Streamlined manufacturing process of active substrate

Explanation of symbols

1: Liquid crystal panel 2: Active substrate (glass substrate)
3: Semiconductor integrated circuit chip 4: TCP film 5: Scanning line electrode terminal, part of scanning line 6: Signal line electrode terminal, part of signal line 9: Color filter (opposing glass substrate)
10: Insulated gate transistor 11: Scan line (gate electrode)
11A: (gate wiring, gate electrode)
12: Signal line (source wiring, source electrode)
16: Common capacitance line (counter electrode in IPS type)
17: Liquid crystal
19: Polarizing plate 20: Alignment film 21: Drain electrode (pixel electrode in IPS type)
22: (transparent conductive) picture element electrode 30, 30A, 30B, 30C: gate insulating layer (first SiNx layer)
31, 31A, 31B, 31C: first amorphous silicon layer (without impurities) 32, 32A, 32B, 32C: second SiNx layer 32D: channel protective insulating layer (etch stop layer)
33, 33A, 33B, 33C: second amorphous silicon layer (including impurities) 34, 34A: refractory metal layer (anodizable) 35, 35A: low resistance metal layer (AL) )
36, 36A: (Anodically oxidizable) intermediate conductive layer 37: Passivation insulating layer 50, 51, 52: Storage capacitor formation region 62: Opening (on the drain electrode) 63, 63A: Opening (on the scanning line) 64 64A: Opening (on the signal line) 65, 65A: Opening (on the counter electrode) 66: Silicon oxide layer containing impurities 68: Anodized layer (titanium oxide, TiO 2)
69: Anodized layer (alumina, Al2O3)
70: Anodized layer (tantalum pentoxide, Ta2O5)
72: Storage electrode 73: Part of the scanning line 74: Part of the signal line 76: Insulating layer formed on the side surface of the scanning line 81A, 81B, 82A, 82B, 84A, 84B, 87A, 87B
: Photosensitive resin pattern (formed by halftone exposure) 83A: Photosensitive resin pattern (ordinary for pixel electrode formation) 85: Photosensitive organic insulating layers 86A, 86B: (formed by halftone exposure) ) Photosensitive organic insulating layer 91: transparent conductive layer 92: first metal layer

Claims (20)

Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
A scanning line comprising at least one first metal layer on one main surface of the first transparent insulating substrate and having an insulating layer on its side surface is formed,
One or more gate insulating layers are formed on the scanning lines;
A first semiconductor layer containing no impurities is formed in an island shape on the gate insulating layer over the gate electrode;
A protective insulating layer is formed on the first semiconductor layer so as to be narrower than the gate electrode;
A second semiconductor layer including a pair of impurities is formed on a part of the protective insulating layer and on the first semiconductor layer;
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display part, and a part of the scanning line is exposed,
Source (signal line) / drain wiring comprising at least one anodizable metal layer including a refractory metal layer on the second semiconductor layer and the first transparent insulating substrate, and the opening and opening The electrode terminal of the scanning line is also formed including the first and second semiconductor layers around the part,
A transparent conductive pixel electrode is formed on a part of the drain wiring and the first transparent insulating substrate, and a transparent conductive electrode terminal is formed on the signal line in a region outside the image display unit,
A liquid crystal display device, wherein an anodized layer is formed on a surface of the source / drain wiring except for a region overlapping the pixel electrode of the drain wiring and an electrode terminal region of the signal line. Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
A scanning line comprising at least one first metal layer on one main surface of the first transparent insulating substrate and having an insulating layer on its side surface, transparent conductive pixel electrodes, and electrode terminals for signal lines are provided. Formed,
One or more gate insulating layers are formed on the scanning lines;
A first semiconductor layer containing no impurities is formed in an island shape on the gate insulating layer over the gate electrode;
A protective insulating layer is formed on the first semiconductor layer so as to be narrower than the gate electrode;
A second semiconductor layer including a pair of impurities is formed on a part of the protective insulating layer and on the first semiconductor layer;
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display part, and a part of the scanning line is exposed,
An electrode terminal of a transparent conductive scanning line is formed including the opening and the first and second semiconductor layers around the opening,
A source wiring (signal line) including one or more second metal layers including a refractory metal layer on the second semiconductor layer, the first transparent insulating substrate, and a part of the electrode terminal of the signal line. ), Drain wiring is also formed on the second semiconductor layer, the first transparent insulating substrate, and a part of the pixel electrode,
A liquid crystal display device, wherein a photosensitive organic insulating layer is formed on the source / drain wiring. Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
A scanning line comprising a laminate of a transparent conductive layer and a first metal layer on at least one main surface of the first transparent insulating substrate and having an insulating layer on its side surface; a transparent conductive pixel electrode; and a signal line Electrode terminals are formed,
One or more gate insulating layers are formed on the scanning lines;
A first semiconductor layer containing no impurities is formed in an island shape on the gate insulating layer over the gate electrode;
A protective insulating layer is formed on the first semiconductor layer so as to be narrower than the gate electrode;
A second semiconductor layer including a pair of impurities is formed on a part of the protective insulating layer and on the first semiconductor layer;
The gate insulating layer and the first metal layer on the scanning line are removed in a region outside the image display unit to expose a transparent conductive layer serving as an electrode terminal of the scanning line,
A source wiring (signal line) including one or more second metal layers including a refractory metal layer on the second semiconductor layer, the first transparent insulating substrate, and a part of the electrode terminal of the signal line. ), Drain wiring is also formed on the second semiconductor layer, the first transparent insulating substrate, and a part of the pixel electrode,
A liquid crystal display device, wherein a photosensitive organic insulating layer is formed on the source / drain wiring. Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
A scanning line consisting of a laminate of a transparent conductive layer and a first metal layer on at least one main surface of the first transparent insulating substrate and having an insulating layer on its side surface, and a transparent conductive pixel electrode are formed,
One or more gate insulating layers are formed on the scanning lines;
A first semiconductor layer containing no impurities is formed in an island shape on the gate insulating layer over the gate electrode;
A protective insulating layer is formed on the first semiconductor layer so as to be narrower than the gate electrode;
A second semiconductor layer including a pair of impurities is formed on a part of the protective insulating layer and on the first semiconductor layer;
The gate insulating layer and the first metal layer on the scanning line are removed in a region outside the image display unit to expose a transparent conductive layer that is a part of the scanning line,
A source wiring (signal line) including one or more second metal layers including a refractory metal layer on the second semiconductor layer, the first transparent insulating substrate, and a part of the electrode terminal of the signal line. ), Drain wiring on the second semiconductor layer, on the first transparent insulating substrate, and on part of the pixel electrode, and
An electrode terminal of the scanning line, which includes a part of the scanning line, and an electrode terminal of the signal line made up of a part of the signal line in a region outside the image display unit,
A liquid crystal display device, wherein a photosensitive organic insulating layer is formed on the signal line except on the electrode terminal of the signal line. Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
A scanning line consisting of a laminate of a transparent conductive layer and a first metal layer on at least one main surface of the first transparent insulating substrate and having an insulating layer on its side surface, and a transparent conductive pixel electrode are formed,
One or more gate insulating layers are formed on the scanning lines;
A first semiconductor layer containing no impurities is formed in an island shape on the gate insulating layer over the gate electrode;
A protective insulating layer is formed on the first semiconductor layer so as to be narrower than the gate electrode;
A second semiconductor layer including a pair of impurities is formed on a part of the protective insulating layer and on the first semiconductor layer;
The gate insulating layer and the first metal layer on the scanning line are removed in a region outside the image display unit to expose a transparent conductive layer that is a part of the scanning line,
A source wiring (signal line) made of one or more anodizable metal layers including a refractory metal layer on the second semiconductor layer and the first transparent insulating substrate, and a part of the protective insulating layer The drain wiring on the top, the first semiconductor layer, the first transparent insulating substrate, and a part of the pixel electrode, the electrode terminal of the scanning line including a part of the scanning line, and an image A signal line electrode terminal formed of a part of the signal line is formed in a region outside the display unit,
A liquid crystal display device, wherein an anodized layer is formed on the source / drain wiring except on the electrode terminal of the signal line. At least an insulated gate transistor on one main surface, a scanning line also serving as a gate electrode of the insulated gate transistor and a signal line also serving as a source line, a pixel electrode connected to a drain of the insulated gate transistor, A first transparent insulating substrate in which unit picture elements each having a counter electrode formed at a predetermined distance from the pixel electrode are arranged in a two-dimensional matrix, and opposed to the first transparent insulating substrate In a liquid crystal display device in which liquid crystal is filled between the second transparent insulating substrate or the color filter,
A scanning line and a counter electrode, which are composed of at least one first metal layer on one main surface of the first transparent insulating substrate and have an insulating layer on its side surface, are formed,
One or more gate insulating layers are formed on the scanning line and the counter electrode,
A first semiconductor layer containing no impurities is formed in an island shape on the gate insulating layer over the gate electrode;
A protective insulating layer is formed on the first semiconductor layer so as to be narrower than the gate electrode;
A second semiconductor layer including a pair of impurities is formed on a part of the protective insulating layer and on the first semiconductor layer;
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display part, and a part of the scanning line is exposed,
A source wiring (signal line) / drain wiring (picture element electrode) composed of one or more second metal layers including a refractory metal layer on the second semiconductor layer and the first transparent insulating substrate; Similarly, the scanning line electrode terminal including the opening and the first and second semiconductor layers around the opening, and the signal line electrode terminal formed of a part of the signal line in the region outside the image display unit,
A liquid crystal display device, wherein a photosensitive organic insulating layer is formed on the signal line except on the electrode terminal of the signal line. At least an insulated gate transistor on one main surface, a scanning line also serving as a gate electrode of the insulated gate transistor and a signal line also serving as a source line, a pixel electrode connected to a drain of the insulated gate transistor, A first transparent insulating substrate in which unit picture elements each having a counter electrode formed at a predetermined distance from the pixel electrode are arranged in a two-dimensional matrix, and opposed to the first transparent insulating substrate In a liquid crystal display device in which liquid crystal is filled between the second transparent insulating substrate or the color filter,
A scanning line and a counter electrode, which are composed of at least one first metal layer on one main surface of the first transparent insulating substrate and have an insulating layer on its side surface, are formed,
One or more gate insulating layers are formed on the scanning line and the counter electrode,
A first semiconductor layer containing no impurities is formed in an island shape on the gate insulating layer over the gate electrode;
A protective insulating layer is formed on the first semiconductor layer so as to be narrower than the gate electrode;
A second semiconductor layer including a pair of impurities is formed on a part of the protective insulating layer and on the first semiconductor layer;
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display part, and a part of the scanning line is exposed,
A source wiring (signal line) / drain wiring (picture element electrode) made of one or more anodizable metal layers including a refractory metal layer on the second semiconductor layer and the first transparent insulating substrate; The electrode terminal of the scanning line is also formed including the first and second semiconductor layers around the opening and the opening, and the electrode terminal of the signal line made up of a part of the signal line is formed in a region outside the image display unit. ,
A liquid crystal display device, wherein an anodized layer is formed on the source / drain wiring except on the electrode terminal of the signal line. According to claim 1, claim 2, claim 3, claim 4, claim 5, claim 6 and claim 7, wherein the insulating layer formed on the side surface of the scanning line is an organic insulating layer. The liquid crystal display device described. The claim 1, claim 2, claim 6, and claim 7, wherein the first metal layer is made of an anodizable metal layer and the insulating layer formed on the side surface of the scanning line is an anodized layer. A liquid crystal display device according to 1. Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
At least one first metal layer, one or more gate insulating layers, a first amorphous silicon layer not containing impurities, and a protective insulating layer are sequentially formed on at least one main surface of the first transparent insulating substrate. A process of depositing;
Selectively forming a protective insulating layer serving as a channel protective layer of the insulated gate transistor to expose the first amorphous silicon layer;
Depositing a second amorphous silicon layer containing impurities;
A step of forming a photosensitive resin pattern corresponding to the scanning line and having a film thickness on the contact formation region of the scanning line that is thinner than other regions in a region outside the image display unit;
Sequentially etching the second amorphous silicon layer, the first amorphous silicon layer, the gate insulating layer, and the first metal layer using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose the second amorphous silicon layer on the contact formation region;
Forming an insulating layer on a side surface of the scanning line;
A portion of the scanning line is etched by etching the second amorphous silicon layer, the first amorphous silicon layer, and the gate insulating layer in the contact region using the photosensitive resin pattern having the reduced thickness as a mask. Exposing the step,
After depositing one or more anodizable metal layers including a refractory metal layer, including source (signal lines) / drain wirings and part of the scanning lines so as to partially overlap the protective insulating layer Forming a scanning line electrode terminal;
A transparent conductive pixel electrode on the first transparent insulating substrate and a part of the drain wiring, a transparent conductive electrode terminal on the signal line in a region outside the image display unit, and an electrode terminal of the scanning line Forming a transparent conductive electrode terminal thereon;
A step of anodizing the source / drain wiring while protecting the transparent conductive pixel electrode and the transparent conductive electrode terminal using the photosensitive resin pattern used for the selective pattern formation of the pixel electrode and the electrode terminal as a mask A method of manufacturing a liquid crystal display device having Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
At least one first metal layer, one or more gate insulating layers, a first amorphous silicon layer not containing impurities, and a protective insulating layer are sequentially formed on at least one main surface of the first transparent insulating substrate. A process of depositing;
Selectively forming a protective insulating layer serving as a channel protective layer of the insulated gate transistor to expose the first amorphous silicon layer;
Depositing a second amorphous silicon layer containing impurities;
A step of forming a photosensitive resin pattern corresponding to the scanning line and having a film thickness on the contact formation region of the scanning line that is thinner than other regions in a region outside the image display unit;
Sequentially etching the second amorphous silicon layer, the first amorphous silicon layer, the gate insulating layer, and the first metal layer using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose the second amorphous silicon layer on the contact formation region;
Forming an insulating layer on a side surface of the scanning line;
A portion of the scanning line is etched by etching the second amorphous silicon layer, the first amorphous silicon layer, and the gate insulating layer in the contact region using the photosensitive resin pattern having the reduced thickness as a mask. Exposing the step,
Forming a transparent conductive pixel electrode on the first transparent insulating substrate, a signal line electrode terminal, and a scanning line electrode terminal including a part of the scanning line;
After depositing one or more second metal layers including a heat-resistant metal layer, a photosensitive organic insulating layer is formed on the surface including a part of the electrode terminal of the signal line so as to partially overlap the protective insulating layer. A method of manufacturing a liquid crystal display device, comprising: forming a source wiring (signal line) having a drain wiring having a photosensitive organic insulating layer on a surface thereof, which also includes a part of a pixel electrode. Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
A transparent conductive layer, a first metal layer, one or more gate insulating layers, a first amorphous silicon layer not containing impurities, and a protective insulating layer are sequentially formed on at least one main surface of the first transparent insulating substrate. A process of depositing;
Selectively forming a protective insulating layer serving as a channel protective layer of the insulated gate transistor to expose the first amorphous silicon layer;
Depositing a second amorphous silicon layer containing impurities;
Corresponding to the electrode terminals of the scanning line and the pixel electrode and the scanning line and the signal line, the film thickness on the electrode terminal forming area of the scanning line and the signal line in the area outside the image display part and the image display part is larger than that in the other areas Forming a thin photosensitive resin pattern,
Sequentially etching the second amorphous silicon layer, the first amorphous silicon layer, the gate insulating layer, the first metal layer, and the transparent conductive layer using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose a second amorphous silicon layer on the pixel electrode and on the electrode terminal formation region of the scanning line and the signal line;
Forming an insulating layer on a side surface of the scanning line;
The second amorphous silicon layer and the first amorphous silicon layer on the pixel electrode and on the electrode terminal formation region of the scanning line and the signal line, using the photosensitive resin pattern having the reduced thickness as a mask, Etching the gate insulating layer and the first metal layer to expose the transparent conductive pixel electrode, the electrode terminal of the scanning line, and the electrode terminal of the signal line;
After depositing one or more second metal layers including a refractory metal layer, a photosensitive organic insulating layer is formed on the surface including a part of the electrode terminal of the signal line so as to partially overlap the protective insulating layer. A method of manufacturing a liquid crystal display device, comprising: forming a source wiring (signal line) having a drain wiring having a photosensitive organic insulating layer on a surface thereof, which also includes a part of a pixel electrode. Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
A transparent conductive layer, a first metal layer, one or more gate insulating layers, a first amorphous silicon layer not containing impurities, and a protective insulating layer are sequentially formed on at least one main surface of the first transparent insulating substrate. A process of depositing;
Selectively forming a protective insulating layer serving as a channel protective layer of the insulated gate transistor to expose the first amorphous silicon layer;
Depositing a second amorphous silicon layer containing impurities;
A photosensitive resin pattern corresponding to the scanning line, the pixel electrode, and the electrode terminal of the scanning line, the film thickness on the electrode terminal forming area of the scanning line being thinner on the pixel electrode and the area outside the image display area than other areas. Forming a step;
Sequentially etching the second amorphous silicon layer, the first amorphous silicon layer, the gate insulating layer, the first metal layer, and the transparent conductive layer using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose the second amorphous silicon layer on the pixel electrode and the electrode terminal formation region of the scanning line;
Forming an insulating layer on a side surface of the scanning line;
The second amorphous silicon layer, the first amorphous silicon layer, and the gate insulating layer on the pixel electrode and the electrode terminal formation region of the scanning line, using the photosensitive resin pattern having the reduced thickness as a mask And etching the first metal layer to expose the transparent conductive pixel electrode and a part of the scanning line;
After depositing one or more second metal layers including a refractory metal layer, a source wiring (signal line) so as to partially overlap the protective insulating layer, and a drain wiring also including a part of the pixel electrode Corresponding to the electrode terminal of the scanning line including a part of the scanning line and the electrode terminal of the signal line formed of a part of the signal line in the region outside the image display portion, and the film thickness on the signal line is another region. Forming a thicker photosensitive organic insulating layer pattern;
Using the photosensitive organic insulating layer pattern as a mask, the second metal layer, the second amorphous silicon layer, and the first amorphous silicon layer are selectively removed to form source / drain wirings, scanning lines, and signal lines. Forming an electrode terminal of
A method of manufacturing a liquid crystal display device, comprising: exposing a drain wiring line, a scanning line, and a signal line electrode terminal by reducing the film thickness of the photosensitive organic insulating layer pattern. Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
A transparent conductive layer, a first metal layer, one or more gate insulating layers, a first amorphous silicon layer not containing impurities, and a protective insulating layer are sequentially formed on at least one main surface of the first transparent insulating substrate. A process of depositing;
Selectively forming a protective insulating layer serving as a channel protective layer of the insulated gate transistor to expose the first amorphous silicon layer;
Depositing a second amorphous silicon layer containing impurities;
A photosensitive resin pattern corresponding to the scanning line, the pixel electrode, and the electrode terminal of the scanning line, the film thickness on the electrode terminal forming area of the scanning line being thinner on the pixel electrode and the area outside the image display area than other areas. Forming a step;
Sequentially etching the second amorphous silicon layer, the first amorphous silicon layer, the gate insulating layer, the first metal layer, and the transparent conductive layer using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose the second amorphous silicon layer on the pixel electrode and the electrode terminal formation region of the scanning line;
Forming an insulating layer on a side surface of the scanning line;
The second amorphous silicon layer, the first amorphous silicon layer, and the gate insulating layer on the pixel electrode and the electrode terminal formation region of the scanning line, using the photosensitive resin pattern having the reduced thickness as a mask And etching the first metal layer to expose the transparent conductive pixel electrode and a part of the scanning line;
After depositing one or more anodizable metal layers including the refractory metal layer, the source wiring (signal line) and the drain including the part of the pixel electrode so as to partially overlap the protective insulating layer Corresponding to the wiring, the electrode terminal of the scanning line including a part of the scanning line, and the electrode terminal of the signal line consisting of a part of the signal line in the region outside the image display unit, the electrode terminal of the scanning line and the signal line Forming a photosensitive resin pattern whose upper film thickness is thicker than other regions;
Using the photosensitive resin pattern as a mask, the anodizable metal layer, the second amorphous silicon layer, and the first amorphous silicon layer are selectively removed to form source / drain wirings, scanning lines, and signal lines. Forming an electrode terminal;
Reducing the film thickness of the photosensitive resin pattern to expose the source / drain wiring; and
A method of manufacturing a liquid crystal display device, comprising a step of anodizing a source / drain wiring while protecting the electrode terminal. At least an insulated gate transistor on one main surface, a scanning line also serving as a gate electrode of the insulated gate transistor and a signal line also serving as a source line, a pixel electrode connected to a drain of the insulated gate transistor, A first transparent insulating substrate in which unit picture elements each having a counter electrode formed at a predetermined distance from the pixel electrode are arranged in a two-dimensional matrix, and opposed to the first transparent insulating substrate In a liquid crystal display device in which liquid crystal is filled between the second transparent insulating substrate or the color filter,
At least one first metal layer, one or more gate insulating layers, a first amorphous silicon layer not containing impurities, and a protective insulating layer are sequentially formed on at least one main surface of the first transparent insulating substrate. A process of depositing;
Selectively forming a protective insulating layer serving as a channel protective layer of the insulated gate transistor to expose the first amorphous silicon layer;
Depositing a second amorphous silicon layer containing impurities;
Selectively etching the second amorphous silicon layer, the first amorphous silicon layer, the gate insulating layer, and the first metal layer corresponding to the scanning line and the counter electrode;
Forming an insulating layer on the side surfaces of the scanning line and the counter electrode;
A portion of the scanning line is selectively exposed by etching the second amorphous silicon layer, the first amorphous silicon layer, and the gate insulating layer in the contact region on the scanning line in a region outside the image display portion. Process,
After depositing one or more second metal layers including the heat-resistant metal layer, the source wiring (signal line) / drain wiring (pixel electrode) so as to partially overlap the protective insulating layer, and the scanning line A photosensitive organic material that corresponds to the electrode terminal of the scanning line including a part and the electrode terminal of the signal line made up of a part of the signal line in the area outside the image display part, and the film thickness on the signal line is thicker than other areas Forming an insulating layer pattern;
Using the photosensitive organic insulating layer pattern as a mask, the second metal layer, the second amorphous silicon layer, and the first amorphous silicon layer are selectively removed to form source / drain wirings, scanning lines, and signals. Forming a wire electrode terminal;
A method of manufacturing a liquid crystal display device, comprising: exposing a drain wiring line, a scanning line, and a signal line electrode terminal by reducing the film thickness of the photosensitive organic insulating layer pattern. At least an insulated gate transistor on one main surface, a scanning line also serving as a gate electrode of the insulated gate transistor and a signal line also serving as a source line, a pixel electrode connected to a drain of the insulated gate transistor, A first transparent insulating substrate in which unit picture elements each having a counter electrode formed at a predetermined distance from the pixel electrode are arranged in a two-dimensional matrix, and opposed to the first transparent insulating substrate In a liquid crystal display device in which liquid crystal is filled between the second transparent insulating substrate or the color filter,
At least one first metal layer, one or more gate insulating layers, a first amorphous silicon layer not containing impurities, and a protective insulating layer are sequentially formed on at least one main surface of the first transparent insulating substrate. A process of depositing;
Selectively forming a protective insulating layer serving as a channel protective layer of the insulated gate transistor to expose the first amorphous silicon layer;
Depositing a second amorphous silicon layer containing impurities;
Selectively etching the second amorphous silicon layer, the first amorphous silicon layer, the gate insulating layer, and the first metal layer corresponding to the scanning line and the counter electrode;
Forming an insulating layer on the side surfaces of the scanning line and the counter electrode;
A portion of the scanning line is selectively exposed by etching the second amorphous silicon layer, the first amorphous silicon layer, and the gate insulating layer in the contact region on the scanning line in a region outside the image display portion. Process,
After depositing one or more anodizable metal layers including a heat-resistant metal layer, a source wiring (signal line) / drain wiring (pixel electrode) so as to partially overlap the protective insulating layer, and the scanning line A photosensitive resin pattern corresponding to the electrode terminal of the scanning line including a part of the scanning line and the electrode terminal of the signal line including a part of the signal line is formed, and the film thickness on the electrode terminal is thicker than other regions. Process,
Using the photosensitive resin pattern as a mask, the anodizable metal layer, the second amorphous silicon layer, and the first amorphous silicon layer are selectively removed to form source / drain wirings, scanning lines, and signal lines. Forming an electrode terminal of
Reducing the film thickness of the photosensitive resin pattern to expose the source / drain wiring; and
A method of manufacturing a liquid crystal display device, comprising a step of anodizing a source / drain wiring while protecting the electrode terminal. At least an insulated gate transistor on one main surface, a scanning line also serving as a gate electrode of the insulated gate transistor and a signal line also serving as a source line, a pixel electrode connected to a drain of the insulated gate transistor, A first transparent insulating substrate in which unit picture elements each having a counter electrode formed at a predetermined distance from the pixel electrode are arranged in a two-dimensional matrix, and opposed to the first transparent insulating substrate In a liquid crystal display device in which liquid crystal is filled between the second transparent insulating substrate or the color filter,
At least one first metal layer, one or more gate insulating layers, a first amorphous silicon layer not containing impurities, and a protective insulating layer are sequentially formed on at least one main surface of the first transparent insulating substrate. A process of depositing;
Selectively forming a protective insulating layer serving as a channel protective layer of the insulated gate transistor to expose the first amorphous silicon layer;
Depositing a second amorphous silicon layer containing impurities;
A step of forming a photosensitive resin pattern corresponding to the scanning line and the counter electrode and having a film thickness on the contact formation region of the scanning line that is thinner than other regions in the region outside the image display unit;
Sequentially etching the second amorphous silicon layer, the first amorphous silicon layer, the gate insulating layer, and the first metal layer using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose the second amorphous silicon layer in the contact formation region;
Forming an insulating layer on the side surfaces of the scanning line and the counter electrode;
The second amorphous silicon layer, the first amorphous silicon layer, and the gate insulating layer in the contact formation region are etched using the photosensitive resin pattern with the reduced thickness as a mask to form a scanning line. Exposing the part,
After depositing one or more second metal layers including the heat-resistant metal layer, the source wiring (signal line) / drain wiring (pixel electrode) so as to partially overlap the protective insulating layer, and the scanning line A photosensitive organic material that corresponds to the electrode terminal of the scanning line including a part and the electrode terminal of the signal line made up of a part of the signal line in the area outside the image display part, and the film thickness on the signal line is thicker than other areas Forming an insulating layer pattern;
Using the photosensitive organic insulating layer pattern as a mask, the second metal layer, the second amorphous silicon layer, and the first amorphous silicon layer are selectively removed to form source / drain wirings, scanning lines, and signals. Forming a wire electrode terminal;
A method of manufacturing a liquid crystal display device, comprising: exposing a drain wiring line, a scanning line, and a signal line electrode terminal by reducing the film thickness of the photosensitive organic insulating layer pattern. At least an insulated gate transistor on one main surface, a scanning line also serving as a gate electrode of the insulated gate transistor and a signal line also serving as a source line, a pixel electrode connected to a drain of the insulated gate transistor, A first transparent insulating substrate in which unit picture elements each having a counter electrode formed at a predetermined distance from the pixel electrode are arranged in a two-dimensional matrix, and opposed to the first transparent insulating substrate In a liquid crystal display device in which liquid crystal is filled between the second transparent insulating substrate or the color filter,
At least one first metal layer, one or more gate insulating layers, a first amorphous silicon layer not containing impurities, and a protective insulating layer are sequentially formed on at least one main surface of the first transparent insulating substrate. A process of depositing;
Selectively forming a protective insulating layer serving as a channel protective layer of the insulated gate transistor to expose the first amorphous silicon layer;
Depositing a second amorphous silicon layer containing impurities;
A step of forming a photosensitive resin pattern corresponding to the scanning line and the counter electrode and having a film thickness on the contact formation region of the scanning line that is thinner than other regions in the region outside the image display unit;
Sequentially etching the second amorphous silicon layer, the first amorphous silicon layer, the gate insulating layer, and the first metal layer using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose the second amorphous silicon layer in the contact formation region;
Forming an insulating layer on the side surfaces of the scanning line and the counter electrode;
A part of the scanning line is etched by etching the second amorphous silicon layer, the first amorphous silicon layer, and the gate insulating layer in the contact region using the photosensitive resin pattern having the reduced thickness as a mask. Exposing the step,
After depositing one or more anodizable metal layers including a heat-resistant metal layer, a source wiring (signal line) / drain wiring (pixel electrode) so as to partially overlap the protective insulating layer, and the scanning line A photosensitive resin pattern corresponding to the electrode terminal of the scanning line including a part of the scanning line and the electrode terminal of the signal line including a part of the signal line is formed, and the film thickness on the electrode terminal is thicker than other regions. Process,
Using the photosensitive resin pattern as a mask, the anodizable metal layer, the second amorphous silicon layer, and the first amorphous silicon layer are selectively removed to form source / drain wirings, scanning lines, and signal lines. Forming an electrode terminal of
Reducing the film thickness of the photosensitive resin pattern to expose the source / drain wiring; and
A method of manufacturing a liquid crystal display device, comprising a step of anodizing a source / drain wiring while protecting the electrode terminal. The insulating layer formed on the side surface of the scanning line is an organic insulating layer, and is formed by electrodeposition, wherein the insulating layer is formed by electrodeposition. 11, 12, 13, 14, 15. A method for manufacturing a liquid crystal display device according to claim 16, claim 17, or claim 18. 13. The insulating layer formed on the side surface of the scanning line, wherein the first metal layer is made of an anodizable metal layer, is formed by anodization. 16. A method for manufacturing a liquid crystal display device according to claim 17, 17 and 18.

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