JP2005049667A - Liquid crystal display and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem point that in the conventional manufacturing method decreased in the number of manufacturing stages, manufacture margin is small as a channel length becomes short and the the yield decreases. <P>SOLUTION: Four-mask process and three-mask process plans of a TN type liquid crystal display and an IPS type liquid crystal are structured by a technology combination of new technology for rationalizing a stage of forming scanning lines and a stage of forming contacts by introducing half-tone exposure technology, new technology for rationalizing a stage of forming the protective layer of an electrode terminal by introducing half-tone exposure technology into an anode oxidizing stage of source and drain wiring as known technology, and rationalization technology for forming pixel electrodes and the scanning lines at the same time as known technology. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

The present invention relates to a liquid crystal display device having a color image display function, and more particularly to an active liquid crystal display device.

With recent advances in microfabrication technology, liquid crystal material technology, high-density packaging technology, and the like, television images and various image display devices are provided in large quantities on a commercial basis in 5 to 50 cm diagonal liquid crystal display devices. In addition, color display is easily realized by forming an RGB colored layer on one of the two glass substrates constituting the liquid crystal panel. In particular, so-called active liquid crystal panels in which switching elements are built in for each picture element have little crosstalk, fast response speed, and an image having a high contrast ratio.

 These liquid crystal display devices (liquid crystal panels) generally have a matrix organization of about 200 to 1,200 scanning lines and about 300 to 1,600 signal lines. And high definition are progressing at the same time.

FIG. 28 shows a mounting state on the liquid crystal panel, and a semiconductor integrated circuit for supplying a drive signal to the electrode terminal group 5 of the scanning line formed on one transparent insulating substrate, for example, the glass substrate 2 constituting the liquid crystal panel 1. A COG (Chip-On-Glass) system in which the chip 3 is connected using a conductive adhesive, or a TCP film 4 having a terminal of gold foil or solder-plated copper foil based on a polyimide resin thin film, for example, as a signal An electrical signal is supplied to the image display unit by a mounting means such as a TCP (Tape-Carrier-Package) method in which the electrode terminal group 6 of the wire is fixed by being pressed with an appropriate adhesive containing a conductive medium. Here, for convenience, two mounting methods are shown at the same time, but in actuality, either method is selected as appropriate.

Wiring paths 7 and 8 connect the pixels in the image display unit located almost at the center of the liquid crystal panel 1 to the electrode terminals 5 and 6 of the scanning lines and signal lines, and are not necessarily the same as the electrode terminal groups 5 and 6. It is not necessary to be made of a conductive material. Reference numeral 9 denotes a counter glass substrate or color filter which is another transparent insulating substrate having a transparent conductive counter electrode common to all liquid crystal cells on the counter surface.

  FIG. 29 shows an equivalent circuit diagram of an active liquid crystal display device in which insulated gate transistors 10 are arranged for each picture element as a switching element, 11 (7 in FIG. 28) is a scanning line, and 12 (8 in FIG. 28) is a signal. A line 13 is a liquid crystal cell, and the liquid crystal cell 13 is electrically treated as a capacitive element. The elements drawn with solid lines are formed on one glass substrate 2 constituting the liquid crystal panel, and the counter electrode 14 common to all liquid crystal cells 13 drawn with dotted lines is the main electrode facing the other glass substrate 9. It is formed on the surface. When the OFF resistance of the insulated gate transistor 10 or the resistance of the liquid crystal cell 13 is low, or when importance is attached to the gradation of the display image, an auxiliary storage capacitor 15 for increasing the time constant of the liquid crystal cell 13 as a load. Is added to the liquid crystal cell 13 in parallel. Reference numeral 16 denotes a common bus of the storage capacitor 15.

  FIG. 30 is a cross-sectional view of the main part of the image display portion of the liquid crystal display device, and the two glass substrates 2 and 9 constituting the liquid crystal panel 1 are columnar spacers formed on resinous fibers, beads or color filters 9. Are formed at a predetermined distance of about several μm by a spacer material (not shown) such as a sealing material made of an organic resin and a sealing material (both shown in FIG. The liquid crystal 17 is filled in this closed space.

  In the case of realizing color display, an organic thin film having a thickness of about 1 to 2 μm containing either or both of a dye and a pigment called a colored layer 18 is deposited on the closed space side of the glass substrate 9 to provide a color display function. In this case, the glass substrate 9 is called another color filter (color filter abbreviation is CF). Depending on the properties of the liquid crystal material 17, a polarizing plate 19 is attached to either the upper surface of the glass substrate 9, the lower surface of the glass substrate 2, or both surfaces, and the liquid crystal panel 1 functions as an electro-optical element. Currently, most liquid crystal panels on the market use TN (twisted nematic) type liquid crystal material, and two polarizing plates 19 are usually required. Although not shown, in the transmissive liquid crystal panel, a back light source is disposed as a light source, and white light is irradiated from below.

The polyimide resin thin film 20 having a thickness of, for example, about 0.1 μm formed on the two glass substrates 2 and 9 in contact with the liquid crystal 17 is an alignment film for aligning liquid crystal molecules in a predetermined direction. Reference numeral 21 denotes a drain electrode (wiring) that connects the drain of the insulated gate transistor 10 and the transparent conductive pixel electrode 22, and is often formed simultaneously with the signal line (source line) 12. The semiconductor layer 23 is located between the signal line 12 and the drain electrode 21 and will be described in detail later. The Cr thin film layer 24 having a thickness of about 0.1 μm formed at the boundary between the adjacent colored layers 18 on the color filter 9 prevents external light from entering the semiconductor layer 23, the scanning line 11, and the signal line 12. It is a technology that is fixed as a so-called black matrix (Black Matrix abbreviation is BM).

Here, a structure and a manufacturing method of an insulated gate transistor as a switching element will be described. Two types of insulated gate transistors are currently widely used, and one of them called etch stop type is introduced as a conventional example. FIG. 31 is a plan view of unit picture elements of an active substrate (semiconductor device for display device) that constitutes a conventional liquid crystal panel, on the lines AA ′, BB ′, and CC ′ of FIG. FIG. 32 shows a cross-sectional view of this, and the manufacturing process will be briefly described below.

First, as shown in FIGS. 31 (a) and 32 (a), a glass substrate 2 having a thickness of about 0.5 to 1.1 mm as an insulating substrate having high heat resistance, chemical resistance, and transparency, for example, Corning. A first metal layer having a film thickness of about 0.1 to 0.3 μm is deposited on one main surface of a product name 1737 manufactured by the company using a vacuum film-forming apparatus such as SPT (sputtering), and fine processing technology is used. The scanning lines 11 and the storage capacitor lines 16 that also serve as the gate electrodes 11A are selectively formed. The scanning line material is selected by comprehensively considering heat resistance, chemical resistance, hydrofluoric acid resistance, and conductivity, but generally a metal or alloy having high heat resistance such as Cr, Ta, MoW alloy is used. Is done.

  It is reasonable to use AL (aluminum) as the material of the scanning line in order to reduce the resistance value of the scanning line in response to the increase in the screen size and resolution of the liquid crystal panel, but AL alone has heat resistance. Since it is low, it is a common technique to stack with Cr, Ta, Mo or their silicides as mentioned above, or to add an oxide layer (Al2O3) by anodic oxidation on the surface of AL. That is, the scanning line 11 is composed of one or more metal layers.

Next, a first SiNx (silicon nitride) layer 30 serving as a gate insulating layer is formed on the entire surface of the glass substrate 2 using a PCVD (plasma sieve fluid) apparatus, and a first serving as a channel of an insulated gate transistor containing almost no impurities. The amorphous silicon (a-Si) layer 31, the second SiNx layer 32 serving as an insulating layer for protecting the channel, and three kinds of thin film layers are, for example, about 0.3-0.05-0.1 μm. Sequentially deposited by film thickness, the second SiNx layer on the gate electrode 11A is selectively left narrower than the gate electrode 11A by microfabrication technology as shown in FIGS. 31 (b) and 32 (b). And the first amorphous silicon layer 31 is exposed.

Subsequently, a second amorphous silicon layer 33 containing, for example, phosphorus as an impurity is deposited on the entire surface using a PCVD apparatus in a thickness of about 0.05 μm, for example, and then FIG. c) using a vacuum film forming apparatus such as SPT, a thin film layer 34 of, for example, Ti, Cr, Mo or the like as a heat-resistant metal layer having a film thickness of about 0.1 μm, and a film thickness of 0. For example, a Ti thin film layer 36 is sequentially deposited as an AL thin film layer 35 having a thickness of about 3 μm and an intermediate conductive layer having a thickness of about 0.1 μm, and these three kinds of thin film layers 34A which are source / drain wiring materials are formed by a fine processing technique. , 35A and 36A, the drain electrode 21 of the insulated gate transistor and the signal line 12 also serving as the source electrode are selectively formed. In this selective pattern formation, the Ti thin film layer 36, the AL thin film layer 35, and the Ti thin film layer 34 are sequentially etched using the photosensitive resin pattern used for forming the source / drain wiring as a mask, and then the source / drain electrodes 12, The second amorphous silicon layer 33 between the two regions 21 is removed to expose the second SiNx layer 32D, and the first amorphous silicon layer 31 is also removed in other regions to form the gate insulating layer 30. Made by exposing. Since the second SiNx layer 32D serving as the channel protective layer exists in this manner and the etching of the second amorphous silicon layer 33 is automatically terminated, this manufacturing method is called an etch stop.

  The source / drain electrodes 12 and 21 are formed to partially overlap (several μm) in plan with the etch stop layer 32D so that the insulated gate transistor does not have an offset structure. Since this overlap is electrically acting as a parasitic capacitance, the smaller the better, the better. However, it is determined by the alignment accuracy of the exposure machine, the accuracy of the photomask, the expansion coefficient of the glass substrate, and the glass substrate temperature at the time of exposure. It is about 2 μm.

Further, after removing the photosensitive resin pattern, a SiNx layer having a thickness of about 0.3 μm is deposited on the entire surface of the glass substrate 2 as a transparent insulating layer using a PCVD apparatus in the same manner as the gate insulating layer. As the insulating layer 37, as shown in FIGS. 31D and 32D, the passivation insulating layer 37 is selectively removed by a microfabrication technique, an opening 62 is formed on the drain electrode 21, and an image display unit. In the outer region, an opening 63 is formed on the position where the electrode terminal 5 of the scanning line 11 is formed, and an opening 64 is formed on the position where the electrode terminal 6 of the signal line 12 is formed, so that the drain electrode 21 and the scanning line are formed. 11 and a part of the signal line 12 are exposed. An opening 65 is formed on the storage capacitor line 16 (electrode pattern in which the storage capacitor lines are bundled in parallel) to expose a part of the storage capacitor line 16.

Finally, for example, ITO (Indium-Tin-Oxide) or IZO (Indium-Zinc-Oxide) is applied as a transparent conductive layer having a film thickness of about 0.1 to 0.2 μm using a vacuum film forming apparatus such as SPT. As shown in FIGS. 31 (e) and 32 (e), the pixel electrode 22 is selectively formed on the passivation insulating layer 37 including the opening 62 by a microfabrication technique, and the active substrate 2 is completed. A part of the exposed scanning line 11 in the opening 63 may be used as the electrode terminal 5 and a part of the exposed signal line 12 in the opening 64 may be used as the electrode terminal 6. As shown in FIG. The electrode terminals 5A and 6A made of ITO may be selectively formed on the passivation insulating layer 37 including 63 and 64, but normally the transparent conductive short-circuit line 40 connecting the electrode terminals 5A and 6A is also provided. Formed simultaneously. The reason is that although not shown, the resistance between the electrode terminals 5A and 6A and the short-circuit line 40 can be increased in resistance by increasing the resistance by forming an elongated stripe. Similarly, an electrode terminal to the storage capacitor line 16 is formed including the opening 65.

When the wiring resistance of the signal line 12 does not become a problem, the low resistance wiring layer 35 made of AL is not necessarily required. In this case, the source / drain wiring 12 can be selected by selecting a heat-resistant metal material such as Cr, Ta, and Mo. , 21 can be simplified by forming a single layer. As described above, it is important to ensure electrical connection between the source / drain wiring and the second amorphous silicon layer by using a refractory metal layer, and the heat resistance of the insulated gate transistor is a precedent example. Details are described in Japanese Utility Model Publication No. 7-74368. In FIG. 31C, the storage capacitor 15 is formed by a region 50 (shaded portion to the right) where the storage capacitor line 16 and the drain electrode 21 overlap in a plane via the gate insulating layer 30. Detailed description thereof is omitted here.
JP-A-7-74368

Although the detailed process of the five-mask process described above is omitted, it was obtained as a result of rationalizing the island formation process of the semiconductor layer and reducing the contact formation process once. The photomask which has been reduced to 5 at the present time due to the introduction of the dry etching technology has greatly contributed to the reduction of the process cost. In order to reduce the production cost of the liquid crystal display device, it is a well-known development target that it is effective to reduce the process cost in the manufacturing process of the active substrate and the member cost in the panel assembly process and the module mounting process. To reduce the process cost, there are a process reduction that shortens the process and an inexpensive process development or replacement with a process. Here, the process is reduced to a four-mask process where an active substrate can be obtained with four photomasks. An example will be described. The four-mask process reduces the number of photo-etching steps by introducing halftone exposure technology. FIG. 33 is a plan view of unit picture elements of an active substrate corresponding to the four-mask process. FIG. FIG. 34 is a cross-sectional view taken along the lines AA ′, BB ′, and CC ′. As already described, two types of insulated gate transistors are currently widely used. Here, a channel-etched insulated gate transistor is used.

First, a first metal layer having a film thickness of about 0.1 to 0.3 μm is deposited on one main surface of the glass substrate 2 using a vacuum film forming apparatus such as SPT, as in the five-mask process. As shown in FIGS. 33A and 34A, the scanning lines 11 and the storage capacitor lines 16 that also serve as the gate electrodes 11A are selectively formed by a fine processing technique.

Next, a SiNx layer 30 that becomes a gate insulating layer using a PCVD apparatus on the entire surface of the glass substrate 2, a first amorphous silicon layer 31 that contains almost no impurities and becomes a channel of an insulated gate transistor, and contains impurities. The second amorphous silicon layer 33 that becomes the source / drain of the insulated gate transistor and the three kinds of thin film layers are sequentially deposited with a film thickness of, for example, about 0.3-0.2-0.05 μm. Subsequently, using a vacuum film forming apparatus such as SPT, for example, a Ti thin film layer 34 as a heat-resistant metal layer having a film thickness of about 0.1 μm, an AL thin film layer 35 as a low resistance wiring layer having a film thickness of about 0.3 μm, and a film For example, a Ti thin film layer 36, that is, a source / drain wiring material is sequentially deposited as an intermediate conductive layer having a thickness of about 0.1 μm, and the signal line 12 also serving as the drain electrode 21 and the source electrode of the insulated gate transistor is formed by a fine processing technique. In this selective pattern formation, the source / drain channel formation region 80B (shaded portion) is formed by the halftone exposure technique as shown in FIGS. 33 (b) and 34 (b). Photosensitive resin patterns 80A, 8 having a film thickness of, for example, 1.5 μm and thinner than the film thickness of 3 μm in the source / drain wiring formation regions 80A (12), 80A (21). A major feature is that 0B is formed.

Since the photosensitive resin patterns 80A and 80B usually use a positive type photosensitive resin for the production of a substrate for a liquid crystal display device, the source / drain wiring formation region 80A is black, that is, a Cr thin film is formed. The channel region 80B is gray, for example, a line and space Cr pattern having a width of about 0.5 to 1 μm is formed, and the other region may be white, that is, a photomask from which the Cr thin film is removed may be used. . In the gray area, the line-and-space is not resolved because the resolving power of the exposure machine is insufficient, and it is possible to transmit about half of the photomask irradiation light from the lamp light source. According to the remaining film characteristics, photosensitive resin patterns 80A and 80B having a cross-sectional shape as shown in FIG. 34B can be obtained.

Using the photosensitive resin patterns 80A and 80B as a mask, as shown in FIG. 34B, the Ti thin film layer 36, the AL thin film layer 35, the Ti thin film layer 34, the second amorphous silicon layer 33, and the first non-crystalline layer 33 are used. After sequentially etching the crystalline silicon layer 31 to expose the gate insulating layer 30, as shown in FIGS. 33C and 34C, the photosensitive resin pattern 80A, When the film thickness of 80B is reduced from 3 μm to 1.5 μm or more, for example, the photosensitive resin pattern 80B disappears and the channel region is exposed, and 80C (12) and 80C (21) are formed only on the source / drain wiring formation region. Can leave. Therefore, the Ti thin film layer, the AL thin film layer, the Ti thin film layer, and the second amorphous film between the source and drain wirings (channel formation region) are again formed using the photosensitive resin patterns 80C (12) and 80C (21) whose thickness has been reduced as a mask. The porous silicon layer 33A and the first amorphous silicon layer 31A are sequentially etched, and the first amorphous silicon layer 31A is etched leaving about 0.05 to 0.1 μm. Since the source / drain wiring is formed by etching the metal layer and etching the first amorphous silicon layer 31A leaving about 0.05 to 0.1 μm, an insulated gate type obtained by such a manufacturing method is used. The transistor is called a channel etch. In the oxygen plasma treatment, it is desirable to increase the anisotropy in order to suppress the change in pattern dimension, and the reason will be described later.

Further, after the photosensitive resin patterns 80C (12) and 80C (21) are removed, the entire surface of the glass substrate 2 is formed as shown in FIGS. 33 (d) and 34 (d) as in the five-mask process. A SiNx layer having a thickness of about 0.3 μm is deposited as a transparent insulating layer to form a passivation insulating layer 37, and openings are formed in regions where the electrode terminals of the drain electrode 21, the scanning line 11, and the signal line 12 are formed. 62, 63 and 64 are formed, and the passivation insulating layer 37 and the gate insulating layer 30 in the opening 63 are removed to expose a part of the scanning line, and the passivation insulating layer 37 in the openings 62 and 64 is removed. Then, a part of the drain electrode 21 and a part of the signal line are exposed.

Finally, for example, ITO or IZO was deposited as a transparent conductive layer having a film thickness of about 0.1 to 0.2 μm using a vacuum film forming apparatus such as SPT, and the results are shown in FIGS. 33 (e) and 34 (e). As described above, the transparent conductive picture element electrode 22 including the opening 62 is selectively formed on the passivation insulating layer 37 by the fine processing technique to complete the active substrate 2. As for the electrode terminals, transparent conductive electrode terminals 5A and 6A made of ITO are selectively formed on the passivation insulating layer 37 including the openings 63 and 64 here.

  In this way, in the five-mask process and the four-mask process, the contact formation process to the drain electrode 21 and the scanning line 11 is performed at the same time. Therefore, the thickness of the insulating layer in the openings 62 and 63 corresponding to them is determined. The types are different. The passivation insulating layer 37 has a lower film forming temperature and inferior film quality compared to the gate insulating layer 30, and the etching rate with a hydrofluoric acid-based etching solution is several thousand liters / minute and several hundreds liters / minute, which is an order of magnitude. In contrast, the cross-sectional shape of the opening 62 on the drain electrode 21 employs dry etching using a fluorine-based gas for the reason that too much etching occurs at the upper portion and the hole diameter cannot be controlled.

Even if dry etching is employed, since the opening 62 on the drain electrode 21 is only the passivation insulating layer 37, overetching is unavoidable as compared with the opening 63 on the scanning line 11, and depending on the material, The intermediate conductive layer 36A may be reduced in thickness by the etching gas. In removing the photosensitive resin pattern after the etching, the surface of the photosensitive resin pattern is first scraped by about 0.1 to 0.3 μm by oxygen plasma ashing to remove the polymer on the fluorinated surface. In general, chemical treatment using an organic stripping solution such as Tokyo Ohka stripping solution 106 is performed, but the intermediate conductive layer 36A is reduced in thickness and the underlying aluminum layer 35A is exposed. If so, AL2O3, which is an insulator, is formed on the surface of the aluminum layer 35A by the oxygen plasma ashing process, and ohmic contact with the pixel electrode 22 cannot be obtained. Thus, the thickness of the intermediate conductive layer 36A is set to be as thick as, for example, 0.2 μm so that the film can be reduced. Alternatively, when forming the openings 62 to 65, it is possible to avoid the formation of the pixel electrode 22 after removing the aluminum layer 35A and exposing the Ti thin film layer 34A, which is the underlying heat-resistant metal layer. There is also an advantage that the intermediate conductive layer 36A is unnecessary from the beginning.

However, if the in-plane uniformity of the film thickness of these thin films is not good in the former measure, this approach does not necessarily work effectively, and the same is true when the in-plane uniformity of the etching speed is not good. is there. The latter measure eliminates the need for the intermediate conductive layer 36A, but the number of steps for removing the aluminum layer 35A increases, and if the cross section control of the opening 62 is insufficient, the pixel electrode 22 may be disconnected. .

In addition, in the channel-etched insulated gate transistor, the first amorphous silicon layer 31 that does not contain impurities in the channel region must be thickly deposited (usually 0.2 μm or more). The transistor characteristics, particularly the OFF current, tend to be uneven due to the great influence of the uniformity inside. This greatly affects the operating rate of PCVD and the state of particle generation, and is very important from the viewpoint of production cost.

Further, the channel forming process applied in the four-mask process selectively removes the source / drain wiring material between the source / drain wirings 12 and 21 and the semiconductor layer containing impurities, so that the insulated gate transistor is turned on. This is a step of determining the length of the channel (4 to 6 μm in the current mass-produced product) that greatly affects the characteristics. This variation in the channel length greatly changes the ON current value of the insulated gate transistor, and therefore, strict manufacturing control is usually required. However, the channel length, that is, the pattern size of the halftone exposure region is the exposure amount (light source Strength and pattern accuracy of photomask (especially line and space dimensions), photosensitive resin coating thickness, photosensitive resin phenomenon treatment, and the amount of photosensitive resin film reduction in the etching process, etc. In addition, the in-plane uniformity of these quantities does not necessarily produce a product with a high yield, but it requires more stringent manufacturing control than conventional manufacturing control, and it can be said that it is at a highly completed level. There is no current situation. In particular, when the channel length is 6 μm or less, the influence of the pattern size generated with a decrease in the film thickness of the resist pattern is large, and this tendency becomes remarkable.

The present invention has been made in view of the current situation, and not only avoids the troubles in forming contacts common to the conventional 5-mask process and 4-mask process, but also adopts a halftone exposure technique with a large manufacturing margin. Thus, the manufacturing process can be reduced. In addition, it is clear that there is a need to pursue further reductions in the number of manufacturing processes in order to reduce the price of liquid crystal panels and respond to increasing demand. The value of the present invention is further enhanced by providing a technique for simplifying the process or reducing the cost.

In the present invention, first, the halftone exposure technique is applied to a scanning line forming process in which pattern accuracy management is easy and a contact forming process for electrical connection to the scanning line, thereby realizing a reduction in manufacturing process. Yes. Next, in order to effectively passivate only the source / drain wiring, an anodizing technique for forming an insulating layer on the surface of the source / drain wiring made of aluminum disclosed in JP-A-2-216129, which is a prior art, and It is intended to realize process rationalization and low temperature by fusing. Furthermore, a streamlined pixel electrode forming process disclosed in Japanese Patent Application Laid-Open No. 8-136951, which is a prior art, is adopted in conformity with the present invention. In order to further reduce the process, the halftone exposure technique is applied to the formation of the anodic oxide layer of the source / drain wiring, thereby rationalizing the electrode terminal protective layer forming process.
JP-A-2-216129 JP-A-8-136951

The liquid crystal display device according to claim 1 is connected to at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a drain wiring on one main surface. A first transparent insulating substrate in which unit pixel elements each having a pixel electrode are arranged in a two-dimensional matrix; and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In a liquid crystal display device in which liquid crystal is filled in between,
A scanning line comprising at least one first metal layer on one main surface of the first transparent insulating substrate and having an insulating layer on its side surface is formed,
One or more gate insulating layers and a first semiconductor layer not containing impurities are formed on the gate electrode,
A protective insulating layer is formed on the first semiconductor layer so as to be narrower than the gate electrode;
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display portion, and a part of the scanning line is exposed in the opening,
One or more anodizable metal layers including a second semiconductor layer containing impurities and a refractory metal layer on a part of the protective insulating layer, on the first semiconductor layer, and on the first transparent insulating substrate. The electrode terminal of the scanning line is formed in the same manner including the source (signal line) / drain wiring composed of the laminate and the first semiconductor layer around the opening,
A transparent conductive pixel electrode is formed on a part of the drain wiring and the first transparent insulating substrate, and a transparent conductive electrode terminal is formed on the signal line in a region outside the image display unit,
An anodic oxide layer is formed on the surface of the source / drain wiring except for a region overlapping the pixel electrode of the drain wiring and an electrode terminal region of the signal line.

With this configuration, the gate insulating layer is formed with the same pattern width as the scanning line, and an insulating layer different from the gate insulating layer is provided on the side surface of the scanning line, so that the scanning line and the signal line can intersect. . This is a structural feature common to the liquid crystal display device of the present invention. Further, a protective insulating layer is formed on the channel between the source and drain to protect the channel, and tantalum pentoxide (Ta2O5) or aluminum oxide (Al2O3) which is an insulating anodic oxide layer is formed on the surface of the signal line and the drain wiring. ) To provide a passivation function, it is not necessary to deposit a passivation insulating layer on the entire surface of the glass substrate, and the heat resistance of the insulated gate transistor does not become a problem. Thus, a TN liquid crystal display device having transparent conductive electrode terminals is obtained.

The liquid crystal display device according to claim 2 is also similar.
A scanning line comprising a laminate of a transparent conductive layer and a first metal layer on at least one main surface of the first transparent insulating substrate and having an insulating layer on its side surface; a transparent conductive pixel electrode; and a signal line Electrode terminals are formed,
One or more gate insulating layers and a first semiconductor layer not containing impurities are formed on the gate electrode,
A protective insulating layer is formed on the first semiconductor layer so as to be narrower than the gate electrode;
The gate insulating layer on the scanning line is removed in a region outside the image display portion, and the transparent conductive layer that becomes the electrode terminal of the scanning line is exposed,
A second semiconductor layer containing impurities on one part of the protective insulating layer, a first semiconductor layer, a first transparent insulating substrate, and a part of an electrode terminal of the signal line, and one or more heat resistant layers A source wiring (signal line) including a metal layer and a second metal layer, a part of the protective insulating layer, a first semiconductor layer, a first transparent insulating substrate, and the picture A drain wiring is also formed on a part of the elementary electrode,
A photosensitive organic insulating layer is formed on the source / drain wiring.

With this configuration, a transparent conductive pixel electrode is formed at the same time as the scanning line, so it is automatically formed on the glass substrate. However, a protective insulating layer is formed on the channel between the source and drain to protect the channel. At the same time, a photosensitive organic insulating layer is formed on the surface of the source / drain wiring to provide a passivation function. It will not be a problem. Thus, a TN liquid crystal display device having transparent conductive electrode terminals is obtained.

The liquid crystal display device according to claim 3 is
A scanning line comprising a transparent conductive layer and a first metal layer on at least one main surface of the first transparent insulating substrate and having an insulating layer on its side surface and a transparent conductive pixel electrode are formed,
One or more gate insulating layers and a first semiconductor layer not containing impurities are formed on the gate electrode,
A protective insulating layer is formed on the first semiconductor layer so as to be narrower than the gate electrode;
The gate insulating layer on the scanning line is removed in a region outside the image display portion, and the transparent conductive layer that is a part of the scanning line is exposed,
A second semiconductor layer including impurities on a part of the protective insulating layer, a first semiconductor layer, and a first transparent insulating substrate; and one or more second metal layers including a refractory metal layer; And a source wiring (signal line) made of a laminate of the same, a drain wiring on a part of the protective insulating layer, on the first semiconductor layer, on the first transparent insulating substrate, and on a part of the pixel electrode, In addition, a scanning line electrode terminal including a part of the scanning line, and a signal line electrode terminal formed of a part of the signal line in a region outside the image display unit are formed,
A photosensitive organic insulating layer is formed on the signal line except on the electrode terminal of the signal line.

With this configuration, transparent conductive pixel electrodes are formed at the same time as the scanning lines, so they are automatically formed on the glass substrate. However, a protective insulating layer is formed on the channel between the source and drain to protect the channel. In addition, a photosensitive organic insulating layer is formed on the surface of the signal line (source wiring) to provide a passivation function, and the same effect as the liquid crystal display device according to claim 2 can be obtained. Thus, a TN type liquid crystal display device having the same metallic electrode terminal as the signal line is obtained.

The liquid crystal display device according to claim 4 is also similar.
A scanning line comprising a transparent conductive layer and a first metal layer on at least one main surface of the first transparent insulating substrate and having an insulating layer on its side surface and a transparent conductive pixel electrode are formed,
One or more gate insulating layers and a first semiconductor layer not containing impurities are formed on the gate electrode,
A protective insulating layer is formed on the first semiconductor layer so as to be narrower than the gate electrode;
The gate insulating layer on the scanning line is removed in a region outside the image display portion, and the transparent conductive layer that is a part of the scanning line is exposed,
One or more anodizable metal layers including a second semiconductor layer containing impurities and a refractory metal layer on a part of the protective insulating layer, on the first semiconductor layer, and on the first transparent insulating substrate. And a source wiring (signal line) made of a laminated layer, and a drain wiring on a part of the protective insulating layer, on the first semiconductor layer, on the first transparent insulating substrate, and on a part of the pixel electrode. And an electrode terminal of the scanning line that includes a part of the scanning line, and an electrode terminal of the signal line that is a part of the signal line in a region outside the image display unit,
An anodized layer is formed on the source / drain wiring except for the electrode terminal of the signal line.

With this configuration, transparent conductive pixel electrodes are formed at the same time as the scanning lines, so they are automatically formed on the glass substrate. However, a protective insulating layer is formed on the channel between the source and drain to protect the channel. The tantalum pentoxide (Ta2O5) or aluminum oxide (Al2O3) which is an insulating anodic oxide layer is formed on the surface of the signal line and the drain wiring to provide a passivation function, and the liquid crystal according to claim 1 The same effect as the display device can be obtained. Thus, a TN type liquid crystal display device having the same metallic electrode terminal as the signal line is obtained.

6. The liquid crystal display device according to claim 5, wherein at least one insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source line, and the insulated gate transistor are provided on one main surface. A first transparent insulating substrate in which unit picture elements having a picture element electrode connected to a drain and a counter electrode formed at a predetermined distance from the picture element electrode are arranged in a two-dimensional matrix; In a liquid crystal display device in which liquid crystal is filled between the second transparent insulating substrate or the color filter facing the first transparent insulating substrate,
A scanning line and a counter electrode, each of which is composed of at least one first metal layer on one main surface of the first transparent insulating substrate and has an insulating layer on its side surface, are formed.
One or more gate insulating layers are formed on the counter electrode, and one or more gate insulating layers and a first semiconductor layer containing no impurities are formed on the gate electrode,
A protective insulating layer is formed on the first semiconductor layer so as to be narrower than the gate electrode;
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display portion, and a part of the scanning line is exposed in the opening,
One or more second metal layers including a second semiconductor layer including impurities and a refractory metal layer on a part of the protective insulating layer, on the first semiconductor layer, and on the first transparent insulating substrate; Source wiring (signal line) / drain wiring (picture element electrode) made of a laminate of the above, an electrode terminal of the scanning line including the first semiconductor layer around the opening, and a signal line in a region outside the image display unit The electrode terminal of the signal line consisting of a part of
A photosensitive organic insulating layer is formed on the signal line except on the electrode terminal of the signal line.

With this configuration, the pixel electrode and the counter electrode are formed on the glass substrate, and a protective insulating layer is formed on the channel between the source and drain to protect the channel, and a photosensitive organic insulating layer is formed on the surface of the signal line. Since it is formed to provide a passivation function and a gate insulating layer is formed on the counter electrode, the same effect as the liquid crystal display device according to claim 2 can be obtained. Thus, an IPS liquid crystal display device having the same metallic electrode terminal as the signal line can be obtained.

The liquid crystal display device according to claim 6 is also similar.
A scanning line and a counter electrode, each of which is composed of at least one first metal layer on one main surface of the first transparent insulating substrate and has an insulating layer on its side surface, are formed.
One or more gate insulating layers are formed on the counter electrode, and one or more gate insulating layers and a first semiconductor layer containing no impurities are formed on the gate electrode,
A protective insulating layer is formed on the first semiconductor layer so as to be narrower than the gate electrode;
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display portion, and a part of the scanning line is exposed in the opening,
One or more anodizable metal layers including a second semiconductor layer containing impurities and a refractory metal layer on a part of the protective insulating layer, on the first semiconductor layer, and on the first transparent insulating substrate. Source wiring (signal line) / drain wiring (picture element electrode) made up of a plurality of layers, and the electrode terminal of the scanning line including the first semiconductor layer around the opening, and the signal outside the image display section. An electrode terminal of a signal line made up of a part of the line is formed,
An anodized layer is formed on the surface of the source / drain wiring except on the electrode terminal of the signal line.

With this configuration, the pixel electrode and the counter electrode are formed on the glass substrate, and a protective insulating layer is formed on the channel between the source and drain to protect the channel and the surface of the signal line and drain wiring is insulative. 2. The liquid crystal display device according to claim 1, wherein tantalum pentoxide (Ta 2 O 5) or aluminum oxide (Al 2 O 3) as an anodized layer is formed to provide a passivation function, and a gate insulating layer is formed on the counter electrode. The same effect can be obtained. Thus, an IPS liquid crystal display device having the same metallic electrode terminal as the signal line can be obtained.

The liquid crystal display device according to claim 7 is connected to at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a drain wiring on one main surface. A first transparent insulating substrate in which unit pixel elements each having a pixel electrode are arranged in a two-dimensional matrix; and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In a liquid crystal display device in which liquid crystal is filled in between,
A scanning line comprising a transparent conductive layer and a first metal layer on at least one main surface of the first transparent insulating substrate and having an insulating layer on its side surface and a transparent conductive pixel electrode are formed,
One or more gate insulating layers and a first semiconductor layer not containing impurities are formed on the gate electrode,
A second semiconductor layer containing a pair of impurities to be a source / drain of an insulated gate transistor is formed on the first semiconductor layer,
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display portion, and the transparent conductive layer that is a part of the scanning line is exposed in the opening,
A source wiring (signal line) made of one or more second metal layers including a refractory metal layer on the second semiconductor layer and the first transparent insulating substrate; and on the second semiconductor layer; The drain wiring on the first transparent insulating substrate and a part of the pixel electrode, the electrode terminal of the scanning line including the opening, and the signal line in a region outside the image display unit. The electrode terminal of the signal line is formed,
A passivation insulating layer having openings on the pixel electrodes and on the scanning line and signal line electrode terminals is formed on the first transparent insulating substrate.

With this configuration, the transparent conductive pixel electrode is formed simultaneously with the scanning line, so it is automatically formed on the glass substrate. However, a conventional passivation insulating layer is formed on the active substrate, and an insulated gate transistor is formed. Protects the channel and source / drain wiring. In addition, since the contact formation process to the scanning line and the opening formation process to the passivation insulating layer are independent, there is no risk of the contact becoming unstable unlike the conventional 5-mask process, and the same as the signal line. An IPS liquid crystal display device having metallic electrode terminals can be obtained.

The liquid crystal display device according to claim 8 is
A scanning line comprising a transparent conductive layer and a first metal layer on at least one main surface of the first transparent insulating substrate and having an insulating layer on its side surface and a transparent conductive pixel electrode are formed,
One or more gate insulating layers and a first semiconductor layer not containing impurities are formed on the gate electrode,
A second semiconductor layer containing a pair of impurities to be a source / drain of an insulated gate transistor is formed on the first semiconductor layer,
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display portion, and the transparent conductive layer that is a part of the scanning line is exposed in the opening,
On the second semiconductor layer and on the first transparent insulating substrate, a source wiring (signal line) made of one or more anodizable metal layers including a refractory metal layer, and on the second semiconductor layer And a drain wiring on the first transparent insulating substrate and a part of the pixel electrode, an electrode terminal of the scanning line including the opening, and a part of the signal line in the region outside the image display unit An electrode terminal of a signal line is formed,
An anodic oxide layer is formed on the surface of the source / drain wiring except for the electrode terminal of the signal line,
A silicon oxide layer is formed on the first semiconductor layer between the source / drain wirings.

With this configuration, transparent conductive pixel electrodes are formed at the same time as the scanning lines, so they are automatically formed on the glass substrate, but a silicon oxide layer is formed on the channel between the source and drain to form an insulated gate type. The transistor channel is protected, and an insulating anodic oxide layer, tantalum pentoxide (Ta2O5) or aluminum oxide (Al2O3), is formed on the surface of the signal line and drain wiring to provide a passivation function. The same effects as those of the described TN type liquid crystal display device can be obtained.

The liquid crystal display device according to claim 9 is the same,
A scanning line comprising a transparent conductive layer and a first metal layer on at least one main surface of the first transparent insulating substrate and having an insulating layer on its side surface and a transparent conductive pixel electrode are formed,
One or more gate insulating layers and a first semiconductor layer not containing impurities are formed on the gate electrode,
A second semiconductor layer containing a pair of impurities to be a source / drain of an insulated gate transistor is formed on the first semiconductor layer,
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display portion, and the transparent conductive layer that is a part of the scanning line is exposed in the opening,
A source wiring (signal line) made of one or more second metal layers including a refractory metal layer on the second semiconductor layer and the first transparent insulating substrate; and on the second semiconductor layer; A drain wiring on the first transparent insulating substrate and a part of the pixel electrode, an electrode terminal of the scanning line including the first and second semiconductor layers around the opening, and an image display unit The electrode terminal of the signal line consisting of a part of the signal line is formed in the outer region,
A passivation insulating layer having openings on the pixel electrodes and on the scanning line and signal line electrode terminals is formed on the first transparent insulating substrate.

With this configuration, the transparent conductive pixel electrode is formed simultaneously with the scanning line, so it is automatically formed on the glass substrate. However, a conventional passivation insulating layer is formed on the active substrate, and an insulated gate transistor is formed. Protects the channel and source / drain wiring. In addition, since the contact formation process to the scanning line and the opening formation process to the passivation insulating layer are independent, there is no risk of contact instability unlike the conventional 5-mask process, and the same as the signal line. A TN liquid crystal display device having metallic electrode terminals can be obtained. However, when the channel length is shortened, strict manufacturing control is required to achieve a high yield, and it is necessary to pay attention to the reduction of the film thickness of the pixel electrode.

The liquid crystal display device according to claim 10 is the same,
At least a scanning line comprising a transparent conductive layer and a first metal layer on one main surface of the first transparent insulating substrate and having an insulating layer on its side surface and the first metal layer as part of the peripheral portion Laminated transparent conductive pixel electrodes are formed,
One or more gate insulating layers and a first semiconductor layer not containing impurities are formed on the gate electrode,
A second semiconductor layer containing a pair of impurities to be a source / drain of an insulated gate transistor is formed on the first semiconductor layer,
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display portion, and the transparent conductive layer that is a part of the scanning line is exposed in the opening,
A source wiring (signal line) made of one or more second metal layers including a refractory metal layer on the second semiconductor layer and the first transparent insulating substrate; and on the second semiconductor layer; Similarly, the drain wiring on the first transparent insulating substrate and a part of the first metal layer in the peripheral portion of the pixel electrode, and the first and second semiconductor layers in the periphery of the opening portion are also scanned. A line electrode terminal and a signal line electrode terminal formed of a part of the signal line in a region outside the image display unit,
A passivation insulating layer having openings on the pixel electrodes and on the scanning line and signal line electrode terminals is formed on the first transparent insulating substrate.

With this configuration, the transparent conductive pixel electrode is formed simultaneously with the scanning line, so it is automatically formed on the glass substrate. However, a conventional passivation insulating layer is formed on the active substrate, and an insulated gate transistor is formed. Protects the channel and source / drain wiring. In addition, since the contact formation process to the scanning line and the opening formation process to the passivation insulating layer are independent, there is no risk of contact instability unlike the conventional 5-mask process, and the same as the signal line. A TN liquid crystal display device having metallic electrode terminals can be obtained. However, when the channel length is shortened, strict manufacturing control is necessary to achieve a high yield, but the device is easy to manufacture because the film loss of the pixel electrode is less likely to occur.

The liquid crystal display device according to claim 11 includes at least an insulated gate transistor on one main surface, a scanning line also serving as a gate electrode of the insulated gate transistor and a signal line also serving as a source wiring, and the insulated gate transistor. A first transparent insulating substrate in which unit picture elements having a picture element electrode connected to a drain and a counter electrode formed at a predetermined distance from the picture element electrode are arranged in a two-dimensional matrix; In a liquid crystal display device in which liquid crystal is filled between the second transparent insulating substrate or the color filter facing the first transparent insulating substrate,
A scanning line and a counter electrode, each of which is composed of at least one first metal layer on one main surface of the first transparent insulating substrate and has an insulating layer on its side surface, are formed.
One or more gate insulating layers are formed on the counter electrode, and one or more gate insulating layers and a first semiconductor layer containing no impurities are formed on the gate electrode,
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display portion, and a part of the scanning line is exposed in the opening,
A second semiconductor layer containing a pair of impurities to be a source / drain of an insulated gate transistor is formed on the first semiconductor layer,
A source wiring (signal line) / drain wiring (picture element electrode) composed of one or more second metal layers including a refractory metal layer on the second semiconductor layer and the first transparent insulating substrate; Similarly, the scanning line electrode terminal including the first and second semiconductor layers around the opening and the signal line electrode terminal formed of a part of the signal line in the region outside the image display unit are formed.
A passivation insulating layer having openings on the electrode terminals of the scanning lines and signal lines is formed on the first transparent insulating substrate.

With this configuration, the pixel electrode and the counter electrode are formed on the glass substrate, and a conventional passivation insulating layer is formed on the active substrate to protect the channel and source / drain wiring of the insulated gate transistor. In addition, since the contact formation process to the scanning line and the opening formation process to the passivation insulating layer are independent, there is no risk of the contact becoming unstable unlike the conventional 5-mask process, and the same as the signal line. An IPS liquid crystal display device having metallic electrode terminals can be obtained. However, when the channel length is shortened, strict manufacturing management is required to achieve a high yield.

The liquid crystal display device according to claim 12 is
A scanning line and a counter electrode, each of which is composed of at least one first metal layer on one main surface of the first transparent insulating substrate and has an insulating layer on its side surface, are formed.
One or more gate insulating layers are formed on the counter electrode, and one or more gate insulating layers and a first semiconductor layer containing no impurities are formed on the gate electrode,
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display part, and a part of the scanning line is exposed
A second semiconductor layer containing a pair of impurities to be a source / drain of an insulated gate transistor is formed on the first semiconductor layer,
A source wiring (signal line) / drain wiring (picture element electrode) made of one or more anodizable metal layers including a refractory metal layer on the second semiconductor layer and the first transparent insulating substrate; In addition, an electrode terminal of the scanning line including the first and second semiconductor layers around the opening is formed, and an electrode terminal of the signal line including a part of the signal line is formed in a region outside the image display unit,
An anodic oxide layer is formed on the surface of the source / drain wiring except for the electrode terminal of the signal line,
A silicon oxide layer is formed on the first semiconductor layer between the source / drain wirings.

With this configuration, the pixel electrode and the counter electrode are formed on the glass substrate, and a silicon oxide layer is formed on the channel between the source and drain to protect the channel of the insulated gate transistor and the surface of the signal line and drain wiring In claim 1, tantalum pentoxide (Ta2O5) or aluminum oxide (Al2O3), which is an insulating anodic oxide layer, is formed to provide a passivation function, and a gate insulating layer is formed on the counter electrode. The same effect as the liquid crystal display device described can be obtained. Thus, an IPS liquid crystal display device having the same metallic electrode terminal as the signal line can be obtained.

13. The liquid crystal image display device according to claim 13, wherein the insulating layer formed on the side surface of the scanning line is an organic insulating layer. 4. A liquid crystal display device according to claim 4, claim 6, claim 7, claim 8, claim 9, claim 10, claim 11 and claim 12. With this configuration, an organic insulating layer can be formed on the side surface of the scan line by electrodeposition regardless of the material and configuration of the scan line, and the scan line forming process and the contact forming process can be performed using halftone exposure technology. It becomes possible to process continuously with one photomask.

The liquid crystal image display device according to claim 14, wherein the first metal layer is made of an anodizable metal layer, and the insulating layer formed on the side surface of the scanning line is an anodized layer. A liquid crystal display device according to claim 5, claim 6, claim 11 and claim 12. With this configuration, an anodized layer can be formed by anodic oxidation on the side surface of the scanning line, and the scanning line forming process and the contact forming process are successively processed with a single photomask using a halftone exposure technique. It becomes possible to do.

A fifteenth aspect is the method of manufacturing the liquid crystal display device according to the first aspect,
At least one metal layer, one or more gate insulating layers, a first amorphous silicon layer containing no impurities, and a protective insulating layer are sequentially deposited on at least one main surface of the first transparent insulating substrate. Process,
A step of forming a photosensitive resin pattern corresponding to the scanning line and having a film thickness on the contact formation region of the scanning line that is thinner than other regions in a region outside the image display unit;
Sequentially etching the protective insulating layer, the first amorphous silicon layer, the gate insulating layer, and the first metal layer using the photosensitive resin pattern as a mask;
Reducing the thickness of the photosensitive resin pattern to expose a protective insulating layer on the contact formation region; and
Forming an insulating layer on the side surface of the scanning line;
Etching the protective insulating layer, the first amorphous silicon layer, and the gate insulating layer in the contact region using the photosensitive resin pattern having the reduced thickness as a mask to expose a part of the scanning line; ,
Selectively forming a protective insulating layer narrower than the gate electrode on the gate electrode to expose the first amorphous silicon layer;
Depositing a second amorphous silicon layer containing impurities on the entire surface of the first transparent insulating substrate;
After depositing one or more anodizable metal layers including a refractory metal layer, including source (signal lines) / drain wirings and part of the scanning lines so as to partially overlap the protective insulating layer Forming a scanning line electrode terminal;
A transparent conductive pixel electrode on the first transparent insulating substrate and a part of the drain wiring, a transparent conductive electrode terminal on the signal line in a region outside the image display unit, and an electrode terminal of the scanning line Forming a transparent conductive electrode terminal thereon;
A step of anodizing the source / drain wiring while protecting the transparent conductive pixel electrode and the transparent conductive electrode terminal using the photosensitive resin pattern used for the selective pattern formation of the pixel electrode and the electrode terminal as a mask It is characterized by having.

With this configuration, the scanning line forming process and the contact forming process necessary for electrical connection to the scanning line can be processed using a single photomask, and the number of photolithography steps can be reduced. Moreover, the contact is formed in a self-aligned manner with the scanning line, and an insulating layer different from the gate insulating layer is provided on the side surface of the scanning line, so that the scanning line and the signal line can intersect. This is a manufacturing characteristic common to the liquid crystal display device of the present invention. In addition, a protective insulating layer is formed on the channel between the source and drain to protect the channel and anodize the source / drain wiring when forming the pixel electrode, thereby eliminating the need for forming a passivation insulating layer. As a result of the reduction, a TN liquid crystal display device can be manufactured using four photomasks.

Claim 16 is a method of manufacturing a liquid crystal display device according to claim 2,
A transparent conductive layer, a first metal layer, one or more gate insulating layers, a first amorphous silicon layer not containing impurities, and a protective insulating layer are sequentially formed on at least one main surface of the first transparent insulating substrate. A process of depositing;
Corresponding to the electrode terminals of the scanning line and the pixel electrode and the scanning line and the signal line, the film thickness on the electrode terminal forming area of the scanning line and the signal line in the area outside the image display part and the image display part is larger than that in the other areas Forming a thin photosensitive resin pattern,
Sequentially etching the protective insulating layer, the first amorphous silicon layer, the gate insulating layer, the first metal layer, and the transparent conductive layer using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose a protective insulating layer on the pixel electrode and on the electrode terminal formation region of the scanning line and the signal line;
Forming an insulating layer on the side surface of the scanning line;
A protective insulating layer, a first amorphous silicon layer, a gate insulating layer, and a first insulating layer on the pixel electrode, on the electrode terminal region of the scanning line and the signal line, using the reduced photosensitive resin pattern as a mask. Etching the metal layer and exposing the transparent conductive pixel electrode, the electrode terminal of the scanning line, and the electrode terminal of the signal line,
Selectively forming a protective insulating layer narrower than the gate electrode on the gate electrode to expose the first amorphous silicon layer;
Depositing a second amorphous silicon layer containing impurities on the entire surface of the first transparent insulating substrate;
After depositing one or more second metal layers including a heat-resistant metal layer, a photosensitive organic insulating layer is formed on the surface including a part of the electrode terminal of the signal line so as to partially overlap the protective insulating layer. Similar to the source wiring (signal line), the method includes a step of forming a drain wiring including a part of the pixel electrode.

With this configuration, the number of photo-etching steps for processing the pixel electrodes and the scanning lines using one photomask is reduced, and the scanning line forming step and the contact forming step are processed using one photomask. Simultaneously reduce the number of photo-etching processes. In addition, a protective insulating layer is formed on the channel between the source and drain to protect the channel, and at the time of forming the source / drain wiring, the photosensitive organic insulating layer is selectively left only on the source / drain wiring for passivation insulation. As a result of reducing the number of manufacturing steps that do not require layer formation, a TN liquid crystal display device can be manufactured using three photomasks.

Claim 17 is a method of manufacturing a liquid crystal display device according to claim 3,
A transparent conductive layer, a first metal layer, one or more gate insulating layers, a first amorphous silicon layer not containing impurities, and a protective insulating layer are sequentially formed on at least one main surface of the first transparent insulating substrate. A process of depositing;
A photosensitive resin pattern corresponding to the scanning line, the pixel electrode, and the electrode terminal of the scanning line, the film thickness on the electrode terminal forming area of the scanning line being thinner on the pixel electrode and the area outside the image display area than other areas. Forming a step;
Sequentially etching the protective insulating layer, the first amorphous silicon layer, the gate insulating layer, the first metal layer, and the transparent conductive layer using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose a protective insulating layer on the pixel electrode and on the electrode terminal formation region of the scanning line;
Forming an insulating layer on the side surface of the scanning line;
The protective insulating layer, the first amorphous silicon layer, the gate insulating layer, and the first metal layer on the picture element electrode and on the electrode terminal region of the scanning line using the photosensitive resin pattern having the reduced thickness as a mask. Etching the transparent conductive pixel electrode and exposing a part of the scanning line,
Selectively forming a protective insulating layer narrower than the gate electrode on the gate electrode to expose the first amorphous silicon layer;
Depositing a second amorphous silicon layer containing impurities on the entire surface of the first transparent insulating substrate;
After the deposition of one or more second metal layers including the refractory metal layer, the protective insulating layer partially overlaps the source wiring (signal line), and the drain wiring also includes a part of the pixel electrode; Corresponding to the electrode terminal of the scanning line including a part of the scanning line and the electrode terminal of the signal line consisting of a part of the signal line in the region outside the image display portion, the film thickness on the signal line is larger than that of the other region. Forming a thick photosensitive organic insulating layer pattern;
Using the photosensitive organic insulating layer pattern as a mask, the second metal layer, the second amorphous silicon layer, and the first amorphous silicon layer are selectively removed to form source / drain wirings, scanning lines, and signals. Forming a wire electrode terminal;
The method includes reducing the film thickness of the photosensitive organic insulating layer pattern to expose the electrode terminals of the drain wiring, the scanning line, and the signal line.

With this configuration, the number of photo-etching steps for processing the pixel electrodes and the scanning lines using one photomask is reduced, and the scanning line forming step and the contact forming step are processed using one photomask. Simultaneously reduce the number of photo-etching processes. In addition, a protective insulating layer is formed on the channel between the source and drain to protect the channel, and at the time of forming the source / drain wiring, a photosensitive organic insulating layer is selectively left only on the signal line using a halftone exposure technique. As a result, the number of manufacturing steps that do not require the formation of a passivation insulating layer is reduced. As a result, a TN liquid crystal display device can be manufactured using three photomasks.

Claim 18 is a method of manufacturing a liquid crystal display device according to claim 4,
A transparent conductive layer, a first metal layer, one or more gate insulating layers, a first amorphous silicon layer not containing impurities, and a protective insulating layer are sequentially formed on at least one main surface of the first transparent insulating substrate. A process of depositing;
A photosensitive resin pattern corresponding to the scanning line, the pixel electrode, and the electrode terminal of the scanning line, the film thickness on the electrode terminal forming area of the scanning line being thinner on the pixel electrode and the area outside the image display area than other areas. Forming a step;
Sequentially etching the protective insulating layer, the first amorphous silicon layer, the gate insulating layer, the first metal layer, and the transparent conductive layer using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose a protective insulating layer on the pixel electrode and on the electrode terminal formation region of the scanning line;
Forming an insulating layer on the side surface of the scanning line;
The protective insulating layer, the first amorphous silicon layer, the gate insulating layer, and the first metal layer on the picture element electrode and on the electrode terminal region of the scanning line using the photosensitive resin pattern having the reduced thickness as a mask. Etching the transparent conductive pixel electrode and exposing a part of the scanning line,
Selectively forming a protective insulating layer narrower than the gate electrode on the gate electrode to expose the first amorphous silicon layer;
Depositing a second amorphous silicon layer containing impurities on the entire surface of the first transparent insulating substrate;
After depositing one or more anodizable metal layers including a refractory metal layer, the protective insulating layer partially overlaps the source wiring (signal line), the drain wiring also including a pixel electrode, and the scanning Corresponding to the electrode terminal of the scanning line including a part of the line and the electrode terminal of the signal line consisting of a part of the signal line in the region outside the image display portion, the film thickness on the electrode terminal of the scanning line and the signal line is Forming a photosensitive resin pattern thicker than other regions;
Using the photosensitive resin pattern as a mask, the anodizable metal layer, the second amorphous silicon layer, and the first amorphous silicon layer are selectively removed to form source / drain wirings, scanning lines, and signal lines. Forming an electrode terminal of
Reducing the film thickness of the photosensitive resin pattern to expose the source / drain wiring; and
The method includes a step of anodizing the source / drain wiring while protecting the electrode terminal.

With this configuration, the number of photo-etching steps for processing the pixel electrodes and the scanning lines using one photomask is reduced, and the scanning line forming step and the contact forming step are processed using one photomask. Simultaneously reduce the number of photo-etching processes. A protective insulating layer is formed on the channel between the source and drain to protect the channel, and a half-tone exposure technique is used to selectively form an anodized layer on the source and drain wiring when forming the source and drain wiring. As a result, the number of manufacturing steps that do not require the formation of a passivation insulating layer is reduced. As a result, a TN liquid crystal display device can be manufactured using three photomasks.

Claim 19 is a method of manufacturing a liquid crystal display device according to claim 5,
At least one first metal layer, one or more gate insulating layers, a first amorphous silicon layer not containing impurities, and a protective insulating layer are sequentially formed on at least one main surface of the first transparent insulating substrate. A process of depositing;
A step of forming a photosensitive resin pattern corresponding to the scanning line and the counter electrode and having a film thickness on the contact formation region of the scanning line that is thinner than other regions in the region outside the image display unit;
Sequentially etching the protective insulating layer, the first amorphous silicon layer, the gate insulating layer, and the first metal layer using the photosensitive resin pattern as a mask;
Reducing the thickness of the photosensitive resin pattern to expose a protective insulating layer on the contact formation region; and
Forming an insulating layer on the side surfaces of the scanning line and the counter electrode;
Etching the protective insulating layer, the first amorphous silicon layer, and the gate insulating layer in the contact region using the photosensitive resin pattern having the reduced thickness as a mask to expose a part of the scanning line; ,
Selectively forming a protective insulating layer narrower than the gate electrode on the gate electrode to expose the first amorphous silicon layer;
Depositing a second amorphous silicon layer containing impurities on the entire surface of the first transparent insulating substrate;
After depositing one or more second metal layers including a refractory metal layer, the protective insulating layer partially overlaps the source wiring (signal line) / drain wiring (pixel electrode), and part of the scanning line A photosensitive organic insulating layer corresponding to the electrode terminal of the scanning line and the electrode terminal of the signal line formed of a part of the signal line in the region outside the image display portion, and having a thicker film thickness on the signal line than the other region Forming a pattern;
Using the photosensitive organic insulating layer pattern as a mask, the second metal layer, the second amorphous silicon layer, and the first amorphous silicon layer are selectively removed to form source / drain wirings, scanning lines, and signals. Forming a wire electrode terminal;
The method includes reducing the film thickness of the photosensitive organic insulating layer pattern to expose the electrode terminals of the drain wiring, the scanning line, and the signal line.

With this configuration, it is possible to reduce the number of photolithography steps in which the scanning line and counter electrode forming process and the contact forming process are performed using one photomask. Further, a protective insulating layer is formed on the channel between the source and drain to protect the channel, and at the time of forming the source / drain wiring, a photosensitive organic insulating layer is selectively left only on the signal line using a halftone exposure technique. As a result, the number of manufacturing steps that do not require the formation of a passivation insulating layer is reduced. As a result, an IPS liquid crystal display device can be manufactured using three photomasks.

Claim 20 is a method of manufacturing a liquid crystal display device according to claim 6,
At least one first metal layer, one or more gate insulating layers, a first amorphous silicon layer not containing impurities, and a protective insulating layer are sequentially formed on at least one main surface of the first transparent insulating substrate. A process of depositing;
A step of forming a photosensitive resin pattern corresponding to the scanning line and the counter electrode and having a film thickness on the contact formation region of the scanning line that is thinner than other regions in the region outside the image display unit;
Sequentially etching the protective insulating layer, the first amorphous silicon layer, the gate insulating layer, and the first metal layer using the photosensitive resin pattern as a mask;
Reducing the thickness of the photosensitive resin pattern to expose a protective insulating layer on the contact formation region; and
Forming an insulating layer on the side surfaces of the scanning line and the counter electrode;
Etching the protective insulating layer, the first amorphous silicon layer, and the gate insulating layer in the contact region using the photosensitive resin pattern having the reduced thickness as a mask to expose a part of the scanning line; ,
Selectively forming a protective insulating layer narrower than the gate electrode on the gate electrode to expose the first amorphous silicon layer;
Depositing a second amorphous silicon layer containing impurities on the entire surface of the first transparent insulating substrate;
After depositing one or more anodizable metal layers including a refractory metal layer, the protective insulating layer partially overlaps the source wiring (signal line) / drain wiring (picture element electrode) and one of the scanning lines. Forming a photosensitive resin pattern including a portion corresponding to the electrode terminal of the scanning line and the electrode terminal of the signal line formed of a part of the signal line, the film thickness on the electrode terminal being thicker than other regions; ,
Using the photosensitive resin pattern as a mask, the anodizable metal layer, the second amorphous silicon layer, and the first amorphous silicon layer are selectively removed to form source / drain wirings, scanning lines, and signal lines. Forming an electrode terminal of
Reducing the film thickness of the photosensitive resin pattern to expose the source / drain wiring; and
The method includes a step of anodizing the source / drain wiring while protecting the electrode terminal.

With this configuration, it is possible to reduce the number of photolithography steps in which the scanning line and counter electrode forming process and the contact forming process are performed using one photomask. A protective insulating layer is formed on the channel between the source and drain to protect the channel, and a half-tone exposure technique is used to selectively form an anodized layer on the source and drain wiring when forming the source and drain wiring. As a result, the number of manufacturing steps that do not require the formation of a passivation insulating layer is reduced. As a result, an IPS liquid crystal display device can be manufactured using three photomasks.

Claim 21 is a method of manufacturing a liquid crystal display device according to claim 7,
A transparent conductive layer, a first metal layer, one or more gate insulating layers, a first amorphous silicon layer containing no impurities, and a second containing impurities on at least one main surface of the first transparent insulating substrate. Sequentially depositing the amorphous silicon layers;
A step of forming a photosensitive resin pattern corresponding to the scanning line and the pixel electrode, and having a film thickness on the contact formation region of the scanning line thinner than other regions on the pixel electrode and outside the image display unit;
Sequentially etching the second amorphous silicon layer, the first amorphous silicon layer, the gate insulating layer, the first metal layer, and the transparent conductive layer using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose a second amorphous silicon layer on the pixel electrode and the contact formation region;
Forming an insulating layer on the side surface of the scanning line;
Using the reduced photosensitive resin pattern as a mask, the second amorphous silicon layer, the first amorphous silicon layer, the gate insulating layer, and the first metal layer on the pixel electrode and in the contact region Etching the transparent conductive pixel electrode and exposing a part of the scanning line,
Selectively forming a second amorphous silicon layer and a first amorphous silicon layer on the gate electrode to expose the gate insulating layer on the scan line;
After depositing one or more second metal layers including the refractory metal layer, the gate electrode partially overlaps the source wiring (signal line), and also includes a part of the pixel electrode, the drain wiring, Selectively forming an electrode terminal of the scanning line including a part of the scanning line and an electrode terminal of the signal line formed of a part of the signal line;
Removing the second amorphous silicon layer between the source / drain wirings;
A passivation insulating layer having an opening on the pixel electrode and on the electrode terminals of the scanning line and the signal line is formed on the first transparent insulating substrate.

With this configuration, the number of photo-etching steps for processing the pixel electrodes and the scanning lines using one photomask is reduced, and the scanning line forming step and the contact forming step are processed using one photomask. Simultaneously reduce the number of photo-etching processes. Further, a conventional passivation insulating layer is formed on the active substrate to protect the channel and source / drain wiring of the insulated gate transistor. As a result, a TN liquid crystal display device can be manufactured using four photomasks.

Claim 22 is a method of manufacturing a liquid crystal display device according to claim 8,
A transparent conductive layer, a first metal layer, one or more gate insulating layers, a first amorphous silicon layer containing no impurities, and a second containing impurities on at least one main surface of the first transparent insulating substrate. Sequentially depositing the amorphous silicon layers;
A step of forming a photosensitive resin pattern corresponding to the scanning line and the pixel electrode, and having a film thickness on the contact formation region of the scanning line thinner than other regions on the pixel electrode and outside the image display unit;
Sequentially etching the second amorphous silicon layer, the first amorphous silicon layer, the gate insulating layer, the first metal layer, and the transparent conductive layer using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose a second amorphous silicon layer on the pixel electrode and the contact formation region;
Forming an insulating layer on the side surface of the scanning line;
Using the reduced photosensitive resin pattern as a mask, the second amorphous silicon layer, the first amorphous silicon layer, the gate insulating layer, and the first metal layer on the pixel electrode and in the contact region Etching the transparent conductive pixel electrode and exposing a part of the scanning line,
Selectively forming a second amorphous silicon layer and a first amorphous silicon layer on the gate electrode to expose the gate insulating layer on the scan line;
After depositing one or more anodizable metal layers including a refractory metal layer, the gate electrode partially overlaps the source wiring (signal line), and also includes a part of the pixel electrode, the drain wiring, Corresponding to the electrode terminal of the scanning line including a part of the scanning line and the electrode terminal of the signal line consisting of a part of the signal line in the region outside the image display portion, the film thickness on the electrode terminal of the scanning line and the signal line Forming a photosensitive resin pattern that is thicker than other regions;
Selectively removing an anodizable metal layer using the photosensitive resin pattern as a mask to form source / drain wirings, and electrode terminals for scanning lines and signal lines;
Reducing the film thickness of the photosensitive resin pattern to expose the source / drain wiring; and
The method includes a step of anodizing the amorphous silicon layer between the source / drain wiring and the source / drain wiring while protecting the electrode terminal.

With this configuration, the number of photo-etching steps for processing the pixel electrodes and the scanning lines using one photomask is reduced, and the scanning line forming step and the contact forming step are processed using one photomask. Simultaneously reduce the number of photo-etching processes. In addition, a silicon oxide layer is formed on the channel between the source and drain to protect the channel, and an anodized layer is selectively formed on the source and drain wiring using a halftone exposure technique when forming the source and drain wiring. As a result, the number of manufacturing steps that do not require the formation of a passivation insulating layer is reduced. As a result, a TN liquid crystal display device can be manufactured using three photomasks.

A twenty-third aspect is a method of manufacturing the liquid crystal display device according to the ninth aspect,
A transparent conductive layer, a first metal layer, one or more gate insulating layers, a first amorphous silicon layer containing no impurities, and a second containing impurities on at least one main surface of the first transparent insulating substrate. Sequentially depositing the amorphous silicon layers;
A step of forming a photosensitive resin pattern corresponding to the scanning line and the pixel electrode, and having a film thickness on the contact formation region of the scanning line thinner than other regions on the pixel electrode and outside the image display unit;
Sequentially etching the second amorphous silicon layer, the first amorphous silicon layer, the gate insulating layer, the first metal layer, and the transparent conductive layer using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose a second amorphous silicon layer on the pixel electrode and the contact formation region;
Forming an insulating layer on the side surface of the scanning line;
Using the reduced photosensitive resin pattern as a mask, the second amorphous silicon layer, the first amorphous silicon layer, the gate insulating layer, and the first metal layer on the pixel electrode and in the contact region Etching the transparent conductive pixel electrode and exposing a part of the scanning line,
After depositing one or more second metal layers including the refractory metal layer, the gate electrode partially overlaps the source wiring (signal line), and the drain wiring including the part of the pixel electrode and the source Corresponding to the channel region between the drain wiring, the electrode terminal of the scanning line including a part of the scanning line, and the electrode terminal of the signal line consisting of a part of the signal line, the film thickness of the channel region is other than Forming a photosensitive resin pattern thinner than the area;
Using the photosensitive resin pattern as a mask, the second metal layer, the second amorphous silicon layer, and the first amorphous silicon layer are selectively removed to form source / drain wirings, scanning lines, and signal lines. Selectively forming electrode terminals;
Reducing the film thickness of the photosensitive resin pattern to expose the second metal layer in the channel region;
Selectively removing the second metal layer and the second amorphous silicon layer in the channel region using the photosensitive resin pattern having a reduced thickness as a mask;
A passivation insulating layer having an opening on the pixel electrode and on the electrode terminals of the scanning line and the signal line is formed on the first transparent insulating substrate.

With this configuration, the number of photo-etching steps for processing the pixel electrodes and the scanning lines using one photomask is reduced, and the scanning line forming step and the contact forming step are processed using one photomask. Simultaneously reduce the number of photo-etching processes. As in the conventional four-mask process, the number of photo-etching steps in which the semiconductor layer formation (islandization) step and the source / drain wiring formation step are processed using the same photomask is also reduced. Yes. Further, a conventional passivation insulating layer is formed on the active substrate to protect the channel and source / drain wiring of the insulated gate transistor. As a result, a TN liquid crystal display device can be manufactured using three photomasks.

Claim 24 is a method of manufacturing a liquid crystal display device according to claim 10,
A transparent conductive layer, a first metal layer, one or more gate insulating layers, a first amorphous silicon layer containing no impurities, and a second containing impurities on at least one main surface of the first transparent insulating substrate. Sequentially depositing the amorphous silicon layers;
A step of forming a photosensitive resin pattern corresponding to the scanning line and the pixel electrode, and having a film thickness on the contact formation region of the scanning line thinner than other regions on the pixel electrode and outside the image display unit;
Sequentially etching the second amorphous silicon layer, the first amorphous silicon layer, the gate insulating layer, the first metal layer, and the transparent conductive layer using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose a second amorphous silicon layer on the pixel electrode and the contact formation region;
Forming an insulating layer on the side surface of the scanning line;
Etching the second amorphous silicon layer, the first amorphous silicon layer, and the gate insulating layer on the pixel electrode, the contact region using the photosensitive resin pattern with the reduced thickness as a mask. A step of exposing a part of a scanning line and a pixel electrode made of one metal layer;
After depositing one or more second metal layers including the refractory metal layer, the gate electrode partially overlaps the source wiring (signal line), and the drain wiring including the part of the pixel electrode and the source Corresponding to the channel region between the drain wiring, the electrode terminal of the scanning line including a part of the scanning line, and the electrode terminal of the signal line consisting of a part of the signal line, the film thickness of the channel region is other than Forming a photosensitive resin pattern thinner than the area;
Using the photosensitive resin pattern as a mask, the second metal layer, the second amorphous silicon layer, and the first amorphous silicon layer are selectively removed to form source / drain wirings, scanning lines, and signal lines. Selectively forming electrode terminals;
Reducing the film thickness of the photosensitive resin pattern to expose the second metal layer in the channel region;
The second metal layer and the second amorphous silicon layer in the channel region are selectively removed using the photosensitive resin pattern having the reduced thickness as a mask, and the first metal on the pixel electrode is removed. Removing the layer to expose the transparent conductive pixel electrode;
Forming a passivation insulating layer having openings on the transparent conductive picture element electrodes and on the scanning line and signal line electrode terminals on the first transparent insulating substrate;

With this configuration, the number of photo-etching steps for processing the pixel electrodes and the scanning lines using one photomask is reduced, and the scanning line forming step and the contact forming step are processed using one photomask. Simultaneously reduce the number of photo-etching processes. As in the conventional four-mask process, the number of photo-etching steps in which the semiconductor layer formation (islandization) step and the source / drain wiring formation step are processed using the same photomask is also reduced. Yes. Further, a conventional passivation insulating layer is formed on the active substrate to protect the channel and source / drain wiring of the insulated gate transistor. As a result, a TN liquid crystal display device can be manufactured using three photomasks.

The difference between claim 23 and claim 24 is that the transparent conductive layer and the first metal layer are laminated, and the pseudo electrode terminal exposed at the time of contact formation and the first metal layer constituting the pseudo pixel electrode are changed at this time. Or to be removed when the subsequent source / drain wiring is formed.

Claim 25 is a method of manufacturing a liquid crystal display device according to claim 11,
At least a first metal layer, one or more gate insulating layers, a first amorphous silicon layer not containing impurities, and a second amorphous containing impurities, on at least one main surface of the first transparent insulating substrate Sequentially depositing silicon layers;
A step of forming a photosensitive resin pattern corresponding to the scanning line and the counter electrode and having a film thickness on the contact formation region of the scanning line that is thinner than other regions in the region outside the image display unit;
Sequentially etching the second amorphous silicon layer, the first amorphous silicon layer, the gate insulating layer, and the first metal layer using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose the second amorphous silicon layer on the contact formation region;
Forming an insulating layer on the side surface of the scanning line;
A portion of the scanning line is etched by etching the second amorphous silicon layer, the first amorphous silicon layer, and the gate insulating layer in the contact region using the photosensitive resin pattern having the reduced thickness as a mask. Exposing the step,
After depositing one or more second metal layers including the refractory metal layer, the gate electrode partially overlaps the source wiring (signal line) / drain wiring (pixel electrode) and the channel region between the source / drain wiring And a photosensitive resin corresponding to the electrode terminal of the scanning line including a part of the scanning line and the electrode terminal of the signal line including a part of the signal line, wherein the channel region is thinner than the other regions Forming a pattern;
Using the photosensitive resin pattern as a mask, the second metal layer, the second amorphous silicon layer, and the first amorphous silicon layer are selectively removed to form source / drain wirings, scanning lines, and signal lines. Selectively forming electrode terminals;
Reducing the film thickness of the photosensitive resin pattern to expose the second metal layer in the channel region;
Selectively removing the second metal layer and the second amorphous silicon layer in the channel region using the photosensitive resin pattern having a reduced thickness as a mask;
A passivation insulating layer having openings on the scanning line and signal line electrode terminals is formed on the first transparent insulating substrate.

With this configuration, it is possible to reduce the number of photolithography steps in which the scanning line and counter electrode forming process and the contact forming process are performed using one photomask. As in the conventional four-mask process, the number of photo-etching steps in which the semiconductor layer formation (islandization) step and the source / drain wiring formation step are processed using the same photomask is also reduced. Yes. Further, a conventional passivation insulating layer is formed on the active substrate to protect the channel and source / drain wiring of the insulated gate transistor. As a result, an IPS liquid crystal display device can be manufactured using three photomasks using three photomasks.

Claim 26 is a method of manufacturing a liquid crystal display device according to claim 12,
At least a first metal layer, one or more gate insulating layers, a first amorphous silicon layer not containing impurities, and a second amorphous containing impurities, on at least one main surface of the first transparent insulating substrate Sequentially depositing silicon layers;
A step of forming a photosensitive resin pattern corresponding to the scanning line and the counter electrode and having a film thickness on the contact formation region of the scanning line that is thinner than other regions in the region outside the image display unit;
Sequentially etching the second amorphous silicon layer, the first amorphous silicon layer, the gate insulating layer, and the first metal layer using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose the second amorphous silicon layer on the contact formation region;
Forming an insulating layer on the side surface of the scanning line;
A portion of the scanning line is etched by etching the second amorphous silicon layer, the first amorphous silicon layer, and the gate insulating layer in the contact region using the photosensitive resin pattern having the reduced thickness as a mask. Exposing the step,
Selectively forming a second amorphous silicon layer and a first amorphous silicon layer on the gate electrode to expose the gate insulating layer on the scanning line and the counter electrode;
After depositing one or more anodizable metal layers including a refractory metal layer, the gate electrode partially overlaps the source wiring (signal line) / drain wiring (picture element electrode) and a part of the scanning line. In correspondence with the electrode terminal of the scanning line and the electrode terminal of the signal line formed of a part of the signal line in the region outside the image display portion, the film thickness on the electrode terminal of the scanning line and the signal line is larger than that in the other region. Forming a thick photosensitive resin pattern;
Selectively removing an anodizable metal layer using the photosensitive resin pattern as a mask to form source / drain wirings, and electrode terminals for scanning lines and signal lines;
Reducing the film thickness of the photosensitive resin pattern to expose the source / drain wiring; and
The method includes a step of anodizing the amorphous silicon layer between the source / drain wiring and the source / drain wiring while protecting the electrode terminal.

With this configuration, it is possible to reduce the number of photolithography steps in which the scanning line and counter electrode forming process and the contact forming process are performed using one photomask. In addition, a silicon oxide layer is formed on the channel between the source and drain to protect the channel, and an anodized layer is selectively formed on the source and drain wiring using a halftone exposure technique when forming the source and drain wiring. As a result, the number of manufacturing steps that do not require the formation of a passivation insulating layer is reduced. As a result, an IPS liquid crystal display device can be manufactured using three photomasks.

Claim 27 is claim 15, claim 16, claim 17, claim 18, claim 19, claim 20, claim 21, claim 22, claim 23, claim 24, claim 25 and claim 25. 26. The method for manufacturing a liquid crystal display device according to 26, wherein the insulating layer formed on the side surface of the scanning line is an organic insulating layer and is formed by electrodeposition. With this configuration, an organic insulating layer can be formed on the side surface of the scan line by electrodeposition regardless of the material and configuration of the scan line, and the scan line forming process and the contact forming process can be performed using halftone exposure technology. It becomes possible to process continuously with one photomask.

A twenty-eighth aspect is the method of manufacturing a liquid crystal display device according to the fifteenth, nineteenth, twentieth, twenty-fifth and twenty-sixth aspects, wherein the first metal layer is made of an anodizable metal layer. An insulating layer is formed on the side surface of the scanning line by anodization. With this configuration, an anodized layer can be formed by anodic oxidation on the side surface of the scanning line, and the scanning line forming process and the contact forming process are successively processed with a single photomask using a halftone exposure technique. It becomes possible to do.

In some of the liquid crystal display devices according to the present invention, the insulated gate type transistor has a protective insulating layer on the channel, so that the photosensitive organic insulation is only on the source / drain wiring in the image display section or only on the signal line. A passivation function is given to the active substrate by selectively forming a layer or by anodizing a source / drain wiring made of an anodizable source / drain wiring material and forming an insulating layer on the surface thereof. Similarly, in another part of the liquid crystal display device according to the present invention, a silicon oxide layer is formed on the channel by anodic oxidation. Therefore, the source / drain wiring made of the source / drain wiring material that can be anodized is formed simultaneously with the channel. The active substrate is provided with a passivation function by anodizing and forming an insulating layer on the surface thereof. Therefore, no special heating process is involved in the production of the active substrate constituting these liquid crystal display devices, and the insulated gate transistor having an amorphous silicon layer as a semiconductor layer does not require excessive heat resistance. In other words, an effect of not causing deterioration of electrical performance by forming a passivation is added. In addition, when anodizing the source / drain wiring, it is possible to selectively protect the scanning line and signal line electrode terminals by introducing a halftone exposure technique, and the effect of preventing an increase in the number of photolithography steps can be obtained. It is done.

The main point of the present invention is to reduce the number of steps that make it possible to process a scanning line forming step and a contact forming step for electrical connection to the scanning line with a single photomask by introducing a halftone exposure technique. In addition, by forming an organic insulating layer or an anodic oxide layer on the side surface of the exposed scanning line, a structural feature is created in which the scanning line and the signal line can be crossed.

  In addition, the introduction of pseudo-picture element electrodes, combined with rationalization such as the formation of picture element electrodes and scanning lines with a single photomask, can further reduce the number of photolithography steps from the conventional five times to four or three. A liquid crystal display device can be manufactured using a single photomask, and the industrial value is extremely large from the viewpoint of cost reduction of the liquid crystal display device. Moreover, since the pattern accuracy of these processes is not so high, the production management is also facilitated by not greatly affecting the yield and quality.

Further, in the IPS type liquid crystal display device according to the fifth embodiment, the electric field generated between the counter electrode and the pixel electrode is applied only to the gate insulating layer and the liquid crystal layer on the counter electrode. In the IPS type liquid crystal display device according to the example, since it is also applied to the gate insulating layer on the counter electrode, the liquid crystal layer, and the anodic oxidation layer of the pixel electrode, none of the conventional poor passivation insulating layers with many defects is interposed. Further, the advantage that the display image is not easily burned out cannot be overlooked. This is because the anodic oxide layer of the drain wiring (picture element electrode) functions as a high resistance layer rather than an insulating layer, so that charge accumulation does not occur.

As is clear from the above description, the requirement of the present invention is that the process of forming the scanning line (and the counter electrode) and the process of forming the contact are processed with a single photomask by introducing a half-tone exposure technique. In addition, the organic insulating layer or the anodized layer is formed on the side surface of the exposed scanning line (and the counter electrode), and the other components such as the pixel electrode, the gate insulating layer, etc. It is obvious that semiconductor devices for display devices having different film thicknesses or differences in manufacturing methods also belong to the scope of the present invention, and even in liquid crystal display devices using vertical alignment liquid crystals and reflective liquid crystal display devices. It is clear that the usefulness of the present invention does not change and that the semiconductor layer of the insulated gate transistor is not limited to amorphous silicon.

An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a plan view of a semiconductor device (active substrate) for a display device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view along the lines AA ′, BB ′ and CC ′ of FIG. Sectional drawing of the manufacturing process on a line is shown. 3 and 4 in the second embodiment, FIGS. 5 and 6 in the third embodiment, FIGS. 7 and 8 in the fourth embodiment, FIGS. 9 and 10 in the fifth embodiment, FIGS. 11 and 12 show the sixth embodiment, FIGS. 13 and 14 show the seventh embodiment, FIGS. 15 and 16 show the eighth embodiment, FIGS. 17 and 18 show the ninth embodiment, and FIGS. 19 and 20 show the active substrate, FIGS. 21 and 22 show the eleventh embodiment, and FIGS. 23 and 24 show the twelfth embodiment. FIGS. In addition, about the site | part same as a prior art example, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.

First embodiment

In the first embodiment, as in the conventional example, first, a first metal layer having a film thickness of about 0.1 to 0.3 μm is formed on one main surface of the glass substrate 2 by using a vacuum film forming apparatus such as SPT, for example, Cr. , Ta, Mo, etc. or their alloys and silicides are deposited. As will be clarified in the following description, in the present invention, when an organic insulating layer is selected as the insulating layer formed on the side surface of the gate insulating layer, there is almost no restriction caused by the scanning line material, but on the side surface of the gate insulating layer. When an anodic oxide layer is selected as the insulating layer to be formed, the anodic oxide layer needs to have insulating properties. In that case, the resistance of Ta alone is high and the heat resistance of AL alone is poor. Considering this, in order to reduce the resistance of the scanning line, the scanning line is composed of a single layer such as an AL (Zr, Ta, Nd) alloy or the like, or AL / Ta, Ta / AL / Ta, AL / AL (Ta, Zr). , Nd) A laminated structure such as an alloy can be selected. AL (Ta, Zr, Nd) means an AL alloy having high heat resistance to which Ta, Zr, Nd or the like of several percent or less is added.

Next, a first SiNx layer 30 that becomes a gate insulating layer using a PCVD apparatus on the entire surface of the glass substrate 2, a first amorphous silicon layer 31 that hardly contains impurities and becomes a channel of an insulated gate transistor, and a channel For example, a second SiNx layer 32 serving as an insulating layer for protecting the film and three kinds of thin film layers are sequentially deposited with a film thickness of, for example, about 0.3-0.05-0.1 μm, and FIG. As shown in FIG. 2A, the contact formation region 81B corresponding to the openings 63A and 65A has a film thickness of 1 μm, for example, and is thinner than the film thickness 2 μm of the region 81A corresponding to the scanning line 11 and the storage capacitor line 16. The photosensitive resin patterns 81A and 81B are formed by a halftone exposure technique, and the second SiNx layer 32, the first amorphous silicon layer 31, and the gate insulating layer are formed using the photosensitive resin patterns 81A and 81B as a mask. 0 and a first metal layer is selectively removed to expose the glass substrate 2. Since the size of the contact is usually 10 μm or more, which is comparable to that of the electrode terminal, it is easy to produce a photomask for forming 81B (halftone region) and to control the accuracy of the finished dimensions.

Subsequently, when the photosensitive resin patterns 81A and 81B are reduced by 1 μm or more by ashing means such as oxygen plasma, the photosensitive resin pattern 81B disappears as shown in FIGS. 1B and 2B. The second SiNx layers 32A and 32B in the openings 63A and 65A are exposed, and a photosensitive resin pattern 81C can be selectively formed on the scanning lines 11 and the storage capacitor lines 16. Since the photosensitive resin pattern 81C (black region), that is, the pattern width of the gate electrode 11A is obtained by adding the mask alignment accuracy to the dimensions of the protective insulating layer, the protective insulating layer is 10 to 12 μm and the alignment accuracy is ± 3 μm. The minimum is 16 to 18 μm, and the dimensional accuracy is not severe. Also, the pattern width of the scanning line 11 and the counter electrode 16 is usually set to 10 μm or more because of the resistance value. However, when the resist pattern is isotropically reduced by 1 μm during conversion from the resist pattern 81A to 81C, not only the dimension is reduced by 2 μm, but also the mask alignment accuracy in the subsequent formation of the protective insulating layer is reduced by 1 μm to ± 2 μm. The influence of the latter is more severe in the process than the former. Therefore, in the oxygen plasma treatment, it is desirable to increase the anisotropy in order to suppress the change in pattern dimension. Specifically, an RIE (Reactive Ion Etching) method, an ICP (Inductively Coupled Plasma) method having a high density plasma source, and a TCP (Transfer Coupled Plasma) method oxygen plasma treatment are more desirable. Alternatively, it is desirable to take a process measure by designing the pattern dimension of the resist pattern 81A to be large in advance in consideration of the dimensional change of the resist pattern.

Thereafter, as shown in FIG. 2B, an insulating layer 76 is formed on the side surface of the gate electrode 11A. For this purpose, as shown in FIG. 25, electrodeposition or anodization is performed on the outer peripheral portion of the glass substrate 2 and the wiring 77 that bundles the scanning lines 11 (the storage capacitor line 16 is also similar, but not shown here) in parallel. A connection pattern 78 for applying a potential is sometimes required, and a film formation region 79 using an appropriate mask means for the amorphous silicon layer 31 and the silicon nitride layers 30 and 32 by plasma CVD is located inside the connection pattern 78. It is limited and at least the connection pattern 78 needs to be exposed. In the chemical conversion liquid mainly composed of ethylene glycol by applying a positive (+) potential by breaking through the photosensitive resin pattern 81C (78) on the connection pattern 78 using a connection means such as a hook clip having a sharp cutting edge in the connection pattern 78. When the glass substrate 2 is infiltrated into the glass substrate 2 and anodization is performed, if the scanning line 11 is an AL-based alloy, for example, alumina (AL2O3) having a film thickness of 0.3 μm at a formation voltage of 200 V is formed. In the case of electrodeposition, as shown in the literature, Monthly “Polymer Processing” November 2002 issue, a pendant carboxyl group-containing polyimide electrodeposition solution is used and the electrodeposition voltage number is 0.3 μm. A polyimide resin layer having a film thickness is formed. A matter to be noted in forming the insulating layer on the side surfaces of the exposed scanning line 11 and storage capacitor line 16 is that an electrical inspection of the active substrate 2 is required unless the scanning line 11 is parallelized at least in some subsequent manufacturing process. Needless to say, the actual operation as a liquid crystal display device is hindered. This is a matter common to the following embodiments, and as the release means, transpiration by laser light irradiation or mechanical excision by scribing is simple, but detailed description is omitted.
Monthly “Polymer Processing” November 2002 issue

After the formation of the insulating layer 76, as shown in FIGS. 1C and 2C, the second SiNx layers 32A and 32B and the first SiNx layers 32A and 32B in the openings 63A and 65A are formed using the photosensitive resin pattern 81C as a mask. The amorphous silicon layers 31A and 31B and the gate insulating layers 30A and 30B are selectively etched to expose a part 73 of the scanning line 11 and a part 75 of the counter electrode 16, respectively.

After removing the photosensitive resin pattern 81C, as shown in FIGS. 1D and 2D, the second SiNx layer 32A on the gate electrode 11A is made narrower than the gate electrode 11A by a fine processing technique. A second SiNx layer 32D (etch stop layer, channel protective layer, protective insulating layer) is selectively etched, and the first amorphous silicon layer 31A on the scanning line 11 and the storage capacitor line 16 are formed. The first amorphous silicon layer 31B is exposed. At this time, although not shown, if necessary, the exposed part 73 of the scanning line 11 and the part 75 of the counter electrode 16 are covered with a photosensitive resin, so that the part 73 of the scanning line 11 and the counter electrode 16 are covered. A problem that a part 75 of the gate insulating layers 30A and 30B is reduced in thickness or deteriorated when the gate insulating layers 30A and 30B are etched can be easily avoided. That is, the second SiNx layer 32C (not shown) remains around the openings 63A and 65A, but there is no problem with the contact property to the scanning line.

  Further, after depositing a second amorphous silicon layer 33 containing, for example, phosphorus as an impurity on the entire surface of the glass substrate 2 with a film thickness of, for example, about 0.05 μm using a PCVD apparatus, A heat-resistant metal layer that can be anodized with a film thickness of about 0.1 μm using a vacuum film forming apparatus such as SPT, for example, a thin film layer 34 of Ti, Ta, etc., and a low resistance that can also be anodized with a film thickness of about 0.3 μm. An AL thin film layer 35 as a wiring layer and a thin film layer 36 of Ta or the like as an intermediate conductive layer having a film thickness of about 0.1 μm that can be anodized are sequentially deposited. Then, the source / drain wiring material composed of these three thin films, the second amorphous silicon layer 33, and the first amorphous silicon layers 31A and 31B are sequentially etched using a photosensitive resin pattern by a fine processing technique. Then, the gate insulating layers 30A and 30B are exposed, and also serve as the drain electrode 21 and the source electrode of the insulating gate type transistor formed by stacking 34A, 35A and 36A as shown in FIGS. 1 (e) and 2 (e). The signal line 12 is selectively formed. It goes without saying that the source / drain wirings 12 and 21 are formed so as to partially overlap the channel protection layer 32D because they do not become inoperable due to offset. Usually, in order to avoid side effects associated with the battery action, the electrode terminal 5 of the scanning line including the part 73 of the scanning line is formed at the same time as the formation of the source / drain wirings 12, 21. Since 5 is not essential, the transparent conductive electrode terminal 5A may be directly formed in a subsequent process. As the structure of the source / drain wirings 12 and 21, it is reasonable to simplify the Ta / single layer if the restriction of the resistance value is loose, and the AL alloy to which Nd is added reduces the chemical potential and reduces the alkaline solution. In this case, the intermediate conductive layer 36 is not required, and the stacked structure of the source / drain wirings 12 and 21 can be made into a two-layer structure. The configuration of the wirings 12 and 21 is slightly simplified. This is the same even if IZO is used instead of ITO.

After the formation of the source / drain wirings 12 and 21, for example, ITO is deposited on the entire surface of the glass substrate 2 as a transparent conductive layer having a film thickness of about 0.1 to 0.2 μm using a vacuum film forming apparatus such as SPT. As shown in FIG. 1 (f) and FIG. 2 (f), the pixel electrode 22 is selectively formed on the glass substrate 2 including a part of the intermediate conductive layer 36A of the drain electrode 21 by a fine processing technique. At this time, a transparent conductive layer pattern is also formed on the electrode terminal 5 of the scanning line and the electrode terminal 6 which is a part of the signal line in a region outside the image display portion to form the transparent conductive electrode terminals 5A and 6A. . As described above, the electrode terminal 5 may not be formed, and at this time, the electrode terminal 5A may be formed directly including the opening 63A. Here, as in the conventional example, a transparent conductive short-circuit line 40 is provided, and the resistance between the electrode terminals 5A, 6A and the short-circuit line 40 is increased by forming an elongated stripe to increase the resistance to prevent static electricity. Yes.

Subsequently, as shown in FIGS. 1 (g) and 2 (g), the source / drain wirings 12, while irradiating light with the photosensitive resin pattern 83A used for selective pattern formation of the picture element electrode 22 as a mask, 21 is anodized to form an oxide layer on the surface. At this time, the electrode terminals 5A and 6A and the anti-static wire 40 are protected by the photosensitive resin patterns 83B to 83D. Ta and AL, Ti, and the second amorphous silicon layer 33A are exposed on the upper surfaces of the source / drain wirings 12 and 21, and the second amorphous silicon layer 33A is exposed by anodic oxidation. The silicon layer 33A is an impurity-containing silicon oxide layer (SiO2) 66, Ti is a semiconductor titanium oxide (TiO2) 68, AL is an insulating layer alumina (AL2O3) 69, and Ta is an insulating layer. It changes to tantalum pentoxide (Ta2O5) 70, respectively. Although the titanium oxide layer 68 is not an insulating layer, the film thickness is extremely thin and the exposed area is small, so that there is no problem in terms of passivation. However, it is desirable that the refractory metal thin film layer 34A is also selected from Ta. However, it is necessary to pay attention to the characteristic that Ta, unlike Ti, lacks the function of absorbing the underlying surface oxide layer and facilitating ohmic contact.

It has also been disclosed in the previous examples that anodizing while irradiating light is an important point in the anodizing process in order to form an anodized layer having a good film quality also on the drain wiring 21. . More specifically, when a sufficiently strong light of about 10,000 lux is irradiated and the leakage current of the insulated gate transistor exceeds μA, a good film quality is obtained by anodization of about 10 mA / cm 2 calculated from the area of the drain electrode 21. The current density to obtain is obtained. However, even if the film quality of the anodized layer on the drain wiring 21 is insufficient, the reason why sufficient reliability is usually obtained is that the drive signal applied to the liquid crystal cell is basically alternating current, and the color filter Since the voltage of the counter electrode 14 is adjusted during image inspection so that the DC voltage component is reduced between the counter electrode 14 formed on the counter surface and the pixel electrode 22 (drain electrode 21) (flicker reduction adjustment). This is because, in principle, it is only necessary to form an insulating layer so that a direct current component does not flow only on the signal line 12.

The thickness of each oxide layer of tantalum pentoxide 70, alumina 69, titanium oxide 68, and silicon oxide layer 66 formed by anodization is sufficient to be about 0.1 to 0.2 μm for wiring passivation. The applied voltage is also realized at over 100V using a chemical conversion solution such as Although not shown, all signal lines 12 need to be formed electrically in parallel or in series, although not shown in the drawings, in the subsequent manufacturing process. Needless to say, if this series-parallel is not canceled, not only the electrical inspection of the active substrate 2 but also the actual operation as a liquid crystal display device is hindered. As the releasing means, transpiration by laser light irradiation or mechanical excision by scribing is simple, but a detailed description is omitted.

Covering the pixel electrode 22 with the photosensitive resin pattern 83A not only does not need to anodize the pixel electrode 22, but also causes an excessive formation current to flow to the drain electrode 21 via the insulated gate transistor. This is because it is not necessary to secure a large amount.

Finally, the photosensitive resin patterns 83A to 83D are removed to complete the active substrate 2 (display device semiconductor device) as shown in FIGS. 1 (h) and 2 (h). The active substrate 2 and the color filter thus obtained are bonded to form a liquid crystal panel, and the first embodiment of the present invention is completed. Regarding the configuration of the storage capacitor 15, as shown in FIG. 1H, a region 51 where the storage capacitor line 16 and the picture element electrode 22 overlap each other in a plane via the gate insulating layer 30B (shaded portion with a downward slope to the right). However, the configuration of the storage capacitor 15 is not limited to this, and the insulation including the gate insulating layer 30A between the pixel electrode 22 and the preceding scanning line 11 is illustrated. You may comprise through a layer. Although other configurations are possible, detailed description thereof is omitted. Similarly, since there is a step of forming a contact (opening 63) to the scanning line 11, it is easy to take countermeasures against static electricity using a conductive material or a semiconductor layer other than the transparent conductive layer.

In the first embodiment, the halftone exposure technique is applied to a layer with low pattern accuracy, ie, a scanning line forming process and a contact (opening) forming process for electrical connection to the scanning line, thereby reducing the photolithography process. The active substrate is manufactured with four photomasks, but the process of forming pixel electrodes and scanning lines is processed with one photomask to further promote process reduction and active with three photomasks. Since it is possible to produce a substrate, it will be described as second to fourth embodiments.

Second embodiment

In the second embodiment, first, a transparent conductive layer 91 having a film thickness of about 0.1 to 0.2 μm is formed on one main surface of the glass substrate 2 by using a vacuum film-forming apparatus such as SPT, for example, ITO, and a film thickness of 0. A first metal layer 92 of about 1 to 0.3 μm is deposited. As will be clear from the following description, in the second to fourth embodiments, since the scanning line is a laminate of a transparent conductive layer and a metal layer, it is not possible to form an insulating layer on the side surface of the scanning line in anodic oxidation. Is possible. Therefore, since an organic insulating layer is formed by electrodeposition on the insulating layer, a high melting point such as Cr, Ta, Mo or the like is used as the first metal layer that does not cause a battery reaction with the transparent conductive layer ITO as the scanning line material. A metal or an alloy or silicide thereof is selected. If AL is adopted to reduce resistance, the single layer of AL (Nd) alloy is the simplest, then Ta is interposed, and Ta / AL (Zr, Hf) or Ta / Al / Ta laminated The configuration becomes complicated.

Next, a first SiNx layer 30 that becomes a gate insulating layer using a PCVD apparatus on the entire surface of the glass substrate 2, a first amorphous silicon layer 31 that hardly contains impurities and becomes a channel of an insulated gate transistor, and A second SiNx layer 32 serving as an insulating layer for protecting the channel and three kinds of thin film layers are sequentially deposited with a film thickness of, for example, about 0.3-0.05-0.1 μm, and FIG. 4A, the region 82A corresponding to the scanning line 11 which also serves as the gate electrode 11A has a film thickness of 2 μm, for example (consisting of a laminate of the transparent conductive layer 91B and the first metal layer 92B). Pseudo-pixel electrode 93, pseudo-electrode terminal 94 (consisting of a laminate of transparent conductive layer 91A and first metal layer 92A), and pseudo-electrode terminal (consisting of a laminate of transparent conductive layer 91C and first metal layer 92C) Region 82 corresponding to 95 The photosensitive resin patterns 82A and 82B having a thickness of B greater than 1 μm are formed by the halftone exposure technique, and the second SiNx layer (channel protective layer) 32 and the first amorphous film are formed using the photosensitive resin patterns 82A and 82B as a mask. The glass substrate 2 is exposed by sequentially removing the transparent conductive layer 91 in addition to the porous silicon layer 31, the gate insulating layer 30 and the first metal layer 92.

Thus, after obtaining the multilayer film pattern corresponding to the scanning line 11, which also serves as the gate electrode 11A, the pseudo picture element electrode 93, and the pseudo electrode terminals 94, 95, the photosensitive resin is subsequently applied by ashing means such as oxygen plasma. When the film thickness of the patterns 82A and 82B is reduced by 1 μm or more, the photosensitive resin pattern 82B disappears as shown in FIGS. 3B and 4B, the second SiNx layers 32A to 32C are exposed, and the scanning line The photosensitive resin pattern 82 </ b> C can be selectively formed only on 11. As described above, in the oxygen plasma treatment, it is desirable to increase the anisotropy and suppress the change in the pattern dimension so that the mask alignment accuracy in the subsequent etching stop layer forming process is not lowered.

Subsequently, as shown in FIG. 4B, an organic insulating layer 76 is formed on the side surface of the gate electrode 11A. For this purpose, the photosensitive resin pattern 82C (78) on the connection pattern 78 is pierced by using connection means such as a hook clip having a sharp cutting edge in the connection pattern 78 shown in FIG. However, depending on the composition of the electrodeposition liquid, a-(minus) potential may be applied. For example, a polyimide resin layer having a film thickness of 0.3 μm at an electrodeposition voltage number V is formed as the organic insulating layer. Since the pseudo picture element electrode 93 is electrically isolated, the organic insulating layer 76 is not formed around the pseudo picture element electrode 93.

Subsequently, as shown in FIGS. 3C and 4C, the second SiNx layers 32A to 32C and the first amorphous silicon layers 31A to 31C are gate-insulated using the photosensitive resin pattern 82C as a mask. When the layers 30A to 30C and the first metal layers 92A to 92C are sequentially removed to expose the transparent conductive layers 91A to 91C, the scanning line electrode terminal 5A, the picture element electrode 22 and the signal line electrode terminal respectively made of the transparent conductive layer are exposed. 6A is obtained.

After removing the photosensitive resin pattern 82C, as shown in FIGS. 3D and 4D, the second SiNx layer 32A on the gate electrode 11A is made narrower than the gate electrode 11A by a fine processing technique. By selectively etching, a second SiNx layer 32D (protective insulating layer) is formed, and the first amorphous silicon layer 31A on the scanning line 11 is exposed. A fluorine-based gas is used for dry etching (dry etching) of the SiNx layer 32A, but the exposed electrode terminal 5A of the transparent conductive scanning line, the pixel electrode 22 and the electrode terminal 6A of the signal line are fluorine. It is very convenient not to be etched or altered by the gas of the system.

Thereafter, a second amorphous silicon layer 33 containing, for example, phosphorus as an impurity is deposited on the entire surface of the glass substrate 2 using a PCVD apparatus in a film thickness of, for example, about 0.05 μm. Using a vacuum film forming apparatus such as SPT, a thin film layer 34 of, for example, Ti or Ta as a heat-resistant metal layer having a thickness of about 0.1 μm, and an AL thin film layer 35 as a low resistance wiring layer of about 0.3 μm are sequentially formed. Adhere. Then, the source / drain wiring material composed of these two thin films, the second amorphous silicon layer 33, and the first amorphous silicon layer 31A are sequentially etched using the photosensitive resin pattern 85 by a fine processing technique. The gate insulating layer 30A is exposed, and the drain electrode of an insulated gate transistor comprising a part of the pixel electrode 22 and a stack of 34A and 35A as shown in FIGS. 3 (e) and 4 (e). Similarly to 21, the signal line 12 including part of the signal line electrode terminal 6 </ b> A and also serving as the source electrode is selectively formed. It will be understood that the scanning line electrode terminal 5A and the signal line electrode terminal 6A are exposed on the glass substrate 2 after the source / drain wirings 12 and 21 are etched. The configuration of the source / drain wirings 12 and 21 can be simplified to a single layer of Ta, Cr, MoW or the like if the resistance value is loosely restricted.

The active substrate 2 and the color filter thus obtained are bonded to form a liquid crystal panel, and the second embodiment of the present invention is completed. In the second embodiment, since the photosensitive resin pattern 85 is in contact with the liquid crystal, the photosensitive resin pattern 85 is not a normal photosensitive resin mainly composed of a novolac resin, but has a high purity and an acrylic resin as a major component. It is important to use a highly heat-resistant photosensitive organic insulating layer containing polyimide resin, and depending on the material, it may be fluidized by heating to cover the side surfaces of the source / drain wirings 12 and 21. In this case, the reliability of the liquid crystal panel is further improved. As for the configuration of the storage capacitor 15, as shown in FIG. 3E, the storage electrode 72 formed by including a part of the pixel electrode 22 simultaneously with the source / drain wirings 12 and 21, and the scanning line 11 ( The protrusion 52 provided on the first and second amorphous silicon layers 33A (not shown) overlaps in plan view with the gate insulating layer 30A, the first amorphous silicon layer 31A, and the second amorphous silicon layer 33D (not shown). The case where the storage capacitor 15 constitutes the storage capacitor 15 is illustrated as an example (lower right slanted line portion), but the configuration of the storage capacitor 15 is not limited to this, and is formed simultaneously with the scanning line 11 as in the first embodiment. Alternatively, an insulating layer including the gate insulating layer 30 </ b> B may be interposed between the common capacitor line 16 and the pixel electrode 21. The static electricity countermeasure line 40 is composed of a transparent conductive layer connected to the electrode terminals 5A and 6A, but other static electricity countermeasures are possible because an opening forming step is provided in the gate insulating layers 30A to 30C. .

In the second embodiment, there are restrictions on the device configuration in which both the electrode terminals of the scanning lines and the electrode terminals of the signal lines are transparent conductive layers. However, a device process that removes the restrictions is also possible. Will be described as third and fourth embodiments.

Third embodiment

In the third embodiment, as shown in FIGS. 5D and 6D, the steps up to the formation of the etch stop layer 32D are performed in substantially the same manufacturing process as in the second embodiment. However, the pseudo electrode terminal 95 is not always necessary for the reason described later. Subsequently, in the process of forming the source / drain wiring, using a vacuum film forming apparatus such as SPT, as a heat-resistant metal layer having a thickness of about 0.1 μm, for example, a thin film layer 34 of Ti, Ta, etc., and a low resistance of about 0.3 μm. The AL thin film layer 35 is sequentially deposited as a wiring layer. Then, the source / drain wiring material composed of these two thin films, the second amorphous silicon layer 33, and the first amorphous silicon layer 31A are sequentially etched using a photosensitive resin pattern 86 by a fine processing technique. The gate insulating layer 30A is exposed, and the drain electrode of an insulated gate transistor comprising a part of the pixel electrode 22 and a stack of 34A and 35A as shown in FIGS. 5 (e) and 6 (e). 21 and the signal line 12 which also serves as the source wiring are selectively formed, and the scanning line electrode terminal 5 and the signal line including the part 5A of the scanning line exposed simultaneously with the formation of the source / drain wirings 12 and 21 A part of the electrode terminal 6 is also formed at the same time. That is, unlike the second embodiment, the pseudo electrode terminal 95 is not necessarily required. At this time, the film thickness of the region 86A (black region) on the signal line 12 is 3 μm, for example, and the film thickness of the region 86B (halftone region) on the drain electrode 21, the electrode terminals 5 and 6, and the storage electrode 72 is 1.5 μm. It is an important feature of the third embodiment that the thicker photosensitive resin patterns 86A and 86B are formed by the halftone exposure technique. The minimum dimension of 86B corresponding to the electrode terminals 5 and 6 is as large as several tens of μm, and photomask fabrication and finished dimension management are extremely easy. However, the minimum dimension of the area 86A corresponding to the signal line 12 is 4 to 8 μm. Since the dimensional accuracy is relatively high, a thin pattern is required as the black region. However, as described in the conventional example, the source / drain wirings 12 and 21 of the present invention are compared with the single exposure processing and the etching processing twice as compared with the source / drain wirings 12 and 21 formed by one exposure processing. Since it is formed by a single etching process, there are few factors that cause fluctuations in the pattern width, and the dimension management of the source / drain wirings 12 and 21 and the dimension management of the channel length between the source / drain wirings 12 and 21, that is, the channel length are conventional. Pattern accuracy is easier to manage than halftone exposure technology. Compared with the channel etch type insulated gate transistor, the ON current of the etch stop type insulated gate transistor is determined by the dimension of the channel protective insulating layer 32D and not the dimension between the source / drain wirings 12 and 21. Therefore, it should be understood that process management becomes easier.

After the source / drain wirings 12 and 21 are formed, if the photosensitive resin patterns 86A and 86B are reduced by 1.5 μm or more by ashing means such as oxygen plasma, the photosensitive resin pattern 86B disappears, and FIG. As shown in FIG. 6F, the drain electrode 21, the electrode terminals 5, 6 and the storage electrode 72 are exposed, and the photosensitive resin pattern 86C can be selectively formed only on the signal line 12. When the pattern width of the photosensitive resin pattern 86C is narrowed by the oxygen plasma treatment, the upper surface of the signal line 12 is exposed and the reliability is lowered. Therefore, it is desirable to increase the anisotropy and suppress the change in the pattern dimension. The configuration of the source / drain wirings 12 and 21 can be simplified to a single layer of Ta, Cr, Mo or the like if the resistance value is loosely restricted.

The active substrate 2 and the color filter thus obtained are bonded to form a liquid crystal panel, and the third embodiment of the present invention is completed. The electrode terminals 5 and 6 are made of the same metal material as that of the signal line 12. However, it is also easy to make the electrode terminals 5A and 6A as in the second embodiment. Also in the third embodiment, since the photosensitive resin pattern 86C is in contact with the liquid crystal, the photosensitive resin pattern 86C is not a normal photosensitive resin mainly composed of a novolac resin, but has a high purity and an acrylic resin or It is important to use a photosensitive organic insulating layer having a high heat resistance containing a polyimide resin. The configuration of the storage capacitor 15 is the same as that of the second embodiment. The transparent conductive layer pattern connecting the transparent conductive pattern 6A (91C) formed under the part 5A of the scanning line and the signal line 12 and the short-circuit line 40 is formed into an elongated linear shape, thereby generating static electricity. Although it is possible to use high resistance wiring as a countermeasure, of course, countermeasures against static electricity using other conductive members are possible.

In the third embodiment of the present invention, an organic insulating layer is formed only on the signal line 12 and the drain electrode 21 is exposed while maintaining conductivity. The reason why sufficient reliability can be obtained is the liquid crystal. The drive signal applied to the cell is basically alternating current, and the counter electrode 14 has a DC voltage component between the counter electrode 14 and the pixel electrode 22 formed on the counter surface of the color filter so that the DC voltage component is reduced. This is because the voltage is adjusted at the time of image inspection (flicker reduction adjustment). Therefore, it is only necessary to form an insulating layer so that a direct current component does not flow only on the signal line 12.

In the second and third embodiments of the present invention, the organic insulating layer is selectively formed only on the source / drain wiring and the signal line, respectively. However, if the pixel is small in a high-definition panel, the alignment step of the alignment film using a rubbing cloth may cause a non-alignment state, or the gap accuracy of the liquid crystal cell may be impaired. There is also. Therefore, in the fourth embodiment, a passivation technique for changing to an organic insulating layer by adding a minimum number of steps is provided.

Fourth embodiment

In the fourth embodiment, as shown in FIGS. 7 (d) and 8 (d), the process up to the formation of the etch stop layer 32D proceeds in substantially the same process as in the second and third embodiments. Thereafter, in the source / drain wiring formation process, a thin film layer 34 of, for example, Ti, Ta or the like as a heat-resistant metal layer having a film thickness of about 0.1 μm and a film thickness of 0.3 μm using a vacuum film forming apparatus such as SPT. The AL thin film layer 35 is sequentially deposited as a low-resistance wiring layer that can be anodized to the same extent. Then, the source / drain wiring material composed of these two thin films, the second amorphous silicon layer 33, and the first amorphous silicon layer 31A are sequentially etched using the photosensitive resin pattern 87 by a fine processing technique. As shown in FIGS. 7E and 8E, the gate insulating layer 30A is exposed, and the drain electrode 21 of the insulated gate transistor including a part of the picture element electrode 22 and including a stack of 34A and 35A is exposed. And the signal line 12 that also serves as the source wiring are selectively formed, and the scanning line electrode terminal 5 and one of the signal lines including the part 5A of the scanning line exposed simultaneously with the formation of the source / drain wirings 12 and 21 are formed. An electrode terminal 6 composed of a portion is also formed. At this time, the thickness of the region 87A (black region) on the electrode terminals 5 and 6 is 3 μm, for example, and the thickness of the region 87B (halftone region) on the source / drain wirings 12 and 21 and the storage electrode 72 is 1.5 μm. It is an important feature of the fourth embodiment that the thick photosensitive resin patterns 87A and 87B are formed by the halftone exposure technique.

  After the source / drain wirings 12 and 21 are formed, if the photosensitive resin patterns 87A and 87B are reduced by 1.5 μm or more by ashing means such as oxygen plasma, the photosensitive resin pattern 87B disappears and the source / drain wirings 12 are removed. 21 and the storage electrode 72 are exposed, and the photosensitive resin pattern 87C can be selectively formed only on the electrode terminals 5 and 6. Even if the pattern width of the photosensitive resin pattern 87C is narrowed by the oxygen plasma treatment, only an anodic oxide layer is formed around the electrode terminals 5 and 6 having large pattern dimensions, which gives electric characteristics, yield, and quality. It is a remarkable feature that there is almost no influence. Then, while irradiating light using the photosensitive resin pattern 87C as a mask, the source / drain wirings 12 and 21 are anodized to form oxide layers 68 and 69 as shown in FIGS. 7 (f) and 8 (f). At the same time, the second amorphous silicon layer 33A exposed on the lower surface of the source / drain wirings 12 and 21 is anodized to form a silicon oxide layer (SiO 2) 66 as an insulating layer. Since the thickness of the anodic oxide layers 68 and 69 is about 0.1 to 0.2 μm as in the first embodiment and sufficient passivation performance is obtained, there is no possibility of problems in the alignment process.

After the anodic oxidation, the photosensitive resin pattern 87C is removed, and as shown in FIGS. 7 (g) and 8 (g), an electrode terminal 5 comprising a low-resistance thin film layer 35A having an anodic oxide layer formed on its side surface. 6 is exposed. The side surface of the electrode terminal 5 of the scanning line has a thickness of the anodized layer formed on the side surface as compared with the electrode terminal 6 of the signal line because an anodizing current flows through the high resistance short circuit line 40 (91C) for static electricity countermeasures Please understand that is thin. It should be noted that the source / drain wirings 12 and 21 can be simplified and formed into a Ta single layer that can be anodized if the restriction on the resistance value is loose. The active substrate 2 and the color filter thus obtained are bonded to form a liquid crystal panel, and the fourth embodiment of the present invention is completed. The configuration of the storage capacitor 15 is the same as in the second and third embodiments.

In the fourth embodiment, the pixel electrode 22 that is electrically connected to the drain electrode 21 is also exposed during the anodic oxidation of the source / drain wirings 12 and 21 and the second amorphous silicon layer 33A. Therefore, the point that the pixel electrode 22 is also anodized at the same time is greatly different from the first embodiment. For this reason, depending on the film quality of the transparent conductive layer constituting the pixel electrode 22, the resistance value may be increased by anodic oxidation. In this case, the film forming conditions of the transparent conductive layer are changed as appropriate to obtain a film quality lacking oxygen. Although necessary, the transparency of the transparent conductive layer does not decrease due to anodization. In addition, a current for anodizing the drain electrode 21, the pixel electrode 22, and the storage electrode 72 is also supplied through the channel of the insulated gate transistor. However, since the area of the pixel electrode 22 is large, a large formation current or It takes a long time to form, and no matter how strong external light is irradiated, the resistance of the channel part becomes an obstacle, and an anodized layer having the same film quality and thickness as the signal line 12 is formed on the drain electrode 21 and the storage electrode 72. It is difficult to form by simply extending the formation time. However, even if the anodized layer formed on the drain wiring 21 is somewhat incomplete, reliability that does not hinder practical use is often obtained. This is because it is only necessary to form an insulating layer so that a direct current component does not flow only on the signal line 12 as described above.

The liquid crystal display device described above uses a TN type liquid crystal cell. However, a horizontal electric field is generated between a pair of counter electrodes and a pixel electrode formed at a predetermined distance from the pixel electrode. The process reduction proposed in the present invention is also useful in an IPS (In-Plain-Switting) liquid crystal display device to be controlled, and will be described in the following examples.

Fifth embodiment

In the fifth embodiment, as in the conventional example, first, a first metal layer having a film thickness of about 0.1 to 0.3 μm is formed on one main surface of the glass substrate 2 using a vacuum film forming apparatus such as SPT, for example, Cr. , Ta, Mo, etc. or their alloys and silicides are deposited.

Next, a first SiNx layer 30 that becomes a gate insulating layer using a PCVD apparatus on the entire surface of the glass substrate 2, a first amorphous silicon layer 31 that hardly contains impurities and becomes a channel of an insulated gate transistor, and A second SiNx layer 32 serving as an insulating layer for protecting the channel and three kinds of thin film layers are sequentially deposited to a thickness of, for example, about 0.3-0.05-0.1 μm, and FIG. 10A, the contact formation region 84B corresponding to the openings 63A and 65A has a film thickness of 1 μm, for example, and the film in the region 84A corresponding to the counter electrode 16 serving as the scanning line 11 and the storage capacitor line. Photosensitive resin patterns 84A and 84B thinner than 2 μm are formed by a halftone exposure technique, and the second SiNx layer 32 and the first amorphous silicon are formed using the photosensitive resin patterns 84A and 84B as a mask. 31, to expose the glass substrate 2 are sequentially removing the gate insulating layer 30 and the first metal layer.

Subsequently, when the photosensitive resin patterns 84A and 84B are reduced by 1 μm or more by ashing means such as oxygen plasma, the photosensitive resin pattern 84B disappears as shown in FIGS. 9B and 10B. Then, the second SiNx layer 32A is exposed in the opening 63A, the second SiNx layer 32B is exposed in the opening 65A, and the photosensitive resin pattern 84C is selectively formed on the scanning line 11 and the counter electrode 16. Can be formed.

Subsequently, as shown in FIG. 10B, an insulating layer 76 is formed on the side surface of the gate electrode 11A. For this purpose, as shown in FIG. 27, the potentials at the time of electrodeposition or anodization at the outer periphery of the glass substrate 2 and the wiring 77 that bundles the scanning lines 11 (the counter electrode 16 is the same but is not shown here) in parallel. A connection pattern 78 is necessary to form the film, and a film formation region 79 using an appropriate mask means of the amorphous silicon layer 31 and the silicon nitride layers 30 and 32 by plasma CVD is limited to the inside of the connection pattern 78. At least the connection pattern 78 needs to be exposed. The connecting pattern 78 is cut through the photosensitive resin pattern 84C (78) on the connecting pattern 78 using connecting means such as a hook clip having a sharp edge, and an electric potential is applied to the scanning line 11 to perform electrodeposition or anodic oxidation, and an insulating layer Either an organic insulating layer or an anodized layer may be formed on 76.

Further, as shown in FIGS. 9C and 10C, the second SiNx layers 32A and 32B in the openings 63A and 65A and the first amorphous silicon layer are formed using the photosensitive resin pattern 84C as a mask. 31A and 31B and gate insulating layers 30A and 30B are sequentially etched to expose part 73 of scanning line 11 and part 75 of counter electrode 16 respectively.

  After removing the photosensitive resin pattern 84C, as shown in FIGS. 9D and 10D, the second SiNx layer 32A on the gate electrode 11A is made narrower than the gate electrode 11A by a fine processing technique. The second SiNx layer 32D (etch stop layer, channel protective layer, or protective insulating layer) is selectively etched, and the first amorphous silicon layer 31A on the scanning line 11 and the first amorphous silicon layer 31 on the counter electrode 16 are etched. One amorphous silicon layer 31B is exposed.

Then, after depositing a second amorphous silicon layer 33 containing, for example, phosphorus as an impurity on the entire surface of the glass substrate 2 with a film thickness of, for example, about 0.05 μm using a PCVD apparatus, in the source / drain wiring formation process, Using a vacuum film forming apparatus such as SPT, a thin film layer 34 of, for example, Ti or Ta as a heat-resistant metal layer having a thickness of about 0.1 μm, and an AL thin film layer 35 as a low resistance wiring layer of about 0.3 μm are sequentially formed. Adhere. Then, the source / drain wiring material composed of these two thin films, the second amorphous silicon layer 33, and the first amorphous silicon layers 31A and 31B are sequentially eaten using a photosensitive resin pattern 86 by a fine processing technique. The gate insulating layers 30A and 30B are exposed, and as shown in FIGS. 9E and 10E, the drain electrode 21 of the insulated gate transistor, which is formed of a stack of 34A and 35A and becomes a pixel electrode. And the signal line 12 that also serves as the source wiring are selectively formed, and the scanning line electrode terminal 5 and one of the signal lines including the part 73 of the scanning line exposed simultaneously with the formation of the source / drain wirings 12 and 21 are formed. The electrode terminal 6 composed of a portion is also formed at the same time. At this time, the photosensitive resin patterns 86A and 86B having a thickness of 86A on the signal line 12 are, for example, 3 μm and thicker than the thickness of 1.5 μm of 86B on the drain electrode 21 and the electrode terminals 5 and 6 are formed by the halftone exposure technique. The formation is an important feature of the fifth embodiment.

After the source / drain wirings 12 and 21 are formed, if the photosensitive resin patterns 86A and 86B are reduced by 1.5 μm or more by ashing means such as oxygen plasma, the photosensitive resin pattern 86B disappears, and FIG. As shown in FIG. 10F, the drain electrode 21 and the electrode terminals 5 and 6 are exposed, and the photosensitive resin pattern 86C can be selectively formed only on the signal line 12. As the pattern width of the photosensitive resin pattern 86C becomes narrow, the upper surface of the signal line 12 is exposed and the reliability is lowered. is there. The configuration of the source / drain wirings 12 and 21 can be simplified to a single layer of Ta, Cr, MoW alloy or the like if the resistance value is loosely restricted.

The active substrate 2 and the color filter thus obtained are bonded to form a liquid crystal panel, and the fifth embodiment of the present invention is completed. As is apparent from the above description, the IPS liquid crystal display device does not require the transparent conductive pixel electrode 22 on the acti substrate 2, and the transparent conductive counter electrode 14 is also formed on the opposing surface of the color filter. Is unnecessary. Therefore, the intermediate conductive layer on the source / drain wirings 12 and 21 is not required. Also in the fifth embodiment, since the photosensitive resin pattern 86C is in contact with the liquid crystal, the photosensitive resin pattern 86C is not a normal photosensitive resin mainly composed of a novolac resin, but has a high purity and an acrylic resin or It is important to use a photosensitive organic insulating layer having a high heat resistance containing a polyimide resin. Regarding the configuration of the storage capacitor 15, as shown in FIG. 9F, a part of the pixel electrode (drain wiring) 21 and the counter electrode 16 that also serves as the storage capacitor line are formed by the gate insulating layer 30B and the first amorphous layer. An example is shown in which the storage capacitor 15 is configured by a region 50 (lower right hatched portion) overlapping in a plane via the porous silicon layer 31B and the second amorphous silicon layer 33D (not shown). . Although the description of the countermeasure against static electricity is omitted, the countermeasure against static electricity is easy because the step of providing the opening 63A and exposing a part 73 of the scanning line 11 is provided.

In the fifth embodiment of the present invention, the reduction of the manufacturing process is promoted by forming the organic insulating layer only on the signal line. However, since the thickness of the organic insulating layer is usually 1 μm or more, the pixel is formed on the high-definition panel. If the thickness is small, the alignment step using the rubbing cloth may cause a non-aligned state in the alignment step or hinder the gap accuracy of the liquid crystal cell. Therefore, in the sixth embodiment, a passivation technique replacing the organic insulating layer is provided by adding the minimum number of steps.

Sixth embodiment

In the sixth embodiment, as shown in FIGS. 11 (d) and 12 (d), the process up to the formation of the etch stop layer 32D proceeds in substantially the same manufacturing process as in the fifth embodiment. Thereafter, in the step of forming the source / drain wiring, a thin film layer 34 of Ti, Ta or the like as a heat-resistant metal layer having a thickness of about 0.1 μm, for example, using a vacuum film forming apparatus such as SPT, The AL thin film layer 35 is sequentially deposited as a low resistance wiring layer of about 3 μm, which can also be anodized. Then, the source / drain wiring material composed of these two thin films, the second amorphous silicon layer 33, and the first amorphous silicon layers 31A and 31B are sequentially eaten using the photosensitive resin pattern 87 by a fine processing technique. The gate insulating layers 30A and 30B are exposed, and as shown in FIGS. 11E and 12E, the drain electrode 21 of the insulated gate transistor, which is formed by stacking 34A and 35A and becomes a pixel electrode, is formed. And a signal line 12 that also serves as a source wiring are selectively formed, and a portion 73 of the scanning line exposed at the same time as the formation of the source / drain wirings 12 and 21 is included. An electrode terminal 6 composed of a portion is also formed. At this time, photosensitive resin patterns 87A and 87B having a film thickness on the electrode terminals 5 and 6 of, for example, 3 μm and a film thickness of 1.5 μm on the source / drain wirings 12 and 21 are formed by the halftone exposure technique. Is an important feature of the sixth embodiment.

  After the source / drain wirings 12 and 21 are formed, if the photosensitive resin patterns 87A and 87B are reduced by 1.5 μm or more by ashing means such as oxygen plasma, the photosensitive resin pattern 87B disappears and the source / drain wirings 12 are removed. , 21 are exposed, and the photosensitive resin pattern 87C can be selectively formed only on the electrode terminals 5 and 6. Therefore, the source / drain wirings 12 and 21 are anodized to form oxide layers 68 and 69 as shown in FIGS. 11 (f) and 12 (f) while irradiating light with the photosensitive resin pattern 87C as a mask. At the same time, the second amorphous silicon layer 33A exposed on the lower surface of the source / drain wirings 12 and 21 is anodized to form a silicon oxide layer (SiO 2) 66 as an insulating layer.

When the photosensitive resin pattern 87C is removed after the anodic oxidation is completed, the electrode terminals 5 and 6 having the low resistance thin film layer 35A on the surface thereof are exposed as shown in FIGS. 11 (g) and 12 (g). However, in both figures, the antistatic measures for connecting the electrode terminal 5 of the scanning line and the electrode terminal 6 of the signal line with a high resistance member are not shown in particular, so that an anodized layer is formed on the side surface of the electrode terminal 5 of the scanning line. However, since an opening 63A is provided and a step of exposing a part 73 of the scanning line 11 is provided, countermeasures against static electricity are easy. It should be noted that the source / drain wirings 12 and 21 can be simplified and formed into a Ta single layer that can be anodized if the restriction on the resistance value is loose. The active substrate 2 thus obtained and the color filter are bonded to form a liquid crystal panel, and the sixth embodiment of the present invention is completed. The configuration of the storage capacitor 15 is the same as that of the fifth embodiment.

Although the etch stop type insulated gate transistor is used in the liquid crystal display device described above, the process can be reduced in the same manner even if the channel etch type insulated gate transistor is used. Examples will be described.

Seventh embodiment

In the seventh embodiment, first, a transparent conductive layer 91 having a film thickness of about 0.1 to 0.2 μm is formed on one main surface of the glass substrate 2 using a vacuum film forming apparatus such as SPT, for example, ITO, and a film thickness of 0.1 mm. A first metal layer 92 of about 1 to 0.3 μm is deposited.

Next, a first SiNx layer 30 that becomes a gate insulating layer using a PCVD apparatus on the entire surface of the glass substrate 2, a first amorphous silicon layer 31 that hardly contains impurities and becomes a channel of an insulated gate transistor, and The second amorphous silicon layer 33 containing impurities and serving as the source / drain of an insulated gate transistor and three kinds of thin film layers are sequentially deposited in a thickness of, for example, about 0.3-0.2-0.05 μm. As shown in FIGS. 13A and 14A, the thickness of the region 82A corresponding to the scanning line 11 that also serves as the gate electrode 11A is 2 μm, for example (transparent conductive layer 91B and first metal layer). The pseudo-pixel electrode 93 (consisting of a stack with 92B), the antistatic line 95 (consisting of the stack of the transparent conductive layer 91C and the first metal layer 92C), and the film thickness of the region 82B corresponding to the contact formation region 63A 1μ Thicker photosensitive resin patterns 82A and 82B are formed by a halftone exposure technique, and the second amorphous silicon layer 33, the first amorphous silicon layer 31 and the gate insulation are formed using the photosensitive resin patterns 82A and 82B as a mask. In addition to the layer 30 and the first metal layer 92, the transparent conductive layer 91 is also sequentially removed to expose the glass substrate 2.

Thus, after obtaining the multilayer film pattern corresponding to the scanning line 11 which also serves as the gate electrode 11A, the pseudo picture element electrode 93, and the static electricity countermeasure line 95, the photosensitive resin pattern is subsequently obtained by ashing means such as oxygen plasma. When the film thickness of 82A and 82B is reduced by 1 μm or more, the photosensitive resin pattern 82B disappears as shown in FIGS. 13B and 14B, and the inside of the opening 63A, the pseudo-pixel electrode 93, and the antistatic line Second amorphous silicon layers 33A to 33C are exposed on 95, and photosensitive resin pattern 82C can be selectively formed on the scanning line formation region. In the above oxygen plasma treatment, it is desirable to increase the anisotropy and suppress the change in the pattern dimension so that the mask alignment accuracy in the subsequent source / drain wiring forming process is not lowered. It is the same kind.

Subsequently, as shown in FIG. 14B, an organic insulating layer 76 is formed on the side surface of the gate electrode 11A. For this purpose, as shown in FIG. 26, a wiring 77 for bundling the scanning lines 11 in parallel and a connection pattern 78 for applying a potential at the outer periphery of the glass substrate 2 at the time of electrodeposition are necessary. The film forming region 79 using the appropriate mask means of the crystalline silicon layers 31 and 33 and the silicon nitride layer 30 is limited to the inside of the connection pattern 78, and at least the connection pattern 78 needs to be exposed. A connection means such as a hook clip having a sharp cutting edge in the connection pattern 78 is used to break through the photosensitive resin pattern 82C (78) on the connection pattern 78 to give a + (plus) potential, but depending on the composition of the electrodeposition liquid A minus (minus) potential may be applied. For example, a polyimide resin layer having a film thickness of 0.3 μm at an electrodeposition voltage number V is formed as the organic insulating layer 76.

Subsequently, as shown in FIGS. 13C and 14C, the second amorphous silicon layers 33A to 33C and the first amorphous silicon layers 31A to 31C are formed using the photosensitive resin pattern 82C as a mask. When the gate insulating layers 30A to 30C and the first metal layers 92A to 92C are selectively removed to expose the transparent conductive layers 91A to 91C, a part 5A of the scanning line made of the transparent conductive layer, the pixel electrode 22, and the static electricity A countermeasure line 40 is obtained.

After removing the photosensitive resin pattern 82C, as shown in FIGS. 13D and 14D, the second amorphous silicon layer 33A and the first amorphous silicon layer 33A are formed only on the gate electrode 11A by a fine processing technique. The gate insulating layer 30A on the scanning line 11 is exposed leaving the amorphous silicon layer 31A selectively. A fluorine-based gas is used for dry etching (dry etching) of the amorphous silicon layer. However, the exposed portion 5A of the transparent conductive scanning line and the pixel electrode 22 are etched with the fluorine-based gas. It is very convenient not to be engraved or altered.

Further, in the source / drain wiring formation process, a thin film layer 34 of, for example, Ti or Ta as a heat-resistant metal layer having a film thickness of about 0.1 μm and a low resistance of about 0.3 μm are formed using a vacuum film forming apparatus such as SPT. The AL thin film layer 35 is sequentially deposited as a wiring layer. Then, as shown in FIGS. 13 (e) and 14 (e), these thin film layers are sequentially etched by a microfabrication technique, and an insulation composed of a stack of 34A and 35A including a part of the pixel electrode 22 is formed. A drain electrode 21 of the gate type transistor, a signal line 12 also serving as a source wiring, an electrode terminal 5 of the scanning line including a part 5A of the scanning line, and an electrode terminal 6 of the signal line including a part of the signal line In this case, the second amorphous silicon layer 33A and the first amorphous silicon layer 31A are sequentially etched as in the conventional example, and the first amorphous silicon layer 31A is zero. Etching leaving about 0.05 to 0.1 μm. The configuration of the source / drain wirings 12 and 21 can be simplified to a single layer of Ta, Cr, MoW alloy or the like if the resistance value is loosely restricted. When the source / drain wirings 12 and 21 are formed, electrodes 100A and 100B are provided at both ends of the static electricity countermeasure line 40 having a stripe shape as shown in FIG. It will not be necessary to explain that connecting to the signal line 12 is an effective countermeasure against static electricity.

After the formation of the source / drain wirings 12, 21, a second SiNx layer having a thickness of about 0.3 μm is deposited on the entire surface of the glass substrate 2 as a transparent insulating layer using a PCVD apparatus. 13 (f) and FIG. 14 (f), openings 38, 63 and 64 are formed on the pixel electrode 22 and the electrode terminals 5 and 6, respectively, and a passivation insulating layer in each opening is formed. Are selectively removed to expose most of the pixel electrode 22 and the electrode terminals 5 and 6.

The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel, and the seventh embodiment of the present invention is completed. With respect to the configuration of the storage capacitor 15, as shown in FIG. 13F, the storage electrode 72 formed at the same time as the source / drain wirings 12 and 21 including a part of the pixel electrode 22, the scanning line 11 in the previous stage, and the like. However, the storage capacitor 15 is illustrated as an example in which the region 52 (inclined to the right) that overlaps in plan view via the gate insulating layer 30A constitutes the storage capacitor 15, but the configuration of the storage capacitor 15 is not limited to this. As in the second embodiment, an insulating layer including a gate insulating layer 30B may be provided between the pixel electrode 22 and the storage capacitor line 16 formed simultaneously with the scanning line 11. Although other configurations are possible, detailed description thereof is omitted.

Instead of passivation using SiNx in the seventh embodiment, a metal thin film that can be anodized is used for the source / drain wiring material as in the fourth and sixth embodiments, and anodization is performed when forming the source / drain wiring. It is possible to form a passivation layer for the source and drain wiring by forming an insulating anodic oxide layer, and in the channel etch type insulated gate transistor, a silicon oxide layer is simultaneously formed on the channel surface to form a channel passivation. This also promotes a reduction in the number of photolithography steps, which will be described as an eighth embodiment.

Eighth embodiment

In the eighth embodiment, as shown in FIGS. 15 (d) and 16 (d), the steps up to the island formation of the semiconductor layers 31A and 33A constituting the channel are substantially the same as those in the seventh embodiment. proceed. However, the first amorphous silicon layer 31 may be formed as thin as 0.1 μm. In the source / drain wiring formation process, a heat-resistant metal layer having a film thickness of about 0.1 μm and a thin film layer 34 of, for example, Ti, Ta, and the like, and a film thickness of about 0.3 μm, using a vacuum film forming apparatus such as SPT. Similarly, the AL thin film layer 35 is sequentially deposited as a low resistance wiring layer that can be anodized. Then, as shown in FIGS. 15 (e) and 16 (e), the source / drain wiring materials made of these thin films are sequentially etched using the photosensitive resin patterns 87A and 87B by a microfabrication technique, and the pixel electrodes are formed. The drain electrode 21 of the insulated gate transistor formed by stacking 34A and 35A including a part of the line 22, the signal line 12 also serving as the source electrode, and the scanning line of the preceding stage including the part of the pixel electrode 22 11, the storage electrode 72 is selectively formed. Etching of the second amorphous silicon layer 33A containing impurities and the first amorphous silicon layer 31A containing no impurities is unnecessary. Simultaneously with the formation of the source / drain wirings 12 and 21, the electrode terminal 5 of the scanning line and the electrode terminal 6 of a part of the signal line including the part 5A of the scanning line made of the transparent conductive layer are simultaneously formed. Photosensitive resin patterns 87A and 87B having a thickness of 3 μm on the electrode terminals 5 and 6 and a thickness of 1.5 μm on the source / drain wirings 12 and 21 and the storage electrode 72 are formed by the halftone exposure technique. This is also an important feature of the eighth embodiment.

  After the source / drain wirings 12 and 21 are formed, if the photosensitive resin patterns 87A and 87B are reduced by 1.5 μm or more by ashing means such as oxygen plasma, the photosensitive resin pattern 87B disappears and the source / drain wirings 12 are removed. 21 and the storage electrode 72 are exposed, and the photosensitive resin pattern 87C can be selectively formed only on the electrode terminals 5 and 6. Even if the pattern width of the photosensitive resin pattern 87C is narrowed by the oxygen plasma treatment, only an anodic oxide layer is formed around the electrode terminals 5 and 6 having large pattern dimensions, which gives electric characteristics, yield, and quality. It is a remarkable feature that there is almost no influence. Therefore, as shown in FIGS. 15F and 16F, the source / drain wirings 12 and 21 are anodized while irradiating light with the photosensitive resin pattern 87C as a mask in the same manner as in the first embodiment. The oxide layers 68 and 69 are formed, and a part of the first amorphous silicon layer 31A adjacent to the second amorphous silicon layer 33A exposed between the source / drain wirings 12 and 21 is anodized. Thus, a silicon oxide layer 66 containing impurities, which is an insulating layer, and a silicon oxide layer (not shown) containing no impurities are formed.

AL is exposed on the upper surface of the source / drain wirings 12 and 21, and a laminate of AL and Ti is exposed on both side surfaces. Ti is oxidized to titanium oxide (TiO2) 68 which is a semiconductor by anodic oxidation, and AL is insulated. Each layer is transformed into alumina (AL 2 O 3) 69.

If the second amorphous silicon layer 33A containing impurities between channels is not completely insulated in the thickness direction, the leakage current of the insulated gate transistor is increased. Therefore, it is also disclosed in the prior examples that anodizing while irradiating light is an important point in the anodizing process. Specifically, when the leakage current of the insulated gate transistor exceeds μA by irradiating with sufficiently strong light of about 10,000 lux, the calculation is made from the area of the channel portion between the source / drain wirings 12 and 21 and the drain electrode 21. The current density for obtaining good film quality can be obtained by anodization of about 10 mA / cm 2.

In addition, the second amorphous silicon layer 33A containing impurities is formed by anodizing and setting the formation voltage higher than about 100V, which is sufficient to transform the silicon oxide layer 66, which is an insulating layer, into an insulating layer. By changing the part of the first amorphous silicon layer 31A not containing impurities (about 100 mm) in contact with the silicon oxide layer 66 containing impurities to a silicon oxide layer (not shown) containing no impurities, The electrical purity is increased, and the electrical separation between the source / drain wirings 12 and 21 can be made complete. That is, the OFF current of the insulated gate transistor is sufficiently reduced to obtain a high ON / OFF ratio.

The thickness of each oxide layer of alumina 69 and titanium oxide 68 formed by anodic oxidation is sufficient to be about 0.1 to 0.2 μm for wiring passivation, and the applied voltage using a chemical conversion solution such as ethylene glycol is It is also realized at over 100V. As noted in the first embodiment, all signal lines 12 are formed electrically in parallel or in series as described in the first embodiment, and the subsequent manufacturing process is noted in the anodic oxidation of the source / drain wirings 12 and 21. It is necessary to cancel this series parallel at some point.

After the anodic oxidation, the photosensitive resin pattern 87C is removed. As shown in FIGS. 15 (g) and 16 (g), electrode terminals 5 and 6 each having an anodized layer on its side surface and made of the low resistance metal layer 35A. Is exposed. However, as a countermeasure against static electricity, a part 5A of the scanning line is connected to, for example, the short-circuit line 40 (91C), and if the signal line 12 or the electrode terminal 6 is not formed including the short-circuit line 40 as illustrated, the electrode An anodized layer is not formed on the side surface of the terminal 5. It should be noted that the source / drain wirings 12 and 21 can be simplified and formed into a Ta single layer that can be anodized if the restriction on the resistance value is loose. The active substrate 2 and the color filter thus obtained are bonded to form a liquid crystal panel, and the eighth embodiment of the present invention is completed. The configuration of the storage capacitor 15 is the same as that of the seventh embodiment.

Also in the eighth embodiment, the pixel electrode 22 electrically connected to the drain electrode 21 at the time of anodic oxidation of the second amorphous silicon layer 33A between the source / drain wirings 12 and 21 and the source / drain wiring in this way. Since the pixel electrode 22 is also exposed, the point that the pixel electrode 22 is simultaneously anodized is greatly different from the first embodiment. For this reason, depending on the film quality of the transparent conductive layer constituting the pixel electrode 22, the resistance value may be increased by anodic oxidation. In this case, the film forming conditions of the transparent conductive layer are changed as appropriate to obtain a film quality lacking oxygen. Although necessary, the transparency of the transparent conductive layer does not decrease due to anodization. Further, a current for anodizing the drain electrode 21 and the pixel electrode 22 is also supplied through the channel of the insulated gate transistor. However, since the area of the pixel electrode 22 is large, a large formation current or a long-time formation is performed. Therefore, the resistance of the channel portion becomes an obstacle regardless of how much external light is irradiated, and an anodic oxide layer having the same film quality and thickness as the signal line 12 is formed on the drain electrode 21 and the storage electrode 72. It is difficult to cope with the problem by extending the formation time alone. However, as already described, it is often possible to obtain a practically reliable reliability even if the anodic oxide layer formed on the drain electrode 21 is somewhat incomplete.

It is also possible to combine the technology for rationalizing the source / drain wiring formation process and semiconductor layer island formation process described in the conventional example using a single photomask with the process reduction technique proposed in the present invention. Are described in the ninth and tenth embodiments.

Ninth embodiment

In the ninth and ninth embodiments, as shown in FIGS. 17 (c) and 18 (c), a part 5A of the scanning line made of the transparent conductive layer, the pixel electrode 22, and the electrostatic countermeasure line 40 (91C) are exposed. The process proceeds up to substantially the same process as in the seventh embodiment.

In the source / drain wiring forming process, for example, a Ti thin film layer 34 as a heat-resistant metal layer having a thickness of about 0.1 μm and an AL thin film as a low resistance wiring layer having a thickness of about 0.3 μm using a vacuum film forming apparatus such as SPT. Layer 35 is deposited sequentially. Then, the source / drain wiring materials made of these thin films are sequentially etched using a photosensitive resin pattern by a microfabrication technique, and the drain electrode 21 of the insulated gate transistor including a part of the pixel electrode 22 and the source electrode The signal line 12 also serving as a part, the storage electrode 72 on the scanning line 11 including the part of the pixel electrode 22, the electrode terminal 5 of the scanning line including the opening 63A, and a part of the signal line. The electrode terminal 6 of the signal line is selectively formed. As described in the conventional example, the film thickness of the channel formation region 80B (shaded portion) between the source and the drain is formed by the halftone exposure technique in forming this selective pattern. Is 1.5 μm, for example, and the source / drain wiring formation regions 80A (12), 80A (21), the storage electrode formation region 80A (72), and the electrode terminal formation regions 80A (5), 8 Thin photosensitive resin pattern 80A than the thickness 3μm of A (6), to form a 80B. Then, using the photosensitive resin patterns 80A and 80B as masks, as shown in FIGS. 17D and 18D, the AL thin film layer 35, the Ti thin film layer 34, the second amorphous silicon layer 33A, and the first amorphous silicon layer 33A are formed. When the amorphous silicon layer 31A is sequentially etched to expose the gate insulating layer 30A on the scanning line 11, the picture element electrode 22 is exposed.

Subsequently, as shown in FIGS. 17 (e) and 18 (e), if the film thickness of the photosensitive resin patterns 80A and 80B is reduced, for example, from 3 μm to 1.5 μm or more by ashing means such as oxygen plasma. The photosensitive resin pattern 80B disappears, the channel region is exposed, and the photosensitive resin patterns 80C (12), 80C (21), and 80C (72) are formed in the source / drain wiring formation region, the storage electrode formation region, and the electrode terminal formation region. , 80C (5) and 80C (6). Therefore, using these photosensitive resin patterns reduced in thickness as a mask, the AL thin film layer, the Ti thin film layer, the second amorphous silicon layer 33A and the first amorphous layer again between the source and drain wirings (channel formation region). The silicon layer 31A is sequentially etched, and the first amorphous silicon layer 31A is etched leaving about 0.05 to 0.1 μm.

Subsequently, after removing the photosensitive resin patterns 80C (12), 80C (21), 80C (72), 80A (5) and 80A (6), a PCVD apparatus is formed as a transparent insulating layer on the entire surface of the glass substrate 2. A second SiNx layer having a thickness of about 0.3 μm is deposited to form a passivation insulating layer 37, and pixel electrodes are formed by microfabrication technology as shown in FIGS. 17 (f) and 18 (f). 22 and electrode terminals 5 and 6 are formed with openings 38, 63 and 64, respectively, and the second SiNx layer in each opening is selectively removed to form pixel electrodes 22 and electrode terminals 5 and 6, respectively. Expose most.

The active substrate 2 thus obtained and the color filter are bonded together to form a liquid crystal panel, and the ninth embodiment of the present invention is completed. Regarding the configuration of the storage capacitor 15, as shown in FIG. 17F, the storage electrode 72 formed at the same time as the drain wiring 21 including a part of the pixel electrode 22 and the scanning line 11 in the previous stage are the second. An example in which the storage capacitor 15 is constituted by a region 52 (inclined to the right) that is planarly overlapped with the amorphous silicon layer 33A, the first amorphous silicon layer 31A, and the gate insulating layer 30A is illustrated. Yes.

In the ninth embodiment, the pixel electrode 22 remains exposed during the second etching process in the source / drain wiring formation process, and the pixel electrode 22 depends on the source / drain wiring material and the etching method. There is a high possibility that 22 is considerably reduced in film thickness or disappears. An invention incorporating measures for avoiding such problems will be described as a tenth embodiment.

Tenth embodiment

In the tenth embodiment, the second amorphous silicon layers 33A to 33C and the first amorphous silicon layers 33A to 33C are used as a mask with the photosensitive resin pattern 82C reduced in thickness as shown in FIGS. 19C and 20C. The amorphous metal layers 31A to 31C and the gate insulating layers 30A to 30C are selectively removed to expose the first metal layers 92A to 92C, and a part 73 of the scanning line, the pseudo pixel electrode 93, and the pseudo static electricity are respectively exposed. Until the countermeasure line 95 is obtained, the process proceeds in substantially the same manner as in the seventh embodiment. That is, the difference from the ninth embodiment is that the first metal layer is not etched in this etching process.

In the source / drain wiring forming process, for example, a Ti thin film layer 34 as a heat-resistant metal layer having a thickness of about 0.1 μm and an AL thin film as a low resistance wiring layer having a thickness of about 0.3 μm using a vacuum film forming apparatus such as SPT. Layer 35 is deposited sequentially. Then, source / drain wiring materials made of these thin films are sequentially etched using a photosensitive resin pattern by a microfabrication technique, so that the drain electrode 21 of the insulated gate transistor including part of the pseudo-pixel electrode 93, the source The signal line 12 that also serves as an electrode, the storage electrode 72 on the preceding scanning line 11 including a part of the pseudo picture element electrode 93, the electrode terminal 5 of the scanning line including the opening 63A, and a part of the signal line The electrode terminal 6 of the signal line is selectively formed. The film thickness of the channel forming region 80B (shaded portion) between the source and the drain is, for example, 1 by the halftone exposure technique as in the ninth embodiment. More than the film thickness of 3 μm of the source / drain wiring formation regions 80A (12), 80A (21), the storage electrode formation region 80A (72), and the electrode terminal formation regions 80A (5), 80A (6). Thin photosensitive resin patterns 80A and 80B are formed. Then, using the photosensitive resin patterns 80A and 80B as a mask, as shown in FIGS. 19D and 20D, the AL thin film layer 35, the Ti thin film layer 34, the second amorphous silicon layer 33A and the first thin film layer 33A are formed. When the amorphous silicon layer 31A is sequentially etched to expose the gate insulating layer 30A on the scanning line 11, the pseudo picture element electrode 93 is exposed. Here, there is no problem even if the first metal layer 92B of the pseudo picture element electrode 93 is somewhat reduced in film thickness.

Thereafter, as shown in FIGS. 19 (e) and 20 (e), if the film thickness of the photosensitive resin patterns 80A and 80B is reduced, for example, from 3 μm to 1.5 μm or more by ashing means such as oxygen plasma. The resin pattern 80B disappears and the channel region is exposed, and the photosensitive resin patterns 80C (12), 80C (21), 80C (80C) reduced in the source / drain wiring formation region, the storage electrode formation region, and the electrode terminal formation region 72), 80C (5) and 80C (6) can be left. Therefore, the AL thin film layer, the Ti thin film layer, the second amorphous silicon layer 33A, and the first amorphous silicon layer between the source and drain wirings (channel formation region) are used again using the reduced photosensitive resin pattern as a mask. 31A is sequentially etched, and the first amorphous silicon layer 31A is etched leaving about 0.05 to 0.1 μm. In the second etching step, the upper first metal layer 92B constituting the pseudo picture element electrode 93 is also removed, and the transparent conductive layer 91B to be the picture element electrode 22 is exposed.

After removing the photosensitive resin patterns 80C (12), 80C (21), 80C (72), 80C (5) and 80C (6), the entire surface of the glass substrate 2 is formed as in the ninth embodiment. As a transparent insulating layer, a PSi apparatus is used to deposit a second SiNx layer having a thickness of about 0.3 μm to form a passivation insulating layer 37, as shown in FIGS. 19 (f) and 20 (f). Then, openings 38, 63 and 64 are respectively formed on the pixel electrode 22 and the electrode terminals 5 and 6 by microfabrication technology, and the second SiNx layer in each opening is selectively removed to thereby respectively remove the pixel electrode. 22 and most of the electrode terminals 5 and 6 are exposed.

The active substrate 2 thus obtained and the color filter are bonded to form a liquid crystal panel, and the tenth embodiment of the present invention is completed. The same static electricity countermeasure as that of the seventh embodiment is adopted, and the configuration of the storage capacitor 15 is the same as that of the ninth embodiment.

In the seventh to tenth embodiments described above, the liquid crystal display device employs a channel etch type insulated gate transistor and uses a TN type liquid crystal cell, but has a predetermined distance from the pixel electrode. The process reduction proposed in the present invention is also useful in an IPS (In-Plain-Switting) type liquid crystal display device in which a horizontal electric field is controlled by a pair of counter electrodes and pixel electrodes formed with a gap therebetween. This will be described in the following examples.

Eleventh embodiment

Also in the eleventh embodiment, first, a first metal layer having a thickness of about 0.1 to 0.3 μm is formed on one main surface of the glass substrate 2 by using a vacuum film forming apparatus such as SPT, for example, Cr, Ta, Mo or the like. Alternatively, an alloy or silicide thereof is deposited.

Next, a first SiNx layer 30 that becomes a gate insulating layer using a PCVD apparatus on the entire surface of the glass substrate 2, a first amorphous silicon layer 31 that hardly contains impurities and becomes a channel of an insulated gate transistor, and a source A second amorphous silicon layer 33 containing impurities serving as a drain and three kinds of thin film layers are sequentially deposited with a film thickness of, for example, about 0.3-0.2-0.1 μm, and FIG. 22A, the contact formation region 84B corresponding to the openings 63A and 65A has a film thickness of 1 μm, for example, and the region 84A corresponding to the counter electrode 16 serving as the scanning line 11 and the storage capacitor line. The photosensitive resin patterns 84A and 84B having a thickness of less than 2 μm are formed by the halftone exposure technique, and the second amorphous silicon layer 33 and the first amorphous silicon layer 33 are formed using the photosensitive resin patterns 84A and 84B as a mask. Si layer 31, to expose the glass substrate 2 are sequentially removing the gate insulating layer 30 and the first metal layer.

Subsequently, when the photosensitive resin patterns 84A and 84B are reduced by 1 μm or more by ashing means such as oxygen plasma, the photosensitive resin pattern 84B disappears and the second amorphous silicon layer 33A is formed in the opening 63A. The second amorphous silicon layer 33B is exposed in the opening 65A, and the photosensitive resin pattern 84C can be selectively formed on the scanning line 11 and the counter electrode 16.

Subsequently, as shown in FIGS. 21B and 22B, an insulating layer 76 is formed on the side surface of the gate electrode 11A. For this purpose, as shown in FIG. 27, the potentials at the time of electrodeposition or anodization at the outer periphery of the glass substrate 2 and the wiring 77 that bundles the scanning lines 11 (the counter electrode 16 is the same but is not shown here) in parallel. A connection pattern 78 is necessary to provide the film, and a film forming region 79 using the appropriate mask means of the amorphous silicon layers 31 and 33 and the silicon nitride layer 30 by plasma CVD is limited to the inside of the connection pattern 78. At least the connection pattern 78 needs to be exposed. Using a connecting means such as a hook clip having a sharp cutting edge in the connection pattern 78, the photosensitive resin pattern 84C (78) on the connection pattern 78 is pierced, and a potential is applied to the scanning line 11 to perform electrodeposition or anodization, thereby performing the insulating layer 76. Either an organic insulating layer or an anodized layer may be formed.

Then, as shown in FIGS. 21C and 22C, the second amorphous silicon layers 33A and 33B in the openings 63A and 65A and the first amorphous resin pattern 84C are used as a mask. The silicon layers 31A and 31B and the gate insulating layers 30A and 30B are selectively etched to expose a part 73 of the scanning line 11 and a part 75 of the counter electrode 16, respectively.

After removing the photosensitive resin pattern 84C, in the source / drain wiring formation process, for example, a Ti thin film layer 34 having a thickness of about 0.1 μm is formed as a heat resistant metal layer having a thickness of about 0.1 μm using a vacuum film forming apparatus such as SPT. The AL thin film layer 35 is sequentially deposited as a low resistance wiring layer of about 3 μm. Then, the source / drain wiring material made of these thin films is sequentially etched using a photosensitive resin pattern by a microfabrication technique, and the drain electrode 21 of the insulated gate transistor to be the pixel electrode 22 and the signal line also serving as the source electrode 12, the electrode terminal 5 of the scanning line including the opening 63A and the electrode terminal 6 of the signal line made up of a part of the signal line are selectively formed. In pattern formation, the film thickness of the source / drain channel formation region 80B (shaded portion) is, for example, 1.5 μm by the halftone exposure technique, and the source / drain wiring formation regions 80A (12), 80A (21) and electrode terminal formation. Photosensitive resin patterns 80A and 80B thinner than the film thickness of 3 μm in the regions 80A (5) and 80A (6) are formed. Then, using the photosensitive resin patterns 80A and 80B as a mask, as shown in FIGS. 21D and 22D, the AL thin film layer 35, the Ti thin film layer 34, the second amorphous silicon layers 33A and 33B, and the second One amorphous silicon layer 31A, 31B is sequentially etched to expose the gate insulating layers 30A, 30B on the scanning line 11 and the counter electrode 16, respectively.

Furthermore, as shown in FIGS. 21 (e) and 22 (e), if the film thickness of the photosensitive resin patterns 80A and 80B is reduced from 3 μm to 1.5 μm or more by ashing means such as oxygen plasma, the photosensitive resin is used. The pattern 80B disappears, the channel region is exposed, and the photosensitive resin patterns 80C (12), 80C (21), 80C (5), and 80C (6) are left in the source / drain wiring formation region and the electrode terminal formation region. Can do. Therefore, using these photosensitive resin patterns reduced in thickness as a mask, the AL thin film layer, the Ti thin film layer, the second amorphous silicon layer 33A and the first amorphous layer again between the source and drain wirings (channel formation region). The silicon layer 31A is sequentially etched, and the first amorphous silicon layer 31A is etched leaving about 0.05 to 0.1 μm.

After removing the photosensitive resin patterns 80C (12), 80C (21), 80C (5) and 80C (6), 0.3 μm is formed on the entire surface of the glass substrate 2 using a PCVD apparatus as a transparent insulating layer. A second SiNx layer having a thickness of about 10 is deposited to form a passivation insulating layer 37, and openings are formed on the electrode terminals 5 and 6 by microfabrication techniques as shown in FIGS. 21 (f) and 22 (f). The portions 63 and 64 are selectively formed, and the second SiNx layer in each opening is selectively removed to expose most of the electrode terminals 5 and 6, respectively.

The active substrate 2 thus obtained and the color filter are bonded to form a liquid crystal panel, and the eleventh embodiment of the present invention is completed. Regarding the configuration of the storage capacitor 15, as shown in FIG. 21 (f), the pixel electrode 21 also serving as the drain wiring and the counter electrode 16 also serving as the storage capacitor line are the second amorphous silicon layer 33B, the first An example is shown in which the storage capacitor 15 is formed by a region 50 (shaded portion to the right) that overlaps in plan with the amorphous silicon layer 31B and the gate insulating layer 30B. In addition, description about static electricity measures is omitted.

In place of the passivation using SiNx in the eleventh embodiment, it is also possible to simultaneously perform the passivation formation of the channel of the insulated gate transistor and the source / drain wiring as in the eighth embodiment. Since the reduction of the number of processes is also promoted, this will be described as a twelfth embodiment.

12th embodiment

In the twelfth embodiment, as shown in FIGS. 23 (c) and 24 (c), the process up to contact formation proceeds in substantially the same manufacturing process as in the eleventh embodiment. However, the film thickness of the first amorphous silicon layer 31 may be as thin as 0.1 μm. Then, after removing the reduced photosensitive resin pattern 84C, as shown in FIGS. 23 (d) and 24 (d), the second pattern is formed on the gate electrode 11A using the photosensitive resin pattern 88A by a fine processing technique. The gate insulating layers 30A and 30B on the scanning line 11 and the counter electrode 16 are exposed leaving the amorphous silicon layer 33A and the first amorphous silicon layer 31A selectively. At this time, a part 73 of the scanning line exposed in the openings 63A and 65A and a part 75 of the counter electrode are protected by the photosensitive resin patterns 88B and 88C to prevent unnecessary film reduction and generation of reaction products. It is common to suppress. Therefore, the second amorphous silicon layer and the first amorphous silicon layer remain around the openings 63A and 65A, but there is no problem with the contact property to the scanning line.

Subsequently, after removing the photosensitive resin patterns 88A to 88C, in the source / drain wiring formation process, a thin film such as Ti or Ta is formed as a heat-resistant metal layer having a thickness of about 0.1 μm using a vacuum film forming apparatus such as SPT. The AL thin film layer 35 is sequentially deposited as a layer 34 and a low resistance wiring layer having a thickness of about 0.3 μm. Then, the source / drain wiring material composed of these two layers of thin films is sequentially etched using a photosensitive resin pattern 87 by a fine processing technique to expose the gate insulating layers 30A and 30B, and FIG. 23 (e) and FIG. As shown in e), the signal line 12 which also serves as the source electrode and the drain electrode 21 of the insulated gate transistor which is formed by stacking 34A and 35A and serves as the pixel electrode is selectively formed, and the source / drain wirings 12, 21 are formed. The electrode terminal 5 of the scanning line and the electrode terminal 6 made of a part of the signal line are formed at the same time including the part 73 of the scanning line exposed at the same time. At this time, photosensitive resin patterns 87A and 87B having a film thickness on the electrode terminals 5 and 6 of, for example, 3 μm and a film thickness of 1.5 μm on the source / drain wirings 12 and 21 are formed by the halftone exposure technique. Is an important feature of the twelfth embodiment.

  After the source / drain wirings 12 and 21 are formed, if the photosensitive resin patterns 87A and 87B are reduced by 1.5 μm or more by ashing means such as oxygen plasma, the photosensitive resin pattern 87B disappears and the source / drain wirings 12 are removed. , 21 are exposed, and the photosensitive resin pattern 87C can be selectively formed only on the electrode terminals 5 and 6. Therefore, the source / drain wirings 12 and 21 are anodized to form oxide layers 68 and 69 as shown in FIGS. 23 (f) and 24 (f) while irradiating light using the photosensitive resin pattern 87C as a mask. At the same time, the second amorphous silicon layer 33A exposed between the source / drain wirings 12 and 21 is anodized to form a silicon oxide layer (SiO 2) 66 as an insulating layer.

When the photosensitive resin pattern 87C is removed after the anodic oxidation, the electrode terminals 5 and 6 having the low resistance thin film layer 35A on the surface thereof are exposed as shown in FIGS. 23 (g) and 24 (g). The active substrate 2 and the color filter thus obtained are bonded to form a liquid crystal panel, and the twelfth embodiment of the present invention is completed. Regarding the configuration of the storage capacitor 15, as shown in FIG. 23 (g), a region 50 where the part of the picture element electrode 21 and the counter electrode 16 overlap each other in a plane via the gate insulating layer 30B (the hatched portion with the lower right). ) Illustrates the case where the storage capacitor 15 is configured. Although the description of the countermeasure against static electricity is omitted, the countermeasure against static electricity is easy because the step of providing the opening 63A and exposing a part 73 of the scanning line 11 is provided.

The top view of the semiconductor device for display apparatuses concerning the 1st Embodiment of this invention Sectional drawing of the manufacturing process of the semiconductor device for display apparatuses concerning the 1st Embodiment of this invention The top view of the semiconductor device for display apparatuses concerning the 2nd Embodiment of this invention Sectional drawing of the manufacturing process of the semiconductor device for display apparatuses concerning the 2nd Embodiment of this invention. The top view of the semiconductor device for display apparatuses concerning the 3rd Embodiment of this invention Manufacturing process sectional drawing of the semiconductor device for display apparatuses concerning the 3rd Embodiment of this invention. The top view of the semiconductor device for display apparatuses concerning the 4th Embodiment of this invention Manufacturing process sectional drawing of the semiconductor device for display apparatuses concerning the 4th Embodiment of this invention The top view of the semiconductor device for display apparatuses concerning the 5th Embodiment of this invention Sectional drawing of the manufacturing process of the semiconductor device for display apparatuses concerning the 5th Embodiment of this invention The top view of the semiconductor device for display apparatuses concerning the 6th Embodiment of this invention Manufacturing process sectional drawing of the semiconductor device for display apparatuses concerning the 6th Embodiment of this invention The top view of the semiconductor device for display apparatuses concerning the 7th Embodiment of this invention Manufacturing process sectional drawing of the semiconductor device for display apparatuses concerning the 7th Embodiment of this invention The top view of the semiconductor device for display apparatuses concerning the 8th Embodiment of this invention. Manufacturing process sectional drawing of the semiconductor device for display apparatuses concerning the 8th Embodiment of this invention The top view of the semiconductor device for display apparatuses concerning the 9th Embodiment of this invention Manufacturing process sectional drawing of the semiconductor device for display apparatuses concerning the 9th Embodiment of this invention The top view of the semiconductor device for display apparatuses concerning the 10th Embodiment of this invention. Manufacturing process sectional drawing of the semiconductor device for display apparatuses concerning the 10th Embodiment of this invention The top view of the semiconductor device for display apparatuses concerning the 11th Embodiment of this invention Manufacturing process sectional drawing of the semiconductor device for display apparatuses concerning the 11th Embodiment of this invention The top view of the semiconductor device for display apparatuses concerning the 12th Embodiment of this invention Manufacturing process sectional drawing of the semiconductor device for display apparatuses concerning the 12th Embodiment of this invention Arrangement of connection patterns for forming an insulating layer in the first embodiment Arrangement of connection patterns for forming an insulating layer in the second, third, fourth, seventh, eighth, ninth and tenth embodiments Arrangement of connection pattern for forming an insulating layer in the fifth, sixth, eleventh and twelfth embodiments The perspective view which shows the mounting state of a liquid crystal panel Equivalent circuit diagram of LCD panel Sectional view of a conventional LCD panel Plan view of conventional active substrate Cross-sectional view of manufacturing process of conventional active substrate Plan view of streamlined active substrate Streamlined manufacturing process of active substrate

Explanation of symbols

1: Liquid crystal panel 2: Active substrate (glass substrate)
3: Semiconductor integrated circuit chip 4: TCP film 5: Scanning line electrode terminal, part of scanning line 6: Signal line electrode terminal, part of signal line 9: Color filter (opposing glass substrate)
10: Insulated gate transistor 11: Scanning line 11A: Gate wiring, gate electrode 12: Signal line (source wiring, source electrode)
16: Storage capacitor line (counter electrode in IPS type)
17: Liquid crystal
19: Polarizing plate 20: Alignment film 21: Drain electrode (pixel electrode in IPS type)
22: (transparent conductive) picture element electrode 30, 30A, 30B, 30C: gate insulating layer (first SiNx layer)
31, 31A, 31B, 31C: first amorphous silicon layer (without impurities) 32, 32A, 32B, 32C: second SiNx layer 32D: channel protective insulating layer (etch stop layer, protective insulating layer)
33, 33A, 33B, 33C: second amorphous silicon layer (including impurities) 34, 34A: refractory metal layer (anodizable) 35, 35A: low resistance metal layer (AL) )
36, 36A: (Anodically oxidizable) intermediate conductive layer 37: Passivation insulating layer 38: Opening (on the pixel electrode) 50, 51, 52: Storage capacitor forming region 62: Opening (on the drain electrode) 63 63A: Opening (on the scanning line) 64, 64A: Opening (on the signal line) 65, 65A: Opening (on the counter electrode) 66: Silicon oxide layer containing impurities 68: Anodized layer (titanium oxide, TiO2)
69: Anodized layer (alumina, Al2O3)
70: Anodized layer (tantalum pentoxide, Ta2O5)
72: Storage electrode 73: Part of the scanning line 74: Part of the signal line 76: Insulating layer formed on the side surface of the scanning line 81A, 81B, 82A, 82B, 84A, 84B, 87A, 87B
: Photosensitive resin pattern (formed by halftone exposure) 83A: Photosensitive resin pattern (ordinary for pixel electrode formation) 85: Photosensitive organic insulating layers 86A, 86B: (formed by halftone exposure) ) Photosensitive organic insulating layer 91, 91A, 91B, 91C: transparent conductive layer 92, 92A, 92B, 02C: first metal layer

Claims (28)

Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
A scanning line comprising at least one first metal layer on one main surface of the first transparent insulating substrate and having an insulating layer on its side surface is formed,
One or more gate insulating layers and a first semiconductor layer not containing impurities are formed on the gate electrode,
A protective insulating layer is formed on the first semiconductor layer so as to be narrower than the gate electrode;
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display portion, and a part of the scanning line is exposed in the opening,
One or more anodizable metal layers including a second semiconductor layer containing impurities and a refractory metal layer on a part of the protective insulating layer, on the first semiconductor layer, and on the first transparent insulating substrate. The electrode terminal of the scanning line is formed in the same manner including the source (signal line) / drain wiring composed of the laminate and the first semiconductor layer around the opening,
A transparent conductive pixel electrode is formed on a part of the drain wiring and the first transparent insulating substrate, and a transparent conductive electrode terminal is formed on the signal line in a region outside the image display unit,
A liquid crystal display device, wherein an anodized layer is formed on a surface of the source / drain wiring except for a region overlapping the pixel electrode of the drain wiring and an electrode terminal region of the signal line. Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
A scanning line comprising a laminate of a transparent conductive layer and a first metal layer on at least one main surface of the first transparent insulating substrate and having an insulating layer on its side surface; a transparent conductive pixel electrode; and a signal line Electrode terminals are formed,
One or more gate insulating layers and a first semiconductor layer not containing impurities are formed on the gate electrode,
A protective insulating layer is formed on the first semiconductor layer so as to be narrower than the gate electrode;
The gate insulating layer on the scanning line is removed in a region outside the image display portion, and the transparent conductive layer that becomes the electrode terminal of the scanning line is exposed,
A second semiconductor layer containing impurities and a refractory metal layer on a part of the protective insulating layer, on the first semiconductor layer, on the first transparent insulating substrate, and on a part of the electrode terminal of the signal line; A source wiring (signal line) made of a laminate of one or more second metal layers, a part of the protective insulating layer, a first semiconductor layer, a first transparent insulating substrate, and the picture. A drain wiring is also formed on a part of the elementary electrode,
A liquid crystal display device, wherein a photosensitive organic insulating layer is formed on the source / drain wiring. Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
A scanning line comprising a transparent conductive layer and a first metal layer on at least one main surface of the first transparent insulating substrate and having an insulating layer on its side surface and a transparent conductive pixel electrode are formed,
One or more gate insulating layers and a first semiconductor layer not containing impurities are formed on the gate electrode,
A protective insulating layer is formed on the first semiconductor layer so as to be narrower than the gate electrode;
The gate insulating layer on the scanning line is removed in a region outside the image display portion, and the transparent conductive layer that is a part of the scanning line is exposed,
A second semiconductor layer including impurities on a part of the protective insulating layer, a first semiconductor layer, and a first transparent insulating substrate; and one or more second metal layers including a refractory metal layer; And a source wiring (signal line) made of a laminate of the same, a drain wiring on a part of the protective insulating layer, on the first semiconductor layer, on the first transparent insulating substrate, and on a part of the pixel electrode, In addition, a scanning line electrode terminal including a part of the scanning line, and a signal line electrode terminal formed of a part of the signal line in a region outside the image display unit are formed,
A liquid crystal display device, wherein a photosensitive organic insulating layer is formed on the signal line except on the electrode terminal of the signal line. Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
A scanning line comprising a transparent conductive layer and a first metal layer on at least one main surface of the first transparent insulating substrate and having an insulating layer on its side surface and a transparent conductive pixel electrode are formed,
One or more gate insulating layers and a first semiconductor layer not containing impurities are formed on the gate electrode,
A protective insulating layer is formed on the first semiconductor layer so as to be narrower than the gate electrode;
The gate insulating layer on the scanning line is removed in a region outside the image display portion, and the transparent conductive layer that is a part of the scanning line is exposed,
One or more anodizable metal layers including a second semiconductor layer containing impurities and a refractory metal layer on a part of the protective insulating layer, on the first semiconductor layer, and on the first transparent insulating substrate. And a source wiring (signal line) made of a laminated layer, and a drain wiring on a part of the protective insulating layer, on the first semiconductor layer, on the first transparent insulating substrate, and on a part of the pixel electrode. And an electrode terminal of the scanning line that includes a part of the scanning line, and an electrode terminal of the signal line that is a part of the signal line in a region outside the image display unit,
A liquid crystal display device, wherein an anodized layer is formed on the source / drain wiring except on the electrode terminal of the signal line. At least an insulated gate transistor on one main surface, a scanning line also serving as a gate electrode of the insulated gate transistor and a signal line also serving as a source line, a pixel electrode connected to a drain of the insulated gate transistor, A first transparent insulating substrate in which unit picture elements each having a counter electrode formed at a predetermined distance from the pixel electrode are arranged in a two-dimensional matrix, and opposed to the first transparent insulating substrate In a liquid crystal display device in which liquid crystal is filled between the second transparent insulating substrate or the color filter,
A scanning line and a counter electrode, each of which is composed of at least one first metal layer on one main surface of the first transparent insulating substrate and has an insulating layer on its side surface, are formed.
One or more gate insulating layers are formed on the counter electrode, and one or more gate insulating layers and a first semiconductor layer containing no impurities are formed on the gate electrode,
A protective insulating layer is formed on the first semiconductor layer so as to be narrower than the gate electrode;
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display portion, and a part of the scanning line is exposed in the opening,
One or more second metal layers including a second semiconductor layer including impurities and a refractory metal layer on a part of the protective insulating layer, on the first semiconductor layer, and on the first transparent insulating substrate; Source wiring (signal line) / drain wiring (picture element electrode) made of a laminate of the above, an electrode terminal of the scanning line including the first semiconductor layer around the opening, and a signal line in a region outside the image display unit The electrode terminal of the signal line consisting of a part of
A liquid crystal display device, wherein a photosensitive organic insulating layer is formed on the signal line except on the electrode terminal of the signal line. At least an insulated gate transistor on one main surface, a scanning line also serving as a gate electrode of the insulated gate transistor and a signal line also serving as a source line, a pixel electrode connected to a drain of the insulated gate transistor, A first transparent insulating substrate in which unit picture elements each having a counter electrode formed at a predetermined distance from the pixel electrode are arranged in a two-dimensional matrix, and opposed to the first transparent insulating substrate In a liquid crystal display device in which liquid crystal is filled between the second transparent insulating substrate or the color filter,
A scanning line and a counter electrode, each of which is composed of at least one first metal layer on one main surface of the first transparent insulating substrate and has an insulating layer on its side surface, are formed.
One or more gate insulating layers are formed on the counter electrode, and one or more gate insulating layers and a first semiconductor layer containing no impurities are formed on the gate electrode,
A protective insulating layer is formed on the first semiconductor layer so as to be narrower than the gate electrode;
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display portion, and a part of the scanning line is exposed in the opening,
One or more anodizable metal layers including a second semiconductor layer containing impurities and a refractory metal layer on a part of the protective insulating layer, on the first semiconductor layer, and on the first transparent insulating substrate. Source wiring (signal line) / drain wiring (picture element electrode) made up of a plurality of layers, and the electrode terminal of the scanning line including the first semiconductor layer around the opening, and the signal outside the image display section. An electrode terminal of a signal line made up of a part of the line is formed,
A liquid crystal display device, wherein an anodized layer is formed on the surface of the source / drain wiring except on the electrode terminal of the signal line. Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
A scanning line comprising a transparent conductive layer and a first metal layer on at least one main surface of the first transparent insulating substrate and having an insulating layer on its side surface and a transparent conductive pixel electrode are formed,
One or more gate insulating layers and a first semiconductor layer not containing impurities are formed on the gate electrode,
A second semiconductor layer containing a pair of impurities to be a source / drain of an insulated gate transistor is formed on the first semiconductor layer,
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display portion, and the transparent conductive layer that is a part of the scanning line is exposed in the opening,
A source wiring (signal line) made of one or more second metal layers including a refractory metal layer on the second semiconductor layer and the first transparent insulating substrate; and on the second semiconductor layer; The drain wiring on the first transparent insulating substrate and a part of the pixel electrode, the electrode terminal of the scanning line including the opening, and the signal line in a region outside the image display unit. The electrode terminal of the signal line is formed,
A liquid crystal display device, wherein a passivation insulating layer having openings on the pixel electrodes and on the electrode terminals of the scanning lines and signal lines is formed on the first transparent insulating substrate. Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
A scanning line comprising a transparent conductive layer and a first metal layer on at least one main surface of the first transparent insulating substrate and having an insulating layer on its side surface and a transparent conductive pixel electrode are formed,
One or more gate insulating layers and a first semiconductor layer not containing impurities are formed on the gate electrode,
A second semiconductor layer containing a pair of impurities to be a source / drain of an insulated gate transistor is formed on the first semiconductor layer,
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display portion, and the transparent conductive layer that is a part of the scanning line is exposed in the opening,
On the second semiconductor layer and on the first transparent insulating substrate, a source wiring (signal line) made of one or more anodizable metal layers including a refractory metal layer, and on the second semiconductor layer And a drain wiring on the first transparent insulating substrate and a part of the pixel electrode, an electrode terminal of the scanning line including the opening, and a part of the signal line in the region outside the image display unit An electrode terminal of a signal line is formed,
An anodic oxide layer is formed on the surface of the source / drain wiring except for the electrode terminal of the signal line,
A liquid crystal display device, wherein a silicon oxide layer is formed on a first semiconductor layer between the source / drain wirings. Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
A scanning line comprising a transparent conductive layer and a first metal layer on at least one main surface of the first transparent insulating substrate and having an insulating layer on its side surface and a transparent conductive pixel electrode are formed,
One or more gate insulating layers and a first semiconductor layer not containing impurities are formed on the gate electrode,
A second semiconductor layer containing a pair of impurities to be a source / drain of an insulated gate transistor is formed on the first semiconductor layer,
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display portion, and the transparent conductive layer that is a part of the scanning line is exposed in the opening,
A source wiring (signal line) made of one or more second metal layers including a refractory metal layer on the second semiconductor layer and the first transparent insulating substrate; and on the second semiconductor layer; A drain wiring on the first transparent insulating substrate and a part of the pixel electrode, an electrode terminal of the scanning line including the first and second semiconductor layers around the opening, and an image display unit The electrode terminal of the signal line consisting of a part of the signal line is formed in the outer region,
A liquid crystal display device, wherein a passivation insulating layer having openings on the pixel electrodes and on the electrode terminals of the scanning lines and signal lines is formed on the first transparent insulating substrate. Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
At least a scanning line comprising a transparent conductive layer and a first metal layer on one main surface of the first transparent insulating substrate and having an insulating layer on its side surface and the first metal layer as part of the peripheral portion Laminated transparent conductive pixel electrodes are formed,
One or more gate insulating layers and a first semiconductor layer not containing impurities are formed on the gate electrode,
A second semiconductor layer containing a pair of impurities to be a source / drain of an insulated gate transistor is formed on the first semiconductor layer,
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display portion, and the transparent conductive layer that is a part of the scanning line is exposed in the opening,
A source wiring (signal line) made of one or more second metal layers including a refractory metal layer on the second semiconductor layer and the first transparent insulating substrate; and on the second semiconductor layer; Similarly, the drain wiring on the first transparent insulating substrate and a part of the first metal layer in the peripheral portion of the pixel electrode, and the first and second semiconductor layers in the periphery of the opening portion are also scanned. A line electrode terminal and a signal line electrode terminal formed of a part of the signal line in a region outside the image display unit,
A liquid crystal display device, wherein a passivation insulating layer having openings on the pixel electrodes and on the electrode terminals of the scanning lines and signal lines is formed on the first transparent insulating substrate. At least an insulated gate transistor on one main surface, a scanning line also serving as a gate electrode of the insulated gate transistor and a signal line also serving as a source line, a pixel electrode connected to a drain of the insulated gate transistor, A first transparent insulating substrate in which unit picture elements each having a counter electrode formed at a predetermined distance from the pixel electrode are arranged in a two-dimensional matrix, and opposed to the first transparent insulating substrate In a liquid crystal display device in which liquid crystal is filled between the second transparent insulating substrate or the color filter,
A scanning line and a counter electrode, each of which is composed of at least one first metal layer on one main surface of the first transparent insulating substrate and has an insulating layer on its side surface, are formed.
One or more gate insulating layers are formed on the counter electrode, and one or more gate insulating layers and a first semiconductor layer containing no impurities are formed on the gate electrode,
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display portion, and a part of the scanning line is exposed in the opening,
A second semiconductor layer containing a pair of impurities to be a source / drain of an insulated gate transistor is formed on the first semiconductor layer,
A source wiring (signal line) / drain wiring (picture element electrode) composed of one or more second metal layers including a refractory metal layer on the second semiconductor layer and the first transparent insulating substrate; Similarly, the scanning line electrode terminal including the first and second semiconductor layers around the opening and the signal line electrode terminal formed of a part of the signal line in the region outside the image display unit are formed.
A liquid crystal display device, wherein a passivation insulating layer having openings on electrode terminals of the scanning lines and signal lines is formed on the first transparent insulating substrate. At least an insulated gate transistor on one main surface, a scanning line also serving as a gate electrode of the insulated gate transistor and a signal line also serving as a source line, a pixel electrode connected to a drain of the insulated gate transistor, A first transparent insulating substrate in which unit picture elements each having a counter electrode formed at a predetermined distance from the pixel electrode are arranged in a two-dimensional matrix, and opposed to the first transparent insulating substrate In a liquid crystal display device in which liquid crystal is filled between the second transparent insulating substrate or the color filter,
A scanning line and a counter electrode, each of which is composed of at least one first metal layer on one main surface of the first transparent insulating substrate and has an insulating layer on its side surface, are formed.
One or more gate insulating layers are formed on the counter electrode, and one or more gate insulating layers and a first semiconductor layer containing no impurities are formed on the gate electrode,
An opening is formed in the gate insulating layer on the scanning line in a region outside the image display portion, and a part of the scanning line is exposed in the opening,
A second semiconductor layer containing a pair of impurities to be a source / drain of an insulated gate transistor is formed on the first semiconductor layer,
A source wiring (signal line) / drain wiring (picture element electrode) made of one or more anodizable metal layers including a refractory metal layer on the second semiconductor layer and the first transparent insulating substrate; In addition, an electrode terminal of the scanning line including the first and second semiconductor layers around the opening is formed, and an electrode terminal of the signal line including a part of the signal line is formed in a region outside the image display unit,
An anodic oxide layer is formed on the surface of the source / drain wiring except for the electrode terminal of the signal line,
A liquid crystal display device, wherein a silicon oxide layer is formed on a first semiconductor layer between the source / drain wirings. The insulating layer formed on the side surface of the scanning line is an organic insulating layer, wherein the insulating layer is an organic insulating layer, claim 2, claim 3, claim 4, claim 5, claim 6, claim 7, The liquid crystal display device according to claim 8, claim 9, claim 10, claim 11, and claim 12. The first metal layer is an anodizable metal layer, and the insulating layer formed on the side surface of the scanning line is an anodized layer, wherein the first metal layer is an anodized layer. And a liquid crystal display device according to claim 12. Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
At least one metal layer, one or more gate insulating layers, a first amorphous silicon layer containing no impurities, and a protective insulating layer are sequentially deposited on at least one main surface of the first transparent insulating substrate. Process,
A step of forming a photosensitive resin pattern corresponding to the scanning line and having a film thickness on the contact formation region of the scanning line that is thinner than other regions in a region outside the image display unit;
Sequentially etching the protective insulating layer, the first amorphous silicon layer, the gate insulating layer, and the first metal layer using the photosensitive resin pattern as a mask;
Reducing the thickness of the photosensitive resin pattern to expose a protective insulating layer on the contact formation region; and
Forming an insulating layer on the side surface of the scanning line;
Etching the protective insulating layer, the first amorphous silicon layer, and the gate insulating layer in the contact region using the photosensitive resin pattern having the reduced thickness as a mask to expose a part of the scanning line; ,
Depositing a second amorphous silicon layer containing impurities on the entire surface of the first transparent insulating substrate;
After depositing one or more anodizable metal layers including a refractory metal layer, including source (signal lines) / drain wirings and part of the scanning lines so as to partially overlap the protective insulating layer Forming a scanning line electrode terminal;
A transparent conductive pixel electrode on the first transparent insulating substrate and a part of the drain wiring, a transparent conductive electrode terminal on the signal line in a region outside the image display unit, and an electrode terminal of the scanning line Forming a transparent conductive electrode terminal thereon;
A step of anodizing the source / drain wiring while protecting the transparent conductive pixel electrode and the transparent conductive electrode terminal using the photosensitive resin pattern used for the selective pattern formation of the pixel electrode and the electrode terminal as a mask A method of manufacturing a liquid crystal display device having Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
A transparent conductive layer, a first metal layer, one or more gate insulating layers, a first amorphous silicon layer not containing impurities, and a protective insulating layer are sequentially formed on at least one main surface of the first transparent insulating substrate. A process of depositing;
Corresponding to the electrode terminals of the scanning line and the pixel electrode and the scanning line and the signal line, the film thickness on the electrode terminal forming area of the scanning line and the signal line in the area outside the image display part and the image display part is larger than that in the other areas Forming a thin photosensitive resin pattern,
Sequentially etching the protective insulating layer, the first amorphous silicon layer, the gate insulating layer, the first metal layer, and the transparent conductive layer using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose a protective insulating layer on the pixel electrode and on the electrode terminal formation region of the scanning line and the signal line;
Forming an insulating layer on the side surface of the scanning line;
A protective insulating layer, a first amorphous silicon layer, a gate insulating layer, and a first insulating layer on the pixel electrode, on the electrode terminal region of the scanning line and the signal line, using the reduced photosensitive resin pattern as a mask. Etching the metal layer and exposing the transparent conductive pixel electrode, the electrode terminal of the scanning line, and the electrode terminal of the signal line,
Selectively forming a protective insulating layer narrower than the gate electrode on the gate electrode to expose the first amorphous silicon layer;
Depositing a second amorphous silicon layer containing impurities on the entire surface of the first transparent insulating substrate;
After depositing one or more second metal layers including a refractory metal layer, a photosensitive organic insulating layer is formed on the surface including a part of the electrode terminal of the signal line so as to partially overlap the protective insulating layer. A method for manufacturing a liquid crystal display device, which includes a step of forming a drain wiring including a part of a pixel electrode in the same manner as a source wiring (signal line). Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
A transparent conductive layer, a first metal layer, one or more gate insulating layers, a first amorphous silicon layer not containing impurities, and a protective insulating layer are sequentially formed on at least one main surface of the first transparent insulating substrate. A process of depositing;
A photosensitive resin pattern corresponding to the scanning line, the pixel electrode, and the electrode terminal of the scanning line, the film thickness on the electrode terminal forming area of the scanning line being thinner on the pixel electrode and the area outside the image display area than other areas. Forming a step;
Sequentially etching the protective insulating layer, the first amorphous silicon layer, the gate insulating layer, the first metal layer, and the transparent conductive layer using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose a protective insulating layer on the pixel electrode and on the electrode terminal formation region of the scanning line;
Forming an insulating layer on the side surface of the scanning line;
The protective insulating layer, the first amorphous silicon layer, the gate insulating layer, and the first metal layer on the picture element electrode and on the electrode terminal region of the scanning line using the photosensitive resin pattern having the reduced thickness as a mask. Etching the transparent conductive pixel electrode and exposing a part of the scanning line,
Selectively forming a protective insulating layer narrower than the gate electrode on the gate electrode to expose the first amorphous silicon layer;
Depositing a second amorphous silicon layer containing impurities on the entire surface of the first transparent insulating substrate;
After the deposition of one or more second metal layers including the refractory metal layer, the protective insulating layer partially overlaps the source wiring (signal line), and the drain wiring also includes a part of the pixel electrode; Corresponding to the electrode terminal of the scanning line including a part of the scanning line and the electrode terminal of the signal line consisting of a part of the signal line in the region outside the image display portion, the film thickness on the signal line is larger than that of the other region. Forming a thick photosensitive organic insulating layer pattern;
Using the photosensitive organic insulating layer pattern as a mask, the second metal layer, the second amorphous silicon layer, and the first amorphous silicon layer are selectively removed to form source / drain wirings, scanning lines, and signals. Forming a wire electrode terminal;
A method of manufacturing a liquid crystal display device, comprising: exposing a drain wiring line, a scanning line, and a signal line electrode terminal by reducing the film thickness of the photosensitive organic insulating layer pattern. Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
A transparent conductive layer, a first metal layer, one or more gate insulating layers, a first amorphous silicon layer not containing impurities, and a protective insulating layer are sequentially formed on at least one main surface of the first transparent insulating substrate. A process of depositing;
A photosensitive resin pattern corresponding to the scanning line, the pixel electrode, and the electrode terminal of the scanning line, the film thickness on the electrode terminal forming area of the scanning line being thinner on the pixel electrode and the area outside the image display area than other areas. Forming a step;
Sequentially etching the protective insulating layer, the first amorphous silicon layer, the gate insulating layer, the first metal layer, and the transparent conductive layer using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose a protective insulating layer on the pixel electrode and on the electrode terminal formation region of the scanning line;
Forming an insulating layer on the side surface of the scanning line;
The protective insulating layer, the first amorphous silicon layer, the gate insulating layer, and the first metal layer on the picture element electrode and on the electrode terminal region of the scanning line using the photosensitive resin pattern having the reduced thickness as a mask. Etching the transparent conductive pixel electrode and exposing a part of the scanning line,
Selectively forming a protective insulating layer narrower than the gate electrode on the gate electrode to expose the first amorphous silicon layer;
Depositing a second amorphous silicon layer containing impurities on the entire surface of the first transparent insulating substrate;
After depositing one or more anodizable metal layers including a refractory metal layer, the protective insulating layer partially overlaps the source wiring (signal line), the drain wiring also including a pixel electrode, and the scanning Corresponding to the electrode terminal of the scanning line including a part of the line and the electrode terminal of the signal line consisting of a part of the signal line in the region outside the image display portion, the film thickness on the electrode terminal of the scanning line and the signal line is Forming a photosensitive resin pattern thicker than other regions;
Using the photosensitive resin pattern as a mask, the anodizable metal layer, the second amorphous silicon layer, and the first amorphous silicon layer are selectively removed to form source / drain wirings, scanning lines, and signal lines. Forming an electrode terminal of
Reducing the film thickness of the photosensitive resin pattern to expose the source / drain wiring; and
A method of manufacturing a liquid crystal display device, comprising a step of anodizing a source / drain wiring while protecting the electrode terminal. At least an insulated gate transistor on one main surface, a scanning line also serving as a gate electrode of the insulated gate transistor and a signal line also serving as a source line, a pixel electrode connected to a drain of the insulated gate transistor, A first transparent insulating substrate in which unit picture elements each having a counter electrode formed at a predetermined distance from the pixel electrode are arranged in a two-dimensional matrix, and opposed to the first transparent insulating substrate In a liquid crystal display device in which liquid crystal is filled between the second transparent insulating substrate or the color filter,
At least one first metal layer, one or more gate insulating layers, a first amorphous silicon layer not containing impurities, and a protective insulating layer are sequentially formed on at least one main surface of the first transparent insulating substrate. A process of depositing;
A step of forming a photosensitive resin pattern corresponding to the scanning line and the counter electrode and having a film thickness on the contact formation region of the scanning line that is thinner than other regions in the region outside the image display unit;
Sequentially etching the protective insulating layer, the first amorphous silicon layer, the gate insulating layer, and the first metal layer using the photosensitive resin pattern as a mask;
Reducing the thickness of the photosensitive resin pattern to expose a protective insulating layer on the contact formation region; and
Forming an insulating layer on the side surfaces of the scanning line and the counter electrode;
Etching the protective insulating layer, the first amorphous silicon layer, and the gate insulating layer in the contact region using the photosensitive resin pattern having the reduced thickness as a mask to expose a part of the scanning line; ,
Selectively forming a protective insulating layer narrower than the gate electrode on the gate electrode to expose the first amorphous silicon layer;
Depositing a second amorphous silicon layer containing impurities on the entire surface of the first transparent insulating substrate;
After depositing one or more second metal layers including a refractory metal layer, the protective insulating layer partially overlaps the source wiring (signal line) / drain wiring (pixel electrode), and part of the scanning line A photosensitive organic insulating layer corresponding to the electrode terminal of the scanning line and the electrode terminal of the signal line formed of a part of the signal line in the region outside the image display portion, and having a thicker film thickness on the signal line than the other region Forming a pattern;
Using the photosensitive organic insulating layer pattern as a mask, the second metal layer, the second amorphous silicon layer, and the first amorphous silicon layer are selectively removed to form source / drain wirings, scanning lines, and signals. Forming a wire electrode terminal;
A method of manufacturing a liquid crystal display device, comprising: exposing a drain wiring line, a scanning line, and a signal line electrode terminal by reducing the film thickness of the photosensitive organic insulating layer pattern. At least an insulated gate transistor on one main surface, a scanning line also serving as a gate electrode of the insulated gate transistor and a signal line also serving as a source line, a pixel electrode connected to a drain of the insulated gate transistor, A first transparent insulating substrate in which unit picture elements each having a counter electrode formed at a predetermined distance from the pixel electrode are arranged in a two-dimensional matrix, and opposed to the first transparent insulating substrate In a liquid crystal display device in which liquid crystal is filled between the second transparent insulating substrate or the color filter,
At least one first metal layer, one or more gate insulating layers, a first amorphous silicon layer not containing impurities, and a protective insulating layer are sequentially formed on at least one main surface of the first transparent insulating substrate. A process of depositing;
A step of forming a photosensitive resin pattern corresponding to the scanning line and the counter electrode and having a film thickness on the contact formation region of the scanning line that is thinner than other regions in the region outside the image display unit;
Sequentially etching the protective insulating layer, the first amorphous silicon layer, the gate insulating layer, and the first metal layer using the photosensitive resin pattern as a mask;
Reducing the thickness of the photosensitive resin pattern to expose a protective insulating layer on the contact formation region; and
Forming an insulating layer on the side surfaces of the scanning line and the counter electrode;
Etching the protective insulating layer, the first amorphous silicon layer, and the gate insulating layer in the contact region using the photosensitive resin pattern having the reduced thickness as a mask to expose a part of the scanning line; ,
Selectively forming a protective insulating layer narrower than the gate electrode on the gate electrode to expose the first amorphous silicon layer;
Depositing a second amorphous silicon layer containing impurities on the entire surface of the first transparent insulating substrate;
After depositing one or more anodizable metal layers including a refractory metal layer, the protective insulating layer partially overlaps the source wiring (signal line) / drain wiring (picture element electrode) and one of the scanning lines. Forming a photosensitive resin pattern including a portion corresponding to the electrode terminal of the scanning line and the electrode terminal of the signal line formed of a part of the signal line, the film thickness on the electrode terminal being thicker than other regions; ,
Using the photosensitive resin pattern as a mask, the anodizable metal layer, the second amorphous silicon layer, and the first amorphous silicon layer are selectively removed to form source / drain wirings, scanning lines, and signal lines. Forming an electrode terminal of
Reducing the film thickness of the photosensitive resin pattern to expose the source / drain wiring; and
A method of manufacturing a liquid crystal display device, comprising a step of anodizing a source / drain wiring while protecting the electrode terminal. Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
A transparent conductive layer, a first metal layer, one or more gate insulating layers, a first amorphous silicon layer containing no impurities, and a second containing impurities on at least one main surface of the first transparent insulating substrate. Sequentially depositing the amorphous silicon layers;
A step of forming a photosensitive resin pattern corresponding to the scanning line and the pixel electrode, and having a film thickness on the contact formation region of the scanning line thinner than other regions on the pixel electrode and outside the image display unit;
Sequentially etching the second amorphous silicon layer, the first amorphous silicon layer, the gate insulating layer, the first metal layer, and the transparent conductive layer using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose a second amorphous silicon layer on the pixel electrode and the contact formation region;
Forming an insulating layer on the side surface of the scanning line;
Using the reduced photosensitive resin pattern as a mask, the second amorphous silicon layer, the first amorphous silicon layer, the gate insulating layer, and the first metal layer on the pixel electrode and in the contact region Etching the transparent conductive pixel electrode and exposing a part of the scanning line,
Selectively forming a second amorphous silicon layer and a first amorphous silicon layer on the gate electrode to expose the gate insulating layer on the scan line;
After depositing one or more second metal layers including the refractory metal layer, the gate electrode partially overlaps the source wiring (signal line), and also includes a part of the pixel electrode, the drain wiring, Selectively forming an electrode terminal of the scanning line including a part of the scanning line and an electrode terminal of the signal line formed of a part of the signal line;
Removing the second amorphous silicon layer between the source / drain wirings;
A method of manufacturing a liquid crystal display device, comprising: forming a passivation insulating layer having an opening on the first transparent insulating substrate on the pixel electrodes and on the scanning line and signal line electrode terminals. Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
A transparent conductive layer, a first metal layer, one or more gate insulating layers, a first amorphous silicon layer containing no impurities, and a second containing impurities on at least one main surface of the first transparent insulating substrate. Sequentially depositing the amorphous silicon layers;
A step of forming a photosensitive resin pattern corresponding to the scanning line and the pixel electrode, and having a film thickness on the contact formation region of the scanning line thinner than other regions on the pixel electrode and outside the image display unit;
Sequentially etching the second amorphous silicon layer, the first amorphous silicon layer, the gate insulating layer, the first metal layer, and the transparent conductive layer using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose a second amorphous silicon layer on the pixel electrode and the contact formation region;
Forming an insulating layer on the side surface of the scanning line;
Using the reduced photosensitive resin pattern as a mask, the second amorphous silicon layer, the first amorphous silicon layer, the gate insulating layer, and the first metal layer on the pixel electrode and in the contact region Etching the transparent conductive pixel electrode and exposing a part of the scanning line,
Selectively forming a second amorphous silicon layer and a first amorphous silicon layer on the gate electrode to expose the gate insulating layer on the scan line;
After depositing one or more anodizable metal layers including a refractory metal layer, the gate electrode partially overlaps the source wiring (signal line), and also includes a part of the pixel electrode, the drain wiring, Corresponding to the electrode terminal of the scanning line including a part of the scanning line and the electrode terminal of the signal line consisting of a part of the signal line in the region outside the image display portion, the film thickness on the electrode terminal of the scanning line and the signal line Forming a photosensitive resin pattern that is thicker than other regions;
Selectively removing an anodizable metal layer using the photosensitive resin pattern as a mask to form source / drain wirings, and electrode terminals for scanning lines and signal lines;
Reducing the film thickness of the photosensitive resin pattern to expose the source / drain wiring; and
A method of manufacturing a liquid crystal display device comprising a step of anodizing a source / drain wiring and an amorphous silicon layer between the source / drain wiring while protecting the electrode terminal. Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
A transparent conductive layer, a first metal layer, one or more gate insulating layers, a first amorphous silicon layer containing no impurities, and a second containing impurities on at least one main surface of the first transparent insulating substrate. Sequentially depositing the amorphous silicon layers;
A step of forming a photosensitive resin pattern corresponding to the scanning line and the pixel electrode, and having a film thickness on the contact formation region of the scanning line thinner than other regions on the pixel electrode and outside the image display unit;
Sequentially etching the second amorphous silicon layer, the first amorphous silicon layer, the gate insulating layer, the first metal layer, and the transparent conductive layer using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose a second amorphous silicon layer on the pixel electrode and the contact formation region;
Forming an insulating layer on the side surface of the scanning line;
Using the reduced photosensitive resin pattern as a mask, the second amorphous silicon layer, the first amorphous silicon layer, the gate insulating layer, and the first metal layer on the pixel electrode and in the contact region Etching the transparent conductive pixel electrode and exposing a part of the scanning line,
After depositing one or more second metal layers including the refractory metal layer, the gate electrode partially overlaps the source wiring (signal line), and the drain wiring including the part of the pixel electrode and the source Corresponding to the channel region between the drain wiring, the electrode terminal of the scanning line including a part of the scanning line, and the electrode terminal of the signal line consisting of a part of the signal line, the film thickness of the channel region is other than Forming a photosensitive resin pattern thinner than the area;
Using the photosensitive resin pattern as a mask, the second metal layer, the second amorphous silicon layer, and the first amorphous silicon layer are selectively removed to form source / drain wirings, scanning lines, and signal lines. Selectively forming electrode terminals;
Reducing the film thickness of the photosensitive resin pattern to expose the second metal layer in the channel region;
Selectively removing the second metal layer and the second amorphous silicon layer in the channel region using the photosensitive resin pattern having a reduced thickness as a mask;
A method of manufacturing a liquid crystal display device, comprising: forming a passivation insulating layer having an opening on the first transparent insulating substrate on the pixel electrodes and on the scanning line and signal line electrode terminals. Two unit picture elements each having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to the drain wiring on one main surface. A liquid crystal display device in which a liquid crystal is filled between a first transparent insulating substrate arranged in a three-dimensional matrix and a second transparent insulating substrate or a color filter facing the first transparent insulating substrate. In
A transparent conductive layer, a first metal layer, one or more gate insulating layers, a first amorphous silicon layer containing no impurities, and a second containing impurities on at least one main surface of the first transparent insulating substrate. Sequentially depositing the amorphous silicon layers;
A step of forming a photosensitive resin pattern corresponding to the scanning line and the pixel electrode, and having a film thickness on the contact formation region of the scanning line thinner than other regions on the pixel electrode and outside the image display unit;
Sequentially etching the second amorphous silicon layer, the first amorphous silicon layer, the gate insulating layer, the first metal layer, and the transparent conductive layer using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose a second amorphous silicon layer on the pixel electrode and the contact formation region;
Forming an insulating layer on the side surface of the scanning line;
Etching the second amorphous silicon layer, the first amorphous silicon layer, and the gate insulating layer on the pixel electrode, the contact region using the photosensitive resin pattern with the reduced thickness as a mask. A step of exposing a part of a scanning line and a pixel electrode made of one metal layer;
After depositing one or more second metal layers including the refractory metal layer, the gate electrode partially overlaps the source wiring (signal line), and the drain wiring including the part of the pixel electrode and the source Corresponding to the channel region between the drain wiring, the electrode terminal of the scanning line including a part of the scanning line, and the electrode terminal of the signal line consisting of a part of the signal line, the film thickness of the channel region is other than Forming a photosensitive resin pattern thinner than the area;
Using the photosensitive resin pattern as a mask, the second metal layer, the second amorphous silicon layer, and the first amorphous silicon layer are selectively removed to form source / drain wirings, scanning lines, and signal lines. Selectively forming electrode terminals;
Reducing the film thickness of the photosensitive resin pattern to expose the second metal layer in the channel region;
The second metal layer and the second amorphous silicon layer in the channel region are selectively removed using the photosensitive resin pattern having the reduced thickness as a mask, and the first metal on the pixel electrode is removed. Removing the layer to expose the transparent conductive pixel electrode;
A method of manufacturing a liquid crystal display device, comprising: forming a passivation insulating layer having openings on the transparent conductive picture element electrodes and electrode terminals of scanning lines and signal lines on the first transparent insulating substrate. At least an insulated gate transistor on one main surface, a scanning line also serving as a gate electrode of the insulated gate transistor and a signal line also serving as a source line, a pixel electrode connected to a drain of the insulated gate transistor, A first transparent insulating substrate in which unit picture elements each having a counter electrode formed at a predetermined distance from the pixel electrode are arranged in a two-dimensional matrix, and opposed to the first transparent insulating substrate In a liquid crystal display device in which liquid crystal is filled between the second transparent insulating substrate or the color filter,
At least a first metal layer, one or more gate insulating layers, a first amorphous silicon layer not containing impurities, and a second amorphous containing impurities, on at least one main surface of the first transparent insulating substrate Sequentially depositing silicon layers;
A step of forming a photosensitive resin pattern corresponding to the scanning line and the counter electrode and having a film thickness on the contact formation region of the scanning line that is thinner than other regions in the region outside the image display unit;
Sequentially etching the second amorphous silicon layer, the first amorphous silicon layer, the gate insulating layer, and the first metal layer using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose the second amorphous silicon layer on the contact formation region;
Forming an insulating layer on the side surface of the scanning line;
A portion of the scanning line is etched by etching the second amorphous silicon layer, the first amorphous silicon layer, and the gate insulating layer in the contact region using the photosensitive resin pattern having the reduced thickness as a mask. Exposing the step,
After depositing one or more second metal layers including the refractory metal layer, the gate electrode partially overlaps the source wiring (signal line) / drain wiring (pixel electrode) and the channel region between the source / drain wiring And a photosensitive resin corresponding to the electrode terminal of the scanning line including a part of the scanning line and the electrode terminal of the signal line including a part of the signal line, wherein the channel region is thinner than the other regions Forming a pattern;
Using the photosensitive resin pattern as a mask, the second metal layer, the second amorphous silicon layer, and the first amorphous silicon layer are selectively removed to form source / drain wirings, scanning lines, and signal lines. Selectively forming electrode terminals;
Reducing the film thickness of the photosensitive resin pattern to expose the second metal layer in the channel region;
Selectively removing the second metal layer and the second amorphous silicon layer in the channel region using the photosensitive resin pattern having a reduced thickness as a mask;
A method for manufacturing a liquid crystal display device, comprising: forming a passivation insulating layer having openings on electrode terminals of the scanning lines and signal lines on the first transparent insulating substrate. At least an insulated gate transistor on one main surface, a scanning line also serving as a gate electrode of the insulated gate transistor and a signal line also serving as a source line, a pixel electrode connected to a drain of the insulated gate transistor, A first transparent insulating substrate in which unit picture elements each having a counter electrode formed at a predetermined distance from the pixel electrode are arranged in a two-dimensional matrix, and opposed to the first transparent insulating substrate In a liquid crystal display device in which liquid crystal is filled between the second transparent insulating substrate or the color filter,
At least a first metal layer, one or more gate insulating layers, a first amorphous silicon layer not containing impurities, and a second amorphous containing impurities, on at least one main surface of the first transparent insulating substrate Sequentially depositing silicon layers;
A step of forming a photosensitive resin pattern corresponding to the scanning line and the counter electrode and having a film thickness on the contact formation region of the scanning line that is thinner than other regions in the region outside the image display unit;
Sequentially etching the second amorphous silicon layer, the first amorphous silicon layer, the gate insulating layer, and the first metal layer using the photosensitive resin pattern as a mask;
Reducing the film thickness of the photosensitive resin pattern to expose the second amorphous silicon layer on the contact formation region;
Forming an insulating layer on the side surface of the scanning line;
A portion of the scanning line is etched by etching the second amorphous silicon layer, the first amorphous silicon layer, and the gate insulating layer in the contact region using the photosensitive resin pattern having the reduced thickness as a mask. Exposing the step,
Selectively forming a second amorphous silicon layer and a first amorphous silicon layer on the gate electrode to expose the gate insulating layer on the scanning line and the counter electrode;
After depositing one or more anodizable metal layers including a refractory metal layer, the gate electrode partially overlaps the source wiring (signal line) / drain wiring (picture element electrode) and a part of the scanning line. In correspondence with the electrode terminal of the scanning line and the electrode terminal of the signal line formed of a part of the signal line in the region outside the image display portion, the film thickness on the electrode terminal of the scanning line and the signal line is larger than that in the other region. Forming a thick photosensitive resin pattern;
Selectively removing an anodizable metal layer using the photosensitive resin pattern as a mask to form source / drain wirings, and electrode terminals for scanning lines and signal lines;
Reducing the film thickness of the photosensitive resin pattern to expose the source / drain wiring; and
A method of manufacturing a liquid crystal display device comprising a step of anodizing a source / drain wiring and an amorphous silicon layer between the source / drain wiring while protecting the electrode terminal. The insulating layer formed on the side surface of the scanning line is an organic insulating layer and is formed by electrodeposition, wherein the insulating layer is formed by electrodeposition. A method for manufacturing a liquid crystal display device according to claim 21, claim 22, claim 23, claim 24, claim 25, and claim 26. The insulating layer formed on the side surface of the scanning line, the first metal layer being made of an anodizable metal layer, is formed by anodic oxidation. 25. A method for manufacturing a liquid crystal display device according to claim 25.

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