JP2005051135A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make the surface of an insulating film formed on a semiconductor substrate even having a high density and a low density regions of a convex part flat, and to decrease the variations in film thickness. <P>SOLUTION: When forming a memory cell array region having a high density convex part and a periphery circuit region having a low density convex part on the semiconductor substrate, after forming a two-dimensional arrangement of capacitor 216 as a memory cell in the memory cell array region, the insulating film 217 is formed all over the surface of the semiconductor substrate. After that, a long linear concave part 218 in a narrow direction of a gap between the capacitors 216 two dimensionally arranged in the memory cell array region is formed on the insulating film 217 so as to run through on the plurality of capacitors 216, and then the surface of the insulating film 217 is made flat by the CMP method. This method can decrease the variations in the film thickness of the insulating film 217 and make the surface of the insulating film 217 flat. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, and in particular, a semiconductor device in which an interlayer insulating film is formed on a semiconductor substrate having a region having a high density of protrusions and a region having a low density of protrusions, and the surface thereof is planarized. It relates to the manufacturing method.

  With the recent miniaturization of semiconductor devices, for example, a step difference between a high density area of convex parts such as a transistor, a capacitor, and a memory cell and a low density area of the convex parts, such as a memory cell array and a peripheral circuit area. Elimination is important. If such a step exists, problems such as insufficient focus margin of photolithography, short-circuiting or disconnection of wiring due to the step, or high resistance of the connection hole or disconnection occur.

  As a method for solving such a problem, a general conventional manufacturing method will be described with reference to FIG. Here, an example of a ferroelectric memory (FeRAM) is given.

  First, as shown in FIG. 15A, a capacitor 701 having a general stack structure is formed. Next, as shown in FIG. 15B, an insulating film 702 is formed on the entire surface. Next, as shown in FIG. 15C, the insulating film 702 on the entire memory cell array is etched to form a recess 703. Next, as shown in FIG. 15D, the insulating film 702 is polished and planarized by CMP. By this method, the step of the insulating film 702 can be reduced in advance, and planarization during CMP can be facilitated.

  An example of such a manufacturing method is described in Patent Document 1, for example. In this example, the interlayer insulating film on the DRAM memory cell is etched to form a recess. However, the position of the end of the recess in the boundary region between the memory cell region and the peripheral circuit region is controlled, for example, as shown in FIG. ) Within 10 μm, the large area convex pattern of 10 μm or more is eliminated, and the level difference between the high density area and the low density area of the convexity is made almost completely flat by the CMP method. In addition, the ratio of the distance L to the height H (distance L / height H) in FIG.

  In the example of Patent Document 2, the position of the end of the recess in the boundary area of the large area pattern is controlled, and for example, by making the distance L in FIG. The level difference between the high density area and the low density area of the protrusions is almost completely flattened.

Further, in the example of Patent Document 3, the chemistry of the insulating film, such as a dot shape or a line shape, is not formed in the insulating film over the entire region of the high density of the convex portions (for example, the memory cell array). The shape of the concave portion is optimized regardless of the arrangement of the convex portion, depending on the polishing amount of the mechanical polishing, the material to be polished, and the shape and size of the high density region of the convex portion. By this method, accumulation of polishing slurry that occurs when the concave portions are formed on the entire surface of the high density region of the convex portions is prevented.
Japanese Patent Laid-Open No. 10-284702 Japanese Unexamined Patent Publication No. 7-235537 JP 2000-269179 A

  FIG. 16 is a process cross-sectional view for illustrating problems of the conventional manufacturing method. As in FIG. 15, an insulating film 801 is formed on a semiconductor substrate having a convex portion, but the actual shape of the insulating film 801 is not flat as in FIG. 15B, but in FIG. 16B. As shown, the shape of the convex portion is reflected. Next, the recess 802 is formed in the entire memory cell array by general wet etching or dry etching, and the shape also reflects the shape of the insulating film as shown in FIG.

  Next, when the insulating film 801 is planarized by the CMP method, for example, if the lowest surface of the recess is lower than the polished surface, a local step 803 remains as shown in FIG.

  In order to prevent the occurrence of this local step, it is necessary to increase the thickness of the insulating film 801 to be formed. However, in this case, the thickness of the insulating film 801 after polishing increases, and the film thickness variation also increases. Further, when the polishing amount is increased in order to reduce the thickness of the insulating film 801 after polishing, the variation in the polishing amount increases, and the variation in the thickness of the insulating film 801 after polishing further increases. Therefore, the connection reliability of the connection hole formed in the insulating film 801 in the subsequent process (the certainty of whether it can be connected) decreases.

  An object of the present invention is to manufacture a semiconductor device capable of flattening the surface of an insulating film formed on a semiconductor substrate having a high density area and a low density area of protrusions and reducing variations in the thickness of the insulating film. It is to provide a method.

  The method of manufacturing a semiconductor device according to claim 1, wherein the density of the convex portions is high, and the density of the convex portions is such that the convex portions are arranged so that there are a narrow direction and a wide direction between adjacent convex portions. A first step of forming an insulating film so as to cover a region having a high density of protrusions and a region having a low density of protrusions on a semiconductor substrate having a low area of the region; and a region having a high density of protrusions A second step of forming recesses in the insulating film so that the interval between adjacent protrusions is long in a narrow direction and passes over the plurality of protrusions, and a third step of flattening the surface of the insulating film by polishing Process.

  By this method, even when the insulating film to be formed is thin, local steps can be prevented, and a recess sufficient to flatten the step between the high density area and the low density area of the protrusion is formed in the insulating film. be able to. As a result, variations in the thickness of the insulating film after polishing can be reduced.

  The method for manufacturing a semiconductor device according to claim 2 is the method for manufacturing a semiconductor device according to claim 1, characterized in that an interval in a direction in which an interval between adjacent convex portions is narrow is 0.1 μm or less.

  According to this method, the embedded surface of the insulating film in a narrow space (interval) is formed at a higher position than the embedded surface of the insulating film in a wide space, and even if the insulating film to be formed is thinner, the convex portion It is possible to form a recess in the insulating film sufficient to flatten the step between the high density region and the low region. As a result, the thickness variation of the insulating film after polishing can be further reduced.

  The method for manufacturing a semiconductor device according to claim 3 is the method for manufacturing a semiconductor device according to claim 1, wherein the interval in the direction in which the interval between adjacent projections is wide is not more than twice the height of the projection. It is characterized by.

  In order to fill the convex portion with the insulating film, a film thickness that is at least the height of the convex portion is required. When the gap in the wide direction is less than twice the height of the convex part, the space between the convex parts in the wide direction can be completely filled with the minimum insulation film thickness to prevent the occurrence of local steps Can do.

  The method for manufacturing a semiconductor device according to claim 4 is the method for manufacturing a semiconductor device according to claim 1, wherein the concave portion is formed even on a region including the convex portion at the extreme end of the region having a high density of convex portions. It is characterized by.

  By this method, by removing the convex portions of the insulating film having a certain size or larger in advance, the level difference after polishing can be further reduced.

  The method for manufacturing a semiconductor device according to claim 5 is the method for manufacturing a semiconductor device according to claim 1, wherein the concave portion is not formed on the convex portion at the extreme end of the region where the density of the convex portions is high. And

  This method prevents the formation of fine convex portions of the insulating film at the extreme end of the high density region of the convex portions, and prevents the fine convex portions (insulating film) from being broken during polishing. This eliminates pattern defects and scratches.

  The method of manufacturing a semiconductor device according to claim 6, wherein the density of the protrusions is increased on a semiconductor substrate having a high density area of the protrusions on which the line-shaped protrusions are arranged and a low density area of the protrusions. In the first step of forming the insulating film so as to cover the high area and the low density area of the convex part, and in the high density area of the convex part, the line shape is formed on the insulating film on the line-shaped convex part. A second step of forming the recess and a third step of flattening the surface of the insulating film by polishing are included.

  By this method, even when the insulating film is thin, it is possible to prevent the occurrence of a local step and to form a recess in the insulating film sufficient to flatten the step between the high density area and the low density area of the protrusion. it can. As a result, variations in the thickness of the insulating film after polishing can be reduced.

  The method of manufacturing a semiconductor device according to claim 7 is the method of manufacturing a semiconductor device according to claim 1 or 6, wherein the third step exposes the surface of the convex portion in the region where the density of the convex portion is high. To do.

  As described above, when the insulating film is flattened and the surface of the convex portion is exposed, it is necessary to reduce the variation in the thickness of the insulating film as compared with the case where the insulating film is only flattened. Therefore, the effect of the present invention is great.

  A method for manufacturing a semiconductor device according to claim 8 is the method for manufacturing a semiconductor device according to claim 1 or 6, wherein the recess is formed by wet etching.

  Since this method has good controllability of the wet etching rate and uniformity, it is possible to reduce the shape variation of the recesses.

  A method for manufacturing a semiconductor device according to a ninth aspect is characterized in that, in the method for manufacturing a semiconductor device according to the first or sixth aspect, the recess is formed by dry etching.

  In this method, it is easy to control the shape of the recess by dry etching anisotropic etching.

  The method for manufacturing a semiconductor device according to claim 10 is the method for manufacturing a semiconductor device according to claim 1 or 6, wherein the lowest surface of the surface of the insulating film in the portion where the recess is formed is a region where the density of the protrusion is low. A concave portion is formed so as to be almost the same height as the surface of the insulating film in a portion having no convex portion below.

  By this method, it is possible to effectively reduce the step between the high density area and the low density area of the protrusions.

  11. The method of manufacturing a semiconductor device according to claim 11, wherein the lowest surface of the surface of the insulating film in the portion where the recess is formed is the surface of the insulating film after planarization. A concave portion is formed so as to be at a higher position.

  By this method, the occurrence of local steps can be completely prevented.

  The method for manufacturing a semiconductor device according to claim 12 is the method for manufacturing a semiconductor device according to claim 1 or 6, wherein the polishing volume in the region where the density of the convex portions is low and the density of the convex portions where the concave portions are formed are high. The insulating film and its recess are formed so that the polishing volume in the region is substantially the same.

  By this method, the step between the high density area and the low density area of the protrusions can be made closer to zero.

  A semiconductor device manufacturing method according to a thirteenth aspect is the semiconductor device manufacturing method according to the first or sixth aspect, wherein the insulating film is a heat-meltable insulating film.

  If a heat-meltable film is used in this way, the embedding property of the space between the protrusions is improved, and the space between the protrusions can be embedded with a thinner insulating film, and the occurrence of local steps can be prevented. It is possible to form a recess in the insulating film sufficient to flatten the step between the high density region and the low region. As a result, variations in the thickness of the insulating film after polishing can be reduced.

  A method for manufacturing a semiconductor device according to a fourteenth aspect is the method for manufacturing a semiconductor device according to the thirteenth aspect, wherein the insulating film contains at least one of boron and phosphorus.

  This insulating film has a high heat melting property, and the effect of claim 13 is greater.

According to a fifteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the thirteenth aspect, wherein the insulating film is a silicon oxide film formed using O ₃ and TEOS.

  This insulating film has heat melting properties, and the effect of claim 13 is great. In addition, since it does not contain impurities, it is not necessary to select usage conditions. There is also an advantage that hydrogen is not generated during formation.

  A semiconductor device manufacturing method according to a sixteenth aspect is the semiconductor device manufacturing method according to the first or sixth aspect, wherein the convex portion is a memory cell of a dielectric memory or a part of the memory cell. .

  In a capacitor which is a memory cell of a dielectric memory, it is common to form an oxygen barrier film on the lower electrode and a hydrogen barrier film so as to surround the capacitor upper part and the capacitor. As a result, the height of the capacitor or memory cell is increased. Becomes very high. In such a case, the polished insulating film must be thin and variation must be reduced, and the effect of the present invention is great.

  The semiconductor memory device according to claim 17, wherein a plurality of capacitors including a ferroelectric film are formed on a semiconductor substrate, and a barrier film is formed so as to cover an upper part and a side part of the capacitor or to surround the entire periphery of the capacitor. A semiconductor memory device comprising: a memory cell array region in which an insulating film is formed on a barrier film; and a peripheral circuit region disposed around the memory cell array region on the semiconductor substrate and having an insulating film formed thereon, The variation in the film thickness of the insulating film on the surface of the barrier film formed on the upper part is within 0.3 μm.

  A ferroelectric film is an insulating film formed by etching, such as HDP-NSG, which easily relaxes the level difference on the projection during polishing, and its characteristics deteriorate due to plasma damage. For this reason, it is more difficult to eliminate the level difference between the memory cell array region and the peripheral circuit region in a capacitor including a ferroelectric. In addition, since the ferroelectric film causes characteristic deterioration due to hydrogen, a barrier film that stops the diffusion of hydrogen covering the upper and side portions of the capacitor or the entire periphery of the capacitor is required, and the height of the memory cell array is increased. It gets even higher. However, if the present invention is used, the height variation of the interlayer insulating film on the memory cell from this barrier film can be reduced to 0.3 μm or less, and the reliability of the contact plug with the upper wiring can be ensured.

  The semiconductor memory device according to claim 18 is the semiconductor memory device according to claim 17, wherein the barrier film is a film containing at least one of Ti and Al.

  Such a film can prevent deterioration of the ferroelectric film mainly with respect to hydrogen.

  A semiconductor memory device according to a nineteenth aspect is the semiconductor memory device according to the seventeenth aspect, wherein the barrier film is a SiN film.

  This film can prevent deterioration of the ferroelectric film mainly with respect to hydrogen.

  According to the present invention, even if there are a high density area and a low density area on the semiconductor substrate, the surface of the insulating film formed thereon is divided into a high density area and a low area of the convex area. Steps and local steps can be reduced, flattening can be easily performed, and in-plane variation of the insulating film can be suppressed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a plan view showing an example of a ferroelectric memory (FeRAM) to which a semiconductor device manufacturing method according to an embodiment of the present invention is applied. The FeRAM shown in FIG. 1 includes a peripheral circuit region 101 and a memory cell array region 102 formed on a semiconductor substrate.

  In the peripheral circuit region 101, since elements such as MOSFETs constituting the circuit are formed sparsely, the pattern formed on the surface of the insulating film covering the convex portion such as the interlayer insulating film is a fine pattern on the order of μm. In contrast, in the memory cell array region 102, since elements such as MOSFETs are formed at a high density, the insulating film is embedded to some extent between the convex portions, and the pattern formed on the surface has a large size of several mm. It becomes an area pattern. If an insulating film in which such a fine pattern and a large area pattern are mixed is polished and planarized by CMP, the large area pattern is harder to be polished than the fine pattern, so that complete planarization is difficult. Moreover, if it is made close to perfect flatness, the amount of polishing increases and the in-plane variation of the surface of the insulating film increases. In FeRAM, since capacitors are formed in a high density in the memory cell array region, it is difficult to completely planarize the peripheral circuit region 101 and the memory cell array region 102 for the same reason for the insulating film thereon.

  However, if the manufacturing method described below is used, a concave portion is formed in the insulating film on the convex portion, and then flattened by the CMP method to improve the flatness, and further, in-plane variation of the insulating film is reduced. Can be reduced.

  Hereinafter, the manufacturing method of the first embodiment will be described with reference to FIGS. 2 to 4 are cross-sectional views showing an example of the manufacturing method of the semiconductor device of Embodiment 1 in the order of the steps.

  As shown in FIG. 2A, a BPSG is formed on a semiconductor substrate 201 on which an STI (Shallow Trench Isolation) isolation region 202 and a transistor including a high-concentration impurity layer 203, a gate insulating film 204, and a gate electrode 205 are formed. An insulating film 206 such as HDP-NSG or O3NSG is formed by, for example, 0.6 to 1.2 μm by CVD, and the first interlayer insulating film 206 has a thickness of 0.4 to 0.8 μm by using CMP or the like. To form. Next, as shown in FIG. 2B, a resist pattern is formed at a desired position of the insulating film 206, and a first contact hole 207 is formed in the insulating film 206 by dry etching using the resist pattern as a mask.

  Next, as shown in FIG. 2 (c), a conductive film 208 (for example, a metal such as tungsten, molybdenum, titanium, titanium nitride, tantalum nitride, or metal silicide) is formed on the entire surface by sputtering, CVD, or plating. This metal silicide forms Ti, Ni or Co, Cu, or doped polycrystalline silicon. Next, as shown in FIG. 2D, the conductive film 208 is removed by using an etch back method or a CMP method until the upper surface of the insulating film 206 is exposed, and a contact plug 209 is formed.

  Next, as shown in FIG. 2E, a conductive film (for example, W) is formed on the entire surface, and patterned to be connected to the contact plug 209 using a desired mask, thereby forming a bit wiring 210. . At this time, before forming the conductive film, for example, when the bit wiring 210 is W, an adhesion layer such as TiN / Ti may be formed. The height of the bit wiring 210 is determined by wiring resistance and design rules, and is preferably 20 to 150 nm. Further, when forming a stack type contact with the wiring above the capacitor, a bit wiring pattern (a pattern formed of the same material simultaneously with the bit wiring) so as to cover the contact plug and the one contact plug in advance. Form it.

  Next, as shown in FIG. 2 (f), an insulating film is formed to 200 to 800 nm on the bit wiring 210, and is flattened by using CMP, etch back method or reflow, and a second interlayer insulating film 211 is formed. Form. By this planarization, the capacitor formed on the second interlayer film 211 can be easily formed. In particular, the step due to the bit wiring 210 can be further planarized by using the CMP method.

  Next, as shown in FIG. 3A, a resist pattern is formed at a desired position of the laminated film of the first interlayer insulating film 206 and the second interlayer insulating film 211, and dry etching is performed using the resist pattern as a mask. The second contact hole is formed by sputtering, and the entire surface is made of a conductive film (for example, metal such as tungsten, molybdenum, titanium, titanium nitride, tantalum nitride, metal silicide) by sputtering, CVD, or plating. Metal oxide is Ti, Ni or Co, Cu, or doped polycrystalline silicon), and the conductive film is removed using an etch back method or a CMP method until the upper surface of the insulating film 211 is exposed, A second contact plug 212 is formed.

  Next, as shown in FIG. 3B, a capacitor lower electrode 213, dielectric capacitor film 214, and upper electrode 215 are formed in this order on the entire surface of the wafer. Next, as shown in FIG. 3C, patterning is performed using a desired mask so as to cover the second contact plug 212, thereby forming a capacitor 216. Here, a stack type capacitor structure has been described, but a three-dimensional type or other structure capacitor may be used, and the present invention is not limited to this. Further, although the lower electrode 213, the dielectric capacitor film 214, and the upper electrode 215 are dry-etched at once, the respective films or the laminated film may be dry-etched each time. Furthermore, other methods may be used as long as the shape of the capacitor can be formed. In the case where a film for preventing the deterioration of the dielectric is formed so as to cover the capacitor or to cover the capacitor, the capacitor (memory cell) including the film is regarded as a convex part.

Next, the perovskite system including lead (Pb) such as BST (Ba _x Sr _1-x TiO ₃ ) -based dielectric, PZT (Pb (Zr _x Ti _1-x O ₃ )), which constitutes the dielectric capacitor film 214 In order to crystallize a dielectric or a perovskite-based dielectric containing Bi such as SBT (SrBi ₂ Ta ₂ O ₉ ), sintering is performed at a high temperature in an oxygen atmosphere. Anneal).

  Here, the arrangement of the memory cells in the memory cell array is shown in FIG. In order to reduce the area of the memory cell array 102, the memory cells 301 are regularly arranged as shown in FIG. In the example of FIG. 5, a plurality of memory cells 301 (here, capacitors 216) are two-dimensionally arranged at predetermined intervals (Y, X) in the vertical and horizontal directions, and the vertical intervals Y and , The horizontal distance X is different.

  Next, as shown in FIG. 3D, an insulating film 217 such as BPSG, O3NSG, or HDP-NSG is formed on the entire surface of the wafer by a CVD method or a sputtering method to a thickness of 700 to 1500 nm.

  Here, (a) dot shape, (b) line shape, and (c) concave portion 302 are formed in the entire array as shown in FIG. 6 for the convex portion (capacitor 216 of memory cell 301) having a height of 800 nm. FIG. 7 shows a comparison of the global level difference between the case where this is done and the case where no recess is formed. The dot-shaped concave portion is almost the same as the case where the concave portion is not formed, and the effect of reducing the step difference is small. On the other hand, the line-shaped concave portion can achieve a step reduction effect substantially equivalent to the case where the concave portion is formed in the entire array. Therefore, if the concave portions are formed in a dot shape on the memory cell, the effect of reducing the level difference is small. Therefore, it is desirable to form the concave portions in the line shape or the entire memory cell array.

  Next, as shown in FIG. 3E, recesses 218 that are long in the direction in which the space between adjacent capacitors is narrow and pass over the plurality of capacitors are formed in the memory cell array region. The recess 218 is a portion where the insulating film 217 is removed by etching.

  4A to 4C, the processes from FIGS. 3C to 3E are divided into a narrow direction and a wide direction between the memory cells, and the upper portion from the capacitor 216 is divided. It is shown. When the insulating film 217 is formed on the base on which the capacitor shown in FIG. 4 (a) is mounted as shown in FIG. 4 (b), insulation is caused by the difference between the narrow space and the wide space between the capacitors. The lowermost surface of the surface of the film 217 is different. Next, as shown in FIG. 4C, the horizontal space X between the memory cells shown in FIG. 5 is compared with the vertical space Y, and a long line-shaped recess 218 is formed in the narrow space direction. And no recess is formed in the wide space direction. A line-shaped recess 218 is formed over the plurality of capacitors 216. The dotted line 220 shows the shape of a virtual recess when a recess is also formed in a wide space direction. This is also true when a recess is formed in the entire memory cell array.

  FIG. 3 (e) is a diagram showing a cross section in a narrow direction of the space between the memory cells, which is the same as the conventional FIG. 16 (c), but the difference from the conventional one is the space of FIG. 4 (c). It appears in the cross section in the wide direction.

  Next, as shown in FIG. 4D, the third interlayer insulating film 221 is formed by planarizing the insulating film 217 by CMP. Here, a dotted line 219 in FIG. 4C shows the surface of the insulating film 221 after polishing. If a concave portion is formed in a direction where the space is large, the dotted line 220 is lower than the final polishing surface 219. The step remains as a local step even after polishing. In order to prevent this, it is necessary to increase the thickness of the insulating film. At this time, if the polishing amount is the same, the thickness of the insulating film after polishing increases. Further, when the polishing amount is increased in order to reduce the thickness of the insulating film after polishing, the variation in the thickness of the insulating film 221 after polishing increases.

  Therefore, if the recess is formed so as to include a plurality of memory cells only in the direction in which the space of the memory cells is narrow as in the present invention, the thickness of the insulating film can be reduced while preventing the occurrence of local steps. . Further, as described with reference to FIG. 7, by forming a line-shaped concave portion, a region having a high density of convex portions (memory cell array region 102) and a region having a low density of convex portions (peripheral circuit region 101) The step (global step) can be sufficiently reduced. In addition, since the polishing amount can be reduced, there is an effect that variation in the thickness of the insulating film can be suppressed. Note that the density of convex portions is the ratio of the sum of the areas of all convex portions existing in a certain region (constant area) to the total area of the region.

  As a method for forming the recess 218, it is desirable to form the recess 218 by wet etching using a photoresist as a mask. In the present invention, in order not to leave a local step, it is important to control the shape of the recess, and wet etching excellent in etching surface uniformity and etching rate reproducibility is desirable.

  Further, as a method for forming the recess 218, it is more preferable to form the recess 218 by dry etching using a photoresist as a mask. This is because the dry etching is an anisotropic etching, so that the lateral shape of the concave portion can be easily controlled.

  Next, as shown in FIG. 4E, a contact hole connecting the wiring above the capacitor and the diffusion region of the transistor is formed by the first interlayer insulating film 206, the second interlayer insulating film 211, and the third interlayer insulating film. The film 221 is formed by dry etching using a desired mask, and a conductive film (for example, tungsten, molybdenum, titanium, titanium nitride, tantalum nitride, silicide) is formed on the entire surface by sputtering, CVD, or plating. The metal silicide is formed of Ti, Ni, Co, Cu, or doped polycrystalline silicon), and the top surface of the insulating film 221 is formed using an etch back method or a CMP method. The conductive film is removed until it is exposed, and a third contact plug 222 is formed so that it can be connected to the wiring above the capacitor. When stack type contacts are employed, contact plugs are formed between the second interlayer insulating film 211 and the third interlayer insulating film 221 on the previously formed bit wiring pattern by the same method.

  By the above method, the thickness of the insulating film 221 can be reduced and the variation can be reduced. Therefore, the connection reliability of the contact plug 222 that connects the wiring above the capacitor and the diffusion region of the transistor (high-concentration impurity diffusion layer 203). Improves. Note that the wiring above the capacitor is not shown, but is formed on the insulating film 221 and the contact plug 222 after the contact plug 222 is formed.

  Further, it is desirable that the space in the narrow direction between adjacent convex portions (capacitors 216) is 0.1 μm or less. At this time, as shown in FIG. 4 (b), the buried surface of the insulating film 217 in the space in the narrow direction is formed at a position higher than the buried surface of the insulating film 217 in the space in the wide direction. Even if the thickness of the film 217 is thin, a recess sufficient for flattening the global step can be formed in the insulating film. As a result, variations in the thickness of the insulating film 221 after polishing can be reduced.

  In addition, it is desirable that the space in the wide direction between adjacent convex portions (capacitors 216) is not more than twice the height of the convex portions. In order to fill the convex portion with the insulating film, a film thickness that is at least the height of the convex portion is required. When the space L ′ in the wide direction shown in FIG. 4A is not more than twice the height H ′ of the convex portion, the space between the convex portions in the wide direction may be completely filled with the minimum insulating film thickness. And the occurrence of local steps can be prevented.

  Further, it is desirable to form the recess 218 formed in the memory cell array 102 up to the end of the memory cell array 102 as shown in FIG. At this time, the convex portion of the insulating film 217 having a certain size or larger can be completely eliminated, and the insulating film after CMP can be further planarized. In FIG. 8, only one recess 218 is shown, but the other portions are similarly arranged and formed.

  Further, it is desirable that the recess 218 formed in the memory cell array 102 is formed in a state where the most convex portion (memory cell 301, that is, the capacitor 216) of the memory cell array 102 is left as shown in FIG. As a result, the fine convex portion of the insulating film 217 is not formed at the extreme end of the memory cell array 102, and the fine convex portion can be prevented from being broken during polishing. Scratch due to the insulating film can be eliminated. In FIG. 9, only one recess 218 is shown, but the other portions are similarly arranged and formed.

  In the first embodiment, an FeRAM memory cell has been described as an example of the convex portion. However, the shape of the convex portion is not limited to that of a transistor, a DRAM capacitor, or a wiring.

  Further, when the convex portion is the lower electrode of the capacitor, the insulating film must be planarized by CMP to expose the surface of the lower electrode. Alternatively, after the insulating film is planarized by the CMP method, the surface of the lower electrode needs to be exposed by another method such as dry etching or wet etching. At this time, in order to uniformly expose the surface of the lower electrode, it is necessary to further reduce the film thickness variation of the insulating film rather than the film thickness variation at the time of forming the interlayer insulating film. Become.

(Embodiment 2)
The second embodiment will be described with reference to FIGS.

  Since the manufacturing process of the second embodiment is the same from FIG. 2 (a) to FIG. 3 (a), it is omitted here.

  Subsequently, as shown in FIG. 10A, a conductive film 401 to be a lower electrode is formed by sputtering or CVD. The conductive film 401 is, for example, a single layer of a noble metal film, or a laminated film in which the noble metal film is disposed as the uppermost layer, and the noble metal film is preferably a Pt, Ir, Ru film, or an alloy film containing them, preferably 20 to The film is formed with a thickness of 100 nm on the entire surface by sputtering or CVD. Under the noble metal film, a conductive film may be formed that serves as a barrier against oxidation of the contact plug 212 against the thermal history during dielectric sintering. This conductive barrier film is, for example, TiAlN, or a film containing at least one of Ti and Al, a film containing at least a noble metal film, or a laminated film thereof, or Ir / IrOx / TiAlN. The film thickness is preferably 10 to 200 nm.

  Next, as shown in FIG. 10B, a resist pattern is formed at a desired position, and the lower electrode 402 is formed by dry etching using the resist pattern as a mask. Alternatively, hard mask etching using an insulating film or the like as a mask may be used. Next, as shown in FIG. 10C, a third insulating film such as O3NSG, BPSG or HDP-NSG is formed on the lower electrode 402 and the second interlayer insulating film 211 by the CVD method. The insulating film is flattened by CMP or etch back, the surface of the lower electrode 402 is exposed, and a buried insulating film 403 is formed.

  Next, as shown in FIG. 10D, a ferroelectric film 404 is formed by a spin coating method or a sputtering method, and a conductive film 405 to be an upper electrode is formed thereon by a sputtering method or a CVD method. The conductive film 405 serving as the upper electrode is a film such as Pt, Ir, or IrOx. Next, as shown by a solid line in FIG. 11A, a ferroelectric film 404 and a conductive film 405 are formed so as to straddle a plurality of lower electrodes 402 by lithography and dry etching, and a line-shaped upper electrode 406 and The ferroelectric film 404 is assumed. The cross section at this time is shown in FIG.

Next, the perovskite system containing lead (Pb) such as BST (Ba _x Sr _1-x TiO ₃ ) system dielectric, PZT (Pb (Zr _x Ti _1-x O ₃ )), which constitutes the ferroelectric film 404 In order to crystallize a dielectric or a perovskite-based dielectric containing Bi such as SBT (SrBi ₂ Ta ₂ O ₉ ), sintering is performed at a high temperature in an oxygen atmosphere. Anneal), and this crystallization may be performed after this other step.

  Next, as shown in FIG. 11C, a fourth insulating film 407 such as O3NSG, O3BPSG, HDP-NSG, and P-TEOS is formed on the upper electrode 406 by CVD or sputtering. Next, as shown in FIG. 11D, a line-shaped recess 408 as shown by a dotted line in FIG. 11A is formed in the insulating film 407 on the line-shaped upper electrode 406. The recess 408 is formed by wet etching or dry etching using a photoresist as a mask, as in the first embodiment. Next, as shown in FIG. 12A, the insulating film 407 is planarized by CMP and an interlayer insulating film 409 is formed. Next, as shown in FIG. 12B, contact plugs 410 are formed in the interlayer insulating films (409, 403, 211, 206) to connect the wirings above the capacitors and the diffusion layers 203 of the transistors.

  Here, the FeRAM plate line (the upper electrode 406 and the ferroelectric film 404) has been exemplified as the convex portion having a line shape, but is not limited thereto. Further, instead of the capacitor, for example, a transistor, a part of a capacitor, or a lower electrode / wiring of the capacitor may be used. Furthermore, when it is necessary to expose the surface of the convex portion, it is necessary to further suppress variations in the thickness of the insulating film, and the effect of the present invention is increased.

  Further, in the first and second embodiments, the lowest surface of the surface of the insulating film (217, 407) where the recesses (218, 408) are formed is located below the region where the density of the protrusions is low (peripheral circuit region). It is desirable to form the concave portion so as to be almost the same height as the surface of the insulating film (217, 407) in the portion without the convex portion. As described above, by aligning the surface of the insulating film having no protrusions with the surface of the insulating film in the recesses in advance, the area having high density of protrusions (memory cell array area) and the area having low density (peripheral circuit area) ) Can be reduced.

  In the first and second embodiments, it is desirable that the surface of the recess be formed at a position higher than the surface of the insulating film after planarization by polishing. By this method, the occurrence of local steps can be completely prevented.

  Further, in the first and second embodiments, the insulating film and the insulating film are formed so that the polishing volume in the low density area of the protrusions is substantially the same as the polishing volume in the high density area of the protrusions where the depressions are formed. It is desirable to form a recess. By this method, the step between the high density area and the low density area of the protrusions can be made closer to zero. The polishing volume is the volume of the film to be polished that is actually removed before and after polishing.

  In the first and second embodiments, the insulating film is preferably a heat-meltable oxide film. If a heat-meltable film is used, as shown in FIG. 13A, the embedding property of the insulating film 501 in the space between the protrusions is improved, and the space between the protrusions can be embedded with a thinner insulating film. . Therefore, as shown in FIG. 13C, the occurrence of local steps can be prevented. In addition, variations in the thickness of the insulating film after polishing can be reduced. FIG. 13 shows the case of Embodiment 1 as an example. The capacitor 216 is a convex portion. FIG. 13A shows the state when the insulating film 501 is formed (during deposition). FIG. 13B shows the state after the recess 502 is formed in the insulating film 501, FIG. 13C shows the state after polishing, 503 shows the polishing level, and 504 shows the surface of the insulating film 501 after polishing.

  The insulating film preferably contains at least either boron or phosphorus. This insulating film has a high heat melting property and a greater effect.

  The insulating film is preferably a silicon oxide film formed using O3 and TEOS. This insulating film is heat-meltable and has a great effect. In addition, since it does not contain impurities, it is not necessary to select usage conditions. There is also an advantage that hydrogen is not generated during formation.

  Further, it is desirable that the convex portion is a memory cell of the dielectric memory or a part thereof. In the dielectric memory, a three-dimensional capacitor is often formed in order to increase the capacity, and the height of the memory cell is increased. In such a case, the aspect ratio of the contact plug between the upper wiring of the memory cell and the diffusion layer becomes high, and the thickness of the interlayer insulating film can be reduced while reducing the thickness variation of the interlayer insulating film using the present invention. By reducing the thickness, connection reliability can be increased.

  Next, an example of a semiconductor memory device according to the present invention is shown in FIG. In general, in order to reduce the global level difference, the effect of a film formed by etching such as HDP-NSG in which the deposit shape becomes a convex portion is great as the insulating film on the convex portion. However, the characteristics of the ferroelectric film deteriorate due to the plasma damage of such a film. For this reason, in a capacitor including a ferroelectric material, such a film cannot be used, so that it becomes more difficult to eliminate a step between the memory cell array and the peripheral circuit region.

In addition, since the ferroelectric film deteriorates characteristics due to hydrogen, a barrier film 601 covering the upper and side portions of the capacitor, or a barrier film 602 is also provided at the bottom of the capacitor to surround the entire periphery of the capacitor. The barrier film 600 is required, and the height of the convex portion is increased. The films 601 and 602 are, for example, films containing at least part of Al ₂ O ₃ , TiAlOx, TiAlN, TiAlON, SiN, or Ti, Al. Further, when surrounding the entire periphery of the capacitor, the capacitor may be surrounded by two or more types of films. In addition, when a W plug is disposed under the lower electrode, it is necessary to dispose a film for preventing oxygen permeation on the lower electrode in order to prevent oxidation of W during sintering of the ferroelectric film. Yes, the height of the convex portion is further increased. Further, when a three-dimensional capacitor is formed in order to increase the capacitance, the height of the convex portion is further increased. When the height of such a convex portion is high, the aspect ratio of the contact plug 603 that connects the upper wiring and the diffusion layer is high, and the connection reliability is extremely lowered.

  Therefore, the barrier film 601 and 600 has a flat surface using the manufacturing method of the present invention so that the height variation of the interlayer insulating film 604 is 0.3 μm or less from the film surface of the portion formed above the capacitor. By forming the insulating film 604, connection reliability of the contact plug 603 with the upper wiring can be ensured.

  In the case of FIG. 14, there are a plurality (not shown) of convex portions including capacitors and barrier films 601 and 600, and a concave portion is formed on the convex portions by applying one of the manufacturing methods of the first and second embodiments. Can be formed. For example, FIG. 14 shows a convex portion including two capacitors in the cross-sectional direction (for example, the horizontal direction when viewed in plan), but the barrier films 601 and 600 are formed in the depth direction (for example, the vertical direction when viewed in plan). When the protrusions are formed so as to extend in a line and include a plurality of capacitors also in the depth direction within one protrusion, it is common to apply the manufacturing method of Embodiment 2. The manufacturing method of Embodiment 1 may be applied. Note that FIG. 14 shows a case where two capacitors are included in a cross-sectional direction (for example, a horizontal direction in a plan view) in one convex portion, but a case where one capacitor is included in the same cross-sectional direction or 2 A plurality of capacitors may be included, including not only three but also three or more.

  The method for manufacturing a semiconductor device according to the present invention makes it possible to flatten the surface of the insulating film formed on the semiconductor substrate and reduce the variation in the film thickness of the insulating film. This is useful as a method for manufacturing a semiconductor device in which an insulating film is formed over a semiconductor substrate having a low density region.

The top view which shows an example of FeRAM to which the manufacturing method of the semiconductor device of Embodiment 1 of this invention is applied Process sectional drawing of the manufacturing method which shows Embodiment 1 of this invention Process sectional drawing of the manufacturing method which shows Embodiment 1 of this invention Process sectional drawing of the manufacturing method which shows Embodiment 1 of this invention Plan view showing arrangement of memory cells in memory cell array The top view which shows the shape of the recessed part formed with respect to the area | region where the density of a convex part is high Diagram showing the relationship between the shape of the recess and the global level difference Plan view showing an arrangement example 1 of the memory cell and the recess Plan view showing an arrangement example 2 of the memory cell and the recess Process sectional drawing of the manufacturing method which shows Embodiment 2 of this invention Process sectional drawing of the manufacturing method which shows Embodiment 2 of this invention Process sectional drawing of the manufacturing method which shows Embodiment 2 of this invention Cross-sectional process diagram showing the difference in shape between non-heat-meltable film and heat-meltable film Sectional drawing which shows the structure of the semiconductor memory device by this invention Process cross-sectional view showing a conventional manufacturing method Cross-sectional process diagram for showing problems in conventional manufacturing methods

Explanation of symbols

101 Peripheral circuit region 102 Memory cell array region 201 Semiconductor substrate 202 Isolation region 203 High-concentration impurity diffusion layer 204 Gate insulating film 205 Gate electrode 206 First interlayer insulating film 207 First contact hole 208 Conductive film 209 Contact plug 210 Bit wiring 211 Second interlayer insulating film 212 Second contact plug 213 Lower electrode 214 Dielectric capacitor film 215 Upper electrode 216 Capacitor 217 Third interlayer insulating film 218 Recess 219 Third interlayer insulating film surface 220 after polishing Capacitor space Insulating film shape 221 in the case where concave portions are formed in a wide direction Third interlayer insulating film 222 Third contact plug 301 Memory cell (capacitor)
302 Recess 401 Conductive film 402 Lower electrode 403 Third insulating film 404 Dielectric capacitor film 405 Conductive film 406 Upper electrode 407 Fourth insulating film 408 Recess 409 Fourth interlayer insulating film 410 Third contact plug 501 Insulating film 502 Concave part 503 Polishing level 504 Surface shape of insulating film after polishing 600 Barrier film 601 Barrier film 602 Barrier film 603 Contact plug 604 Insulating film 701 Capacitor 702 Insulating film 703 Concave part 704 Protruding part 801 Insulating film 802 Concave part 803 Local step

Claims (19)

On a semiconductor substrate having a high density area of convex areas where the convex areas are arranged so that there are narrow directions and wide directions between adjacent convex areas, and a low density area of the convex areas, A first step of forming an insulating film so as to cover a region having a high density of convex portions and a region having a low density of convex portions;
A second step of forming a recess in the insulating film so that the interval between adjacent protrusions is long in a narrow direction and passes over the plurality of protrusions in the high density region of the protrusions;
And a third step of planarizing the surface of the insulating film by polishing.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the interval in the direction in which the interval between adjacent convex portions is narrow is 0.1 [mu] m or less.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the interval in the direction in which the interval between adjacent convex portions is wide is not more than twice the height of the convex portion.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the concave portion is formed even on a region including a convex portion at an endmost portion of a region where the density of the convex portions is high.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the concave portion is not formed on a convex portion at an outermost portion of a region where the density of the convex portions is high. A region having a high density of the convex portions and a region having a low density of the convex portions on a semiconductor substrate having a high density region of the convex portions where the line-shaped convex portions are arranged and a low density region of the convex portions. A first step of forming an insulating film so as to cover
A second step of forming a line-shaped concave portion in the insulating film on the line-shaped convex portion in a high-density region of the convex portions;
And a third step of planarizing the surface of the insulating film by polishing.   7. The method of manufacturing a semiconductor device according to claim 1, wherein in the third step, the surface of the convex portion in the region where the density of the convex portion is high is exposed.   The method of manufacturing a semiconductor device according to claim 1, wherein the recess is formed by wet etching.   The method of manufacturing a semiconductor device according to claim 1, wherein the recess is formed by dry etching.   The lowest surface of the surface of the insulating film in the portion where the concave portion is formed is approximately the same height as the surface of the insulating film in the portion where the convex portion has a low density in the region where the density of the convex portion is low. The method for manufacturing a semiconductor device according to claim 1, wherein a recess is formed.   The concave portion is formed so that a lowest surface of the surface of the insulating film in a portion where the concave portion is formed is higher than a surface of the insulating film after planarization. The manufacturing method of the semiconductor device of description.   Forming the insulating film and the recess so that the polishing volume in the low density area of the protrusions and the polishing volume in the high density area of the protrusions where the recesses are formed are substantially the same; A method for manufacturing a semiconductor device according to claim 1 or 6.   The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film is a heat-meltable insulating film.   14. The method of manufacturing a semiconductor device according to claim 13, wherein the insulating film contains at least either boron or phosphorus. 14. The method of manufacturing a semiconductor device according to claim 13, wherein the insulating film is a silicon oxide film formed using O ₃ and TEOS.   7. The method of manufacturing a semiconductor device according to claim 1, wherein the convex portion is a memory cell of a dielectric memory or a part of the memory cell. A plurality of capacitors including a ferroelectric film are formed on a semiconductor substrate, a barrier film is formed so as to cover an upper part and a side part of the capacitor or to surround the entire periphery of the capacitor, and an insulating film is formed on the barrier film A memory cell array region formed on the semiconductor substrate, and a peripheral circuit region disposed around the memory cell array region on which the insulating film is formed.
A semiconductor memory device, wherein a variation in thickness of the insulating film on the surface of the barrier film formed on the capacitor is within 0.3 μm.   The semiconductor memory device according to claim 17, wherein the barrier film is a film containing at least one of Ti and Al.   18. The semiconductor memory device according to claim 17, wherein the barrier film is a SiN film.

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