JP2004311865A - Wiring structure - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring structure which can suppress stress migration failure (conduction failure caused by the growth of a void in a via plug bottom) resulting from a thermal load to a wiring part. <P>SOLUTION: A wiring part (upper and lower wiring patterns 5, 1) of the wiring structure has first conductors 1a, 8, second conductors 1c, 10, and intermediate conductor films 1b, 9 disposed between the first conductors 1a, 8 and the second conductors 1c, 10. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a wiring structure, and can be applied to, for example, a wiring structure in which an upper wiring and a lower wiring are connected by a via plug.
[0002]
[Prior art]
Conventionally, aluminum wiring has been used as a wiring applied in a multilayer wiring structure. However, since the resistance value is 30 to 40% lower than that of aluminum and the resistance to electromigration is excellent, development of a buried copper wiring is also in progress (for example, see Patent Document 1).
[0003]
The multilayer wiring structure generally includes an upper wiring, a lower wiring, and a via plug for connecting both wirings.
[0004]
Other techniques related to the embedded copper wiring are also described in Patent Documents 2, 3, and 4 and Non-Patent Document 1.
[0005]
[Patent Document 1]
JP-A-11-97441 (page 2)
[Patent Document 2]
JP-A-11-204644 (FIG. 1)
[Patent Document 3]
JP 2000-183064 A (FIG. 1-7)
[Patent Document 4]
JP-A-2000-124310 (FIGS. 1-3 and 5)
[Non-patent document 1]
Technical Digest of International Interconnect Technology Conference 2002 "Thermal Stress of 140nm-width Cudamacene interconnects", Norio OKADA, No. 38, No. 1
[0006]
[Problems to be solved by the invention]
When a thermal load is applied to the copper wiring, the stress gradient inside the copper wiring increases. As a result, in the conventional copper wiring structure, in order to alleviate the stress gradient, a phenomenon has occurred in which minute voids present in the upper wiring and the lower wiring are drawn to the bottom surface of the via plug.
[0007]
Due to the above phenomenon, if minute voids are concentrated on the bottom surface of the via plug, a large void is generated at a connection portion between the via plug and the lower layer wiring, which causes a problem of conduction failure (referred to as stress migration failure) at the location. Had occurred.
[0008]
In particular, when thick copper wiring is used, stress migration failure tends to occur more easily. It is considered that the reason for this is that as the wiring becomes thicker, the wiring portion contains many minute voids, and the stress gradient generated inside the wiring also increases.
[0009]
Therefore, an object of the present invention is to provide a wiring structure capable of suppressing stress migration failure (the generation of voids at the bottom surface of a via plug).
[0010]
[Means for Solving the Problems]
In order to achieve the above object, the wiring structure according to claim 1 according to the present invention includes a first conductor portion, a second conductor portion, the first conductor portion and the second conductor portion. And an intermediate conductor film interposed between the first wiring portion and the first wiring portion.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be specifically described with reference to the drawings showing the embodiments.
[0012]
<Embodiment 1>
FIG. 1 shows a schematic cross-sectional view of the wiring structure according to the present embodiment.
[0013]
In FIG. 1, a lower wiring 1 is provided in a surface of a first interlayer insulating film 2 having a so-called low relative dielectric constant (lowk), which is formed of a silicon oxide film containing carbon or the like.
[0014]
Here, the lower wiring 1 is made of copper, and is interposed between the first conductor 1a and the second conductor 1c, and between the first conductor 1a and the second conductor 1c. And an intermediate conductor film 1b having a thickness of about 20 nm.
[0015]
The thickness of the intermediate conductor film 1b is not limited to this, but considering the increase in the electric resistance of the entire lower wiring 1 due to the formation of the intermediate conductor film 1b, about 10% or less of the wiring film thickness Desirably.
[0016]
The intermediate conductor film 1b is made of Ti (titanium), TiN (titanium nitride), W (tungsten), WN (tungsten nitride), Ta (tantalum), TaN (tantalum nitride), Zr (zirconium), Cr (chromium). ), Ag (silver), Ni (nickel), Sn (tin), In (indium), Mg (magnesium), Al (aluminum), Hf (hafnium), Nb (niobium), Pt (platinum), Pd (palladium) ), Co (cobalt), CoW (cobalt-tungsten), CoWP (cobalt-tungsten-phosphorus), and other metals.
[0017]
Specifically, the intermediate conductor film 1b may be a simple substance of each of the above metals, an alloy composed of a combination of the above metals, or an alloy composed of copper and at least one of the above metals.
[0018]
Note that, in order to prevent the conductive material (copper) forming the lower wiring 1 from diffusing into the first interlayer insulating film 2, the lower wiring 1 and the first interlayer insulating film 2 are provided between the lower wiring 1 and the first interlayer insulating film 2. A barrier metal layer (for example, Ti, TiN, Ta, or TaN) 11 is formed.
[0019]
Further, in FIG. 1, an etch stopper film 3 is formed so as to cover the first interlayer insulating film 2, and a second interlayer insulating film 4 made of a lowk material is formed on the etch stopper film 3. ing.
[0020]
Here, in addition to the role of the etching stopper, the etch stopper film 3 also has a role of preventing diffusion of a conductive material (copper) forming the lower wiring 1. Therefore, when the lower wiring 1 is made of copper, it is desirable to use SiN (silicon nitride film), SiC (silicon carbide), or the like as the etch stopper film 3.
[0021]
Further, in FIG. 1, an upper wiring 5 is provided in the surface of the second interlayer insulating film 4, and a via plug 6 is formed so as to connect a predetermined upper wiring 5 to the lower wiring 1. ing. Further, an etch stopper film 7 is formed so as to cover the second interlayer insulating film 4 and the upper wiring 5.
[0022]
The predetermined upper layer wiring 5 and the via plug 6 are formed integrally, and the integrally formed upper layer wiring 5 and the via plug 6 are formed of a first conductor 8 and a second It comprises a conductor 10 and an intermediate conductor film 9 interposed between the first conductor 8 and the second conductor 10.
[0023]
Here, the first conductor 8, the intermediate conductor film 9, and the second conductor 10 are formed from the upper wiring 5 to the via plug 6.
[0024]
In addition, the upper wiring 5 which is not connected to the via plug 6 and is provided independently has the same configuration as the lower wiring 1, and includes the first conductor 8 / intermediate conductor film 9 / second conductor 10. It is configured.
[0025]
Further, the thickness of the intermediate conductor film 9, applied materials, and the like are the same as those of the intermediate conductor film 1 b described in the lower wiring 1.
[0026]
Note that, in order to prevent the conductive material (copper) forming the upper wiring 5 and the via plug 6 from diffusing into the second interlayer insulating film 4, the conductive material (copper) between the upper wiring 5 and the second interlayer insulating film 4 is formed. Further, a barrier metal layer 12 such as TiC is formed between the via plug 6 and the second interlayer insulating film 4.
[0027]
Next, a method for manufacturing the wiring structure shown in FIG. 1 will be described.
[0028]
First, a first interlayer insulating film 2 is formed on a substrate (not shown) by a CVD (Chemical Vapor Deposition) method or the like. Next, a groove 15 is formed in the surface of the first interlayer insulating film 2 by a normal lithography process. Next, the barrier metal layer 11 is formed in the groove 15 by an ion sputtering method, a CVD method, or the like (FIG. 2).
[0029]
Here, the groove 15 has a depth of about 250 nm and a minimum width of about 140 nm. The thickness of the barrier metal layer 11 is about 25 nm.
[0030]
Next, a copper film having a thickness of about 40 nm is formed on the barrier metal layer 11 by performing a sputtering method on the groove 15 in which the barrier metal layer 11 is formed. Thereafter, a copper film having a thickness of about 30 nm is further formed on the copper film having a thickness of about 40 nm by a thermal CVD method. Therefore, a copper film (hereinafter, referred to as a second conductor) 1c having a thickness of about 70 nm is formed on the barrier metal layer 11 (FIG. 3).
[0031]
Next, a Cr film or the like (hereinafter referred to as an intermediate conductor film) 1b having a thickness of about 20 nm is formed on the second conductor 1c by ion sputtering (FIG. 4).
[0032]
Next, a copper seed layer having a thickness of 40 nm is formed on the intermediate conductor film 1b by an ion sputtering method. Next, a copper film (hereinafter, referred to as a first conductor) 1a having a thickness of about 300 nm is formed based on the seed layer by electroplating. Here, by performing electrolytic plating using a solution in which a suitable additive is added to a liquid containing copper sulfate as a main component, the film growth rate from the bottom surface of the narrow groove portion 15 can be increased ( Along with bottom-up fill), the embedding of the first conductor 1a into a fine pattern can be improved. Then, the first conductor 1a, the intermediate conductor film 1b, and the second conductor formed on the surface of the first interlayer insulating film 2 by a planarization process using a CMP (Chemical Mechanical Polishing) method. 1c and the barrier metal layer 11 are removed (FIG. 5).
[0033]
As a result, the lower wiring 1 including the first conductor 1a, the intermediate conductor film 1b, and the second conductor 1c is provided in the surface of the first interlayer insulating film 2.
[0034]
Next, an etch stopper film 3 is formed by a CVD method so as to cover the lower wiring 1 and the first interlayer insulating film 2, and a second interlayer insulating film 4 is formed on the etch stopper film 3 by the same CVD method. To form Thereafter, a groove portion 16 is formed by a normal lithography process, and a hole portion 17 reaching the lower wiring 1 is further formed in a part of the groove portion 16 (FIG. 6).
[0035]
Here, the groove 16 has a depth of about 250 nm and a minimum width of about 140 nm. The depth of the hole 17 is about 250 nm.
[0036]
Next, the barrier metal layer 12 having a film thickness of about 25 nm is formed on the bottom and side surfaces of the hole 17 and the side surfaces of the groove 16 by ion sputtering, and then the barrier metal layer 12 is also formed by ion sputtering. A copper film having a thickness of about 40 nm at the bottom of the hole 17 is formed on the metal layer 12. Thereafter, a copper film having a thickness of about 30 nm is formed on the copper film formed above by performing a thermal CVD method. Therefore, a copper film (hereinafter, referred to as a second conductor) 10 having a thickness of about 70 nm is formed on the barrier metal layer 12 at the bottom of the hole 17 (FIG. 7).
[0037]
Here, the thickness of the copper film formed on the bottom of the hole 17 by the ion sputtering method is about 40 nm, but the thickness of the copper film formed on the side surface of the groove 16 and the side surface of the hole 17 is Is 10 nm or less.
[0038]
Therefore, since the thickness of the copper film formed by the thermal CVD method is uniformly formed on the copper film formed by the above-described process, a total thickness of 40 nm is formed on the side surface of the groove 16 and the side surface of the hole 17. Thus, a copper film (second conductor) 10 having a thickness equal to or less than about 10 nm is formed.
[0039]
Therefore, since the minimum width of the groove 16 is 140 nm, even if the second conductor 10 having a thickness of about 40 nm is formed on both side surfaces of the groove 16, the minimum width is formed by the second conductor film 10. The groove 16 is not completely buried (FIG. 7).
[0040]
Next, an intermediate conductor film 9 of Cr or the like having a thickness of about 20 nm is formed on the second conductor 10 by an ion sputtering method (FIG. 8).
[0041]
Next, a copper seed layer having a thickness of 40 nm is formed on the intermediate conductor film 9 by an ion sputtering method. Next, a copper film (hereinafter, referred to as a first conductor) 8 having a thickness of about 600 nm is formed on the basis of the seed layer by electroplating (FIG. 9).
[0042]
Here, the rate of film growth from the bottom of the hole 17 or the narrow groove 16 is increased by performing an electroplating process using a solution obtained by adding a suitable additive to a liquid containing copper sulfate as a main component. (Bottom-up fill), and the ability to embed the first conductor 8 into a fine pattern can be improved.
[0043]
Thereafter, the first conductor 8, the intermediate conductor film 9, the second conductor 10, and the barrier metal layer formed on the surface of the second interlayer insulating film 4 by planarization using the CMP method. 12 is removed (FIG. 10).
[0044]
Thus, the upper wiring 5 including the first conductor 8, the intermediate conductor film 9, and the second conductor 10 and the via plug 6 can be formed in the surface of the second interlayer insulating film 4. .
[0045]
Finally, by forming an etch stopper film 7 by a CVD method so as to cover the upper wiring 5 and the second interlayer insulating film 4, the wiring structure shown in FIG. 1 can be formed.
[0046]
As described above, since the intermediate conductor films 1b and 9 are formed in the lower layer wiring 1 and the upper layer wiring 5 in the formed wiring structure, the following effects are obtained.
[0047]
In other words, as described in the related art, the minute voids existing in the wiring are concentrated (attracted) on the barrier metal layer formed on the bottom surface of the via plug due to the heat load process. It is believed that the concentration in (attracting) the energies is lower and more stable than that scattered in the wiring.
[0048]
Here, FIG. 11 shows a state in which minute voids 20 existing in the wiring are drawn to the bottom of the via plug. FIG. 12 shows that large voids 21 are generated at the bottom of the via plug as a result.
[0049]
Therefore, as in the wiring structure according to the present embodiment, the intermediate conductor film 1b is lower in energy than the concentration of the voids in the barrier metal layer 12 formed on the bottom surface of the via plug 6 (attracted). , 9 are introduced into the lower wiring 1 and the upper wiring 5, so that the voids are also drawn to the intermediate conductor films 1 b, 9. This is shown in FIG.
[0050]
Here, by employing the above-listed metals (including alloys) as the intermediate conductor films 1 b and 9, voids are formed at a probability equal to or higher than that of the barrier metal layer 12. 1b, 9.
[0051]
Therefore, the voids conventionally concentrated on the barrier metal layer 12 formed on the bottom surface of the via plug 6 due to the heat load are attracted to the intermediate conductor films 1 b and 9, so that the voids in the barrier metal layer 12 become large. Generation of voids can be suppressed. Thus, conduction failure (stress migration failure) in the via plug 6 can be eliminated.
[0052]
Further, as can be seen from the wiring structure described above, the intermediate conductor films 1b and 9 are formed along the wiring direction. That is, the intermediate conductor films 1b and 9 are formed with a larger area than the barrier metal layer 12 formed on the bottom surface of the via plug.
[0053]
Therefore, in the related art, the voids that have been concentrated at one location are uniformly drawn along the intermediate conductor films 1b and 9, and no large voids are generated in the intermediate conductor films 1b and 9 It does not affect the wiring continuity.
[0054]
In the present embodiment, a configuration in which barrier metal layers 11 and 12 are provided between lower wiring 1 and first interlayer insulating film 2 and between upper wiring 5 and second interlayer insulating film 4 is described. As described above, since the barrier metal layers 11 and 12 are not essential members of the present invention, they can be omitted.
[0055]
As for the upper wiring 5 connected to the via plug 6, the case where the intermediate conductor film 9 is formed over the upper wiring 5 and the via plug 6 has been described. However, the same effect can be obtained even when the intermediate conductor film 9 is formed only in the upper layer wiring 5, as in the other upper layer wiring 5 and the lower layer wiring 1.
[0056]
Therefore, which configuration is to be adopted is determined in consideration of ease of manufacturing.
[0057]
<Embodiment 2>
In the first embodiment, the case where the intermediate conductor film is formed for all the lower wiring and the upper wiring has been described. However, the present embodiment is characterized in that the intermediate conductor film is formed only on the lower wiring and the upper wiring having a predetermined line width or more.
[0058]
FIG. 14 shows a schematic cross-sectional view of the wiring structure according to the present embodiment.
[0059]
As shown in FIG. 14, intermediate conductor films 1b and 9 are formed in lower wiring 1 and upper wiring 5 having a predetermined line width or more. On the other hand, the lower wiring 1 and the upper wiring 5, which are smaller than the predetermined line width, are made of only copper, similarly to the structure of the conventional copper wiring. The other configuration is the same as the configuration of FIG. 1 described in the first embodiment, and thus the description is omitted here.
[0060]
Here, as the predetermined line width, for example, in the case of a wiring having a wiring thickness of about 250 nm, a line width of 0.7 μm or more can be considered.
[0061]
Next, a method for manufacturing the wiring structure shown in FIG. 14 will be described.
[0062]
First, as shown in FIG. 2, the first interlayer insulating film 2 in which the groove 15 is formed is prepared. Here, the barrier metal layer 11 is formed in the groove 15.
[0063]
Next, a copper seed layer having a thickness of about 80 nm is formed on the barrier metal layer 11 by an ion sputtering method. Next, a second conductor 1c having a film thickness of about 80 nm is formed on the basis of the seed layer using an electroplating method (FIG. 15).
[0064]
Here, by performing an electroplating process using a solution obtained by adding a suitable additive to a liquid containing copper sulfate as a main component, the copper burying speed in the groove portion 15 smaller than the predetermined width can be increased to the predetermined width or more. The filling speed in the groove 15 can be made faster. That is, a bottom-up fill is adopted. Moreover, the embedding property in the narrow groove 15 is improved by the bottom-up fill.
[0065]
Therefore, in the present embodiment, as shown in FIG. 15, the groove 15 having a predetermined width or more is partially filled with the second conductor 1c, and the groove 15 having a width smaller than the predetermined width is not filled. Is completely filled with the second conductor 1c.
[0066]
Next, an intermediate conductor film 1b is formed on the wiring structure in the process of manufacturing shown in FIG. 15 by the same method as in the first embodiment (FIG. 16), and the first conductor film 1b is formed on the intermediate conductor film 1b. The first conductor 1a, the intermediate conductor film 1b and the second conductor 1c formed on the upper surface of the first interlayer insulating film 2 are removed by the CMP method (FIG. 17).
[0067]
Thus, as shown in FIG. 17, lower wiring 1 is provided in the surface of first interlayer insulating film 2. Here, the lower wiring 1 having a predetermined line width or more has a laminated structure of the first conductor 1a / intermediate conductor film 1b / second conductor film 1c. The smaller lower layer wiring 1 is simply composed of only a conductor made of copper. Here, as the material of the intermediate conductor film 1b, those listed in the first embodiment are adopted.
[0068]
Next, an etch stopper film 3 is formed to cover the lower wiring 1 and the first interlayer insulating film 2 by the same method as in the first embodiment, and a second interlayer insulating film 4 is formed on the etch stopper film 3. To form Thereafter, a groove 16 and a hole 17 are formed by a normal lithography process (FIG. 18).
[0069]
Here, the groove 16 has a depth of about 250 nm and a minimum width of about 140 nm. The depth of the hole 17 is about 250 nm.
[0070]
Next, the barrier metal layer 12 is formed in the groove 16 and the hole 17 in the same manner as in the first embodiment. Next, a copper seed layer having a thickness of about 80 nm is formed on the barrier metal layer 12 by an ion sputtering method. Next, a second conductor 10 having a thickness of about 80 nm is formed on the basis of the seed layer using an electroplating method (FIG. 19).
[0071]
Here, the hole 17 and the narrow groove 16 are completely buried by the second conductor 10 at this time by adopting the bottom-up fill as in the case of forming the lower wiring 1 (that is, in this case). At this point, the narrow upper wiring 5 and the via plug 6 are formed.) On the other hand, the wide groove 16 is not completely buried by the second conductor 10 at this time (FIG. 19).
[0072]
Next, an intermediate conductor film 9 and a first conductor film 8 are formed in this order on the second conductor 10 by a method similar to the method described in the first embodiment, and thereafter, a planarization process is performed. The upper wiring 5 having a predetermined line width or more is formed in the surface of the second interlayer insulating film 4 (FIG. 20).
[0073]
Finally, by forming the etch stopper film 7 by the CVD method so as to cover the upper wiring 5 and the second interlayer insulating film 4, the wiring structure shown in FIG. 14 can be formed.
[0074]
As described above, the formed wiring structure has the following effects because the intermediate conductor films 1b and 9 are formed for the lower wiring 1 and the upper wiring 5 having a predetermined line width or more.
[0075]
Normally, when the above-listed members are introduced as the intermediate conductor films 1b and 9 inside the wiring made of copper, the thickness of the copper decreases by the thickness of the intermediate conductor films 1b and 9. Therefore, the electrical resistance may increase by an amount corresponding to a decrease in the thickness of the copper (that is, an amount corresponding to the substitution of the intermediate conductor films 1b and 9).
[0076]
Further, when the intermediate conductor films 1b and 9 are introduced into a wiring having a narrow wiring width, electron scattering in the intermediate conductor films 1b and 9 is large in addition to the interface with the barrier metal layers 11 and 12. Influence is caused, and an increase in the electric resistance more than the above-mentioned decrease in the copper film thickness occurs. The increase in the electric resistance causes a delay in a signal transmitted through the wiring, which is a problem particularly in a high-speed device.
[0077]
On the other hand, conventionally, in a wiring having a narrow wiring width, the total volume of voids diffused in the entire wiring is not so large, and since the volume of the entire wiring is small, a stress gradient generated by a thermal load is also small. Since the size of the via plug 6 is reduced, the voids hardly concentrate on the bottom surface of the via plug 6, and there is almost no problem in practical use.
[0078]
Therefore, by taking into account the occurrence of voids and the increase in electrical resistance, the effect of voids generated at the bottom surface of the via plug 6 is larger than that of electrical resistance for wiring having a predetermined wiring width or more. Therefore, the intermediate conductor films 1b and 9 are formed in order to suppress the generation of voids at the corresponding locations. On the other hand, voids are hardly generated for wiring less than a predetermined wiring width, and Since an increase in the electrical resistance when the body films 1b and 9 are introduced has a greater influence, the intermediate conductor films 1b and 9 are not formed.
[0079]
This can prevent an increase in electric resistance due to the presence of the intermediate conductor films 1b and 9 in a wiring having a narrow wiring width, and can cause a concentration of voids on the bottom surface of the via plug 6 in a wiring having a large wiring width. Can be suppressed.
[0080]
Here, FIG. 21 is a diagram conceptually showing a moving state of minute voids in the wiring structure according to the present embodiment.
[0081]
It should be noted that even in a wiring having a large wiring width, the introduction of the intermediate conductor films 1b and 9 causes an increase in electric resistance corresponding to the thickness of the intermediate conductor films 1b and 9 to occur. However, since the ratio of the intermediate conductor films 1b and 9 to the entire wiring does not increase in the case of a wiring having a large wiring width, the increase in the electric resistance is not so large as to be problematic.
[0082]
Also, in the present embodiment, the barrier metal layers 11 and 12 are not essential members of the present invention, and thus can be omitted.
[0083]
In the above embodiment, the case where copper is used as the first conductors 1a and 8 and the second conductors 1c and 10 has been described. However, the present invention is not limited to this. It can also be applied to conductors.
[0084]
【The invention's effect】
The wiring structure according to claim 1 of the present invention intervenes between a first conductor portion, a second conductor portion, and the first conductor portion and the second conductor portion. Since the wiring portion having the intermediate conductor film is provided, minute voids existing in the wiring portion are uniformly drawn to the intermediate conductor film, and the generation of large voids unevenly distributed in one place can be suppressed.
[Brief description of the drawings]
FIG. 1 is a sectional view showing a wiring structure according to a first embodiment.
FIG. 2 is a cross-sectional view illustrating a method for manufacturing a wiring structure according to the first embodiment.
FIG. 3 is a cross-sectional view for explaining the method for manufacturing the wiring structure according to the first embodiment.
FIG. 4 is a sectional view illustrating the method for manufacturing the wiring structure according to the first embodiment.
FIG. 5 is a sectional view illustrating the method for manufacturing the wiring structure according to the first embodiment.
FIG. 6 is a sectional view illustrating the method for manufacturing the wiring structure according to the first embodiment.
FIG. 7 is a cross-sectional view for explaining the method for manufacturing the wiring structure according to the first embodiment.
FIG. 8 is a sectional view for explaining the method for manufacturing the wiring structure according to the first embodiment.
FIG. 9 is a sectional view illustrating the method for manufacturing the wiring structure according to the first embodiment.
FIG. 10 is a sectional view illustrating the method for manufacturing the wiring structure according to the first embodiment.
FIG. 11 is a diagram conceptually showing a state of movement of minute voids in a conventional wiring structure.
FIG. 12 is a diagram showing a state of a large void generated at the bottom of a via plug.
FIG. 13 is a diagram conceptually showing a state of movement of minute voids in the wiring structure of the first embodiment.
FIG. 14 is a sectional view showing a wiring structure according to a second embodiment.
FIG. 15 is a sectional view illustrating the method for manufacturing the wiring structure according to the second embodiment.
FIG. 16 is a sectional view illustrating the method for manufacturing the wiring structure according to the second embodiment.
FIG. 17 is a sectional view illustrating the method for manufacturing the wiring structure according to the second embodiment.
FIG. 18 is a sectional view illustrating the method for manufacturing the wiring structure according to the second embodiment.
FIG. 19 is a sectional view illustrating the method for manufacturing the wiring structure according to the second embodiment.
FIG. 20 is a sectional view illustrating the method for manufacturing the wiring structure according to the second embodiment.
FIG. 21 is a diagram conceptually showing a state of movement of minute voids in the wiring structure of the second embodiment.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Lower wiring, 1a, 8 First conductor, 1b, 9 Intermediate conductor film, 1c, 10 Second conductor, 2 First interlayer insulating film, 3, 7 Etching stopper film, 4th interlayer Insulating film, 5 upper wiring, 6 via plug, 11, 12 barrier metal layer, 15, 16 groove, 17 hole, 20 minute void, 21 large void.

Claims (5)

A first conductor portion,
A second conductor portion;
An intermediate conductor film interposed between the first conductor portion and the second conductor portion,
Having a first wiring portion,
A wiring structure, comprising: There are multiple wiring parts,
The plurality of wiring portions are configured by the first wiring portion having the intermediate conductive film, and a second wiring portion not including the intermediate conductive film,
The wiring structure according to claim 1, wherein: The first wiring portion is applied to a wiring portion having a predetermined line width or more,
The wiring structure according to claim 2, wherein: A via plug formed integrally with the first wiring portion, further comprising:
The first conductor portion, the second conductor portion and the intermediate conductor film are formed from the first wiring portion to the via plug.
The wiring structure according to any one of claims 1 to 3, wherein: The intermediate conductor film,
Contains at least one of Ti, TiN, W, WN, Ta, TaN, Zr, Cr, Ag, Ni, Sn, In, Mg, Al, Hf, Nb, Pt, Pd, Co, CoW, and CoWP. That
The wiring structure according to any one of claims 1 to 4, wherein:

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