JP2004240233A - Solder resist composition, circuit board and method for manufacturing the same - Google Patents

Solder resist composition, circuit board and method for manufacturing the same Download PDF

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Publication number
JP2004240233A
JP2004240233A JP2003030237A JP2003030237A JP2004240233A JP 2004240233 A JP2004240233 A JP 2004240233A JP 2003030237 A JP2003030237 A JP 2003030237A JP 2003030237 A JP2003030237 A JP 2003030237A JP 2004240233 A JP2004240233 A JP 2004240233A
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Japan
Prior art keywords
solder resist
film
epoxy resin
desmear
resist composition
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Pending
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JP2003030237A
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Japanese (ja)
Inventor
Kentaro Yamashita
健太郎 山下
Keita Harashima
啓太 原嶋
Tatsuya Kiyota
達也 清田
Makoto Yanagawa
誠 柳川
Takao Ono
隆生 大野
Tsutomu Iwai
勤 岩井
Hisashi Kato
久始 加藤
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Tamura Kaken Corp
Ibiden Co Ltd
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Tamura Kaken Corp
Ibiden Co Ltd
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Priority to JP2003030237A priority Critical patent/JP2004240233A/en
Publication of JP2004240233A publication Critical patent/JP2004240233A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Materials For Photolithography (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a solder resist film from being damaged even when the solder resist film is formed on a circuit board and a residual component (smear) associated with via hole formation thereto with a laser beam is subjected to a desmear consisting of dissolution and removal with an aqueous potassium permanganate solution. <P>SOLUTION: The solder resist composition is characterized in that a hardened coating film of a composition containing an epoxy resin to be hardly desmeared is laminated on a hardened coating film of a composition containing an epoxy resin to be easily desmeared to use the laminated hardened coating films as the solder resist film. This invention includes the circuit board using the composition and a method for manufacturing the circuit board. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【産業上の利用分野】
本発明は、例えば回路基板上のソルダーレジスト膜にレーザーによりビアホールを形成したときにそのホール内に残留する成分であるスミアを除去し易くするとともにその除去の際ソルダーレジスト膜が損傷されないようなソルダーレジスト組成物、これを用いた回路基板及びその製造方法に関する。
【０００２】
【従来の技術】
回路基板は、基板の上に導体回路のパターンを形成し、そのパターンのはんだ付けランドに電子部品をはんだ付けすることにより搭載するためのものであり、そのはんだ付けランドを除く回路部分は永久保護皮膜としてのソルダーレジスト膜で被覆される。これにより、プリント配線板に電子部品をはんだ付けする際にはんだが不必要な部分に付着するのを防止すると共に、回路の導体が空気に直接曝されて酸化や湿度により腐食されるのを防止する。
このように基板にソルダーレジスト膜のパターン（はんだ付ランドを除く回路部分を覆うパターン）を形成する単層の回路基板のみならず、基板上に導体回路パターンを形成し、ついでその上に層間絶縁材料の塗布層を形成し、その塗布層に基板の導体回路パターンと連通するビアホールをレーザーにより形成し、さらにこのビアホールを含む塗布層表面に無電解めっき膜を設け、そのめっき膜について導体回路部分は樹脂膜で被覆してそれ以外の部分をエッチングにより除去し、最後にその樹脂膜を剥離して導体回路パターンを形成し、これにソルダーレジスト膜を形成する。順次これを繰り返し、積層する各層に回路を形成しこれをビアホールで接続した、いわゆる多層回路基板には、ソルダーレジスト組成物を塗布し、露光、現像、ポストキュアを順次行って絶縁膜のパターンを形成する。この場合、通常のソルダーレジスト膜のパターンの場合には、上記の露光は多くの場合、メタルハライドランプによる散乱光露光装置を使用しているが、微細なソルダーレジスト膜のパターンを形成する際は、高圧水銀ランプによる平行光露光装置あるいは投影露光装置を使用するのが一般的である。
ところが、さらに微細なソルダーレジスト膜のパターンが要求される場合には、炭酸ガスレーザーやＵＶ−ＹＡＧレーザー、エキシマレーザー等を用いて、ソルダーレジスト膜のはんだ付ランドに対応する部分を分解除去してそのはんだ付ランドを露出するが、そのはんだ付ランドには、除去されないで残留するソルダーレジスト膜の成分（スミア）が生じる。このようなスミアが生じると、めっき処理を行なってもめっきされない部分（めっき未着部分）が生じ易いのみならず、電子部品をはんだ付しても接合不良を起こすことがあるので、このスミアを除く、いわゆるデスミアを行なうデスミア工程を設ける必要がある。
【０００３】
特に、ＦＣ−ＢＧＡ（フリップチップポールグリッドアレイ）やＣＳＰ（チップサイズパッケージ）等は、回路基板に半導体チップを搭載するにあたって、接合方法として半導体チップ側に金バンプやはんだバンプを形成して接合される。また、基板のチップを搭載した側とは反対側の他方の片面にははんだボールを搭載する。このように一方の片面に半導体チップを接合により搭載した回路基板は、マザーボードにその他方の片面に搭載したはんだボールによる接合により実装される。金バンプやはんだバンプあるいははんだボールを搭載するいずれにおいても、それぞれの片面に形成されたソルダーレジスト膜にレーザー光を照射してビアホールを形成し、それぞれの面に形成されている導体回路のパターンのそのビアホールに該当する部分を露出するが、そのビアホールの径が小さいため、少しのスミアの存在も、そのビアホールに搭載される金バンプやはんだバンプあるいははんだボールの接合不良を起こし易いので、その除去は一層重要になってくる。
上記の回路基板の製造において、そのデスミアの方法としては、濃アルカリ溶液で膨潤させ、続いて過マンガン酸塩溶液によりスミアを分解除去する湿式法や、プラズマやエキシマレーザーにより分解除去する乾式法があるが、コストや生産効率の点では湿式法が優れており、この湿式法が一般的に使用されている。
【０００４】
ところで、上記のソルダーレジスト膜の形成のためには、ノボラック型エポキシ樹脂と不飽和モノカルボン酸との反応物を、飽和もしくは不飽和多塩基酸無水物と反応して得られるアルカリ可溶性感光性樹脂を用いたアルカリ現像型ソルダーレジスト組成物が用いられる（例えば特開昭６１−２４３８６９号（特許第１７９９３１９号）公報を参照）。
また、多層回路基板においては、層間絶縁材料としてビスフェノールＡ型エポキシ樹脂と末端エポキシ化ポリブタジエンゴムからなる樹脂組成物が用いられている（例えば特開平１１−００１５４７号公報参照）。
【０００５】
【特許文献１】
特開昭６１−２４３８６９号公報
【特許文献２】
特開平１１−００１５４７号公報
【０００６】
【発明が解決しようとする課題】
しかしながら、湿式法によるデスミアを行うときは、ソルダーレジスト膜を形成した回路基板全体を濃アルカリ溶液、続いて過マンガン酸塩溶液に浸漬して処理するため、ビアホール内に残留したスミアの分解除去のみならず、ソルダーレジスト膜表面もこの溶液に侵され易い。例えば上記特開昭６１−２４３８６９号に記載されているようなアルカリ現像型ソルダーレジスト組成物では、濃アルカリ溶液で膨潤させる膨潤工程でアルカリ可溶性感光性樹脂に残存しているカルボン酸が反応し、ソルダーレジスト膜が侵されるため、続いて行う過マンガン酸塩溶液に浸漬する浸漬工程で塗膜の分解、剥離が生じ、良好なソルダーレジスト塗膜が得られないという問題がある。
また、上記特開平１１−００１５４７号公報に開示されているような樹脂組成物を層間絶縁材料として用いる場合には、予め層間絶縁材料の塗布層に導体回路パターンが設けられており、その上にそのソルダーレジスト膜が形成されるが、過マンガン酸塩溶液に浸漬する浸漬工程ではその塗膜の剥離は生じないが、前工程の導体回路パターンを形成する際にその層間絶縁材料の塗布層に無電解銅メッキを良く行うために、その塗布層の全面に凹凸を形成する、いわゆる塗膜の粗化が行なわれているので、その粗化が行われた塗布層の上に形成されるソルダーレジスト膜については、過マンガン酸塩溶液に浸漬する浸漬工程の影響が現れて、その導体回路パターンに電子部品をはんだ付するときに剥離を生じる、いわゆるはんだ耐熱性が低下したり、そのソルダーレジスト膜自体の絶縁信頼性が低下するなど、ソルダーレジスト膜としての必要な特性を低下させ易いという問題がある。
【０００７】
本発明の第１の目的は、スミアを薬液により分解除去する湿式法によるデスミアの処理を行なってもデスミアが良好に行われるとともに、その薬液に侵されない塗膜を形成できるソルダーレジスト組成物、回路基板及びその製造方法を提供することにある。
本発明の第２の目的は、そのデスミアの処理を行った後の後続の処理に悪影響を与えたり、回路基板に必要な特性を低下させたりすることがないソルダーレジスト、回路基板及びその製造方法を提供することにある。
【０００８】
【課題を解決するための手段】
本発明者らは、上記課題を解決するために鋭意研究した結果、デスミアされ易いエポキシ樹脂を含有するデスミア用硬化樹脂膜と、デスミアされ難いエポキシ樹脂を含有する耐デスミア用硬化樹脂膜を積層した積層硬化樹脂膜をソルダーレジスト膜に用いると、上記目的を達成できることを見い出し、本発明をするに至った。
すなわち、本発明は、（１）、電子回路配線が形成された基板に該電子回路配線を被覆するソルダーレジスト膜を形成し、レーザーにより該ソルダーレジスト膜に該電子回路配線に連通するビアホールを形成し、該ビアホール内の配線の導体部に残留する成分であるスミアを除去するデスミアを行ない易い上記ソルダーレジスト膜用のエポキシ樹脂を含有するソルダーレジスト組成物を提供するものである。
また、本発明は、（２）、電子回路配線が形成された基板に該電子回路配線を被覆するソルダーレジスト膜を形成し、レーザーにより該ソルダーレジスト膜に該電子回路配線に連通するビアホールを形成し、該ビアホール内の配線の導体部に残留する成分であるスミアを除去するデスミアを行ない難い上記ソルダーレジスト膜用のエポキシ樹脂を含有するソルダーレジスト組成物、（３）、デスミアされ易いエポキシ樹脂は下記一般式〔化１〕で示される分子構造及び／又は下記一般式〔化２〕で示される分子構造を分子内に有する熱硬化性樹脂である上記（１）のソルダーレジスト組成物、
【化１】

Figure 2004240233
（式中、Ｒ１ はＣＨ２ 又はＣ（ＣＨ３ ）２ を表わし、ｍは１又は複数を表わす。）
【化２】
Figure 2004240233
（式中、Ｒ２ はＣＨ２ 又はＣ（ＣＨ３ ）２ を表わし、ｎは１又は複数を表わす。）
（４）、デスミアされ難いエポキシ樹脂は下記一般式〔化１〕で示される分子構造及び／又は下記一般式〔化２〕で示される分子構造を分子内に有しない熱硬化性樹脂である上記（２）のソルダーレジスト組成物、
【化１】
Figure 2004240233
（式中、Ｒ１ はＣＨ２ 又はＣ（ＣＨ３ ）２ を表わし、ｍは１又は複数を表わす。）
【化２】
Figure 2004240233
（式中、Ｒ２ はＣＨ２ 又はＣ（ＣＨ３ ）２ を表わし、ｎは１又は複数を表わす。）
（５）、エポキシ基を有しないエポキシ樹脂硬化性化合物を含有する上記（１）ないし（４）のいずれかのソルダーレジスト組成物、（６）、デスミアはスミアを除去する薬液を用いる湿式法で行なう上記（１）ないし（５）のいずれかのソルダーレジスト組成物、（７）、電子回路配線が形成された基板に該電子回路配線を被覆するソルダーレジスト膜を形成し、レーザーにより該ソルダーレジスト膜に該電子回路配線に連通するビアホールを形成し、該ビアホール内の配線の導体部に残留する成分であるスミアを除去するデスミアを行なうことを少なくとも行なって得られる回路基板であって、上記ソルダーレジスト膜は、
（１）請求項１、３、５又は６に記載のデスミアを行い易いエポキシ樹脂を含有するソルダーレジスト組成物（Ａ）を塗布し、硬化させたデスミア用硬化樹脂膜と、
（２）該デスミア用硬化樹脂膜の上に請求項２、４、５又は６に記載のデスミアされ難いエポキシ樹脂を含有するソルダーレジスト組成物（Ｂ）を塗布し、硬化させた耐デスミア用硬化樹脂膜を積層して有する
回路基板、（８）、電子回路配線が形成された基板に該電子回路配線を被覆するソルダーレジスト膜を形成し、レーザーにより該ソルダーレジスト膜に該電子回路配線に連通するビアホールを形成し、該ビアホール内の配線の導体部に残留する成分であるスミアを除去するデスミアを行なうことを少なくとも行なって得られる回路基板の製造方法であって、上記ソルダーレジスト膜は、
（１）請求項１、３、５又は６に記載のデスミアを行い易いエポキシ樹脂を含有するソルダーレジスト組成物（Ａ）を塗布し、硬化させたデスミア用硬化樹脂膜を形成した後、
（２）該デスミア用硬化樹脂膜の上に請求項２、４、５又は６に記載のデスミアされ難いエポキシ樹脂を含有するソルダーレジスト組成物（Ｂ）を塗布し、硬化させた耐デスミア用硬化樹脂膜を形成する
回路基板の製造方法を提供するものである。
【０００９】
【発明の実施の形態】
本発明において、ソルダーレジスト組成物（Ａ）に含有される「デスミアされ易いエポキシ樹脂」としては、この樹脂を含有するソルダーレジスト組成物の塗布膜の硬化物が濃アルカリ溶液及び／又は過マンガン酸塩溶液（デスミアの薬液）に侵され易い、例えば分解し易かったり、溶解し易かったり、膨潤し易かったり、あるいは金属導体に付着した場合に容易に剥離し易く、したがって除去され易くなるエポキシ樹脂を挙げることができる。「デスミアされ易い」ことの目安としては、その塗布膜の硬化物が濃アルカリ溶液、ついで過マンガン酸塩溶液により処理（デスミア処理）された後ではその前に比べて表面粗さが平均で５μｍ以上増大した場合を挙げることができ、これを基準にして樹脂を選択すればよい。
このようなエポキシ樹脂としては、、上記一般式〔化１〕で示される分子構造及び上記一般式〔化２〕で示される分子構造のいずれか一方又は両方を分子内に有するエポキシ樹脂が挙げられる。これらの一般式〔化１〕、〔化２〕中、Ｒ１ 、Ｒ２ はそれぞれＣＨ２ 又はＣ（ＣＨ３ ）２ を表わすが、同一でも良く異なってもよく、また、ｍ、ｎは分子中にそれぞれの〔 〕内の分子構造をいくつ有するかを示すものであり、その数は平均値であるが、それぞれが１のときは分子中に平均１個のそれぞれの分子構造を有し、それぞれが２以上の複数を示すときは、分子中に平均してその複数個、例えば３のときは３個のそれぞれの分子構造を有することを示す。このような分子構造の樹脂が「デスミアされ易い」理由としては、分子内の水酸基部分及び／又はメチレン鎖部分、エーテル結合部分に、濃アルカリ溶液や過マンガン酸塩溶液が下記反応式〔化３〕に示されるように反応して膨潤、溶解あるいは分解され易いためであると考えられる。
【００１０】
【化３】
Figure 2004240233
（Ｒは〔化１〕、〔化２〕における−Ｏ −ＣＨ２（ＯＨ） −ＣＨ２ −の左側に結合する残基を表わす。）
【００１１】
具体的には、ビスフェノールＡ型エポキシ樹脂として、エピコート １００１、同１００２、同１００３（以上、ジャパンエポキシレジン社製）、エピクロン１０５０、同３０５０（以上、大日本インキ化学工業社製）、アラルダイト ＡＥＲ６０７１、同６０７２（以上、旭チバ社製）、エポトート ＹＤ−０１１、同ＹＤ−０１２（以上、東都化成社製）、ビスフェノールＦ型エポキシ樹脂として、エポトート ＹＤＦ−２００１、同２００４（東都化成社製）、水添ビスフェノールＡ型エポキシ樹脂として、エピクロン ＥＸＡ−７０１５（大日本インキ化学工業社製）が挙げられる。
【００１２】
また、塗工用硬化性樹脂組成物（Ｂ）に含有される「デスミアされ難いエポキシ樹脂」としては、この樹脂を含有するソルダーレジスト組成物の塗布膜の硬化物が濃アルカリ溶液及び／又は過マンガン酸塩溶液に侵され難い、例えば分解や溶解しないのは勿論のこと、膨潤もし難いエポキシ樹脂を挙げることができる。「デスミアされ難い」ことの目安としては、上記したように、デスミア処理された後ではその前に比べて表面粗さが平均５μｍ未満である場合を挙げることができ、これを基準にして樹脂を選択すればよい。
このようなエポキシ樹脂としては、上記一般式〔化１〕で示される分子構造及び上記一般式〔化２〕で示される分子構造の両方のいずれも分子内に有しないエポキシ樹脂が挙げられる。
具体的には、フェノールノボラック型エポキシ樹脂として、エピコート １５２、同１５４（以上、ジャパンエポキシレジン社製）、エピクロン Ｎ−７４０、同Ｎ−７７０（以上、大日本インキ化学工業社製）、クレゾールノボラック型エポキシ樹脂として、エピクロン Ｎ−６８０、同Ｎ−６９５（以上、大日本インキ化学工業社製）、ジシクロペンタジエン型エポキシ樹脂として、エピクロンＨＰ−７２００（大日本インキ化学工業社製）、ナフタレン型エポキシ樹脂として、エピクロン ＨＰ−４０３２（大日本インキ化学工業社製）、その他のエポキシ樹脂として、エピコート ＹＸ−４０００、エピコート １０３１Ｓ（以上、ジャパンエポキシレジン社製）、エポトート ＹＳＬＶ−８０ＸＹ（東都化成社製）、ＮＣ−３０００、ＮＣ−３０００Ｓ−Ｈ（以上、日本化薬社製）が挙げられる。
【００１３】
また、ソルダーレジスト組成物（Ａ）及び（Ｂ）に含有される「エポキシ基を有しないエポキシ樹脂硬化性化合物」としては、エポキシ樹脂を硬化させる硬化剤ということもできる。
具体的には、シヨウノール ＢＲＧ−５５５、同ＢＲＧ−５５６（以上、昭和高分子社製）、フェノライト ＴＤ−２０９０、同２１３１、ベスモール ＣＺ−２５６−Ａ（以上、大日本インキ化学工業社製）、ミレックス ＸＬＣ−４Ｌ、同ＸＬＣ−ＬＬ（以上、三井化学社製）、ＰＰ−７００、同１０００、ＤＰＰ−Ｍ、同３Ｈ、ＤＰＡ−１４５、同１５５（以上、新日本石油化学社製）、ＳＫ−レジンＨＥ１００Ｃ、ＳＫ−レジンＨＥ５１０、同９００（以上、住金ケミカル社製）が挙げられる。
【００１４】
上記ソルダーレジスト組成物（Ａ）及び（Ｂ）には、硬化触媒を含有させてもよく、その硬化触媒としては、ジシアンジアミド、芳香族アミン、イミダゾール類、酸無水物等が挙げられる。また、シリカ、硫酸バリウム、アルミナ、タルク、マイカ等の体質顔料、銅フタロシアニン、イソインドリン、カーボンブラック等の着色顔料、消泡剤、レオロジー調整剤等の各種添加剤、グリコールエーテル類、エステル類等の溶剤を含有させてもよく、具体的には、通常用いられるアルカリ現像型のソルダーレジスト組成物に使用されているものも使用できる。
上記ソルダーレジスト組成物（Ａ）及び（Ｂ）の組成は、「デスミアされ易いエポキシ樹脂」又は「デスミアされ難いエポキシ樹脂」１００部（「部」は質量部を意味する。以下同様。）に対して、「エポキシ基を有しないエポキシ樹脂硬化性化合物」３０〜５０部、硬化触媒を４〜６部、体質顔料５０〜８０部、添加剤２〜５部、溶剤３５〜５５部含有させることが好ましい。また、ソルダーレジスト組成物（Ａ）及び（Ｂ）において「デスミアされ易いエポキシ樹脂」と「デスミアされ難いエポキシ樹脂」を混合して用いても良く、その比率としては、エポキシ樹脂１００部中「デスミアされ易いエポキシ樹脂」を２５〜１００部添加すると、その塗布膜の表面粗さ（平均値Ｒｔｍ）が５μｍ以上でデスミアされ易い塗膜となり、ソルダーレジスト組成物（Ａ）として使用可能となる。逆に「デスミアされ易いエポキシ樹脂」の添加量が２５部未満である場合はデスミアされ難い塗膜となり、ソルダーレジスト組成物（Ｂ）として使用可能となる。上記ソルダーレジスト組成物（Ａ）及び（Ｂ）ともに共通の使用量で表すことができるが、具体的には各成分について上記の例示した化合物を用いる。
このような組成のソルダーレジスト組成物（Ａ）及び（Ｂ）は、「エポキシ基を有しないエポキシ樹脂硬化性化合物」や、硬化触媒が多過ぎると、粘度が上昇し易く、保存安定性が良くなく、少な過ぎるとその組成物の塗布膜の硬化を十分に行ない難くなる。体質顔料が多過ぎると塗工性がよくなく、塗布した後に平坦化する性能のレベリング性がよくならず、また、レーザー加工後のデスミア工程では、ビアホールの側面や周囲から体質顔料が抜け落ちる、いわゆる脱粒が発生してビアホールの形状を不安定にし、少な過ぎるとその塗布膜の硬化膜の硬度等の塗膜性能が向上しない。添加剤、特に消泡剤が多過ぎると塗布膜の表面に消泡剤が溶出するいわゆるブリード現象によりソルダーレジスト組成物（Ａ）の塗布膜の上にソルダーレジスト組成物（Ｂ）の塗布膜を積層する際の接着性が良くならず、少な過ぎると塗布膜の脱泡、破泡性が良くならない。溶剤が多過ぎるとソルダーレジスト組成物（Ａ）又は（Ｂ）が低粘度となり、導体回路パターンへのカバーリング（被覆性）が良くならず、また、回路基板を垂直に立てた状態で乾燥した際に塗布膜が垂れ易くなり、少な過ぎると塗布膜のレベリング性が良くならず塗布膜の平滑性が得られない。
【００１５】
上記ソルダーレジスト組成物（Ａ）及び（Ｂ）を用いてソルダーレジスト膜を形成するには、図１に示すように、導体パターンを形成しただけの回路基板１の一方の片面には回路配線１ａ、他方の片面には回路配線１ｂが形成されているが、まず、▲１▼ その回路配線１ａ、１ｂについて脱脂、ソフトエッチング等の基板の表面処理を行なった後、▲２▼ それぞれの面にソルダーレジスト組成物（Ａ）を液膜厚（未乾燥状態の膜厚）１０〜５０μｍ程度で均一に塗布する。その塗布方法は、スクリーン印刷、ロールコート法、カーテンコート法、静電塗装法のいずれも使用できるが、均一に塗布できるものであればその他の塗布方法を用いてもよい。その塗布をした後、８０〜１８０℃の温度で１５〜６０分間程度乾燥、硬化させて第１層の硬化塗膜（デスミア用硬化樹脂膜）２ａ、２ｂを形成する。続いて、▲３▼ ソルダーレジスト組成物（Ａ）を塗布したと同様にして、ソルダーレジスト組成物（Ｂ）を塗布し、乾燥、硬化処理させて第２層の硬化塗膜（耐デスミア用硬化樹脂膜）３ａ、３ｂを形成する。
また、ソルダーレジスト組成物（Ｂ）をポリエステル等のフィルムに塗布し、さらにその塗布膜の上にソルダーレジスト組成物（Ａ）を塗布し、ついでこれらの積層した塗布膜を加熱等により半硬化状態にし、それから基板の導体回路パターンを含む表面にその半硬化膜側を圧着し、さらにその半硬化膜からフィルムを剥離してその半硬化膜を転写し、ついでその半硬化膜を加熱等により完全硬化させて硬化膜を形成してもよい。
次に、▲４▼ 第１層の硬化塗膜２ａに第２層の硬化塗膜３ａを積層して得られた積層硬化塗膜の上記回路配線１ａの所定の対応する位置及び第１層の硬化塗膜２ｂに第２層の硬化塗膜３ｂを積層して得られた積層硬化塗膜の上記回路配線１ｂの所定の対応する位置にレーザーを照射してビアホール４ａ、４ｂを形成し、回路配線１ａ、１ｂを露出させる。その後、そのビアホール４ａ、４ｂ内の回路配線１ａ、１ｂの導体上には除去し切れないで残留した成分（スミア）が存在するが、そのスミアを過マンガン酸塩溶液等のデスミア処理の薬液により分解除去するデスミアを行ない、▲５▼ 最後に回路配線１ａ、１ｂに金めっきを施すか、プリフラックス処理した後、半導体チップ６をその下面に搭載した金バンプやはんだバンプ５により接合して搭載し、はんだボールからなるバンプ７を形成する。なお、バンプ５の形成方法及び半導体チップの搭載方法としては、金ワイヤーを半導体チップに溶接して金バンプを形成した後、導電性樹脂で接合し、アンダーフィルム樹脂で固定するＥＳＣ（ｅｐｏｘｙ ｓｏｌｄｅｒ ｅｎｃａｐｓｕｌａｔｅｄ ｃｏｎｎｅｃｔｉｏｎ）アンダーフィル工法、異方導電性フィルムで接合、固定するＡＣＦ（ａｎｉｓｏｔｒｏｐｉｃ ｃｏｎｄｕｃｔｉｖｅ ｆｉｌｍ ｃｏｎｎｅｃｔｉｏｎ）工法、ソルダーペーストを印刷してはんだバンプを形成し、リフローにて接合するＣ４（ｃｏｎｔｒｏｌｌｅｄ ｃｏｌｌａｐｓｅｃｈｉｐ ｃｏｎｎｅｃｔｉｏｎ）工法などが挙げられるが、バンプ形成及びチップ搭載には上記のいずれの方法を用いてもよい。また、バンプ７の形成方法としては、ビアホール内のランド上にはんだボールを載置し、リフローにより加熱溶解させて形成する方法や、ソルダーペーストを塗布した後、リフローにより加熱溶解させて形成する方法が挙げられるが、いずれの方法を用いてもよい。
なお、図示省略したが、導体回路パターンを形成しただけの回路基板１の基板にはスルーホールが形成され、上記回路配線１ａと１ｂはスルーホール内壁に形成されためっき膜により接続されている。
【００１６】
【実施例】
本発明の一実施例を説明するが、本発明はこれに限定されるものではない。
実施例１
（ソルダーレジスト組成物（Ａ）の具体例の調製）
エピコート １００１（ジャパンエポキシレジン社製、ビスフェノールＡ型エポキシ樹脂）４０ｇにミレックス ＸＬＣ−ＬＬ（三井化学社製フェノール樹脂）１５ｇを加え、さらに溶剤としてＤＢＥ（デュポン社製のエステル系溶剤）１７ｇを加え、混合溶液を調製した。得られた混合溶液にＦＢ−３ＳＤＣ（電気化学工業社製の溶融シリカ）２５ｇ、ＤＩＣＹ−７（ジャパンエポキシレジン社製のジシアンジミアド）１ｇ、ＫＳ−６６（信越化学社製のシリコン系消泡剤）１ｇ、アエロジルＲ−９７４（日本アエロジル社製のヒュームドシリカ）０．５ｇを加え攪拌した。続いて、この混合物を３本ロールミルで混練し、ソルダーレジスト組成物Ａ１を調製した。
（塗工用硬化性樹脂組成物（Ｂ）の具体例の調製）
エピクロン Ｎ−６９５（大日本インキ化学工業社製のクレゾールノボラック型エポキシ樹脂）４０ｇにミレックス ＸＬＣ−ＬＬ（三井化学社製フェノール樹脂）１５ｇを加え、さらに溶剤としてＤＢＥ（デュポン社製のエステル系溶剤）１７ｇを加え、混合溶液を調製した。得られた混合溶液にＦＢ−３ＳＤＣ（電気化学工業社製の溶融シリカ）２５ｇ、ＤＩＣＹ−７（ジャパンエポキシレジン社製のジシアンジミアド）１ｇ、ＫＳ−６６（信越化学社製のシリコン系消泡剤）１ｇ、アエロジルＲ−９７４（日本アエロジル社製のヒュームドシリカ）０．５ｇを加え攪拌した。続いて、この混合物を３本ロールミルで混練し、ソルダーレジスト組成物Ｂ１を調製した。
【００１７】
（回路基板の製造）
図１に示す手順に従って、各工程をより具体的に行なうが、▲１▼ 銅張り積層板をエッチング処理して形成した導体回路パターン１ａ、１ｂを有する回路基板１に脱脂、ソフトエッチング等の前処理を施し、▲２▼ 上記で得られたソルダーレジストＡ１をスクリーン印刷により塗布し、１５０℃で１時間乾燥、熱硬化処理を行ない、第１層の硬化塗膜２ａ、２ｂを形成する。ついで、▲３▼ ソルダーレジスト組成物Ａ１の代わりに上記で得られたソルダーレジスト組成物Ｂ１を使用したこと以外は同様にして、第２層の硬化塗膜３ａ、３ｂを形成し、第１層の硬化塗膜２ａと第２層の硬化塗膜３ａとを合わせて厚さ２０μｍの積層硬化塗膜を形成し、同様に第１層の硬化塗膜２ｂと第２層の硬化塗膜３ｂとを合わせて厚さ２０μｍの積層硬化塗膜を形成した。
次に、▲４▼ この積層硬化塗膜について上記導体回路パターン１ａ、１ｂに対応する個所に炭酸ガスレーザー光を照射し、直径（ランド径）５０μｍのビアホール４ａ、４ｂを形成し、導体回路パターン１ａ、１ｂを露出させる。ついで、上記▲１▼〜▲３▼の処理をした回路基板１をエンプレート ＭＬＢ−４９６Ａ（メルテック社製の水酸化ナトリウム水溶液を主成分とした溶液）及び同４９６Ｂ（メルテック社製の１−メトキシ−２−プロパノールを含む溶液）と蒸留水の混合液に５５〜６５℃で、２〜２０分浸漬し、ビアホール４ａ、４ｂ内の導体回路パターン１ａ、１ｂ上に見られるスミアを膨潤させ、ついでエンプレート ＭＬＢ−４９７Ａ液（メルテック社製の過マンガン酸ナトリウム水溶液を主成分とした溶液）及び同４９７Ｂ（メルテック社製の水酸化ナトリウムを主成分とした溶液）と蒸留水の混合液に６０〜９５℃、５〜２０分浸漬して膨潤したスミアを分解し、除去する。そしてさらにエンプレート ＭＬＢ−７９０（メルテック社製の硫酸ヒドロキシルアミン水溶液を主成分とする溶液）と濃硫酸及び蒸留水の混合液に６０〜６５℃で、５〜１０分間浸漬し、中和処理する。▲５▼ その後、金メッキ処理又はプリフラックス処理を行ない、バンプ５を形成した半導体チップ６をそのバンプ５の溶融による接合により搭載する。また、そのチップを搭載した側とは反対側の他方の面にははんだボール７を搭載する。このようにして得られた半導体チップを搭載した実装用回路基板はマザーボードにそのはんだボールの溶融による接合により実装される。
【００１８】
実施例２、３
実施例１において、表１に示すように、エピクロン Ｎ−６９５の代わりに、エピコート １０３１Ｓ（ジャパンエポキシレジン社製のエポキシ樹脂）、エピクロン ＨＰ−７２００（大日本インキ化学工業社製のジシクロペンタジエン型エポキシ樹脂）をそれぞれ用いたこと以外は同様にしてそれぞれのソルダーレジスト組成物Ｂ２、Ｂ３を調製し、表２に示すように、これらのそれぞれを使用したこと以外は実施例１と同様にしてそれぞれ実施例２、３の実装用回路基板を製造した。
【００１９】
実施例４
実施例１において、表１に示すように、エピコート １００１の代わりにエポトート ＹＤＦ−２００１（東都化成社製ビスフェノールＦ型エポキシ樹脂）を用いたこと以外は同様にしてソルダーレジスト組成物Ａ２を調製し、表２に示すように、このソルダーレジスト組成物Ａ２をソルダーレジスト組成物Ａ１の代わりに使用したこと以外は同様にして実装用回路基板を製造した。
【００２０】
実施例５、６
実施例２、３において、表２に示すように、実施例４で用いたソルダーレジスト組成物Ａ２をソルダーレジスト組成物Ａ１の代わりに使用したこと以外は同様にしてそれぞれ実施例５、６の実装用回路基板を製造した。
【００２１】
比較例１
実施例１において、表２に示すように、ソルダーレジスト組成物Ａ１の代わりにソルダーレジスト組成物Ｂ１、ソルダーレジスト組成物Ｂ１の代わりにソルダーレジテト組成物Ａ１を用いたこと、すなわちＡ１とＢ１を逆にして用いたこと以外は同様にして実装用回路基板を製造した。
【００２２】
比較例２
実施例４において、表２に示すように、ソルダーレジスト組成物Ａ２の代わりにソルダーレジスト組成物Ｂ１、ソルダーレジスト組成物Ｂ１の代わりにソルダーレジスト組成物Ａ２を用いたこと、すなわちＡ２とＢ１を逆にして用いたこと以外は同様にして実装用回路基板を製造した。
【００２３】
（回路基板の評価）
（１）デスミア耐性試験
各実施例、比較例において、実施例１と同様に上記▲４▼までの処理をした回路基板、すなわちデスミア処理した回路基板を試験片にして、それぞれの積層硬化塗膜（第１層の硬化塗膜２と第２層の硬化塗膜３の積層硬化塗膜）表面の表面粗さを表面粗さ計（東京精密社製）で測定し、その平均値Ｒｔｍを示す。また、その積層硬化塗膜の表面状態を目視により観察し、以下の基準に従い評価した。
○：全く変化が見られない
△：わずかに変化が見られる
×：塗膜が粗化ないし剥離している
なお、実施例１において、ソルダーレジスト組成物（Ａ）中、エピコート１００１（ＥＰ−１００１）４０ｇにおいて、その一部をエピクロンＨＰ−７２００（ＨＰ−７２００）に置き換えて使用した（ＨＰ−７２００ １００部中のＥＰ−１００１の添加量（置換量）を２５部毎に０（ＨＰ−７２００：４０ｇ、ＥＰ−１００１：０ｇ）〜１００部（ＥＰ−１００１：４０ｇ、ＨＰ−７２００：０ｇ）まで変化させて添加）こと以外は同様にして▲２▼までの工程を行なって第１層の硬化塗膜２ａ、２ｂを形成し、その塗膜について上記と同様にして表面粗さ（平均値Ｒｔｍ）を測定した結果を図２に示す。図２から、ＥＰ−１００１（デスミアされ易いエポキシ樹脂）をＨＰ−７２００（デスミアされ難いエポキシ樹脂）１００部中に２５〜１００部添加（置換）すると、Ｒｔｍは５μｍ以上となり、デスミアされ易い塗膜となることがわかる。
【００２４】
（２）はんだ耐熱性試験
前項（１）の試験片について、ＪＩＳ Ｃ ６４８１の試験方法に従って、２６０℃のはんだ槽に３０秒浸漬後、セロハン粘着テープ（セロハンは商品名）によるピーリング試験を１サイクルとし、計１〜３サイクルを行った後の塗膜状態を目視により観察し、以下の基準に従い評価した。
◎：３サイクル後も塗膜に変化がないもの
○：３サイクル後に剥離が生じているもの
△：２サイクル後に剥離が生じているもの
×：１サイクル後に剥離が生じているもの
（４）耐溶剤性試験
前項（１）の試験片について、その試験片を常温のジクロロメタンに３０分間浸漬したのち、塗膜状態を目視により観察し、以下の基準に従い評価した。
○：全く変化が見られないもの
△：わずかに変化が見られるもの
×：塗膜が膨潤し剥離しているのもの
（５）絶縁抵抗
前項（１）の試験片について、ＩＰＣ−ＴＭ−６５０のＩＰＣ−ＳＭ８４０ＣＢ−２５テストクーポンのくし型電極を用い、８５℃、８５％Ｒ．Ｈ．（相対湿度）の雰囲気下で５００時間加湿した後の塗膜の絶縁抵抗をＤＣ（直流）５０Ｖを印加して測定した
【００２５】
【表１】
Figure 2004240233
【００２６】
【表２】
Figure 2004240233
【００２７】
上記表２から、実施例のものは比較例のものに比べ、「デスミア耐性」が表面粗さではほぼ１０倍もよく、「表面状態」も優れ、「はんだ耐熱性」、「耐溶剤性」、「絶縁抵抗」においても優れることがわかる。これは、デスミア処理ではビアホール内の導体部（銅箔）に残留しているレジスト成分（スミア）の除去は、積層硬化塗膜において第１層の硬化塗膜が下側になるか第２層の硬化塗膜が下側になるかに関係なく良く行われるが、その積層硬化塗膜の損傷（デスミア処理の薬液に硬化塗膜が侵されること）についてはその積層の順序が重要であり、第１層のデスミアされ易い硬化塗膜が下側（導体回路パターン上）になり第２層のデスミアされ難い硬化塗膜が上側（回路基板表面）になる必要があり、この第２の硬化塗膜がデスミア処理の薬液に侵されない性質が極めて重要であることを示す。なお、スミアは第１層の硬化塗膜、第２層の硬化塗膜の両者の硬化塗膜の樹脂成分が混じったものとなり、しかもその樹脂成分はレーザー光の照射により変質し、デスミア処理により除去され易くなっている。
このように第２層の硬化塗膜が侵されないことにより「はんだ耐熱性」、「耐溶剤性」、「絶縁抵抗」も優れた結果が得られるということができる。
第１層の硬化塗膜は上記一般式〔化１〕、〔化２〕のいずれの分子構造、すなわちビスフェノール型エポキシ樹脂の連結鎖が嵩高い分子団による立体障害の少ないことによりデスミアされ易いものと考えられ、逆にいえばエポキシ基の連結鎖が分子団により保護（立体障害によりデスミア処理の薬液による浸食が起こり難い）されている分子構造を有していればデスミア耐性か高いということができる。
【００２８】
【発明の効果】
本発明によれば、エポキシ樹脂についてデスミアされ易いものとされ難いものを前者を含む組成物の硬化膜の上に、後者を含む組成物の硬化膜を積層して用いたので、スミアを薬液を用いて溶解除去する湿式法によるデスミアの処理を行なってもビアホール内部に残留するスミアの除去が良好に行われるとともに、そのデスミアの薬液に侵されない塗膜を形成できるソルダーレジスト組成物、回路基板及びその製造方法を提供することができる。
また、そのデスミアの処理を行った後の後続の処理に悪影響を与えたり、回路基板に必要な特性を低下させたりすることがない塗膜を形成できるソルダーレジスト組成物、回路基板及びその製造方法を提供することができる。
【図面の簡単な説明】
【図１】本発明の一実施例の回路基板の製造工程を示す説明図である。
【図２】エポキシ樹脂についてデスミアされ易いものとされ難いものの構成比による塗膜の平均粗さＲｔｍの変化を示すグラフである。
【符号の説明】
１ 回路基板
１ａ、１ｂ 導体回路パターン
２ａ、２ｂ 第１層の硬化塗膜（デスミア用硬化樹脂膜）
３ａ、３ｂ 第２層の硬化塗膜（耐デスミア用硬化樹脂膜）
４ａ、４ｂ ビアホール[0001]
[Industrial applications]
The present invention provides a solder resist that facilitates removal of smear, which is a component remaining in a via hole formed in a solder resist film on a circuit board by a laser, and that does not damage the solder resist film during the removal. The present invention relates to a resist composition, a circuit board using the same, and a method for manufacturing the same.
[0002]
[Prior art]
A circuit board is used to mount a circuit pattern on a circuit board by soldering electronic components to the soldering lands of the pattern.The circuit parts except the soldering lands are permanently protected. It is covered with a solder resist film as a film. This prevents solder from sticking to unnecessary parts when soldering electronic components to the printed wiring board, and also prevents the conductors of the circuit from being directly exposed to air and corroded by oxidation and humidity. I do.
In this way, not only a single-layer circuit board that forms a solder resist film pattern (pattern covering a circuit part except soldered lands) on the board, but also a conductor circuit pattern is formed on the board, and then an interlayer insulation A coating layer of a material is formed, a via hole communicating with the conductor circuit pattern of the substrate is formed in the coating layer by a laser, and further, an electroless plating film is provided on the coating layer surface including the via hole, and the plating film is subjected to a conductor circuit portion. Is covered with a resin film, the other portions are removed by etching, and finally the resin film is peeled off to form a conductor circuit pattern, and a solder resist film is formed thereon. This is sequentially repeated, a circuit is formed in each layer to be laminated, and this is connected by a via hole, so-called a multilayer circuit board, a solder resist composition is applied, and exposure, development, and post cure are sequentially performed to form a pattern of the insulating film. Form. In this case, in the case of a normal solder resist film pattern, the above exposure is often performed using a scattered light exposure device using a metal halide lamp, but when forming a fine solder resist film pattern, In general, a parallel light exposure device or a projection exposure device using a high-pressure mercury lamp is used.
However, when a finer solder resist film pattern is required, a portion corresponding to the soldering land of the solder resist film is decomposed and removed using a carbon dioxide laser, a UV-YAG laser, an excimer laser, or the like. The soldering lands are exposed, but components (smears) of the solder resist film remaining without being removed are generated in the soldering lands. When such a smear occurs, not only a portion that is not plated even if a plating process is performed (unplated portion) easily occurs, but also a bonding failure may occur even when an electronic component is soldered. It is necessary to provide a desmearing step for performing so-called desmearing.
[0003]
Particularly, when mounting a semiconductor chip on a circuit board, an FC-BGA (flip chip pole grid array), a CSP (chip size package) and the like are bonded by forming gold bumps or solder bumps on the semiconductor chip side as a bonding method. You. A solder ball is mounted on the other surface of the substrate opposite to the side on which the chip is mounted. Thus, the circuit board having the semiconductor chip mounted on one side by bonding is mounted on the motherboard by bonding with the solder balls mounted on the other side. Irrespective of mounting gold bumps, solder bumps or solder balls, the solder resist film formed on one side is irradiated with laser light to form via holes, and the conductor circuit pattern formed on each side is formed. Although the portion corresponding to the via hole is exposed, since the diameter of the via hole is small, even the presence of a small amount of smear tends to cause a bonding failure of the gold bump, the solder bump or the solder ball mounted on the via hole. Becomes even more important.
In the manufacture of the above circuit board, as a desmear method, a wet method of swelling with a concentrated alkaline solution and subsequently decomposing and removing smear with a permanganate solution or a dry method of decomposing and removing with a plasma or excimer laser is used. However, the wet method is superior in terms of cost and production efficiency, and this wet method is generally used.
[0004]
By the way, for the formation of the above solder resist film, an alkali-soluble photosensitive resin obtained by reacting a reaction product of a novolak type epoxy resin and an unsaturated monocarboxylic acid with a saturated or unsaturated polybasic anhydride is used. (See, for example, JP-A-61-243869 (Japanese Patent No. 1799319)).
In a multilayer circuit board, a resin composition comprising a bisphenol A type epoxy resin and a terminally epoxidized polybutadiene rubber is used as an interlayer insulating material (see, for example, JP-A-11-001547).
[0005]
[Patent Document 1]
JP-A-61-243869
[Patent Document 2]
JP-A-11-001547
[0006]
[Problems to be solved by the invention]
However, when performing desmearing by the wet method, the entire circuit board on which the solder resist film has been formed is immersed in a concentrated alkaline solution and then a permanganate solution, so that only the decomposition and removal of smears remaining in the via holes are performed. In addition, the surface of the solder resist film is easily affected by this solution. For example, in an alkali-developing solder resist composition as described in JP-A-61-243869, the carboxylic acid remaining in the alkali-soluble photosensitive resin reacts in a swelling step of swelling with a concentrated alkali solution, Since the solder resist film is attacked, there is a problem that the coating film is decomposed and peeled in a subsequent immersion step of immersion in a permanganate solution, and a good solder resist coating film cannot be obtained.
When a resin composition as disclosed in JP-A-11-001547 is used as an interlayer insulating material, a conductor circuit pattern is provided in advance on a coating layer of the interlayer insulating material, and a conductive circuit pattern is formed thereon. Although the solder resist film is formed, the coating film does not peel off in the dipping step of dipping in the permanganate solution, but when forming the conductor circuit pattern in the previous step, the coating layer of the interlayer insulating material is formed. In order to perform electroless copper plating well, irregularities are formed on the entire surface of the coating layer, that is, so-called roughening of the coating film is performed, so a solder formed on the roughened coating layer Regarding the resist film, the influence of the immersion process of immersing in the permanganate solution appears, and when soldering electronic components to the conductor circuit pattern, peeling occurs, so-called solder heat resistance decreases. Ri and insulation reliability of the solder resist film itself decreases, it is liable to reduce the required characteristics as a solder resist film.
[0007]
A first object of the present invention is to provide a solder resist composition and a circuit which can perform desmearing well even when performing desmearing treatment by a wet method of decomposing and removing smears with a chemical solution, and can form a coating film not affected by the chemical solution. It is to provide a substrate and a method for manufacturing the same.
A second object of the present invention is to provide a solder resist, a circuit board, and a method of manufacturing the same, which do not adversely affect subsequent processing after the desmear processing and do not deteriorate characteristics required for the circuit board. Is to provide.
[0008]
[Means for Solving the Problems]
The present inventors have conducted intensive studies to solve the above problems, and as a result, laminated a desmear cured resin film containing an epoxy resin that is easily desmeared and a desmear resistant cured resin film containing an epoxy resin that is hardly desmeared. The present inventors have found that the above object can be achieved by using a laminated cured resin film as a solder resist film, and have accomplished the present invention.
That is, according to the present invention, (1) a solder resist film for covering the electronic circuit wiring is formed on a substrate on which the electronic circuit wiring is formed, and a via hole communicating with the electronic circuit wiring is formed in the solder resist film by laser. It is another object of the present invention to provide a solder resist composition containing the epoxy resin for the solder resist film, which is easy to perform desmearing for removing smear which is a component remaining in a conductor portion of a wiring in the via hole.
Further, according to the present invention, (2) a solder resist film for covering the electronic circuit wiring is formed on the substrate on which the electronic circuit wiring is formed, and a via hole communicating with the electronic circuit wiring is formed in the solder resist film by laser. However, the solder resist composition containing the epoxy resin for the solder resist film, which does not easily perform desmear to remove smear, which is a component remaining in the conductor portion of the wiring in the via hole, (3), the epoxy resin that is easily desmeared, A solder resist composition according to the above (1), which is a thermosetting resin having a molecular structure represented by the following general formula [Chemical formula 1] and / or a molecular structure represented by the following general formula [Chemical formula 2] in the molecule;
Embedded image
Figure 2004240233
(Where R 1 Is CH 2 Or C (CH 3 ) 2 And m represents one or more. )
Embedded image
Figure 2004240233
(Where R 2 Is CH 2 Or C (CH 3 ) 2 And n represents one or more. )
(4) The epoxy resin which is hardly desmeared is a thermosetting resin having no molecular structure represented by the following general formula [Chemical formula 1] and / or a molecular structure represented by the following general formula [Chemical formula 2] in the molecule. (2) a solder resist composition,
Embedded image
Figure 2004240233
(Where R 1 Is CH 2 Or C (CH 3 ) 2 And m represents one or more. )
Embedded image
Figure 2004240233
(Where R 2 Is CH 2 Or C (CH 3 ) 2 And n represents one or more. )
(5) The solder resist composition according to any one of the above (1) to (4), which contains an epoxy resin curable compound having no epoxy group, (6), desmear is a wet method using a chemical solution for removing smear. Performing a solder resist composition according to any one of the above (1) to (5), (7), a solder resist film for covering the electronic circuit wiring on a substrate on which the electronic circuit wiring is formed, and applying the solder resist film with a laser. A circuit board obtained by forming at least a via hole communicating with the electronic circuit wiring in a film, and performing desmearing to remove smear as a component remaining in a conductor portion of the wiring in the via hole, wherein the solder is provided. The resist film is
(1) a cured resin film for desmear obtained by applying and curing a solder resist composition (A) containing an epoxy resin which easily performs desmear according to claim 1,
(2) Desmear-resistant hardening by applying and curing the solder resist composition (B) containing the epoxy resin which is hardly desmeared according to claim 2, 4, 5 or 6 on the hardened resin film for desmear. Having laminated resin films
(8) forming a solder resist film covering the electronic circuit wiring on the substrate on which the electronic circuit wiring is formed, forming a via hole communicating with the electronic circuit wiring in the solder resist film by laser; A method for manufacturing a circuit board obtained by performing at least desmearing to remove smear which is a component remaining in a conductor portion of a wiring in a via hole, wherein the solder resist film is
(1) After applying the solder resist composition (A) containing the epoxy resin which easily performs desmear according to claim 1, 3, and 6, and forming a cured desmear cured resin film,
(2) Desmear-resistant hardening by applying and curing the solder resist composition (B) containing the epoxy resin which is hardly desmeared according to claim 2, 4, 5 or 6 on the hardened resin film for desmear. Form a resin film
A method of manufacturing a circuit board is provided.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
In the present invention, as the “epoxy resin that is easily desmeared” contained in the solder resist composition (A), a cured product of a coating film of the solder resist composition containing this resin is a concentrated alkaline solution and / or permanganic acid. An epoxy resin that is easily attacked by a salt solution (desmear solution), for example, easily decomposed, dissolved, swelled, or easily peeled off when attached to a metal conductor, and thus easily removed. Can be mentioned. As a guideline of "easiness of desmearing", after the cured product of the coating film is treated with a concentrated alkali solution and then with a permanganate solution (desmear treatment), the surface roughness is 5 μm on average compared to before. The above case can be mentioned, and the resin may be selected based on this.
Examples of such an epoxy resin include an epoxy resin having one or both of a molecular structure represented by the general formula [Chemical Formula 1] and a molecular structure represented by the general formula [Chemical Formula 2] in a molecule. . In these general formulas [Chemical Formula 1] and [Chemical Formula 2], R 1 , R 2 Is CH 2 Or C (CH 3 ) 2 Which may be the same or different, and m and n indicate how many molecular structures in each [] are present in the molecule, and the numbers are average values. In the case of 1, each molecule has an average of one molecular structure in the molecule, and when each of them shows two or more pluralities, the plurality of molecules are averaged in the molecule. Indicates that it has a molecular structure. The reason why the resin having such a molecular structure is “easy to be desmeared” is that a concentrated alkali solution or a permanganate solution is added to a hydroxyl group portion and / or a methylene chain portion and an ether bond portion in the molecule according to the following reaction formula This is considered to be due to the fact that the swelling, dissolution, or decomposition easily occurs as shown in [1].
[0010]
Embedded image
Figure 2004240233
(R is -O-CH in [Chemical Formula 1] or [Chemical Formula 2] 2 (OH) -CH 2 -Represents the residue bound to the left side. )
[0011]
Specifically, as a bisphenol A type epoxy resin, Epicoat 1001, 1002, and 1003 (all manufactured by Japan Epoxy Resin Co., Ltd.), Epicron 1050 and 3050 (all manufactured by Dainippon Ink and Chemicals, Inc.), Araldite AER6071, 6072 (all manufactured by Asahi Ciba), Epototo YD-011 and YD-012 (all manufactured by Toto Kasei), and as a bisphenol F type epoxy resin, Epototo YDF-2001 and 2004 (manufactured by Toto Kasei); Examples of the hydrogenated bisphenol A type epoxy resin include Epicron EXA-7015 (manufactured by Dainippon Ink and Chemicals, Inc.).
[0012]
Further, as the “epoxy resin that is hardly desmeared” contained in the curable resin composition for coating (B), a cured product of a coating film of a solder resist composition containing this resin is a concentrated alkaline solution and / or Epoxy resins that are not easily attacked by a manganate solution, for example, are not decomposed or dissolved, and are also hardly swelled. As a guideline of “it is hard to be desmeared”, as described above, after desmearing, the case where the surface roughness is less than 5 μm on average compared to before, can be cited. Just select.
Examples of such an epoxy resin include an epoxy resin having neither the molecular structure represented by the general formula [Chemical Formula 1] nor the molecular structure represented by the general formula [Chemical Formula 2] in a molecule.
Specifically, as a phenol novolak type epoxy resin, Epicoat 152, Epicoat 154 (all manufactured by Japan Epoxy Resin), Epicron N-740, N-770 (all manufactured by Dainippon Ink and Chemicals), cresol novolak Epicron N-680 and N-695 (above, manufactured by Dainippon Ink and Chemicals, Inc.) as epoxy resins, Epicron HP-7200 (by Dainippon Ink and Chemicals, Inc.) and naphthalene type as dicyclopentadiene-type epoxy resins As an epoxy resin, Epicron HP-4032 (manufactured by Dainippon Ink and Chemicals, Inc.), and as other epoxy resins, Epicoat YX-4000, Epicoat 1031S (above, manufactured by Japan Epoxy Resin) and Epototo YSLV-80XY (manufactured by Toto Kasei Co., Ltd.) ), NC-3000, NC- 3000SH (all manufactured by Nippon Kayaku Co., Ltd.).
[0013]
The “epoxy resin curable compound having no epoxy group” contained in the solder resist compositions (A) and (B) can also be referred to as a curing agent for curing an epoxy resin.
Specifically, Shonool BRG-555 and BRG-556 (all manufactured by Showa Polymer Co., Ltd.), phenolite TD-2090 and 2131, Vesmall CZ-256-A (all manufactured by Dainippon Ink and Chemicals, Inc.) , Millex XLC-4L, XLC-LL (Mitsui Chemicals), PP-700, 1000, DPP-M, 3H, DPA-145, 155 (Mixed by Nippon Petrochemical), SK-Resin HE100C, SK-Resin HE510, and SK-Resin HE900 (all manufactured by Sumikin Chemical Co., Ltd.).
[0014]
The solder resist compositions (A) and (B) may contain a curing catalyst, and examples of the curing catalyst include dicyandiamide, aromatic amines, imidazoles, and acid anhydrides. In addition, extenders such as silica, barium sulfate, alumina, talc, and mica; coloring pigments such as copper phthalocyanine, isoindoline, and carbon black; various additives such as antifoaming agents and rheology modifiers; glycol ethers and esters; May be contained. Specifically, those used in a commonly used alkali development type solder resist composition can also be used.
The composition of the solder resist compositions (A) and (B) is based on 100 parts of “an epoxy resin that is easy to be desmeared” or “an epoxy resin that is hard to be desmeared” (“parts” means parts by mass; the same applies hereinafter). 30 to 50 parts of an "epoxy resin curable compound having no epoxy group", 4 to 6 parts of a curing catalyst, 50 to 80 parts of an extender, 2 to 5 parts of an additive, and 35 to 55 parts of a solvent. preferable. Further, in the solder resist compositions (A) and (B), "an epoxy resin which is easy to be desmeared" and an "epoxy resin which is hard to be desmeared" may be mixed and used. When 25 to 100 parts of an "epoxy resin which is easy to be added" is added, the coating film has a surface roughness (average value Rtm) of 5 [mu] m or more, and becomes a coating film which is easily desmeared and can be used as the solder resist composition (A). Conversely, if the amount of the “epoxy resin that is easily desmeared” is less than 25 parts, the resulting coating film is less likely to be desmeared and can be used as the solder resist composition (B). Although the above solder resist compositions (A) and (B) can be represented by a common use amount, specifically, the compounds exemplified above are used for each component.
When the solder resist compositions (A) and (B) having such a composition have too much “epoxy resin curable compound having no epoxy group” or too much curing catalyst, viscosity tends to increase and storage stability is good. If the amount is too small, it becomes difficult to sufficiently cure the coating film of the composition. If the amount of the extender pigment is too large, the coating property is not good, the leveling property of the performance of flattening after application is not good, and in the desmear process after laser processing, the extender pigment falls off from the side surface and surroundings of the via hole, so-called Shedding occurs and makes the shape of the via hole unstable, and if too small, the coating film performance such as the hardness of the cured film of the coating film does not improve. When the amount of the additive, especially the antifoaming agent, is too large, the antifoaming agent is eluted on the surface of the coating film, and the so-called bleed phenomenon causes the coating film of the solder resist composition (B) on the coating film of the solder resist composition (A). Adhesion at the time of lamination is not improved, and when too small, the defoaming and foam breaking properties of the coating film are not improved. If the amount of the solvent is too large, the viscosity of the solder resist composition (A) or (B) becomes low, the covering (coverability) to the conductor circuit pattern is not improved, and the circuit board is dried in an upright state. In this case, the coating film easily drips, and when the amount is too small, the leveling property of the coating film is not improved and the smoothness of the coating film cannot be obtained.
[0015]
To form a solder resist film using the solder resist compositions (A) and (B), as shown in FIG. 1, a circuit wiring 1a is formed on one surface of a circuit board 1 on which only a conductor pattern is formed. The circuit wiring 1b is formed on the other surface. First, (1) the circuit wirings 1a and 1b are subjected to surface treatment such as degreasing and soft etching, and The solder resist composition (A) is applied uniformly at a liquid film thickness (film thickness in an undried state) of about 10 to 50 μm. As the coating method, any of screen printing, roll coating, curtain coating, and electrostatic coating can be used, but other coating methods may be used as long as they can be applied uniformly. After the application, it is dried and cured at a temperature of 80 to 180 ° C. for about 15 to 60 minutes to form a first cured coating film (cured resin film for desmear) 2 a, 2 b. Subsequently, (3) the solder resist composition (B) is applied in the same manner as the application of the solder resist composition (A), followed by drying and curing to form a second cured coating film (cured for desmear resistance). Resin films) 3a and 3b are formed.
Further, the solder resist composition (B) is applied to a film of polyester or the like, and further, the solder resist composition (A) is applied on the applied film. Then, the semi-cured film side is pressed against the surface of the substrate containing the conductive circuit pattern, the film is peeled from the semi-cured film, the semi-cured film is transferred, and the semi-cured film is completely heated or the like. It may be cured to form a cured film.
Next, (4) the laminated cured coating obtained by laminating the second cured coating 3a on the first cured coating 2a at a predetermined corresponding position of the circuit wiring 1a and the first layer. By irradiating a laser to a predetermined corresponding position of the circuit wiring 1b of the laminated cured coating film obtained by laminating the second cured coating film 3b on the cured coating film 2b, via holes 4a and 4b are formed. The wirings 1a and 1b are exposed. After that, components (smears) that cannot be completely removed and remain on the conductors of the circuit wirings 1a and 1b in the via holes 4a and 4b are present, but the smears are removed by a desmear treatment chemical such as a permanganate solution. Desmearing for disassembly and removal is performed. (5) Finally, the circuit wirings 1a and 1b are subjected to gold plating or pre-flux treatment, and then the semiconductor chip 6 is mounted by bonding with gold bumps or solder bumps 5 mounted on its lower surface. Then, a bump 7 made of a solder ball is formed. In addition, as a method of forming the bump 5 and a method of mounting the semiconductor chip, an ESC (epoxy solder encapsulated) in which a gold wire is welded to the semiconductor chip to form a gold bump, then bonded with a conductive resin and fixed with an under film resin. (connection) underfill method, ACF (anisotropic conductive film connection) method of bonding and fixing with an anisotropic conductive film, C4 (control collapse method) such as solder bump formation by printing solder paste and joining by reflow However, any of the above methods may be used for bump formation and chip mounting. The bump 7 may be formed by placing a solder ball on a land in a via hole and heating and melting the solder ball by reflow, or by applying a solder paste and then heating and melting by reflow. However, any method may be used.
Although not shown, a through-hole is formed in the substrate of the circuit board 1 on which only the conductor circuit pattern is formed, and the circuit wirings 1a and 1b are connected by a plating film formed on the inner wall of the through-hole.
[0016]
【Example】
An embodiment of the present invention will be described, but the present invention is not limited to this.
Example 1
(Preparation of Specific Examples of Solder Resist Composition (A))
To 40 g of Epicoat 1001 (manufactured by Japan Epoxy Resin, bisphenol A type epoxy resin), 15 g of MILEX XLC-LL (phenol resin manufactured by Mitsui Chemicals, Inc.) was added, and 17 g of DBE (ester solvent manufactured by DuPont) was further added as a solvent. A mixed solution was prepared. 25 g of FB-3SDC (fused silica manufactured by Denki Kagaku Kogyo), 1 g of DICY-7 (dicyandimidad manufactured by Japan Epoxy Resin), and KS-66 (silicon-based defoaming agent manufactured by Shin-Etsu Chemical) were added to the obtained mixed solution. 1 g and 0.5 g of Aerosil R-974 (fumed silica manufactured by Nippon Aerosil Co., Ltd.) were added and stirred. Subsequently, the mixture was kneaded with a three-roll mill to prepare a solder resist composition A1.
(Preparation of specific examples of curable resin composition for coating (B))
To 40 g of Epicron N-695 (cresol novolak type epoxy resin manufactured by Dainippon Ink and Chemicals, Inc.) was added 15 g of MILEX XLC-LL (phenolic resin manufactured by Mitsui Chemicals, Inc.), and DBE (ester solvent manufactured by DuPont) was further used as a solvent. 17 g was added to prepare a mixed solution. 25 g of FB-3SDC (fused silica manufactured by Denki Kagaku Kogyo), 1 g of DICY-7 (dicyandimidad manufactured by Japan Epoxy Resin), and KS-66 (silicon-based defoaming agent manufactured by Shin-Etsu Chemical) were added to the obtained mixed solution. 1 g and 0.5 g of Aerosil R-974 (fumed silica manufactured by Nippon Aerosil Co., Ltd.) were added and stirred. Subsequently, the mixture was kneaded with a three-roll mill to prepare a solder resist composition B1.
[0017]
(Manufacture of circuit boards)
Each step is performed more specifically in accordance with the procedure shown in FIG. 1. (1) The circuit board 1 having the conductor circuit patterns 1a and 1b formed by etching the copper-clad laminate is subjected to degreasing, soft etching, etc. (2) The solder resist A1 obtained above is applied by screen printing, dried at 150 ° C. for 1 hour, and heat-cured to form first-layer cured coatings 2a and 2b. (3) The second layer cured coatings 3a and 3b were formed in the same manner except that the solder resist composition B1 obtained above was used in place of the solder resist composition A1, and the first layer The cured film 2a of the second layer and the cured film 3a of the second layer are combined to form a laminated cured film having a thickness of 20 μm. Similarly, the cured film 2b of the first layer and the cured film 3b of the second layer are similarly formed. Were combined to form a laminated cured coating film having a thickness of 20 μm.
Next, (4) the portions corresponding to the conductor circuit patterns 1a and 1b are irradiated with carbon dioxide laser light on the laminated cured coating film to form via holes 4a and 4b having a diameter (land diameter) of 50 μm. 1a and 1b are exposed. Then, the circuit board 1 having been subjected to the above-mentioned processes (1) to (3) was placed on an enplate MLB-496A (a solution mainly containing an aqueous sodium hydroxide solution manufactured by Meltech) and 496B (a 1-methoxy solution manufactured by Meltech). -2-propanol solution) and distilled water at 55 to 65 ° C for 2 to 20 minutes to swell the smears seen on the conductor circuit patterns 1a and 1b in the via holes 4a and 4b. Enplate MLB-497A solution (solution based on sodium permanganate solution manufactured by Meltec) and 497B (solution based on sodium hydroxide manufactured by Meltech) and a mixed solution of distilled water with 60 to 50% The swollen smear is decomposed and removed by immersion at 95 ° C. for 5 to 20 minutes. Further, the plate is immersed in a mixed solution of Enplate MLB-790 (a solution mainly containing an aqueous solution of hydroxylamine sulfate manufactured by Meltec Co., Ltd.), concentrated sulfuric acid and distilled water at 60 to 65 ° C. for 5 to 10 minutes for neutralization. . (5) Thereafter, a gold plating process or a pre-flux process is performed, and the semiconductor chip 6 on which the bumps 5 are formed is mounted by bonding the bumps 5 by melting. Further, a solder ball 7 is mounted on the other surface opposite to the side on which the chip is mounted. The mounting circuit board on which the semiconductor chip thus obtained is mounted is mounted on a motherboard by joining the solder balls by melting.
[0018]
Examples 2 and 3
In Example 1, as shown in Table 1, instead of Epicron N-695, Epicoat 1031S (epoxy resin manufactured by Japan Epoxy Resin) and Epicron HP-7200 (dicyclopentadiene type manufactured by Dainippon Ink and Chemicals, Inc.) Each of the solder resist compositions B2 and B3 was prepared in the same manner except that each of the above (epoxy resins) was used. As shown in Table 2, each of the solder resist compositions B2 and B3 was prepared in the same manner as in Example 1 except that each of these was used. The mounting circuit boards of Examples 2 and 3 were manufactured.
[0019]
Example 4
In Example 1, as shown in Table 1, a solder resist composition A2 was prepared in the same manner except that Epototo YDF-2001 (a bisphenol F type epoxy resin manufactured by Toto Kasei Co., Ltd.) was used instead of Epicoat 1001. As shown in Table 2, a mounting circuit board was manufactured in the same manner except that this solder resist composition A2 was used instead of the solder resist composition A1.
[0020]
Examples 5 and 6
In Examples 2 and 3, as shown in Table 2, mounting of Examples 5 and 6 was performed in the same manner except that the solder resist composition A2 used in Example 4 was used instead of the solder resist composition A1. A circuit board was manufactured.
[0021]
Comparative Example 1
In Example 1, as shown in Table 2, a solder resist composition B1 was used instead of the solder resist composition A1, and a solder resist composition A1 was used instead of the solder resist composition B1, that is, A1 and B1 were used. A mounting circuit board was manufactured in the same manner except that the circuit board was used in reverse.
[0022]
Comparative Example 2
In Example 4, as shown in Table 2, the solder resist composition B1 was used instead of the solder resist composition A2, and the solder resist composition A2 was used instead of the solder resist composition B1, that is, A2 and B1 were reversed. A mounting circuit board was manufactured in the same manner except that the above-mentioned circuit board was used.
[0023]
(Evaluation of circuit board)
(1) Desmear resistance test
In each of the examples and comparative examples, the circuit board subjected to the processing up to (4) above, that is, the circuit board subjected to the desmear treatment as in Example 1, was used as a test piece, and each of the laminated cured coating films (the first layer was cured). The surface roughness of the surface of the coated cured film of the coating film 2 and the second-layer cured coating film 3) is measured by a surface roughness meter (manufactured by Tokyo Seimitsu Co., Ltd.), and the average value Rtm is shown. The surface condition of the laminated cured coating film was visually observed and evaluated according to the following criteria.
○: No change is seen
△: slight change
×: Coating is roughened or peeled
In Example 1, 40 g of Epicoat 1001 (EP-1001) in the solder resist composition (A) was partially replaced with Epicron HP-7200 (HP-7200) and used (100 parts of HP-7200). The addition amount (replacement amount) of EP-1001 in the medium was changed from 0 (HP-7200: 40 g, EP-1001: 0 g) to 100 parts (EP-1001: 40 g, HP-7200: 0 g) every 25 parts. 1) to form cured first coating films 2a and 2b in the same manner as described above except that the surface roughness (average value Rtm) of the coating films is as described above. FIG. 2 shows the measurement results. From FIG. 2, when 25 to 100 parts of EP-1001 (epoxy resin which is easy to be desmeared) is added (substituted) to 100 parts of HP-7200 (epoxy resin which is hard to be desmeared), the Rtm becomes 5 μm or more, and the coating film which is easily desmeared It turns out that it becomes.
[0024]
(2) Solder heat resistance test
The test piece of (1) above was immersed in a solder bath at 260 ° C. for 30 seconds in accordance with the test method of JIS C 6481, and the peeling test with a cellophane adhesive tape (cellophane is a trade name) was taken as one cycle, for a total of 1 to 3 cycles The state of the coating film after performing the above was visually observed and evaluated according to the following criteria.
A: No change in coating film after 3 cycles
：: peeling occurred after 3 cycles
Δ: Peeling occurred after 2 cycles
×: peeling after one cycle
(4) Solvent resistance test
With respect to the test piece of the above (1), the test piece was immersed in dichloromethane at room temperature for 30 minutes, and then the state of the coating film was visually observed and evaluated according to the following criteria.
○: No change is observed
△: Slight change
×: The coating film swelled and peeled off
(5) Insulation resistance
About the test piece of the preceding paragraph (1), using the comb type electrode of IPC-SM840CB-25 test coupon of IPC-TM-650, 85 degreeC, 85% R. H. The insulation resistance of the coating film after humidification for 500 hours in an atmosphere of (relative humidity) was measured by applying DC (direct current) 50V.
[0025]
[Table 1]
Figure 2004240233
[0026]
[Table 2]
Figure 2004240233
[0027]
From the above Table 2, the "desmear resistance" of the example is almost 10 times better in surface roughness than that of the comparative example, "surface condition" is excellent, "solder heat resistance", "solvent resistance". It is also found that the “insulation resistance” is excellent. This is because in the desmear treatment, the resist component (smear) remaining in the conductor portion (copper foil) in the via hole is removed by lowering the first cured film or the second layer in the laminated cured film. This is often done regardless of whether the cured film is on the lower side, but for the damage of the laminated cured film (the cured film is attacked by the chemical solution of desmear treatment), the order of lamination is important, It is necessary that the first layer of the cured coating which is easily smeared is on the lower side (on the conductive circuit pattern) and the second layer of the hardened coating which is not easily desmeared is on the upper side (the surface of the circuit board). This shows that the property that the film is not affected by the chemical solution of the desmear treatment is extremely important. The smear is a mixture of the resin components of both the cured coating film of the first layer and the cured coating film of the second layer, and the resin component is altered by irradiation with laser light, and is subjected to desmear treatment. It is easier to remove.
As described above, since the cured coating film of the second layer is not damaged, it can be said that excellent results are obtained in "solder heat resistance", "solvent resistance", and "insulation resistance".
The cured coating film of the first layer has a molecular structure of any of the above-mentioned general formulas [Chemical Formula 1] and [Chemical Formula 2], that is, a bisphenol-type epoxy resin, in which the connecting chain is liable to be desmeared due to less steric hindrance by a bulky molecular group Conversely, conversely, if the connecting chain of the epoxy group has a molecular structure that is protected by molecular groups (it is unlikely that erosion by the chemical solution of desmear treatment occurs due to steric hindrance), it means that desmear resistance is high. it can.
[0028]
【The invention's effect】
According to the present invention, the epoxy resin is hardly considered to be desmeared, and the cured film of the composition containing the latter is used by laminating the cured film of the composition containing the latter. Even if the desmear treatment by a wet method of dissolving and removing is performed, the removal of smear remaining inside the via hole is favorably performed, and a solder resist composition, a circuit board, and a circuit board capable of forming a coating film not affected by the chemical solution of the desmear The manufacturing method can be provided.
Further, a solder resist composition capable of forming a coating film without adversely affecting subsequent processing after performing the desmear processing or deteriorating characteristics required for the circuit board, a circuit board, and a method of manufacturing the same Can be provided.
[Brief description of the drawings]
FIG. 1 is an explanatory view showing a manufacturing process of a circuit board according to one embodiment of the present invention.
FIG. 2 is a graph showing a change in an average roughness Rtm of a coating film according to a composition ratio of an epoxy resin that is easily and desirably smeared.
[Explanation of symbols]
1 circuit board
1a, 1b Conductor circuit pattern
2a, 2b First layer cured coating (cured resin film for desmear)
3a, 3b Cured coating film of second layer (cured resin film for desmear resistance)
4a, 4b Via hole

Claims (8)

電子回路配線が形成された基板に該電子回路配線を被覆するソルダーレジスト膜を形成し、レーザーにより該ソルダーレジスト膜に該電子回路配線に連通するビアホールを形成し、該ビアホール内の配線の導体部に残留する成分であるスミアを除去するデスミアを行ない易い上記ソルダーレジスト膜用のエポキシ樹脂を含有するソルダーレジスト組成物。Forming a solder resist film covering the electronic circuit wiring on the substrate on which the electronic circuit wiring is formed, forming a via hole communicating with the electronic circuit wiring in the solder resist film by laser, and forming a conductor portion of the wiring in the via hole; A solder resist composition containing the epoxy resin for a solder resist film, which easily performs desmearing for removing smear as a component remaining in the solder resist film. 電子回路配線が形成された基板に該電子回路配線を被覆するソルダーレジスト膜を形成し、レーザーにより該ソルダーレジスト膜に該電子回路配線に連通するビアホールを形成し、該ビアホール内の配線の導体部に残留する成分であるスミアを除去するデスミアを行ない難い上記ソルダーレジスト膜用のエポキシ樹脂を含有するソルダーレジスト組成物。Forming a solder resist film covering the electronic circuit wiring on the substrate on which the electronic circuit wiring is formed, forming a via hole communicating with the electronic circuit wiring in the solder resist film by laser, and forming a conductor portion of the wiring in the via hole; A solder resist composition containing the epoxy resin for a solder resist film, which is difficult to desmear to remove smear as a component remaining in the solder resist film. デスミアされ易いエポキシ樹脂は下記一般式〔化１〕で示される分子構造及び／又は下記一般式〔化２〕で示される分子構造を分子内に有する熱硬化性樹脂である請求項１に記載のソルダーレジスト組成物。
Figure 2004240233
（式中、Ｒ１ はＣＨ２ 又はＣ（ＣＨ３ ）２ を表わし、ｍは１又は複数を表わす。）
Figure 2004240233
（式中、Ｒ２ はＣＨ２ 又はＣ（ＣＨ３ ）２ を表わし、ｎは１又は複数を表わす。）The epoxy resin according to claim 1, wherein the epoxy resin which is apt to be desmeared is a thermosetting resin having a molecular structure represented by the following general formula [Formula 1] and / or a molecular structure represented by the following general formula [Formula 2] in the molecule. Solder resist composition.
Figure 2004240233
 (In the formula, R 1 represents CH 2 or C (CH 3 ) 2 , and m represents one or more.)
Figure 2004240233
 (Wherein, R 2 represents CH 2 or C (CH 3 ) 2 , and n represents one or more) デスミアされ難いエポキシ樹脂は下記一般式〔化１〕で示される分子構造及び／又は下記一般式〔化２〕で示される分子構造を分子内に有しない熱硬化性樹脂である請求項２に記載のソルダーレジスト組成物。
Figure 2004240233
（式中、Ｒ１ はＣＨ２ 又はＣ（ＣＨ３ ）２ を表わし、ｍは１又は複数を表わす。）
Figure 2004240233
（式中、Ｒ２ はＣＨ２ 又はＣ（ＣＨ３ ）２ を表わし、ｎは１又は複数を表わす。）The epoxy resin which is hardly desmeared is a thermosetting resin having no molecular structure represented by the following general formula [Chemical formula 1] and / or a molecular structure represented by the following general formula [Chemical formula 2] in a molecule. Solder resist composition.
Figure 2004240233
 (In the formula, R 1 represents CH 2 or C (CH 3 ) 2 , and m represents one or more.)
Figure 2004240233
 (Wherein, R 2 represents CH 2 or C (CH 3 ) 2 , and n represents one or more) エポキシ基を有しないエポキシ樹脂硬化性化合物を含有する請求項１ないし４のいずれかに記載のソルダーレジスト組成物。The solder resist composition according to any one of claims 1 to 4, further comprising an epoxy resin curable compound having no epoxy group. デスミアはスミアを除去する薬液を用いる湿式法で行なう請求項１ないし５のいずれかに記載のソルダーレジスト組成物。The solder resist composition according to any one of claims 1 to 5, wherein the desmear is performed by a wet method using a chemical solution for removing smear. 電子回路配線が形成された基板に該電子回路配線を被覆するソルダーレジスト膜を形成し、レーザーにより該ソルダーレジスト膜に該電子回路配線に連通するビアホールを形成し、該ビアホール内の配線の導体部に残留する成分であるスミアを除去するデスミアを行なうことを少なくとも行なって得られる回路基板であって、上記ソルダーレジスト膜は、
（１）請求項１、３、５又は６に記載のデスミアを行い易いエポキシ樹脂を含有するソルダーレジスト組成物（Ａ）を塗布し、硬化させたデスミア用硬化樹脂膜と、
（２）該デスミア用硬化樹脂膜の上に請求項２、４、５又は６に記載のデスミアされ難いエポキシ樹脂を含有するソルダーレジスト組成物（Ｂ）を塗布し、硬化させた耐デスミア用硬化樹脂膜を積層して有する
回路基板。Forming a solder resist film covering the electronic circuit wiring on the substrate on which the electronic circuit wiring is formed, forming a via hole communicating with the electronic circuit wiring in the solder resist film by laser, and a conductor portion of the wiring in the via hole; A circuit board obtained by performing at least desmearing to remove smear which is a component remaining in the solder resist film,
(1) a cured resin film for desmear obtained by applying and curing a solder resist composition (A) containing an epoxy resin which easily performs desmear according to claim 1,
(2) Desmear-resistant hardening by applying and curing the solder resist composition (B) containing the epoxy resin which is hardly desmeared according to claim 2, 4, 5 or 6 on the hardened resin film for desmear. A circuit board having a laminated resin film. 電子回路配線が形成された基板に該電子回路配線を被覆するソルダーレジスト膜を形成し、レーザーにより該ソルダーレジスト膜に該電子回路配線に連通するビアホールを形成し、該ビアホール内の配線の導体部に残留する成分であるスミアを除去するデスミアを行なうことを少なくとも行なって得られる回路基板の製造方法であって、上記ソルダーレジスト膜は、
（１）請求項１、３、５又は６に記載のデスミアを行い易いエポキシ樹脂を含有するソルダーレジスト組成物（Ａ）を塗布し、硬化させたデスミア用硬化樹脂膜を形成した後、
（２）該デスミア用硬化樹脂膜の上に請求項２、４、５又は６に記載のデスミアされ難いエポキシ樹脂を含有するソルダーレジスト組成物（Ｂ）を塗布し、硬化させた耐デスミア用硬化樹脂膜を形成する
回路基板の製造方法。Forming a solder resist film covering the electronic circuit wiring on the substrate on which the electronic circuit wiring is formed, forming a via hole communicating with the electronic circuit wiring in the solder resist film by laser, and a conductor portion of the wiring in the via hole; A method of manufacturing a circuit board obtained by performing at least desmearing to remove smear which is a component remaining in the solder resist film,
(1) After applying the solder resist composition (A) containing the epoxy resin which easily performs desmear according to claim 1, 3, and 6, and forming a cured desmear cured resin film,
(2) Desmear-resistant hardening by applying and curing the solder resist composition (B) containing the epoxy resin which is hardly desmeared according to claim 2, 4, 5 or 6 on the hardened resin film for desmear. A method for manufacturing a circuit board on which a resin film is formed.
JP2003030237A 2003-02-07 2003-02-07 Solder resist composition, circuit board and method for manufacturing the same Pending JP2004240233A (en)

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Cited By (7)

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JP2006216719A (en) * 2005-02-02 2006-08-17 Fujitsu Ltd Method of manufacturing chip mounting substrate and method of forming plating film
KR20100117035A (en) 2009-04-23 2010-11-02 아지노모토 가부시키가이샤 Method for manufacturing printed circuit board
JP4968257B2 (en) * 2006-04-28 2012-07-04 住友ベークライト株式会社 Solder resist material, wiring board using the same, and semiconductor package
JP2013530523A (en) * 2010-05-20 2013-07-25 クアルコム，インコーポレイテッド Process for improving package warpage and connection reliability by using backside mold configuration (BSMC)
US8841168B2 (en) 2011-09-09 2014-09-23 Qualcomm Incorporated Soldering relief method and semiconductor device employing same
US9188871B2 (en) 2012-05-17 2015-11-17 Taiyo Ink Mfg. Co., Ltd. Pattern forming method, alkali-developable thermosetting resin composition, printed circuit board and manufacturing method thereof
JP2016012002A (en) * 2014-06-27 2016-01-21 日立化成株式会社 Cured product of photosensitive resin composition, photosensitive resin composition used therefor, method for manufacturing substrate for mounting semiconductor device, and method for manufacturing semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006216719A (en) * 2005-02-02 2006-08-17 Fujitsu Ltd Method of manufacturing chip mounting substrate and method of forming plating film
JP4968257B2 (en) * 2006-04-28 2012-07-04 住友ベークライト株式会社 Solder resist material, wiring board using the same, and semiconductor package
KR20100117035A (en) 2009-04-23 2010-11-02 아지노모토 가부시키가이샤 Method for manufacturing printed circuit board
JP2013530523A (en) * 2010-05-20 2013-07-25 クアルコム，インコーポレイテッド Process for improving package warpage and connection reliability by using backside mold configuration (BSMC)
US8742603B2 (en) 2010-05-20 2014-06-03 Qualcomm Incorporated Process for improving package warpage and connection reliability through use of a backside mold configuration (BSMC)
US8841168B2 (en) 2011-09-09 2014-09-23 Qualcomm Incorporated Soldering relief method and semiconductor device employing same
US9188871B2 (en) 2012-05-17 2015-11-17 Taiyo Ink Mfg. Co., Ltd. Pattern forming method, alkali-developable thermosetting resin composition, printed circuit board and manufacturing method thereof
JP2016012002A (en) * 2014-06-27 2016-01-21 日立化成株式会社 Cured product of photosensitive resin composition, photosensitive resin composition used therefor, method for manufacturing substrate for mounting semiconductor device, and method for manufacturing semiconductor device

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