JP2004173292A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for a high side switch which cuts off an inductive load at high speed and is also usable for a battery of a high voltage. <P>SOLUTION: In order to cut off a power MOSFET 1 to be used as the high side switch for driving an inductive load 40, a MOSFET 2 connected to a first ground line 34 and a MOSFET 3 connected to a second ground (output terminal 33) are used. For driving the MOSFET 3, a MOSFET 4 may be used. The voltage of the output terminal 33 is sufficiently lowered to a negative potential from a ground terminal 30, thereby cutting off the inductive load at high speed. High withstand voltage elements may then be used as the MOSFET 2, 3, 4 for control, thereby making possible application of the semiconductor device to the high battery voltage. <P>COPYRIGHT: (C)2004,JPO

Description

  The present invention relates to a semiconductor device using a power MOSFET as a source follower in an output stage, and more particularly to a semiconductor device suitable for a high-side switch for driving an inductive load at high speed.

As a circuit for this type of high-side switch, for example, a configuration disclosed in US Pat. No. 4,928,053 (see Patent Document 1) is known. FIG. 11 shows a configuration of a main part of this conventional high-side switch circuit (source follower circuit). In FIG. 11, reference numeral 70 denotes a power MOSFET. The drain of the power MOSFET 70 is connected to the power supply terminal _VDD , and the source is connected to the inductive load 71 via the output terminal OUT. The drain and source of an N-channel MOSFET 72 for shutting off the power MOSFET 70 are connected between the gate and the source of the power MOSFET 70, and the gate of the N-channel MOSFET 72 is connected to the ground of the circuit. The drain and gate of the P-channel MOSFET 75 are connected to the gate of the power MOSFET 70 and the circuit ground, respectively. A series circuit of a clamp diode 74 for determining the minimum value of the voltage of the output terminal OUT when the power MOSFET 70 is cut off and a diode 73 for blocking current by a reverse voltage is provided between the power supply terminal V _DD and the gate of the power MOSFET 70. Is connected.

The high-side switch circuit thus configured operates as follows.
Are driven gate of the power MOSFET70 and P-channel MOSFET75 is turned on and conducts power MOSFET70 by the potential V _S of the source of the P-channel MOSFET75 from the low potential to the high potential, the drain-from the power supply terminal V _DD of the power MOSFET70 A current is supplied to the inductive load 71 via the source.

Meanwhile, the potential V _S of the source of the P-channel MOSFET 75 from the high potential to the low potential, the parasitic diode built into the P-channel MOSFET 75 (shown in phantom) by forward bias, and the charge from the gate of the power MOSFET70 is withdrawn The power MOSFET 70 is turned off. When the power MOSFET 70 is cut off, a back electromotive voltage is generated in the inductive load 71, the source (output terminal OUT) of the power MOSFET 70 drops below the ground potential, and after the source of the power MOSFET 70 becomes a negative voltage, the N channel When the MOSFET 72 is turned on, the power MOSFET 70 is kept shut off. Thereafter, when a negative output voltage value determined by the clamp diode 74 (hereinafter, referred to as a negative output maintaining voltage) is reached, the power MOSFET 70 is turned on and the output voltage stops decreasing. Thus, the energy stored in the inductive load 71 continues to be released until the load current is cut off. Here, in order to cut off the current supplied to the inductive load 71 at high speed, it is necessary to lower the output voltage below the ground voltage as much as possible.

U.S. Pat. No. 4,980,053

PCIM'88 PROCEEDINGS, pp.32-40, Proceedings of PCIM'88

  However, according to the above-described conventional circuit configuration, the lower limit value of the output voltage is limited by the gate-source breakdown voltage of the N-channel MOSFET 72 (usually about 20 V). Furthermore, when a battery is used as a power supply, there is a power supply voltage fluctuation (about 5 V) depending on the charge level of the battery. Therefore, it is necessary to allow for this margin in the conventional circuit configuration, and the negative output maintaining voltage is limited to about -15 V. Met. For this reason, there has been a problem that it is difficult to increase the breaking speed of the inductive load.

  In the conventional circuit configuration, the gate of the P-channel MOSFET 75 is connected to the ground, and the drain is connected to the gate of the power MOSFET. Therefore, the voltage applied between the gate of the power MOSFET and the ground (battery voltage +8 V) is It is necessary to lower the breakdown voltage between the gate and the source of the P-channel MOSFET 75. For this reason, there is a problem that the battery cannot be used when a battery having a high voltage such as 24 V is used.

  Further, in the conventional high-side switch circuit, no countermeasure has been taken against the case where an overcurrent flows in the control circuit that drives the power MOSFET when the battery is incorrectly reversely connected.

  Another object of the present invention is to provide a semiconductor device for a high-side switch that can use a battery having a high voltage of 24 V or more. Still another object of the present invention is to provide a semiconductor device for a high-side switch that does not break even when a battery is reversely connected by mistake.

  In order to achieve the above object, a semiconductor device according to the present invention includes a power MOSFET 1 having a drain connected to a power supply terminal 31 and a source connected to an output terminal 33, as shown in FIG. A first MOSFET, MOSFET2, which is disposed between the gate and the control circuit ground, that is, the ground line 34, and turns off the power MOSFET1 based on the voltage of the input terminal 32, between the gate of the power MOSFET1 and the output terminal 33; And a second MOSFET that turns off the power MOSFET 1 based on the voltage of the input terminal 32, that is, a MOSFET 3, and that is connected to the gate of the power MOSFET 1 and turns on the power MOSFET 1 based on the voltage of the input terminal 32. Circuit or boost circuit And 19, is characterized in that the at least composed.

  In the semiconductor device, a diode for blocking a current flowing between a gate of the power MOSFET and a control circuit ground via a parasitic diode existing between a drain and a source of the first MOSFET, that is, a diode shown in FIG. It is preferable to connect and arrange the diode 8 as shown in FIG.

  Further, a third MOSFET for turning on the second MOSFET, that is, a MOSFET 4 as shown in FIG. 1 and a resistor 17 connected between the gate and the source of the MOSFET 3 for turning off the MOSFET 3 are further provided. It is suitable.

  FIG. 4 shows a third MOSFET for turning on the second MOSFET and a fourth MOSFET connected between the gate and the source of the second MOSFET for turning off the second MOSFET. As shown, a MOSFET 23 may be provided instead of the resistor 17.

  Further, a constant voltage power supply that obtains a predetermined constant voltage from a power supply voltage, for example, a voltage regulator 20 is provided as shown in FIG. 3, and the MOSFET 4 and the drain of the MOSFET 4 are connected between the voltage regulator 20 and the gate of the MOSFET 3. A series circuit with a diode 9 that blocks a current flowing through a parasitic diode existing between the sources can be provided.

  Further, if a clamping diode, for example, as shown in FIG. 1 or 4, a clamping diode 13 and / or 14 is further provided between the gate of the power MOSFET and a power supply terminal and / or a constant voltage power supply. It is suitable.

  Further, a series circuit of a first diode and a fifth MOSFET connected between the gate of the power MOSFET and a power supply terminal, for example, as shown in FIG. 5, a series circuit of a diode 12 and a MOSFET 6 is provided. A resistor 18 is provided between the power supply terminal 31 and the power supply terminal 31 via a gate of the power MOSFET 1 to the power supply terminal 31 via the gate of the MOSFET 6. A constant voltage power supply that obtains a predetermined constant voltage from an applied power supply voltage, that is, a voltage regulator 20 is provided, and a third clamping diode is provided from the gate of the power MOSFET 1 to the voltage regulator 20 via the gate of the MOSFET 6. That is, the diode 14 may be provided.

  In this case, instead of the resistor 18 provided between the gate and the source of the fifth MOSFET, that is, the resistor 18, a sixth MOSFET having a drain and a gate diode-connected, that is, as shown in FIG. Between the gate and the source.

  A seventh MOSFET having a gate connected to an output terminal between the gate of the power MOSFET and the first MOSFET, that is, a MOSFET 5 may be further provided as shown in FIG.

  Further, an eighth MOSFET in which a drain is connected to a ground terminal, a source and a body are connected to the control circuit ground, and a gate is connected to the power supply terminal or a portion having a voltage of the same polarity as the power supply terminal, that is, FIG. 8, it is preferable to connect the MOSFET 7.

  Further, the semiconductor device according to the present invention includes at least a vertical power MOSFET 1 and a control circuit for controlling the gate of the power MOSFET 1 on the same semiconductor substrate of the first conductivity type, for example, as shown in FIG. In the semiconductor device, the region of the power MOSFET 1 includes, in order from the substrate 101 side, a first conductive type, that is, an N-type first semiconductor layer, and a second conductive type second conductive type having a lower concentration than the first semiconductor layer. A third semiconductor layer of a first conductivity type having a higher concentration than the second semiconductor layer, which has a semiconductor layer, that is, an N-type epitaxial layer 105a, and has a higher concentration than the second semiconductor layer extending from the surface to the first semiconductor layer at the periphery of the power MOSFET region; The control circuit region includes, in order from the substrate side 101, a fourth semiconductor layer of the second conductivity type, that is, a P-type epitaxial layer. To form a plurality of island-like regions 105b to 105d by separating the semiconductor layers 103a and 103b and the second semiconductor layers 105b to 105d of the first conductivity type into islands. In a semiconductor device having a fifth semiconductor layer of the second conductivity type having a higher concentration than the P-type epitaxial layer reaching the P-type epitaxial layer from the surface, that is, the high-concentration P-type diffusion layers 108a and 108b, at least one of the island regions is formed. A sixth semiconductor layer of the first conductivity type having a higher concentration than the N-type epitaxial layer reaching from the surface to the semiconductor substrate 101 so as to be separated from other island regions, that is, a high-concentration N-type semiconductor in FIG. A semiconductor layer including a region 107a and high-concentration N-type buried layers 102a and 104a is provided.

  In this case, on the surface of a required portion of the fourth semiconductor layer, a seventh semiconductor layer of the first conductivity type having a higher concentration than the second semiconductor layer, that is, high concentration N-type buried layers 104b to 104d as shown in FIG. May be provided.

  Further, the first semiconductor layer includes a layer of an impurity of a first conductivity type provided on the semiconductor substrate before the formation of the fourth semiconductor layer, that is, a high-concentration N-type buried layer 102a as shown in FIG. It is preferable to use the high-concentration N-type buried layer 104a.

  Further, the sixth semiconductor layer is composed of the raised layer, that is, the high-concentration N-type buried layer 102a, the high-concentration N-type buried layer 104a, and the high-concentration N-type semiconductor region 107a as shown in FIG. be able to.

  Further, as shown in FIG. 9, the sixth semiconductor layer in the control circuit region, that is, the P-type epitaxial layer of at least one island region separated by the high-concentration N-type buried layers 102a and 104a and the high-concentration N-type region 107a. The layer 103a and the high-concentration P-type diffusion layer 108a are electrically connected to the source potential of the power MOSFET 1 formed in the power MOSFET region, and the P-type epitaxial layer of at least one other island-like region separated by the sixth semiconductor layer It is preferable that 103b and the high concentration P-type diffusion layer 108b be electrically connected to the ground of the control circuit.

  In addition, a drain is provided outside the at least one other island-shaped region separated by the sixth semiconductor layer, wherein the fourth semiconductor layer and the fifth semiconductor layer are connected to the ground of a control circuit. The power supply is electrically connected to a ground terminal, that is, the ground terminal 30 in FIG. 8, and the source and the body are the ground of the control circuit, that is, the ground line 34 in FIG. In the island region, the P-type epitaxial layer 103b and the high-concentration P-type diffusion layer 108b that are connected to the ground of the control circuit are electrically connected to each other. In other words, it is preferable to provide the MOSFET 7 connected to the power supply terminal 31 or a portion having a voltage of the same polarity as the power supply terminal.

  As is apparent from the above-described embodiment, according to the present invention, the first power MOSFET is connected between the gate of the power MOSFET and the control circuit ground, and performs the power MOSFET cutoff operation when the gate voltage of the power MOSFET is higher than the ground voltage. A MOSFET and a second MOSFET connected between the gate and the output terminal of the power MOSFET, performing a cutoff operation when the gate voltage of the power MOSFET is equal to or lower than the power supply voltage, and performing a cutoff operation even when the output terminal voltage becomes a negative voltage. By using the power MOSFET, the power MOSFET driving the inductive load can be cut off at high speed.

  Further, since the gate voltage of the power MOSFET is not limited by the gate withstand voltage of the first and second MOSFETs, a high withstand voltage MOSFET of 60 V or more can be used for the first and second MOSFETs. High voltages of 24V or more can be used.

  Further, the eighth MOSFET provided between the control circuit ground and the ground terminal is turned off when the battery is reversely connected, and disconnects the control circuit ground and the ground terminal. The parasitic diode existing between the power supply terminals does not operate, so that destruction of the semiconductor device can be prevented.

  According to the semiconductor device of the present invention, the first MOSFET disposed between the gate of the power MOSFET for driving the inductive load and the control circuit ground has a voltage higher than the gate voltage of the power MOSFET than the ground terminal. The power MOSFET is turned off by the second MOSFET disposed between the gate of the power MOSFET and the output terminal. The power MOSFET is turned off by the first MOSFET, and the gate voltage of the power MOSFET becomes the power supply voltage. The gate charging circuit that turns off the power MOSFET while turning off the power MOSFET even when the output terminal becomes a negative voltage equal to or less than the voltage of the ground terminal when the output terminal becomes a negative voltage equal to or lower than the voltage of the ground terminal after the voltage becomes close to the voltage. Drive the power MOSFET gate by boosting it to the power supply voltage or higher. .

  Further, a diode provided between the gate of the power MOSFET and the control circuit ground to prevent a current flowing through a parasitic diode existing between the drain and the source of the first MOSFET provides a gate voltage of the power MOSFET. Can be below ground voltage, ie, a negative voltage. Here, the upper limit of the gate voltage of the power MOSFET is limited by the withstand voltage between the drain and the source of the first MOSFET. However, when a vertical MOSFET with a high withstand voltage is used, a withstand voltage of 60 V or more can be easily obtained. Therefore, a battery of 24 V or more can be used.

  Further, the second MOSFET is turned on by turning on the third MOSFET, the second MOSFET is turned off by turning off the third MOSFET, and the second MOSFET is turned on by a resistor connected between the gate and source of the second MOSFET. The gate charge when the MOSFET is turned off is discharged. As a result, the gate voltage of the second MOSFET is lowered below the ground voltage, so that the absolute value of the negative output sustaining voltage can be a large value that is not limited by the gate-source breakdown voltage of the second MOSFET. Therefore, the breaking speed of the inductive load can be increased. Here, a fourth MOSFET may be connected between the gate and the source of the second MOSFET in place of the above-described resistor for shutting off the second MOSFET.

  The constant voltage power supply obtains a predetermined constant voltage from the power supply voltage, and a diode provided between the constant voltage power supply and the gate of the second MOSFET is a parasitic diode existing between the drain and source of the third MOSFET. Block the current flowing through.

  In addition, a clamping diode provided between the gate of the power MOSFET and the power supply terminal determines a negative output sustaining voltage, and a high voltage is applied between the drain and the source of the power MOSFET when the battery voltage increases beyond the standard. To prevent it from being done.

  In addition, the clamping diode provided between the gate of the power MOSFET and the constant voltage power supply determines the negative output sustaining voltage, but due to the connection with the constant voltage power supply, it is caused by the voltage change of the battery connected to the power supply terminal. Therefore, it is possible to prevent the fluctuation of the breaking speed of the inductive load.

  In addition, the first diode of the series circuit of the first diode and the fifth MOSFET connected between the gate of the power MOSFET and the power supply terminal has a gate potential higher than the power supply voltage by the gate charging circuit, that is, the booster circuit. The fifth MOSFET provides a current to maintain the negative output sustain voltage. The resistor provided between the gate and the source of the fifth MOSFET operates to turn off the fifth MOSFET when the output terminal voltage is higher than the negative output sustain voltage. The second clamping diode determines the negative output sustaining voltage as well as the clamping diode provided between the gate of the power MOSFET and the power supply terminal. To prevent a high voltage from being applied between the drain and the source of the semiconductor device. The third clamping diode determines the negative output sustain voltage in the same manner as the clamping diode provided between the gate of the power MOSFET and the constant voltage power supply. To prevent a change in the inductive load cutoff speed caused by a voltage change of a battery connected to the battery. Further, since the fifth MOSFET supplies the gate current of the power MOSFET for maintaining the negative output sustain voltage, the element size of the second and third clamping diodes can be reduced.

  Further, the sixth MOSFET of diode connection provided in place of the resistance between the gate and the source of the fifth MOSFET constitutes a current mirror with the fifth MOSFET, so that the second and third clamping diodes are provided. Element size can be reduced.

  In addition, since the seventh MOSFET is provided between the gate of the power MOSFET and the first MOSFET, the first MOSFET finishes the shut-off operation of the power MOSFET quickly by the threshold voltage of the seventh MOSFET. As a result, the turn-off becomes soft and low-noise switching can be performed.

  An eighth MOSFET having a drain connected to a ground terminal, a source and a body connected to the control circuit ground, and a gate connected to the power supply terminal or a portion having a voltage of the same polarity as the power supply terminal, When the battery is properly connected between the terminal and the ground terminal, it turns on and connects the control circuit ground and the ground terminal. When the battery is reversely connected, it turns off and the control circuit ground and the ground terminal. And blocks a current flowing through a parasitic diode existing between the control circuit ground and the power supply terminal.

  In the semiconductor device according to the present invention, the power MOSFET region includes, in order from the substrate 101 side, a first semiconductor layer of the first conductivity type and a second semiconductor layer of the first conductivity type having a lower concentration than the first semiconductor layer. As a result, the drain terminal of the power MOSFET can be taken out from the substrate side, and the high-concentration third semiconductor layer of the first conductivity type reaching the first semiconductor layer from the surface to the peripheral portion of the power MOSFET region, It functions as a stopper for a leak current between the semiconductor layer of the second conductivity type in the control circuit region on the same semiconductor substrate, the body of the power MOSFET, and the fourth semiconductor layer. The plurality of island-shaped regions of the first conductive type first semiconductor layer surrounded by the second conductive type fourth semiconductor layer and the fifth semiconductor layer in the control circuit region serve as control circuit element forming portions, respectively. The sixth semiconductor layer of the first conductivity type, which reaches from the semiconductor substrate to the semiconductor substrate, allows each of the island regions to be further electrically isolated.

  The high-concentration seventh semiconductor layer of the first conductivity type provided on the surface of the required portion of the fourth semiconductor layer functions as a low-resistance buried layer of the control circuit element, so that the element characteristics are improved.

  In addition, the first semiconductor layer is formed in a power MOSFET region by being composed of a layer of an impurity of a first conductivity type provided on a semiconductor substrate before formation of a fourth semiconductor layer and the seventh semiconductor layer. The formed fourth semiconductor layer can be easily penetrated by the layer of the first conductivity type, so that conduction between the second semiconductor layer and the substrate can be obtained.

  Further, the fourth semiconductor layer and the fifth semiconductor layer of at least one island region separated by the sixth semiconductor layer of the control circuit region are electrically connected to a source potential of a power MOSFET formed in a power MOSFET region, By electrically connecting the fourth semiconductor layer and the fifth semiconductor layer of at least one other island region separated by the sixth semiconductor layer to the ground of the control circuit, the former island region is set to a negative potential. This makes it possible to change the potential, and it can be suitably used as a pull-down element whose potential changes together with the source of the power MOSFET. The absolute value of the negative output sustaining voltage can be increased and the inductive load can be cut off at high speed.

  Further, at least one island-like region separated by a sixth semiconductor layer in the control circuit region, wherein the fourth semiconductor layer and the fifth semiconductor layer are electrically connected to the ground of the control circuit. By providing a MOSFET in which the drain is connected to the ground terminal, the source and the body are connected to the ground of the control circuit, and the gate is connected to the power supply terminal, this MOSFET turns off when the battery is reversely connected, and normally operates. A battery reverse connection protection operation that turns on when connected is performed.

  Next, embodiments of the semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 shows a first embodiment of a semiconductor device according to the present invention, and is a main part circuit diagram of a drive circuit for driving an inductive load. FIG. 2 is an input / output waveform diagram of the drive circuit shown in FIG. is there. In FIG. 1, reference numeral 50 denotes a semiconductor device of the present invention. One terminal of a battery 41 is connected to a power terminal 31 of the semiconductor device 50, and the other terminal of the battery 41 is connected to a ground terminal 30. At the same time, it is connected to the output terminal 33 via an inductive load 40 such as a solenoid or a motor.

  The internal circuit of the semiconductor device 50 according to the present embodiment includes a power MOSFET 1 used as a high-side switch, and a control circuit that controls the gate of the power MOSFET 1. That is, the internal circuit of the semiconductor device 50 includes an N-channel power MOSFET 1 having a drain connected to the power supply terminal 31 and a source connected to the output terminal 33, and a drain and a source connected between the gate and source of the power MOSFET 1. And an N-channel MOSFET 2 having a drain connected to the gate of the power MOSFET 1 via the diode 8 and a source connected to the ground terminal 30 via the ground line (first ground line) 34 of the control circuit. An inverter 21 whose output is connected to the gate of the MOSFET 2, a P-channel MOSFET 4 whose source and drain are connected to the power supply terminal 31 and the gate of the MOSFET 3, respectively, a booster circuit 19 connected to the gate of the power MOSFET 1, A series circuit of diodes 12 and 13 whose anodes are connected between the terminal 31 and the gate of the power MOSFET 1, and the cathodes are connected between the second ground line 36 connected to the output terminal 33 and the gate of the power MOSFET 1 A series circuit of the connected diodes 26 and 27, a resistor 17 connected between the gate and the source of the MOSFET 3, an input side connected to the input terminal 32, and an output side connected to the input of the booster circuit, the gate of the MOSFET 4 and the inverter 21. And an input signal processing circuit 35 connected to the input. Although not shown, the input signal processing circuit 35 includes a level shift circuit, an overheat protection circuit, an overcurrent protection circuit, and the like.

As described above, the semiconductor device 50 is composed of the high-side switch in which the power MOSFET 1 is grounded as the source follower, and the control circuit including the MOSFETs 2, 3, 4 and the booster circuit 19 for controlling the same, as shown in FIG. Has input / output characteristics. FIG. 2 shows an input voltage waveform at the input terminal 32 and an output voltage waveform at the output terminal 33 of the semiconductor device 50 in which the inductive load 40 and the battery 41 having the voltage _VDD are connected as shown in FIG. It is an output characteristic diagram. That is, as shown in FIG. 2, when a voltage of, for example, 5 V is applied to the input terminal 32, the voltage input to the booster circuit 19 via the input signal processing circuit 35 is higher than the power supply voltage V _{DD of the} battery 41 by the booster circuit 19. And is applied to the gate of the power MOSFET 1 to turn on the power MOSFET 1. Since the power MOSFET 1 is driven with a sufficiently high gate voltage equal to or higher than the power supply voltage V _DD , the power MOSFET 1 has a low on-resistance of about 100 mΩ or less, and the output terminal 33 has substantially the same voltage as the power supply voltage V _DD . A specific circuit configuration example of the booster circuit 19 is described in, for example, Proceedings of PCIM'88, pages 32 to 40 (PCIM'88 PROCEEDINGS, pp. 32-40 (see Non-Patent Document 1)). Can be suitably used. In FIG. 1, the diode 12 is provided so that the gate of the power MOSFET 1 can be boosted to the voltage V _DD of the power supply terminal 31 or more, and the diodes 26 and 27 are gate protection diodes of the power MOSFET 1.

In order to turn off the power MOSFET 1, the input voltage V _IN of the input terminal 32 is reduced to 0 V as shown in FIG. At this time, since a high potential (for example, 5 V) is applied to the gate of the MOSFET 2 via the input signal processing circuit 35 and the inverter 21, the MOSFET 2 is turned on. Further, the gate of the MOSFET 4 is set to a low potential (for example, 0 V) via the input signal processing circuit 35, so that the MOSFET 4 is turned on and the MOSFET 3 is driven.

The reason why the MOSFET 2 and the MOSFET 3 are used for lowering the output terminal 33 is as follows. This is because the power MOSFET 1 cannot be cut off within the range of the equation (1) for the MOSFET 2 and the range of the equation (2) for the MOSFET 3 for the voltage V _OUT of the output terminal 33.

上式において、Ｖ_DDは電源端子３１の電圧、Ｖ_th(1)とＶ_th(3)は各々パワーＭＯＳＦＥＴ１とＭＯＳＦＥＴ３のしきい電圧、Ｖ_f(8)はダイオード８の順方向電圧、Ｖ_on(2)とＶ_on(4)はＭＯＳＦＥＴ２とＭＯＳＦＥＴ４のオン電圧である。

In the above equation, V _DD is the voltage of the power supply terminal 31, V _{th (1)} and V _{th (3)} are the threshold voltages of the power MOSFET 1 and MOSFET 3, respectively, V _{f (8)} is the forward voltage of the diode 8, and V _{on (2)} and V _{on (4)} are the ON voltages of MOSFET2 and MOSFET4.

This will be described in more detail below. Since MOSFET2 voltage as the potential of the on almost the ground terminal 30 of the gate voltage of the power MOSFET1 be _{(V on (2) + V} f (8)) is only lowered to the voltage V _OUT at the output terminal 33 is the back electromotive When the potential of the ground terminal, that is, a voltage close to the ground ( _{Von (2)} + _{Vf (8)} ), becomes lower than the potential of the ground terminal by _{Vth (1)} , the power MOSFET1 is turned on.

Further, the source potential of the MOSFET 3 is the voltage of the output terminal 33 when the power MOSFET 1 is in the on state, that is, almost the power supply voltage V _DD . Therefore, even if the MOSFET 4 is turned on, the gate potential of the MOSFET 3 is V _DD −V _{on ( 4) The} MOSFET 3 is lower than the source potential of the MOSFET 3 and cannot be turned on. In order for the MOSFET 3 to be turned on, the source potential must be lower than the gate potential by _{Vth (3)} or more. Therefore, when the voltage V _OUT of the output terminal 33 is higher than the voltage (V _DD −V _{on (4)} −V _{th (3)} ) close to the power supply voltage, the power MOSFET 1 cannot be cut off.

That is, the MOSFET 2 can perform the operation of turning off the power MOSFET 1 from the ON state, and keeping the power MOSFET 1 shut off in a range where the output terminal voltage V _OUT decreases to a voltage close to the above-mentioned ground terminal voltage. MOSFET1 operates the output terminal voltage V _OUT from the off from a voltage close to the power supply voltage, and operation of the output terminal voltage V _OUT continues to turn off the power MOSFET1 be equal to or less than the negative voltage ground terminal level Can be executed. The diode 8 blocks a current flowing from the ground terminal 30 through a parasitic diode existing between the source and the drain of the MOSFET 2 when the gate potential of the power MOSFET 1 becomes a negative voltage. This is for enabling a negative voltage according to the output terminal voltage, and a diode 8 may be connected to the source side of the MOSFET 2.

Next, the negative output maintaining voltage will be described. Since the load of the semiconductor device 50 of the present embodiment is the inductive load 40, when the power MOSFET 1 is cut off, back electromotive force is generated at both ends of the inductive load 40. Therefore, the output current I _OUT flowing through the inductive load 40 continues to flow, and as shown in FIG. 2, the voltage V _OUT at the output terminal 33 decreases until the clamp diode 13 breaks down and the power MOSFET 1 turns on. Assuming that the output voltage at this time is the negative output sustaining voltage _VSUS , the breakdown voltage of the diode 13 is BV ₍₁₃₎ , and the forward voltage of the diode 12 is _{Vf (12)} , the following expression is obtained.

この後、誘導性負荷４０を流れる出力電流Ｉ_OUTは減少し、この電流が流れなくなると出力端子電圧Ｖ_OUTはゼロボルトになる。ここで、誘導性負荷４０のインダクタンス成分をＬ_L、抵抗成分をＲ_Lとすると、誘導性負荷４０に流れる出力電流Ｉ_OUTの遮断時間ｔ_offは、式(4)で表されるため、負出力維持電圧Ｖ_SUSが大きいほど、遮断時間ｔ_offを小さくすることができる。

Thereafter, the output current I _OUT flowing through the inductive load 40 decreases, and when this current stops flowing, the output terminal voltage V _OUT becomes zero volts. Here, assuming that the inductance component of the inductive load 40 is L _L and the resistance component is R _L , the cutoff time t _off of the output current I _OUT flowing through the inductive load 40 is expressed by the equation (4), As the output sustaining voltage _VSUS increases, the cutoff time t _off can be reduced.

図１１に示した従来回路では、本実施例のＭＯＳＦＥＴ３に相当するＮチャネルＭＯＳＦＥＴ７２のゲートが本実施例の第１グランドライン３４に相当するグランドに接続されていたため、負出力維持電圧Ｖ_SUSをＭＯＳＦＥＴ７２のゲート・ソース間耐圧よりも大きくすることができなかった。このため、遮断時間ｔ_offの短縮が制限されていた。これに対して本実施例では、ＭＯＳＦＥＴ３のゲートは抵抗１７を介して出力端子３３に接続されているため、ＭＯＳＦＥＴ３のゲート電圧を第１グランドライン３４の電圧より低くできる分だけ負出力維持電圧Ｖ_SUSの値を大きくすることができる。このため、遮断速度の高速化が可能となる。例えば、本実施例の場合、バッテリ４１の電圧Ｖ_DD＝１２Ｖ、ダイオード１３の降伏電圧ＢＶ₍₁₃₎＝４４Ｖ、ダイオード１２の順方向電圧Ｖ_f(12)＝０．６Ｖ、パワーＭＯＳＦＥＴ１のしきい電圧Ｖ_th(1)＝２Ｖとすると、式(3)より負出力維持電圧Ｖ_SUSは約−３５Ｖと大きい値にできる。このため、パルス幅変調駆動を行う場合には、パルス幅の最小値の制約を受けてパルス幅の制御範囲が制限されるという問題を解決することができる。

Since the conventional circuit shown in FIG. 11, the gate of the N-channel MOSFET 72, which corresponds to MOSFET3 of this example was connected to the ground corresponding to the first ground line 34 of this embodiment, a negative output sustain voltage V _SUS MOSFET 72 Cannot be made larger than the gate-source withstand voltage of the above. For this reason, the shortening of the cutoff time t _off has been limited. On the other hand, in the present embodiment, since the gate of the MOSFET 3 is connected to the output terminal 33 via the resistor 17, the gate voltage of the MOSFET 3 can be made lower than the voltage of the first ground line 34 by the negative output sustaining voltage V The value of _SUS can be increased. Therefore, it is possible to increase the cutoff speed. For example, in the case of the present embodiment, the voltage V _{DD of the} battery 41 = 12 V, the breakdown voltage BV _{(13) of} the diode 13 = 44 V, the forward voltage V _{f (12) of the} diode 12 = 0.6 V, and the threshold of the power MOSFET 1. Assuming that the voltage V _{th (1)} = 2 V, the negative output sustaining voltage V _SUS can be set to a large value of about −35 V from the equation (3). Therefore, when performing pulse width modulation driving, it is possible to solve the problem that the control range of the pulse width is limited due to the restriction of the minimum value of the pulse width.

In the conventional circuit, since the source and the gate of the control P-channel MOSFET 75 are connected between the gate of the power MOSFET 70 and the ground, the gate voltage of the power MOSFET 70 is limited by the gate withstand voltage of the control MOSFET 75 (normally about 20 V). It had been. For this reason, it has not been possible to use a battery having a power supply voltage V _DD of 24 V or more and drive the gate of the power MOSFET 70 at a high voltage of 24 V or more in order to reduce the ON resistance of the power MOSFET 70. On the other hand, in the semiconductor device 50 of the present embodiment, the gate voltage of the power MOSFET 1 is not limited by the gate breakdown voltages of the MOSFETs 2 and 3, and therefore, a high breakdown voltage MOSFET having a drain-source breakdown voltage of about 70 V can be used as the MOSFETs 2 and 3. For this reason, a high voltage of 24 V or more can be used for the battery 41, and the gate voltage of the power MOSFET 1 can be applied by the boosting circuit 19 to a voltage raised by about 8 V from the voltage of the power supply terminal 31, so that the on-resistance of the power MOSFET 1 is small. There is an advantage that you can.

  In the circuit example of FIG. 1, the diodes 12 and 13 are series circuits in which anodes are connected to each other. However, the order may be changed and a series circuit in which cathodes are connected to each other. Further, the clamping diode 13 may be configured by connecting a plurality of diodes in series so as to obtain a desired withstand voltage.

  Here, FIG. 9 shows a cross-sectional structure of main elements such as the power MOSFET 1 and the MOSFETs 2, 3, and 4 which constitute the semiconductor device 50 of the present embodiment. In FIG. 9, semiconductor layer regions having the same reference numerals and different alphabets indicate regions which are formed in the same manufacturing process steps but are electrically separated from each other. Semiconductor layers without alphabets only indicate that they are formed in the same manufacturing process step.

The semiconductor device 50 of this embodiment is a P-type semiconductor having a resistivity of about 3 Ω · cm on a high-concentration N-type semiconductor substrate 101 having a resistivity of about 0.02 Ω · cm to 0.002 Ω · cm using antimony or arsenic as an impurity. Epitaxial layers 103a and 103b are formed to a thickness of about 20 μm, and N-type epitaxial layers 105a to 105d having a resistivity of about 1 Ω · cm are formed to a thickness of about 12 μm. A high-concentration N-type buried layer 102 a formed by selectively ion-implanting phosphorus of about 5 × 10 ¹⁴ cm ⁻² into a predetermined region of the semiconductor substrate 101 using a photoresist mask or the like before forming the P-type epitaxial layer. And a layer resistance 2 containing antimony as an impurity selectively diffused and formed in a predetermined region of the P-type epitaxial layer after forming the P-type epitaxial layer. Omega / □ and a high concentration N-type buried layer 104a extent further perform thermal diffusion connection. Alternatively, the high-concentration N-type buried layer 104a may be connected to the high-concentration N-type buried layer 102a at the same time as the formation by thermal diffusion. Further, in order to separate the N-type epitaxial layer into regions 105a to 105d, high-concentration P-type diffusion layers 108a and 108b having a layer resistance of about 3Ω / □ reach the P-type epitaxial layers 103a and 103b from the semiconductor surface, respectively. Thus, a plurality of island regions for the control circuit separated from the power MOSFET 1 can be formed.

  9, a P-type semiconductor region separated by high-concentration N-type semiconductor regions 101, 102a, 104a, and 107a and composed of a P-type epitaxial layer 103b and a high-concentration P-type diffusion layer 108b is shown in FIG. As a region of the ground line 34, a P-type semiconductor region composed of the P-type epitaxial layer 103a and the high-concentration P-type diffusion layer 108a is defined as a region of the second ground line 36 connected to the output terminal 33 shown in FIG. The power MOSFET 1 has a drain in the high-concentration N-type semiconductor region 101 and the high-concentration N-type buried layers 102a, 104a and the N-type epitaxial layer region 105a, a gate electrode in the polycrystalline silicon layer 110, a source in the N-type diffusion layer 113, and a P-type diffusion. The layer 111 is formed as a channel diffusion layer (body), and the source aluminum of the power MOSFET 1 is formed. Pole 114a is connected to the high concentration P-type diffusion layer 108a serving as the second ground area. MOSFET2 and MOSFET3 are vertical high voltage N-channel MOSFETs each having an N-type diffusion layer 113 as a source, a P-type diffusion layer 111 as a channel diffusion layer, and N-type epitaxial layers 105c and 105b as drains. The devices are separated by a first ground region including the P-type epitaxial layer 103b and the high-concentration P-type diffusion layer 108b, and the MOSFET 3 is separated by a second ground region including the P-type epitaxial layer 103a and the high-concentration P-type diffusion layer 108a. . The MOSFET 4 is a lateral high-breakdown-voltage P-channel MOSFET in which the P-type diffusion layer 112 has a source and a drain, and the low-concentration P-type diffusion layer 115 has an offset drain region for increasing the breakdown voltage. Although not shown, it can be used as needed on the same chip, and is a lateral N-channel MOSFET having an N-type diffusion layer 113 as a source and a drain, and used for a CMOS circuit. Reference numeral 106 is an insulating film such as an oxide film.

  With such a cross-sectional structure, in the semiconductor device 50 of the present embodiment, the potential of the P-type semiconductor layer regions 103a and 108a in the second ground region separating the MOSFET 3 from the source is changed by the source of the power MOSFET 1 (FIG. 1). Of the output terminal 33) together with the potential of the output terminal 33), the potential of the output terminal 33 is lower than that of the P-type semiconductor layer regions 103b and 108b constituting the first ground region (the control circuit ground line 34 of FIG. 1). Also, the MOSFET 3 can be kept on so that the power MOSFET 1 is shut off.

  The withstand voltage between the second ground region (the second ground line 36 connected to the output terminal 33 in FIG. 1) and the conductor substrate 101 (connected to the power terminal 31 in FIG. 1) which is the drain of the power MOSFET 1 is as follows. Since the high-concentration diffusion layers are not in contact with each other, a high withstand voltage design of 80 V or more can be performed. Further, a potential higher than these ground regions is applied between the first ground region and the second ground region (the power supply shown in FIG. 1). Since the high-concentration N-type regions 101, 102a, 104a, and 107a are maintained at the voltage of the terminal 31), the second ground region including the P-type layer regions 103a and 108a has a voltage of 80 V with respect to the semiconductor substrate 101. The potential can be set to a lower potential. Therefore, even if the second ground region has a higher or lower potential than the first ground region including the P-type layer regions 103b and 108b, the parasitic transistor existing between the two ground regions does not operate. Absent.

In addition, since the MOSFET 4 has the low-concentration P-type offset region 115 on the drain side, the drain-source withstand voltage can be easily set to 40 V or more. For example, in order to set the negative output sustaining voltage V _SUS to −35 V as estimated in FIG. 1, when the power supply terminal voltage is 12 V, the breakdown voltage of the MOSFET 4 can be set to a breakdown voltage of 47 V or more. As the MOSFET 2 and the MOSFET 3, as shown in FIG. 9, a vertical MOSFET that can easily achieve a high withstand voltage can be used, so that a drain-source withstand voltage of 70 V or more can be easily obtained. Therefore, when a 12 V or 24 V battery normally used for vehicles is used as the battery 41, the gate voltage of the power MOSFET 1 can be boosted without being limited by the drain-source breakdown voltage of the MOSFETs 2 and 3.

  It should be noted that the numerical values of the conditions of the manufacturing process are merely examples, and the present invention is not limited to the numerical values. Needless to say, the numerical values can be appropriately changed according to the required withstand voltage.

  FIG. 3 shows a second embodiment of the semiconductor device according to the present invention, and is a main part circuit diagram of a drive circuit for driving an inductive load. For convenience of explanation, the same reference numerals in FIG. 3 denote the same constituent parts as those shown in FIG. 1 of the first embodiment, and a detailed description thereof will be omitted. That is, in this embodiment, the voltage regulator 20 connected to the power supply terminal 31 is provided, and a series circuit of diodes 12 and 14 whose anodes are connected between the constant voltage output line 39 of the voltage regulator 20 and the gate of the power MOSFET 1 is provided. And the point that the source of the P-channel MOSFET 4 is connected to the constant voltage output line 39 of the voltage regulator 20 and the drain is connected to the gate of the MOSFET 3 via the diode 9. Is different from

As described above, in the semiconductor device 51 of the present embodiment, the constant voltage of, for example, 5 V is generated by the voltage regulator 20, and the cathode of the clamping diode 14 that determines the negative output sustain voltage _VSUS is connected to the constant voltage output line 39. _Therefore , the value of the negative output sustaining voltage _VSUS is stabilized without fluctuation. Further, since the source of the MOSFET 4 is connected to the constant voltage output line 39, the range of the output terminal voltage V _{OUT at which} the MOSFET 3 cannot cut off the power MOSFET 1 is defined _assuming that the voltage of the constant voltage output line 39 is V _DD0. The following equation is used instead of the equation (2).

なお、本実施例でＭＯＳＦＥＴ４のソースとＭＯＳＦＥＴ３のゲート間に設けたダイオード９は、出力端子３３が定電圧出力ライン３９の電圧Ｖ_DD0より高くなる場合に、ＭＯＳＦＥＴ４のドレイン・ボディ間に存在する寄生ダイオードが順バイアスされて出力端子３３から抵抗１７を通り定電圧出力ライン３９に電流が流入することを防止する働きをする。

In this embodiment, the diode 9 provided between the source of the MOSFET 4 and the gate of the MOSFET 3 is _connected to the parasitic terminal existing between the drain and the body of the MOSFET 4 when the output terminal 33 becomes higher than the voltage V _DD0 of the constant voltage output line 39. The diode is forward-biased and serves to prevent current from flowing from the output terminal 33 through the resistor 17 to the constant voltage output line 39.

Further, since the voltage from the power supply terminal 31 is a source of MOSFET 4 is in this embodiment is connected to a low constant voltage output line 39, MOSFET 4 drain-source necessary to increase the absolute value of the negative output sustaining voltage V _SUS There is an advantage that the breakdown voltage BV _{DSS (4)} can be small. That is, in the configuration of FIG. 1, the absolute value of the negative output sustaining voltage _VSUS needs to satisfy Expression (6), but in this embodiment, Expression (7) may be satisfied. Therefore, the negative output sustaining voltage _VSUS in the present embodiment is represented by Expression (8).

さらに、電圧Ｖ_DD0は定電圧出力ライン３９の電圧であるため、実施例１のようにバッテリ４１の電圧Ｖ_DDを直接使用する場合に比べて負出力維持電圧Ｖ_SUSの変動が低減され、遮断速度の変動が小さくなるという利点がある。その他の点に関しては、図１の実施例と同様の効果があることは勿論である。

Further, since the voltage V _DD0 is the voltage of the constant voltage output line 39, the fluctuation of the negative output sustaining voltage V _SUS is reduced compared to the case where the voltage V _{DD of the} battery 41 is directly used as in the first embodiment, and the voltage is cut off. There is an advantage that fluctuations in speed are reduced. In other respects, it is needless to say that the same effect as in the embodiment of FIG. 1 is obtained.

It should be noted that a series circuit of the clamping diode 14 and the backflow preventing diode 12 that determines the negative output sustaining voltage _VSUS may be connected between the ground terminal 30 and the output terminal 33. The negative output sustaining voltage V _SUS of the case can be designed in the above equation (8) as V _DD0 = 0V.

The diodes 14 and 12 for determining the negative output sustaining voltage are connected and arranged between the constant voltage output line 39 and the gate of the power MOSFET 1 as shown in FIG. 3, and furthermore, as shown in FIG. When a series circuit of the diode 12 and the clamping diode 13 whose anodes are connected to each other between the gate and the gate is arranged, the value of the normal negative output sustaining voltage _VSUS is kept constant by the clamping diode 14, and In addition, even if an overvoltage is applied between the power supply terminal 31 and the output terminal 33 by the clamping diode 13, the power MOSFET 1 can be protected from being destroyed. Incidentally, the withstand voltage of each of the clamping diodes 13 and 14 may have a desired value. For example, if the voltage of the constant voltage output line 39 5V, the voltage of the battery 41 12V, -35 V negative output sustain voltage V _SUS, the breakdown voltage of the power MOSFET1 about 70 V, the breakdown voltage of the clamping diode 14 is 37.4V In addition, the withstand voltage of the clamping diode 13 may be set to 65V. Further, as the clamping diodes 13 and 14, a plurality of diodes may be connected in series so as to obtain a desired required breakdown voltage and may be used as a clamping diode.

Further, since the source of MOSFET4 is connected to a constant voltage output line 39 of 5V, breakdown voltage of MOSFET4 is, when the power source terminal voltage of 12V, for realizing a -35V negative output voltage V _SUS, Example Unlike the case of 1, a low withstand voltage of about 40 V may be set.
Note that the cross-sectional structure of the semiconductor device 51 of this embodiment is the same as that of the first embodiment, and a description thereof will be omitted.

  FIG. 4 shows a third embodiment of the semiconductor device according to the present invention, and is a main part circuit diagram of a drive circuit for driving an inductive load. For convenience of explanation, in FIG. 4, the same components as those of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. That is, in this embodiment, the input signal processing circuit 35 is further provided with one additional output, the inverter 22 having the additional one output as an input, the gate connected to the output of the inverter 22, and the source connected to the power supply terminal 31. A P-channel MOSFET 25 to be connected, an N-channel MOSFET 23 having a drain connected to the gate of the MOSFET 3 and a source connected to the source of the MOSFET 3 instead of the resistor 17 between the gate and the source of the MOSFET 3, and a gate / source of the MOSFET 23 The configuration differs from the configuration of the first embodiment in that a resistor 24 connected between them is provided, and the drain of the MOSFET 25 is connected to the gate of the MOSFET 23.

  In the semiconductor device 52 of the present embodiment thus configured, the MOSFET 23 provided in place of the resistor 17 shown in FIG. When the input terminal 32 goes high, one additional output of the input signal processing circuit 35 goes low via the inverter 22 and is applied to the gate of the MOSFET 25. Therefore, the MOSFET 25 is turned on to drive the gate of the MOSFET 23, so that the MOSFET 23 is turned on and the MOSFET 3 is cut off. When the input terminal 32 has a low potential, the gate voltage applied to the MOSFET 25 via the input signal processing circuit 35 and the inverter 22 has a high potential, so that the MOSFET 25 is turned off, and the electric charge stored in the gate of the MOSFET 23 is Since the electric charge is discharged through the resistor 24, the MOSFET 23 is also turned off. On the other hand, at this time, since the output of the input signal processing circuit 35 applied to the gate of the MOSFET 4 is at a low potential, the MOSFET 4 is turned on to drive the gate of the MOSFET 3, so that the MOSFET 3 is also turned on. In other respects, the semiconductor device has the same configuration and semiconductor structure as those of the first embodiment shown in FIG.

  FIG. 5 shows a fourth embodiment of the semiconductor device according to the present invention, and is a main part circuit diagram of a drive circuit for driving an inductive load. For convenience of explanation, the same reference numerals in FIG. 4 denote the same components as those in the second embodiment shown in FIG. 3, and a detailed description thereof will be omitted. That is, in this embodiment, the N-channel MOSFET 6 whose drain is connected to the power supply terminal 31 and whose source is connected to the anode of the diode 12 for preventing backflow, the diodes 14 and 15 whose cathodes are connected to each other, and the cathode is the power supply A diode 13 whose terminal is connected to the anode of the diode 15 and whose anode is connected to the anode of the diode 15; a diode 16 whose cathode is connected to the anode of the diode 13 and whose anode is connected to the constant voltage output line 39 of the voltage regulator 20; , A resistor 18 connected between the gate and the source of the MOSFET 6, and the anode of the clamping diode 14 is connected to the gate of the MOSFET 6.

In the semiconductor device 53 of the present embodiment configured in this manner, since the current is supplied to keep the negative output sustaining voltage V _SUS by MOSFET 6, it is possible to reduce the element size of the diodes 13, 14, 15, 16 . The resistor 18 serves to turn off the MOSFET6 when the output terminal voltage V _OUT is above the negative output sustaining voltage V _SUS.

The normal negative output sustaining voltage _VSUS in the present embodiment is determined by the voltage value at which the clamping diode 14 _{breaks down, and} is expressed by equation (9). However, when the power supply voltage of the battery 41 becomes too high and the difference between the power supply voltage _VDD applied to the power supply terminal 31 and the negative output sustaining voltage _VSUS becomes larger than the withstand voltage of the power MOSFET 1, the power MOSFET 1 is turned off. For protection, the maximum negative output sustaining voltage _VSUSmax is set as in equation (10).
In other respects, it is needless to say that the same effect as in the embodiment of FIG. 3 is obtained.

  FIG. 6 shows a fifth embodiment of the semiconductor device according to the present invention, and is a main part circuit diagram of a drive circuit for driving an inductive load. For convenience of description, the same reference numerals in FIG. 6 denote the same constituent parts as those shown in FIG. 5 of the fourth embodiment, and a detailed description thereof will be omitted. That is, the present embodiment is different in that an N-channel MOSFET 28 is used instead of the resistor 18 in FIG. The MOSFET 28 has a channel width W smaller than that of the MOSFET 6, and has a drain and a gate connected to the gate of the MOSFET and a source connected to the source of the MOSFET 6, thereby forming a current mirror with the MOSFET 6.

In the semiconductor device 54 of the present embodiment configured in this manner, the diode less than structure breakdown current of Figure 5 flowing in 13,14,15,16, negative output sustain voltage desired at this small breakdown current V _SUS Can be obtained. Therefore, there is an advantage that the element size of the diodes 13, 14, 15, 16 can be further reduced as compared with the fourth embodiment.

  FIG. 7 shows a sixth embodiment of the semiconductor device according to the present invention, and is a main part circuit diagram of a drive circuit for driving an inductive load. For convenience of explanation, the same components as those shown in FIG. 7 of the fourth embodiment in FIG. 7 are denoted by the same reference numerals, and detailed description thereof will be omitted. That is, this embodiment is different from the fourth embodiment in that a P-channel MOSFET 5 having a source connected to the gate of the power MOSFET 1, a drain connected to the anode of the diode 8, and a gate connected to the output terminal 33 is newly provided.

  In the semiconductor device 55 of the present embodiment configured as described above, when the voltage between the gate and the source of the power MOSFET 1 becomes equal to or lower than the threshold voltage of the MOSFET 5, the shut-off operation of the power MOSFET 1 by the MOSFET 2 is terminated. This has the effect of becoming soft and reducing noise.

In this embodiment, the range of the voltage V _{OUT at} the output terminal 33 where the MOSFET 2 discharges the gate charge of the power MOSFET 1 and the power MOSFET 1 cannot perform the shut-off operation is defined by the equation (1) described in the first embodiment. It is not the range but the range of equation (11). However, V _{on (5} ) in equation (11) is the on-voltage of MOSFET5.

また、本実施例の場合、出力端子３３と電源端子３１との間で短絡不良が発生すると、ＭＯＳＦＥＴ５がオフするためＭＯＳＦＥＴ２に電流が流れなくなる。従って、ＭＯＳＦＥＴ２が過電流かつ過電圧の状態になって素子破壊に至ることを防止できるという効果がある。

In the case of this embodiment, when a short circuit occurs between the output terminal 33 and the power supply terminal 31, the MOSFET 5 is turned off, so that no current flows through the MOSFET 2. Therefore, there is an effect that it is possible to prevent the MOSFET 2 from being in an overcurrent and overvoltage state and causing element destruction.

  FIG. 8 shows a seventh embodiment of the semiconductor device according to the present invention, and is a main part circuit diagram of a drive circuit for driving an inductive load. For convenience of explanation, in FIG. 8, the same components as those of the sixth embodiment shown in FIG. 7 are denoted by the same reference numerals, and detailed description thereof will be omitted. That is, in the present embodiment, a low on-resistance (for example, about 10Ω) MOSFET 7 having a drain connected to the ground terminal 30, a source connected to the first ground line 34, and a gate connected to the power supply terminal 31 is newly provided. Different. Note that the diode 29 shown in the figure is a parasitic diode, and is an element that is necessarily inserted structurally between the first ground line 34 and the power supply terminal 31, and is present in the semiconductor devices of the first to sixth embodiments. Things. This parasitic diode 29 is formed between the first ground region including the P-type layers 103b and 108b shown in FIG. 9 and the N-type regions 101, 102a, 104a and 107a.

  In the semiconductor device 56 of the present embodiment configured as described above, when the battery 41 is normally connected as shown in FIG. 8, the MOSFET 7 is turned on, so that the first ground line 34 and the ground terminal 30 are connected. Have the same potential and operate in the same manner as the embodiment of FIG. On the other hand, when the user mistakenly connects the battery 41 in reverse, a negative voltage is applied to the gate of the MOSFET 7, so that the battery is turned off and the ground terminal 30 is disconnected from the first ground line 34. Therefore, no overcurrent flows from the ground terminal 30 through the parasitic diode 29. For this reason, element destruction due to overcurrent due to reverse connection of the battery 41 can be prevented. When the battery 41 is reversely connected, there is also a current flowing from the output terminal 33 to the power supply terminal 31 through a parasitic diode existing between the drain and the body of the power MOSFET 1. In this embodiment, there is no problem because the parasitic resistance is suppressed. Therefore, the semiconductor device 56 for driving the inductive load according to the present embodiment can realize reverse connection protection of the battery.

  Here, a semiconductor structure of the MOSFET 7 for performing reverse connection protection of the battery shown in FIG. 8 and the first ground 34 is shown in a sectional structural view in FIG. The other cross-sectional structures are the same as those in FIG. 9, and the manufacturing process conditions are also the same. As shown in FIG. 10, the MOSFET 7 is the same vertical MOSFET as the MOSFETs 2 and 3 in FIG. The source 113a and the body 111a of the MOSFET 7 are connected to the P-type layer region 108b serving as the first ground region using the aluminum electrode 114d, and the drain electrode 114e of the MOSFET 7 is connected to the ground terminal 30 of the semiconductor device 56 in FIG. The polycrystalline silicon layer 110a serving as the gate electrode of the MOSFET 7 is connected to the power supply terminal 31 in FIG. 8 or a voltage line having the same polarity as the power supply terminal 31 (not shown).

  With this connection, when the battery is connected to the semiconductor device 56 with the correct polarity, the MOSFET 7 is turned on, and the potential of the ground terminal 30 is equal to the potential of the first ground region. On the other hand, when the battery is reversely connected, a negative voltage is applied to the gate, so that the MOSFET 7 is turned off, and the ground terminal 30 is disconnected from the first ground region. In the case of the present embodiment, since the drain-source breakdown voltage of the MOSFET 7 is 70 V or more, a reverse connection protection voltage of the battery of about 70 V or more can be obtained.

  The preferred embodiment of the present invention has been described above. However, the present invention is not limited to the above-described embodiment. For example, in the above-described embodiment, the MOSFETs 2, 3, 7 and the like can easily achieve a high breakdown voltage. However, a similar effect can be obtained by using a lateral MOSFET or a bipolar transistor (in this case, the drain is replaced with the collector, the gate is replaced with the base, and the source is replaced with the emitter), and a range not departing from the spirit of the present invention is obtained. Of course, various design changes can be made within the above.

1 is an inductive load drive circuit diagram showing a first embodiment of a semiconductor device according to the present invention. FIG. 2 is a waveform chart showing input / output characteristics of the inductive load drive circuit shown in FIG. 1. FIG. 5 is an inductive load drive circuit diagram showing a second embodiment of the semiconductor device according to the present invention. FIG. 9 is an inductive load drive circuit diagram showing a third embodiment of the semiconductor device according to the present invention. FIG. 9 is an inductive load drive circuit diagram showing a fourth embodiment of the semiconductor device according to the present invention. FIG. 13 is an inductive load drive circuit diagram showing a fifth embodiment of the semiconductor device according to the present invention. FIG. 13 is an inductive load drive circuit diagram showing a sixth embodiment of the semiconductor device according to the present invention. FIG. 13 is an inductive load drive circuit diagram showing a seventh embodiment of the semiconductor device according to the present invention. FIG. 2 is a cross-sectional structural view of a main part of the semiconductor device shown in FIG. 1. FIG. 9 is a sectional structural view of a main part of the semiconductor device shown in FIG. 8. FIG. 9 is a main part circuit diagram showing a conventional inductive load drive circuit.

Explanation of reference numerals

1. Power MOSFET,
2, 3, 6, 7, 10, 23, 28 ... N-channel MOSFET,
4, 5, 25 ... P-channel MOSFET,
8, 9, 12, 13, 14, 15, 16, 26, 27 ... diodes,
17, 18, 24 ... resistance,
19 ... Booster circuit,
20 ... regulator,
29 ... parasitic diode,
21,22 ... inverter,
30 ... Ground terminal,
31 ... battery power terminal,
32 input terminal,
33 ... output terminal
34 ... ground line (first ground line) of control circuit
35 ... input signal processing circuit,
36: second ground line 39: constant voltage output line,
40 ... inductive load,
41 ... battery,
101: High-concentration N-type silicon substrate,
102a, 104a to 104e ... N-type buried layer,
103a, 103b ... P-type epitaxial layer,
105a to 105e: N-type epitaxial layer,
106 ... insulating film,
107a to 107d, 113, 113a... N-type diffusion layer,
108a, 108b, 109, 111, 111a, 112 ... P-type diffusion layer,
115 ... Low concentration P-type diffusion layer
110, 110a ... polycrystalline silicon layer,
114, 114a ... aluminum electrode layer,
114c, 114d: aluminum electrode layer (first ground).

Claims (3)

A power MOSFEST having a drain connected to the power supply terminal and a source connected to the output terminal;
A first MOSFEST disposed between a gate of the power MOSFEST and a control circuit ground to turn off the power power MOSFEST based on a voltage of an input terminal;
A second MOSFEST disposed between the gate of the power MOSFET and the output terminal to turn off the power MOSFET based on a voltage of the input terminal;
A gate charging circuit connected to a gate of the power MOSFEST to turn on the power MOSFEST based on a voltage of the input terminal;
A semiconductor device wherein each of the first MOSFEST and the second MOSFEST is formed in a p-type region separated by an n-type layer which is a drain region of the power MOSFEST. In claim 1,
The semiconductor device according to claim 1, wherein the p-type region in which the second MOSFEST is formed is connected to a source of the power MOSFEST. A semiconductor device having at least a vertical power MOSFEST and a control circuit for controlling a gate of the MOSFEST on a same semiconductor substrate of a first conductivity type,
The power MOSFEST region includes, in order from the substrate side, a first conductivity type first semiconductor layer and a first conductivity type second semiconductor layer having a lower concentration than the first semiconductor layer. A third conductive layer having a higher concentration than the second semiconductor layer reaching the first semiconductor layer from the surface to the first semiconductor layer in a peripheral portion;
The control circuit region includes, in order from the substrate side, a fourth semiconductor layer of the second conductivity type and the second semiconductor layer of the first conductivity type, and a plurality of the second semiconductor layers separated into islands. In a semiconductor device having a fifth semiconductor layer of a second conductivity type higher in concentration than the fourth semiconductor layer reaching the fourth semiconductor layer from the surface to form an island region,
A sixth semiconductor layer of a first conductivity type having a higher concentration than the second semiconductor layer reaching from the surface to the semiconductor substrate so as to separate at least one of the island regions from another island region. Characteristic semiconductor device.

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