JP2004129169A - Zero cross distortion free phase comparator and pll control method using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a conventional phase comparator shows an input/output characteristic not well in linearity when the phase difference between incoming signals is close to zero, resulting in insufficient reduction of spurious signals when used in a non-integer PLL (phase-locked loop) employing a fraction PLL or a Δ-Σ technique, and is difficult to have an accurate offset when used in the fraction PLL. <P>SOLUTION: According to the phase comparator to be provided, a charge pump continues the discharge and absorption of current for a certain time even if the phase difference is close to zero, eliminating the non-linearity of the comparator due to an internal delay. In addition, by varying the value of the current discharged or absorbed by the charge pump or a time of the discharge and absorption, the phase comparator is made to have an accurate offset, enabling the fraction PLL operation. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a PLL used to generate a signal having a designated frequency and a phase comparator used for the PLL.
[0002]
[Prior art]
[Patent Document 1] Japanese Patent Application Laid-Open No. 05-066958
[Patent Document 2] JP-A-08-046498
[Patent Document 3] JP-A-2000-005873
[Patent Document 4] JP-A-2002-223164
[Non-Patent Document 1] United States Patent 6,141,394
[Non-Patent Document 2] United States Patent 6,236,703
[Non-Patent Document 3] United States Patent 6,308,049
[Non-Patent Document 4] United States Patent 6,407,643
[0003]
In the prior art, the one shown in FIG. 35 has been used as a phase comparator in a PLL. However, in the phase comparator of this system, zero-cross distortion occurs when the phase difference between two signals for comparing the phases is small. This is because when the phase of one signal is ahead of the other, only one of the paired charge pumps operates, and vice versa, only the other of the charge pumps operates. This is because, when the phase difference between the two signals is small, both charge pumps operate instantaneously at the same time or have a dead band in which one of the charge pumps does not operate. This is shown in FIG. However, when trying to realize a fractional PLL using the Δ-Σ method, a problem has arisen that the spuriousness of the generated signal cannot be suppressed so much due to the nonlinearity of the phase comparator.
[0004]
In some cases, it is desired to realize a fractional PLL, but it is not appropriate to use the Δ-Σ method. In such a case, a current injection method has been conventionally used, or a method of generating a polyphase signal by DLL (delay loop lock) has been used. However, the current injection method has a problem in that accurate current injection for compensating a phase shift is not easy. In addition, the method using the DLL has a problem that it is not easy to generate a polyphase signal with high phase accuracy. In either case, these problems become more prominent as the frequency to be handled becomes higher.
[0005]
[Problems to be solved by the invention]
An object of the present invention is to improve the linearity of a phase comparator in a PLL. That is, it aims to make the output of the phase comparator accurately proportional to the phase difference between the two input signals.
[0006]
It is another object of the present invention to realize a highly accurate phase comparator for realizing a fractional PLL. That is, in the relationship between the two input signals and the output signal of the phase comparator, it is aimed to give an accurate offset to the input signal phase difference.
[0007]
[Means for Solving the Problems]
As a means for improving the linearity of the phase comparator, by expanding the range of the phase difference between the two signals operated by both the pair of charge pumps, the phase comparator can be used when the phase difference between the two signals is small. Increase linearity. By setting the range of the phase difference between two signals operated by both of the pair of charge pumps using a counter used to obtain one of the signals, the range of the phase difference can be easily set to an appropriate value. Can be set to
[0008]
Also, by appropriately setting the output value of the charge pump and changing the range of the phase difference, it is possible to change the offset with respect to the input signal phase difference of the phase comparator. To implement a fractional PLL.
[0009]
Also, by using a plurality of sets of phase comparators and charge pumps, by giving a certain difference to the signal phase difference supplied to each phase comparator and changing the ratio of the output current of each charge pump, the overall The non-integer PLL operation is realized by changing the phase offset of the phase comparator.
[0010]
Further, the total time of the positive charge pump working time and the negative charge pump working time of the phase comparator charge pump is fixed, and the ratio of the positive charge pump current to the negative charge pump current is calculated. , The phase offset of the phase comparator is changed, and a non-integer PLL operation is realized.
[0011]
【Example】
○ First embodiment
FIG. 1 is a block diagram of a phase comparator according to a first embodiment of the present invention. A signal corresponding to the phase difference between the first signal and the second signal f2, which is a signal obtained by dividing the third signal f1 by the counter CT1, is output as a phase comparator output Io. The output charge of the phase comparator output Io is a linear function of the phase difference.
[0012]
The third signal f1 is input to the counter CT1. At this time, the counter CT1 starts counting from 0 and counts up to a preset integer N-1, and the count value is reset to 0 by the next input pulse. The integers A and B are preset positive integers. When the count value of the counter CT1 is N−A, the signal 91 indicating the first phase of the first signal becomes H, and at other times, Is L. When the count value of the counter CT1 is B, the signal 93 indicating the second phase of the first signal becomes H, and otherwise becomes L.
[0013]
Switches Q1, Q2, Q3, Q4 are electronic switches. The constant current sources S1, S2, S3, and S4 try to flow a constant current, and when the switches Q1, Q2, Q3, and Q4 are on, the currents I1, I2, I3, and I4 flow, respectively. Is output to the phase comparator output Io. However, it is assumed that the currents I1 and I3 are positive and the currents I2 and I4 are negative. The output Io has a positive discharge current.
[0014]
When the signal f2 rises between the rising edge of the signal 91 and the rising edge of the signal 93, the phase comparator outputs the current I1 as the output Io from the rising edge of the signal 91 to the rising edge of the signal f2. During the period from the rising edge of f2 to the rising edge of the signal 93, the current I2 flows as the output Io. This is shown in FIG.
[0015]
When the signal f2 rises between the rising edge of the signal 91 and the rising edge of the signal 93, if the rising timing of the signal f2 is delayed by ΔT, the time for the current I1 to flow as the output Io becomes longer by ΔT, and the output Io The time during which the current I2 flows becomes shorter by ΔT. This fact does not depend on the delay time of the logic circuit used in the phase comparator, nor does it depend on the delay times of the switches Q1, Q2, Q3, and Q4. Therefore, the phase comparator has a very high linearity in a range where the phase difference is small.
[0016]
In this phase comparator, when the signal f2 rises before the rising edge of the signal 91, a current I4 flows as the output Io from the rising edge of the signal f2 to the rising edge of the signal 91. When the signal f2 rises after the rising edge of the signal 93, the current I3 flows as the output Io from the rising edge of the rising edge of the signal 93 to the rising edge of the signal f2. This is shown in FIG. By making the absolute values of the currents I3 and I4 sufficiently larger than the absolute values of the currents I1 and I2, the gain of the phase comparator when the phase difference is large is sufficiently larger than the gain when the phase difference is small. Can be larger.
[0017]
Such a phase difference dependency of the gain can play a large role in shortening the lock-up time when a PLL is configured using this phase comparator. That is, when the phase difference is small, the gain of the phase comparator can be reduced to suppress the spurious of the signal generated by the PLL, and when the phase difference is large, the gain of the phase difference can be increased to achieve fast lock-up. Can be measured. With respect to such a change in the gain of the phase comparator, there are already proposed methods.However, these methods externally give a command to change the current of the charge pump of the phase comparator, or use a lock-up detecting means. Or changing the current of the charge pump. However, in the first embodiment of the present invention, there is no need to externally set the gain of the phase comparator, and it is not necessary to change the gain of the phase comparator using lock-up detection means. There is an advantage that the gain of the phase comparator is automatically changed according to the magnitude of the phase difference.
[0018]
In the first embodiment of the present invention, in order to obtain the timings of the first phase and the second phase of the first signal, the third signal f1 is divided by the counter CT1, and the count value of the counter CT1 is obtained. Is detected by detecting that the first signal has a specific value. However, the means for obtaining the timing of the first phase and the second phase of the first signal is not limited to this method. For example, the rising edge and the falling edge of the first signal may be the first phase and the second phase, respectively. Further, the third signal f1 is frequency-divided by the counter CT1, the first phase of the first signal is detected by detecting that the count value of the counter CT1 reaches a specific value, and the signal is converted to the third signal. The second phase of the first signal may be detected using a signal delayed by a shift register that uses the signal f1 as a clock.
The second embodiment
FIG. 4 is a block diagram of a phase comparator according to a second embodiment of the present invention. A signal corresponding to the phase difference between the signal obtained by dividing the third signal f1 by the counter CT1 and the second signal f2 is output as the phase comparator output Io. The output charge is a linear function of the phase difference.
[0020]
The third signal f1 is input to the counter CT1. At this time, the counter CT1 starts counting from 0 and counts up to a preset integer N-1, and the count value is reset to 0 by the next input pulse. The integer A is a preset positive integer. When the count value of the counter CT1 is N−A, the signal 91 indicating the first phase of the first signal becomes H, and at other times, it becomes L. It becomes. When the count value of the counter CT1 is A, the signal 93 indicating the second phase of the first signal becomes H, and otherwise becomes L. The signal 92 indicating that the count value of the counter CT1 is zero becomes H when the count value is 0, and becomes L otherwise.
[0021]
Switches Q1, Q2, Q5, and Q6 are electronic switches. The constant current sources S1, S2, S5, and S6 try to pass a constant current, and the currents I1, I2, I5, and I6 flow when the switches Q1, Q2, Q5, and Q6 are on. Is output to the phase comparator output Io. However, the currents I1 and I5 are assumed to be positive, and the currents I2 and I6 are assumed to be negative. The output Io has a positive discharge current. Further, it is assumed that the value of I5 is equal to a value obtained by changing the sign of the value of I2, and a value of I6 is equal to a value obtained by changing the sign of the value of I1.
[0022]
FIG. 5 shows an example of the operation waveform of the second embodiment of the present invention. When the signal f2 rises between the rising edge of the signal 91 and the rising edge of the signal 93, the phase comparator superimposes the current I1 on the output Io from the rising edge of the signal 91 to the rising edge of the signal f2. During the period from the rising edge of the signal f2 to the rising edge of the signal 93, the current I2 is superimposed on the output Io. The current I6 is superimposed on the output Io from the rising edge of the signal 91 to the rising edge of the signal 92, and the current I5 is superimposed on the output Io from the rising edge of the signal 92 to the rising edge of the signal 93. . In an ideal state, when the signal f2 and the signal 92 rise at the same time, the average value of the output Io becomes 0. In such a situation, the current is canceled at any moment and the current flows to the output Io. Absent. When the signal f2 rises between the rising edge of the signal 91 and the rising edge of the signal 92, the current is canceled and not output to the output Io from the rising edge of the signal 91 to the rising edge of the signal f2, and the signal f2 The current I2 + I6 is output to the output Io from the rising edge of the signal 92 to the rising edge of the signal 92, and the current is canceled and not output to the output Io from the rising edge of the signal 92 to the rising edge of the signal 93. During the other periods, no current is output to the output Io. When the signal f2 rises during the rising edge of the signal 93, the current I1 + I5 is output to the output Io during the period from the rising edge of the signal 92 to the rising edge of the signal 93, and in other periods, No current is output to the output Io.
[0023]
As described above, in the second embodiment of the present invention, the phase comparator performs the same operation as the conventional phase comparator, but the linearity between the phase difference and the output when the phase difference is small is equal to that of the present invention. As in the first embodiment, higher linearity than the conventional one can be obtained. Further, when compared with the first embodiment of the present invention, when the phase difference is small, the effective value of the output Io can be reduced. Therefore, when configuring the PLL using this phase comparator, It has the advantage that the design conditions are eased.
[0024]
In the second embodiment of the present invention, the gain of the phase detector is changed when the phase difference is large such as when the signal f2 rises earlier than the signal 91 or when the signal f2 rises later than the signal 93. However, as in the first embodiment of the present invention, the gain of the phase comparator may be changed according to the magnitude of the phase difference.
○ Third embodiment
FIG. 6 is a block diagram of a PLL device according to the third embodiment of the present invention. A signal having a frequency obtained by multiplying the frequency of the reference frequency signal fr by a value given from the outside is obtained as the voltage controlled oscillator output signal fv.
[0026]
The phase comparator PD2 is a phase comparator according to the second embodiment of the present invention. The compensator CP receives the phase comparator output Io as an input, outputs a voltage signal, and supplies the voltage signal to the voltage-controlled oscillator VCO, stabilizes the closed loop system of the PLL, and suppresses the spurious of the voltage-controlled oscillator output signal fv. In addition, the loop filter has a role of realizing a short lock-up time. The voltage controlled oscillator VCO outputs a voltage controlled oscillator output signal fv having a frequency corresponding to the input signal. The controller CR1 functions to give the frequency division number N of the counter CT1 to the phase comparator PD2 for each cycle of the reference frequency signal fr. The frequency setting value X is a command value indicating how many times the frequency of the reference frequency signal fr is to be generated as the voltage controlled oscillator output signal fv, and the value is not necessarily an integer.
[0027]
Since the reference frequency signal fr is input as the second signal f2 of the phase comparator PD2 and the voltage-controlled oscillator output signal fv is input as the third signal f1 of the phase comparator PD2, the frequency of the voltage-controlled oscillator output signal fv Is a value obtained by multiplying the reference frequency signal fr by the average value of the frequency division number N. Further, the controller CR1 outputs the frequency division number N such that the average thereof becomes equal to the frequency set value X, thereby obtaining a voltage controlled oscillator output signal fv of a desired frequency.
[0028]
When the frequency setting value X is not an integer, low-frequency components excluding a DC component when the frequency division number N is treated as a time-series signal are reduced as much as possible so as to suppress spurious components included in the voltage controlled oscillator output signal fv as much as possible. The time series of the frequency division number N is set as described above, but if the linearity of the phase comparator PD2 is not good, a desired spurious suppression characteristic cannot be obtained. By using the phase comparator PD2 according to the second embodiment of the present invention, it is possible to ensure high linearity of the phase comparator and obtain desired spurious suppression characteristics. As a method of setting a time series of the frequency division number N, a method of frequency shaping of quantization noise using a Δ-Σ technique is known.
○ Fourth embodiment
FIG. 7 is a block diagram of a PLL device according to a fourth embodiment of the present invention. A signal having a frequency obtained by multiplying the frequency of the reference frequency signal fr by a value given from the outside is obtained as the voltage controlled oscillator output signal fv.
[0030]
The phase comparator PD2 is a phase comparator according to the second embodiment of the present invention. The compensator CP receives the phase comparator output Io as an input, outputs a voltage signal, and supplies the voltage signal to the voltage-controlled oscillator VCO, stabilizes the closed loop system of the PLL, and suppresses the spurious of the voltage-controlled oscillator output signal fv. In addition, the loop filter has a role of realizing a short lock-up time. The voltage controlled oscillator VCO outputs a voltage controlled oscillator output signal fv having a frequency corresponding to the input signal. The controller CR2 serves to give the frequency division number Y of the counter CT2 for each cycle of the counter CT2. The frequency setting value X is a command value indicating how many times the frequency of the reference frequency signal fr is to be generated as the voltage controlled oscillator output signal fv, and the value is not necessarily an integer.
[0031]
The reference frequency signal fr is input as the third signal f1 of the phase comparator PD2, and the voltage-controlled oscillator output signal fv is Y-divided by the counter CT2 and then input as the second signal f2 of the phase comparator PD2. Therefore, the phase of the signal obtained by dividing the reference frequency signal fr by N and the signal obtained by dividing the voltage-controlled oscillator output signal fv by Y are compared inside the phase comparator PD2. When the frequency is constant, the frequency of the voltage controlled oscillator output signal fv is a value obtained by multiplying the reference frequency signal fr by the average value of the frequency division number Y and dividing by the frequency division number N. Further, the controller CR2 outputs the frequency division number Y such that the average thereof becomes equal to the frequency setting value X, thereby obtaining the voltage controlled oscillator output signal fv of a desired frequency.
[0032]
When the frequency setting value X is not an integer, low frequency components other than DC components when the frequency division number Y is treated as a time series signal are reduced as much as possible so as to suppress spurious components included in the voltage controlled oscillator output signal fv as much as possible. The time series of the frequency division number Y is set as described above, but if the linearity of the phase comparator PD2 is not good, a desired spurious suppression characteristic cannot be obtained. By using the phase comparator PD2 according to the second embodiment of the present invention, it is possible to ensure high linearity of the phase comparator and obtain desired spurious suppression characteristics.
○ Fifth embodiment
The fifth embodiment of the present invention is a signal generator using a PLL in which a modulo value is 2. A signal having a frequency that is a fractional multiple of 2 with respect to the frequency of the reference frequency signal fr is generated. FIG. 8 is a block diagram of the phase comparator PD1 used in the fifth embodiment of the present invention. FIG. 9 is a block diagram of a PLL device according to a fifth embodiment of the present invention.
[0034]
The phase comparator PD1 shown in FIG. 8 is capable of sequentially setting the frequency division number N of the counter CT1 and the values of the integers A and B from outside. When the signal f2 rises between the rising edge of the signal 91 and the rising edge of the signal 93, the phase comparator outputs the current I1 as the output Io from the rising edge of the signal 91 to the rising edge of the signal f2. During the period from the rising edge of f2 to the rising edge of the signal 93, the current I2 flows as the output Io. In the fifth embodiment of the present invention, the values of the current I1 and the current I2 are made equal. Then, if the value of the integer A is increased by 1 or the value of the integer B is reduced by 1, the phase of the third signal f1 in which the average over one cycle of the output Io becomes zero is advanced by a half cycle with respect to the previous state. Conversely, if the value of the integer A is decreased by one or the value of the integer B is increased by one, the phase of the third signal f1 whose output Io has an average of zero over one cycle is delayed by exactly half a cycle. However, since accuracy is required for the relative change of the timing of the signal 91 or the signal 93 when the value of the integer A or the integer B is changed, the signal 91 or the signal 93 is synchronized with the third signal f1. It is desirable to keep.
[0035]
In FIG. 9, the frequency setting value X is a fraction having 2 as a denominator. The phase comparator PD1 inputs the reference frequency signal fr as the second signal f2, and inputs the voltage controlled oscillator output signal fv as the third signal f1. The controller CR3 receives the frequency set value X and supplies the frequency division number N of the counter CT1 and the integers A and B to the phase comparator PD1 for each period of the reference frequency signal fr. Since the phase of the signal obtained by dividing the voltage of the voltage controlled oscillator output signal fv by N and the reference frequency signal fr are compared inside the phase comparator PD1, the frequency of the voltage controlled oscillator output signal fv is countered by the frequency of the reference frequency signal fr. It is a value obtained by multiplying the average value of the dividing number N of CT1.
[0036]
When the frequency setting value X is a multiple of が but not an integer, the dividing number N of the counter CT1 repeats increasing and decreasing by 1 every cycle. At this time, if the values of the integers A and B are constant, the phase comparator output Io repeatedly increases and decreases every cycle, which causes the voltage controlled oscillator output signal fv to include a lot of spurious components. In order to prevent this, the cut-off frequency of the compensator CP needs to be lowered, and the lock-up time of the PLL deteriorates. Therefore, when the frequency division number N of the counter CT1 takes a value larger than the average value, whether the value of the integer A is increased by 1 or the value of the integer B is reduced by 1 is compared with the case where the division number N is not otherwise. The average value of the phase comparator output Io in the cycle can be made constant, and the spurious of the voltage controlled oscillator output signal fv can be suppressed.
[0037]
In the fifth embodiment of the present invention, the accuracy of the phase offset obtained by changing the values of the integers A and B is determined by the relative ratio of the output currents I1 and I2 of the constant current sources S1 and S2. By accurately setting the values of I1 and I2, a high spurious suppression effect can be obtained.
[0038]
In the fifth embodiment of the present invention, the frequency setting value X is a fraction with 2 as the denominator, but need not be a fraction with 2 as the denominator, and another number may be the denominator. . Also at this time, the average value of the frequency division number N of the counter CT1 is made equal to the frequency set value X. By appropriately changing the values of the integers A and B, the output of the phase comparator output Io for each cycle is obtained. Low frequency components other than DC components can be suppressed. As a result, the cutoff frequency of the compensator CP can be increased.
○ Sixth embodiment
The sixth embodiment of the present invention relates to a signal generator using a PLL having a modulo value of 8. A signal having a frequency that is a fractional multiple of 8 with respect to the frequency of the reference frequency signal fr is generated. FIG. 11 is a block diagram of a PLL device according to a sixth embodiment of the present invention. The difference from the one shown in FIG. 9 is that a means for correcting the current I2 by the adjuster AD is added. The block diagram of the phase comparator PD1 in FIG. 11 is as shown in FIG. 8 and is the same as that of the fifth embodiment of the present invention, except that the ratio of the current I1 to the current I2 is different and the current I2 is The difference is that it can be corrected.
[0040]
The ratio between the currents I1 and I2 in the sixth embodiment of the present invention is 5 to -3. The phase comparator PD1 is provided with a phase offset by appropriately setting the values of the integers A and B. However, in order to realize the modulo 8 fractional PLL operation, the period of the voltage control oscillator output signal fv must be adjusted. On the other hand, it is necessary to provide a phase offset at 1/8 intervals. FIG. 10 shows an example of a combination of integers A and B having such a phase offset. In FIG. 10, “the change width of A” means that there is a reference value for the value of the integer A, and the change width of the value of A from the reference value. The same applies to the “change width of B”.
[0041]
The accuracy of the phase offset in the phase comparator PD1 does not depend on the delay time in the circuit inside the phase comparator PD1, but is determined by the accuracy of the ratio between the currents I1 and I2. There is no problem if the ratio between the currents I1 and I2 can be set with sufficient accuracy, but if not, an error in the ratio between the currents I1 and I2 is detected by some method, and the current I1 and I2 are determined based on the error signal. A method of correcting the ratio of I2 is effective.
[0042]
In the sixth embodiment of the present invention, the error of the ratio between the currents I1 and I2 is detected by analyzing the output Io of the phase comparator. Now, consider a case where the frequency setting value X is not an integer. At this time, combinations of the integers A and B for some item numbers in the table shown in FIG. 10 are repeatedly set. However, it is assumed that the repetition is set so as to include a combination of the integers A and B of the item number 1 for any frequency setting value X. At this time, if an error is included in the ratio between the currents I1 and I2, the integral value of the phase comparator output Io in one cycle for each cycle has a perturbation proportional to the inner product pattern in the table shown in FIG. Further, since the average value of the inner product pattern itself is 0, the inner product of the phase comparator output Io and the inner product pattern is obtained over a period of an integral multiple of 8 or for a sufficiently long time, so that the ratio of the currents I1 and I2 is obtained. A signal proportional to the error can be obtained. However, as a practical problem, it is often impossible to use the phase comparator output Io as it is for error detection. In the sixth embodiment of the present invention whose block diagram is shown in FIG. 11, the phase comparator output Io is a current signal, the compensator CP is a passive circuit including a resistor and a capacitor, and the input voltage of the compensator CP is Is used as a signal for detecting an error in the ratio between the currents I1 and I2, and the adjuster AD integrates the inner product of the input voltage of the compensator CP and the inner product pattern to correct the current I2. Getting the signal. Normally, the compensator CP includes an integration characteristic. However, since a zero point is also set for stabilizing the PLL, a closed loop for compensating for an error in the ratio between the currents I1 and I2 can also be stabilized.
[0043]
When the frequency setting value X is an integer, if the frequency setting value X continues to be an integer, there is no problem even if the ratio between the currents I1 and I2 includes an error, but the frequency setting value X becomes a non-integer later. In such a case, it is desirable to always detect and correct the error in the ratio between the currents I1 and I2. However, unless the values of the integers A and B change, an error in the ratio between the currents I1 and I2 cannot be detected. Therefore, when the frequency set value X is an integer, the values of the integers A and B are changed by alternately repeating the item numbers 8 and 9 in the table shown in FIG. Correction of the ratio error is enabled.
[0044]
In the sixth embodiment of the present invention, the patterns of the tables shown in FIG. 10 are used as the patterns of the integers A and B, but the patterns of the integers A and B are not limited to those of the table shown in FIG.
[0045]
In the sixth embodiment of the present invention, the correction of the error of the ratio between the currents I1 and I2 is always performed online, but the correction may be performed by an offline operation when the power is turned on, or the correction may be performed periodically. Operation may be performed. When manufacturing the phase comparator PD1, a similar method may be used to perform correction by trimming. If the required accuracy is obtained for the ratio between the currents I1 and I2, it is not necessary to correct the error in the ratio between the currents I1 and I2.
[0046]
In the sixth embodiment of the present invention, the ratio of the currents I1 and I2 is set to 5 to -3, but the greatest common divisor of I1 and I2 is １ ／ of the value of I1−I2, or one-integral thereof. The ratio between the currents I1 and I2 may be another value.
[0047]
Although the ratio between the currents I1 and I2 in the sixth embodiment of the present invention is set to 5 to -3, when the ratio between the currents I1 and I2 is set to 3 to -5, the "change in A" in the table shown in FIG. By exchanging the value of the “width” and the value of the “change width of B”, it is possible to realize a phase offset having a different sign from the value of the “phase offset” in the table shown in FIG.
○ Seventh embodiment
The seventh embodiment of the present invention is a signal generator using a PLL with a modulo value of 16. A signal having a frequency that is a fractional multiple of 16 with respect to the frequency of the reference frequency signal fr is generated. The block diagram of the PLL device according to the seventh embodiment of the present invention is the same as that shown in FIG. The block diagram of the phase comparator PD1 in FIG. 9 is as shown in FIG. 8 and is the same as that of the fifth embodiment of the present invention, except that the ratio between the current I1 and the current I2 is different.
[0049]
The ratio of the currents I1 and I2 in the seventh embodiment of the present invention is 9 to -7. The phase comparator PD1 is provided with a phase offset by appropriately setting the values of the integers A and B. In order to realize the modulo 16 fractional PLL operation, the period of the voltage controlled oscillator output signal fv must be adjusted. On the other hand, it is necessary to provide a phase offset at intervals of 1/16. FIG. 12 shows an example of a combination of integers A and B having such a phase offset. In FIG. 12, “the change width of A” means that there is a reference value for the value of the integer A and the change width of the value of A from the reference value. The same applies to the “change width of B”.
[0050]
The accuracy of the phase offset in the phase comparator PD1 does not depend on the delay time in the circuit inside the phase comparator PD1, but is determined by the accuracy of the ratio between the currents I1 and I2. There is no problem if the ratio between the currents I1 and I2 can be set with sufficient accuracy, but if not, an error in the ratio between the currents I1 and I2 is detected by some method, and the current I1 and I2 are determined based on the error signal. A method of correcting the ratio of I2 is effective. In the seventh embodiment of the present invention, there is no means for correcting the ratio between the currents I1 and I2.
[0051]
In the seventh embodiment of the present invention, the patterns of the integers A and B shown in the table of FIG. 12 are used, but the patterns of the integers A and B are not limited to those of the table shown in FIG.
[0052]
In the seventh embodiment of the present invention, there is no means for correcting the error of the ratio between the currents I1 and I2. However, as in the sixth embodiment of the present invention, the error of the ratio between the currents I1 and I2 is not corrected. A means for performing the correction may be provided.
[0053]
In the seventh embodiment of the present invention, the ratio of the currents I1 and I2 is set to 9 to -7, but the greatest common divisor of I1 and I2 is 1/16 of the value of I1−I2, or 1 / integer thereof. The ratio between the currents I1 and I2 may be another value.
[0054]
In the seventh embodiment of the present invention, the ratio of the currents I1 and I2 is set to 9 to -7. However, when the ratio of the currents I1 and I2 is set to 7 to -9, the "change of A" in the table shown in FIG. By swapping the value of “width” and the value of “change width of B”, it is possible to realize a phase offset having a different sign from the value of “phase offset” in the table shown in FIG.
[0055]
In the PLL according to the seventh embodiment of the present invention, the modulo value is 16, but for any integer M equal to or greater than 2, the ratio of the currents I1 and I2 is expressed by the greatest common divisor of I1 and I2 is I1-I2 By setting it to be 1 / M of the value of, a PLL having a modulo value of M can be configured.
Eighth Embodiment
The eighth embodiment of the present invention is a signal generator using a PLL with a modulo value of 16. A signal having a frequency that is a fractional multiple of 16 with respect to the frequency of the signal obtained by dividing the reference frequency signal fr by N is generated. FIG. 14 is a block diagram of a PLL device according to the eighth embodiment of the present invention. FIG. 13 shows a block diagram of the phase comparator PD11 in FIG.
[0057]
The operation of the phase comparator PD11 is as follows. When the count value of the counter CT2 becomes A after the count value of the counter CT1 becomes 0, the switch Q1 is closed between the time the count value of the counter CT1 becomes 0 and the count value of the counter CT2 becomes A. The current I1 is superimposed on the phase comparator output Io. When the count value of the counter CT2 becomes Y-B and then the count value of the counter CT1 becomes E, the count value of the counter CT2 becomes Y-B and then the count value of the counter CT1 becomes E. During this period, the switch Q2 is closed, and the current I2 is superimposed on the phase comparator output Io. The operation of the PLL is almost the same as that of the seventh embodiment of the present invention except for this point and the point that the current I2 is not provided. The relationship between the ratio between the currents I1 and I2, the change in the integers A and B, and the phase offset is the same as in the seventh embodiment of the present invention.
[0058]
An advantage of the eighth embodiment of the present invention over the seventh embodiment of the present invention is that a period in which the current I1 is superimposed on the phase comparator output Io and a period in which the current I2 is superimposed are generated. Therefore, the effective value of the signal of the phase comparator output Io can be suppressed, and the spurious of the voltage controlled oscillator output signal fv can be easily suppressed. However, in the eighth embodiment of the present invention, it is necessary to generate a plurality of phase signals for both the signal obtained by dividing the reference frequency signal fr and the signal obtained by dividing the voltage controlled oscillator output signal fv.
The ninth embodiment
The ninth embodiment of the present invention is a signal generator using a PLL with a modulo value of 16. A signal having a frequency that is a fractional multiple of 16 with respect to the frequency of the reference frequency signal fr is generated. FIG. 16 is a block diagram of a PLL device according to the ninth embodiment of the present invention. FIG. 15 shows a block diagram of the phase comparator PD3 in FIG. In the phase comparators according to the sixth embodiment and the seventh embodiment of the present invention, the number of the constant current sources constituting the charge pump is two in total on the positive side and the negative side. The ninth embodiment differs greatly in that it has three positive and negative sides.
[0060]
The ratio of the currents I1, I2, and I7 in the ninth embodiment of the present invention is 5: 7: 4. The phase comparator PD3 is provided with a phase offset by appropriately setting the values of the integers A, B, and C. In order to realize the fractional PLL operation of the modulo 16, the output of the voltage controlled oscillator output signal fv is required. It is necessary to have a phase offset at intervals of 1/16 of the period. FIG. 17 shows an example of a combination of integers A, B, and C having such a phase offset. In FIG. 17, “the change width of A” means that there is a reference value for the value of the integer A, and the change width of the value of A from the reference value. The same applies to the “change width of B” and “change width of C”.
[0061]
The accuracy of the phase offset in the phase comparator PD3 does not depend on the delay time in the circuit inside the phase comparator PD3, but is determined by the accuracy of the ratio of the currents I1, I2, and I7. There is no problem if the ratio between the currents I1, I2 and I7 can be set with sufficient accuracy, but if not, an error in the ratio between the currents I1, I2 and I7 is detected by some method, and the error signal is obtained. The method of correcting the ratio of the currents I1, I2, and I7 is effective. In the ninth embodiment of the present invention, there is no means for correcting the ratio between the currents I1, I2 and I7.
[0062]
The advantage of the ninth embodiment of the present invention over the seventh embodiment of the present invention is that the variation width of the integers A, B, and C can be reduced. As a result, the period during which the phase comparator output Io is output in one cycle can be shortened, so that spurious components included in the voltage controlled oscillator output signal fv can be easily reduced.
[0063]
In the ninth embodiment of the present invention, the patterns of the tables shown in FIG. 17 are used as the patterns of the integers A, B, and C. However, the patterns of the integers A, B, and C are limited to those of the table shown in FIG. Not something.
[0064]
In the ninth embodiment of the present invention, there is no means for correcting the error of the ratio between the currents I1, I2, and I7. However, as in the sixth embodiment of the present invention, there is no means for correcting the currents I1, I2, and I7. Means for correcting the ratio error may be provided. However, when performing correction while performing a non-integer PLL operation, it is necessary to prepare two types of inner product patterns and use them simultaneously. Further, when performing the correction while performing the non-integer PLL operation, it is necessary to prepare at least three sets of integers A, B, and C for realizing the same phase offset, and to switch and use them sequentially.
[0065]
In the ninth embodiment of the present invention, the ratio of the currents I1, I2, and I7 is 5: -7: 4, but the greatest common divisor of I1, I2, and I7 is 1/16 of the value of I1-I2 + I7, or The ratio may be any one of the integers, and the ratio between the currents I1, I2, and I7 may be another value.
[0066]
In the PLL according to the ninth embodiment of the present invention, the modulo value is 16, but for any integer M equal to or greater than 2, the ratio of the currents I1, I2, and I7 is the greatest common divisor of I1, I2, and I7. Is set to be 1 / M of the value of I1−I2 + I7, whereby a PLL having a modulo value of M can be configured. In the case of a large value of M, the provision of three charge pumps makes it possible to reduce the fractions of the integers A, B, and C by a small change width as compared with the case of two charge pumps in the seventh embodiment of the present invention. PLL operation can be realized.
[0067]
In the ninth embodiment of the present invention, as the charge pump, two constant current sources S1 and S7 are used on the positive side and one of the constant current sources S2 is used on the negative side. Two constant current sources may be used on the side.
The tenth embodiment
The tenth embodiment of the present invention is a signal generator using a PLL with a modulo value of 16. A signal having a frequency that is a fractional multiple of 16 with respect to the frequency of the signal obtained by dividing the reference frequency signal fr by N is generated. FIG. 19 is a block diagram of a PLL device according to the tenth embodiment of the present invention. FIG. 18 shows a block diagram of the phase comparator PD12 in FIG.
[0069]
The eighth embodiment of the present invention is different from the seventh embodiment of the present invention in that a constant current source S7 which is a means for giving a phase offset to a phase comparator and an integer C to be compared with a count value are added. Similarly, the tenth embodiment of the present invention is different from the ninth embodiment of the present invention in that a constant current source S7 as a means for providing a phase offset and an integer C to be compared with a count value are added. . Therefore, the ratio of the currents I1, I2 and I7 and the values of the integers A, B and C giving the desired phase offset in the tenth embodiment of the present invention are the same as in the ninth embodiment of the present invention.
[0070]
The advantage of the tenth embodiment of the present invention over the ninth embodiment of the present invention is similar to the advantage of the eighth embodiment of the present invention over the seventh embodiment of the present invention. The value can be suppressed, and the spurious of the voltage controlled oscillator output signal fv can be easily suppressed. However, in the tenth embodiment of the present invention, it is necessary to generate a plurality of phase signals for both the signal obtained by dividing the reference frequency signal fr and the signal obtained by dividing the voltage controlled oscillator output signal fv.
The eleventh embodiment
The eleventh embodiment of the present invention is a signal generator using a PLL in which the modulo value is 8. A signal having a frequency that is a fractional multiple of 8 with respect to the frequency of the reference frequency signal fr is generated. FIG. 21 is a block diagram of a PLL device according to the eleventh embodiment of the present invention. FIG. 20 shows a block diagram of the phase comparator PD4 in FIG. In the phase comparator according to the ninth embodiment of the present invention, the number of the constant current sources constituting the charge pump is three in total on the positive side and the negative side. It has four on the negative side.
[0072]
The ratio of the currents I1, I2, I7 and I8 in the eleventh embodiment of the present invention is 1: 1-1: 2: -4. That is, the absolute value of each current is arranged as a power of two, and there are only two minimum values. The phase comparator PD3 is provided with a phase offset by appropriately setting the values of the integers A, B, C, and D. In order to realize the modulo 8 fractional PLL operation, a voltage controlled oscillator output signal is required. It is necessary to provide a phase offset at 1/8 interval with respect to the period of fv. FIG. 22 shows an example of a combination of integers A, B, C, and D having such a phase offset. In FIG. 22, “the change width of A” means that there is a reference value for the value of the integer A and the change width of the value of A from the reference value. The same applies to the “change width of B”, “change width of C”, and “change width of D”.
[0073]
The accuracy of the phase offset in the phase comparator PD4 does not depend on the delay time in a circuit inside the phase comparator PD4, but is determined by the accuracy of the ratio of the currents I1, I2, I7, and I8. There is no problem if the ratio of the currents I1, I2, I7, and I8 can be set with sufficient accuracy, but if not, an error in the ratio of the currents I1, I2, I7, and I8 is detected by some method, and the error is detected. A method of correcting the ratio of the currents I1, I2, I7, and I8 based on the signal is effective. In the ninth embodiment of the present invention, there is no means for correcting the ratio between the currents I1, I2, I7, and I8.
[0074]
One of the advantages of the eleventh embodiment of the present invention over the ninth embodiment of the present invention is that it can be easily extended to a fractional PLL using a power of 2 as a modulo. This is because the absolute value of the current in each constant current source for the output current is arranged as a power of 2, and only two minimum values are prepared. In the eleventh embodiment of the present invention, a fractional PLL modulo 8 is realized by using four constant current sources for output current, but by using five constant current sources, 16 Can be made modulo, and by making the number of constant current sources six, 32 can be made modulo. Thus, the modulo value can be increased by increasing the number of constant current sources. An advantage of this approach is that a combination of integers A, B, C, D, etc. realizing each phase offset at that time can be calculated regularly. Further, the variation widths of the integers A, B, C, D, etc. are 1 at the maximum. As a result, the period during which the phase comparator output Io is output in one cycle can be shortened, so that the spurious included in the voltage controlled oscillator output signal fv can be easily reduced.
[0075]
In the eleventh embodiment of the present invention, the patterns of the tables shown in FIG. 22 are used as the patterns of the integers A, B, C, and D. However, the patterns of the integers A, B, C, and D are the tables shown in FIG. It is not limited to those. In the eleventh embodiment of the present invention, the ratio of the currents I1, I2, I7, and I8 is 1: 1-1: 2: -4, but the absolute values of the currents are 1: 1 to 1: 1 in any order. In the case of 2 to 4, a fractional PLL in which 8 is modulo can be similarly configured. Further, the ratio of the currents I1, I2, I7, and I8 may be any value. By appropriately setting the ratio of these currents, it is possible to realize a fractional PLL in which a large number is modulo.
[0076]
In the eleventh embodiment of the present invention, there is no means for correcting the error of the ratio between the currents I1, I2, I7, and I8. However, as in the sixth embodiment of the present invention, the current I1, I2 Means for correcting the error of the ratio between I7 and I8 may be provided.
In the eleventh embodiment of the present invention, as the charge pump, two constant current sources S1 and S7 are used on the positive side, and two constant current sources S2 and S8 are used on the negative side. Alternatively, three constant current sources may be used on the negative side, or three constant current sources may be used on the positive side and one constant current source may be used on the negative side.
The twelfth embodiment
The twelfth embodiment of the present invention is a signal generator using a fractional PLL in which the value of M is a natural number and the modulo value is M. A signal having a frequency that is a fraction multiple of the frequency of the reference frequency signal fr with the denominator being M is generated. FIG. 24 is a block diagram of a PLL device according to a twelfth embodiment of the present invention. FIG. 23 shows a block diagram of the phase comparator PD5 in FIG. The phase comparator according to the twelfth embodiment of the present invention has M combinations of positive and negative sides of the constant current source constituting the charge pump, and all the current values are equal. The phase comparator PD5 can be realized by connecting a plurality of phase comparators in parallel. However, since there are many common parts such as the counter CT1, the common parts are put together.
[0078]
The counter CT1 of the phase comparator PD5 outputs a signal indicating that the count value is equal to 0, 1, B, and B + 1. The switches QP1 and QN1 switch QPM and QNM respectively output the count value of the counter CT1. Is a signal that is 0 and B, a timing generated by the second signal f2, or a signal in which the count value of the counter CT1 is 1 and a signal that is B + 1, a timing generated by the second signal f2. The on / off operation is performed according to either of them. The timing at which the operation is performed is switched by the switching signals SW1 to SWM. In the former timing, the period during which the switch for the positive-side constant current source is ON is longer by one clock of the third signal f1 compared to the latter timing, and the switch for the negative-side constant current source is turned on. The ON period is shorter by one clock of the third signal f1. Since the currents of the respective constant current sources are equal, of the M sets of constant current sources, the L sets of constant current sources are turned on / off based on the signal whose counter value of the counter CT1 is 1 and the signal whose value is B + 1. Of the (ML) pairs of constant current sources are turned on / off based on the signal of which the count value of the counter CT1 is 0 and the signal of which is B, the phase comparator PD5 becomes the period of the third signal f1. On the other hand, it has a phase offset of L / M times.
[0079]
Since the value of the phase offset of the phase comparator PD5 can be changed by the switching signals SW1 to SWM, the controller CR6 in FIG. By outputting the value appropriately, a fractional PLL with a modulo value of M can be realized.
[0080]
One advantage of the twelfth embodiment of the present invention is that the current values of the constant current sources SP1 to SPM and the current values of the constant current sources SN1 to SNM can be made equal. By making the current values of the respective constant current sources equal, the relative accuracy of the current can be increased as compared with the case where the current values of the respective constant current sources are weighted. One advantage of the twelfth embodiment of the present invention is that the value of the current of the positive constant current source and the value of the negative constant current source do not necessarily have to be equal. Accordingly, the circuit of each constant current source can be realized by one FET.
[0081]
In the twelfth embodiment of the present invention, the current values of the constant current sources SP1 to SPM and the current values of the constant current sources SN1 to SNM are equal, but weighting may be performed. By performing weighting, a fractional PLL having a large modulo value can be realized using a small number of constant current sources. Also in this case, it is not necessary to match the value of the current of the positive constant current source with the value of the negative constant current source. Further, since the ratio of the current of each constant current source is an integer ratio, each constant current source can be configured by several FETs or one FET having a different channel width.
[0082]
In the twelfth embodiment of the present invention, the timing for turning on / off the switches QPM and QNM from the switches QP1 and QN1 is generated by a signal whose count value of the counter CT1 is 0, a signal of B, and a second signal f2. And the signal generated when the count value of the counter CT1 is 1, the signal B + 1, and the timing generated by the second signal f2 are switched. More timings may be prepared and switched by adding a signal generated by the second signal f2 and the signal generated by the second signal f2. By increasing the number of timings, it is possible to realize a fractional PLL that uses a small number of constant current sources and modulo a large number.
The thirteenth embodiment
The thirteenth embodiment of the present invention is a signal generator using a fractional PLL in which the value of M is a natural number and the value of modulo is 2M. A signal having a frequency that is a fractional multiple of 2M with respect to the frequency of the reference frequency signal fr is generated. FIG. 26 is a block diagram of a PLL device according to a thirteenth embodiment of the present invention. FIG. 25 shows a block diagram of the phase comparator PD6 in FIG. The phase comparator according to the thirteenth embodiment of the present invention has 2M constant-current sources constituting the charge pump on the positive side and the negative side, and the absolute values of the currents are all equal. The phase comparator PD6 can be realized by connecting a plurality of phase comparators in parallel. However, since there are many common parts such as the counter CT1, the common parts are combined into one.
[0084]
The counter CT1 of the phase comparator PD6 outputs a signal indicating that the count value is equal to 0, 1, B, B + 1. The switches QP1, QN1 switch QPM, QNM respectively output the count value of the counter CT1. Is a signal that is 0 and B, a timing generated by the second signal f2, or a signal in which the count value of the counter CT1 is 1 and a signal that is B + 1, a timing generated by the second signal f2. The on / off operation is performed according to either of them. The timing at which the operation is performed is switched by the switching signals SWP1 to SWPM and SWN1 to SWNM. In the former timing, the period during which the switch for the positive-side constant current source is ON is longer by one clock of the third signal f1 compared to the latter timing, and the switch for the negative-side constant current source is turned on. The ON period is shorter by one clock of the third signal f1. Since the currents of the respective constant current sources are equal, of the 2M constant current sources, the L constant current sources are turned on / off based on the signal in which the count value of the counter CT1 is 1 and the signal in which the count value of the counter CT1 is 1; When the (2M−L) constant current sources are turned on / off based on the signal of which the count value of the counter CT1 is 0 and the signal of which is B, the phase comparator PD6 becomes the period of the third signal f1. On the other hand, it has a phase offset of L / (2M) times.
[0085]
Since the value of the phase offset of the phase comparator PD6 can be changed by the switching signals SWP1 to SWPM and SWN1 to SWNM, the controller CR7 in FIG. By appropriately outputting the values of SWP1 to SWPM and SWN1 to SWNM, a fractional PLL with a modulo value of 2M can be realized.
[0086]
One advantage of the thirteenth embodiment of the present invention is that the current values of the constant current sources SP1 to SPM and the current values of the constant current sources SN1 to SNM can all be made equal. By making the current values of the respective constant current sources equal, the relative accuracy of the current can be increased as compared with the case where the current values of the respective constant current sources are weighted. An advantage of the thirteenth embodiment of the present invention over the twelfth embodiment of the present invention is that the number of modulos can be doubled using the same number of constant current sources. However, in the thirteenth embodiment of the present invention, the absolute values of the current of the positive constant current source and the current of the negative constant current source must be equal.
[0087]
In the thirteenth embodiment of the present invention, the current values of the constant current sources SP1 to SPM and the current values of the constant current sources SN1 to SNM are equal, but weighting may be performed. By performing weighting, a fractional PLL having a large modulo value can be realized using a small number of constant current sources. Also in this case, it is necessary to accurately match the value of the current of the positive constant current source with the value of the negative constant current source.
[0088]
In the thirteenth embodiment of the present invention, the timing for turning on / off the switches QPM and QNM from the switches QP1 and QN1 is generated by a signal having a count value of a counter CT1 of 0, a signal of B, and a second signal f2. And the signal generated when the count value of the counter CT1 is 1, the signal B + 1, and the timing generated by the second signal f2 are switched. More timings may be prepared and switched by adding a signal generated by the second signal f2 and the signal generated by the second signal f2. By increasing the number of timings, it is possible to realize a fractional PLL that uses a small number of constant current sources and modulo a large number.
The fourteenth embodiment
The fourteenth embodiment of the present invention is a signal generator using a fractional PLL in which the value of M is a natural number and the value of modulo is M. A signal having a frequency that is a fraction multiple of the frequency of the reference frequency signal fr with the denominator being M is generated. FIG. 28 is a block diagram of a PLL device according to a fourteenth embodiment of the present invention. FIG. 27 shows a block diagram of the phase comparator PD7 in FIG. The phase comparator according to the fourteenth embodiment of the present invention has M combinations of positive and negative sides of the constant current source constituting the charge pump, and all of the current values are equal. The phase comparator PD7 can be realized by connecting a plurality of phase comparators in parallel. However, since there are many common parts such as the counter CT1, the common parts are combined into one.
[0090]
The counter CT2 divides the voltage-controlled oscillator output signal fv by Y, and outputs signals whose count values are equal to 0 and 1 as signals f2 and f3, respectively, and inputs the signals to the phase comparator PD7. The counter CT1 in the phase comparator PD7 divides the reference frequency signal fr by N, and outputs a signal indicating that the count value is equal to 0, 1, B, B + 1. The switches QP1 and QN1 to the switches QPM and QNM respectively determine the timing generated by the signal whose counter value of the counter CT1 is 0 and the signal B, the timing generated by the signal whose counter value of the counter CT2 is 0, or the count of the counter CT1. The on / off operation is performed in accordance with one of a signal generated by a signal having a value of 0, a signal having a value of B, and a signal having a count value of 1 of the counter CT2. The timing at which the operation is performed is switched by the switching signals SW1 to SWM. In the former timing, the period during which the switch for the positive-side constant current source is ON is longer by one clock of the voltage-controlled oscillator output signal fv, and the switch for the negative-side constant current source is different from the latter timing. Is shorter by one clock of the voltage controlled oscillator output signal fv. Since the currents of the respective constant current sources are equal, of the M sets of constant current sources, the L sets of constant current sources are turned on / off based on the signal whose counter value of the counter CT1 is 1 and the signal whose value is B + 1. Of the (ML) pairs of constant current sources are turned on / off based on the signal of which the count value of the counter CT1 is 0 and the signal of which is B, the phase comparator PD7 outputs the cycle of the voltage-controlled oscillator output signal fv. Has a phase offset of L / M times as long as.
[0091]
Since the value of the phase offset of the phase comparator PD7 can be changed by the switching signals SW1 to SWM, the controller CR8 in FIG. 28 controls the value of the frequency division number Y of the counter CT2 and the switching signals SW1 to SWM every cycle. By outputting the value appropriately, a fractional PLL with a modulo value of M can be realized.
[0092]
An advantage of the fourteenth embodiment of the present invention over the twelfth embodiment of the present invention is that the number of output signals of the counter CT2 for dividing the voltage controlled oscillator output signal fv which may be a high frequency is as small as two. . In the twelfth embodiment of the present invention, the frequency of the voltage controlled oscillator output signal fv is divided by the counter CT1, but the number of output signals is four. Since the timing of these signals requires relative accuracy, it is necessary to synchronize the signals directly obtained from the counter with the voltage controlled oscillator output signal fv or the like. Therefore, a small number of outputs of the counter that divides the voltage-controlled oscillator output signal fv leads to a reduction in circuit size and a reduction in current consumption. However, since the frequency of the reference frequency signal fr is divided, if the frequency of the reference frequency signal fr is not sufficiently high, the period for performing the phase comparison becomes longer, and the phase comparator output Io is output. There are points to consider, such as a longer period.
[0093]
One advantage of the fourteenth embodiment of the present invention is that, like the twelfth embodiment of the present invention, the current values of the constant current sources SP1 to SPM and the current values of the constant current sources SN1 to SNM can be made equal. It is. By making the current values of the respective constant current sources equal, the relative accuracy of the current can be increased as compared with the case where the current values of the respective constant current sources are weighted. One advantage of the fourteenth embodiment of the present invention is that the value of the current of the positive constant current source and the value of the negative constant current source do not always have to be equal. Accordingly, the circuit of each constant current source can be realized by one FET.
[0094]
In the fourteenth embodiment of the present invention, the current values of the constant current sources SP1 to SPM are equal to the current values of the constant current sources SN1 to SNM, but weighting may be performed. By performing weighting, a fractional PLL having a large modulo value can be realized using a small number of constant current sources.
[0095]
In the fourteenth embodiment of the present invention, the timing at which the switches QP1 and QN1 turn on / off the switches QPM and QNM is determined by the timing at which the count value of the counter CT1 is 0 and the count value of the counter CT2 are 0. , A signal having a count value of a counter CT1 of 0 and a signal of B, and a timing generated by a signal having a count value of a counter CT1 of 1. However, more timings are prepared and switched by adding a timing generated by a signal whose counter value of the counter CT1 is 0 and a signal which is B, a timing generated by a signal whose counter value of the counter CT2 is 2, and the like. You may do so. By increasing the number of timings, it is possible to realize a fractional PLL that uses a small number of constant current sources and modulo a large number.
[0096]
In the fourteenth embodiment of the present invention, the on / off timing of the switch for the positive constant current source and the on / off timing of the switch for the negative constant current source are switched as a set. As in the thirteenth embodiment, the timing may be individually switched. By doing so, it is necessary to match the currents of the positive and negative constant current sources. However, it is possible to realize a fractional PLL having a larger number modulo with the same number of constant current sources. it can.
The fifteenth embodiment
The fifteenth embodiment of the present invention is a PLL that generates a signal having a frequency obtained by multiplying the frequency of the reference frequency signal fr by a positive real number X that is not necessarily an integer. FIG. 30 is a block diagram of a PLL according to the fifteenth embodiment of the present invention. FIG. 29 shows a block diagram of the phase comparator PD8 in FIG. In the phase comparator according to the fifteenth embodiment of the present invention, the value of the current of the constant current source constituting the charge pump can be set from outside the phase comparator by the current setting values Ia and Ib of the constant current source. I have. The phase comparator PD8 can be realized by connecting two phase comparators in parallel. However, since there are many common parts such as the counter CT1, the common parts are combined into one.
[0098]
The counter CT1 of the phase comparator PD8 outputs signals indicating that the count value is equal to 0, P, B, B + P. Here, P is a positive integer smaller than NB. The switches Q1 and Q2 perform an on / off operation in accordance with the timing generated by the signal of which the count value of the counter CT1 is 0, the signal of B, and the second signal f2. The switches Q7 and Q8 perform on / off operations in accordance with the timing generated by the signal whose counter value of the counter CT1 is P, the signal whose value is B + P, and the second signal f2. In the former timing, the period during which the switch for the positive-side constant current source is on is longer by the P clock of the third signal f1 compared to the latter timing, and the switch for the negative-side constant current source is turned on. The ON period is shorter by P clocks of the third signal f1. Since the current set values Ia of the constant current sources S1 and S2 and the current set values Ib of the constant current sources S7 and S8 can be externally changed, the phase offset is added to the phase comparator PD8 by the values of the current set values Ia and Ib. Can be provided. The value of the phase offset is a time obtained by multiplying the cycle of the third signal f1 by P × Ib / (Ia + Ib). Therefore, the resolution of the phase offset is determined by the resolution of the current setting values Ia and Ib. A non-integer PLL can be realized by the controller CR9 in FIG. 30 outputting the value of the frequency division number N of the counter CT1 and the current set values Ia and Ib appropriately every cycle.
[0099]
An advantage of the fifteenth embodiment of the present invention is that the resolution of the frequency set value of the voltage controlled oscillator output signal fv can be increased by increasing the set resolution of the current set values Ia and Ib.
○ Sixteenth embodiment
The sixteenth embodiment of the present invention is a PLL that generates a signal having a frequency obtained by multiplying the frequency of the reference frequency signal fr by a positive real number X, which is not necessarily an integer. FIG. 32 is a block diagram of a PLL according to the sixteenth embodiment of the present invention. FIG. 31 shows a block diagram of the phase comparator PD9 in FIG. In the phase comparator according to the sixteenth embodiment of the present invention, the current value of the constant current source constituting the charge pump can be set from the outside of the phase comparator by the current setting values Ia and Ib of the constant current source. I have. The phase comparator PD9 can be realized by connecting two phase comparators in parallel. However, since there are many common parts such as the counter CT1, the common parts are put together.
[0101]
The counter CT1 in the phase comparator PD9 outputs signals indicating that the count value is equal to 0 or B, respectively. The counter CT2 outputs signals indicating that the count value is equal to 0 or 1, respectively. The switches Q1 and Q2 perform on / off operations in accordance with timings generated by a signal having the count value of the counter CT1 being 0 and a signal having a count value of B, and a signal having the count value of the counter CT2 being 0. The switches Q7 and Q8 perform on / off operations in accordance with timings generated by a signal whose counter value of the counter CT1 is 0 and a signal which is B, and a signal whose counter value of the counter CT2 is 1. In the former timing, the period during which the switch for the positive-side constant current source is ON is longer by one clock of the third signal f1 compared to the latter timing, and the switch for the negative-side constant current source is turned on. The ON period is shorter by one clock of the third signal f1. Since the current set values Ia of the constant current sources S1 and S2 and the current set values Ib of the constant current sources S7 and S8 can be externally changed, the phase offset is added to the phase comparator PD8 by the values of the current set values Ia and Ib. Can be provided. The value of the phase offset is a time obtained by multiplying the cycle of the third signal f1 by Ib / (Ia + Ib). Therefore, the resolution of the phase offset is determined by the resolution of the current setting values Ia and Ib. A non-integer PLL can be realized by the controller CR10 in FIG. 32 outputting the value of the frequency division number Y of the counter CT2 and the current set values Ia and Ib appropriately every cycle.
[0102]
An advantage of the sixteenth embodiment of the present invention is that the resolution of the frequency set value of the voltage controlled oscillator output signal fv can be increased by increasing the set resolution of the current set values Ia and Ib.
[0103]
An advantage of the sixteenth embodiment of the present invention over the fifteenth embodiment of the present invention is that the number of output signals of the counter CT2 which divides the voltage controlled oscillator output signal fv which may be a high frequency is as small as two. . In the fifteenth embodiment of the present invention, the frequency of the voltage controlled oscillator output signal fv is divided by the counter CT1, but the number of output signals is four. Since the timing of these signals requires relative accuracy, it is necessary to synchronize the signals directly obtained from the counter with the voltage controlled oscillator output signal fv or the like. Therefore, a small number of outputs of the counter that divides the voltage-controlled oscillator output signal fv leads to a reduction in circuit size and a reduction in current consumption. However, since the frequency of the reference frequency signal fr is divided, if the frequency of the reference frequency signal fr is not sufficiently high, the period for performing the phase comparison becomes longer, and the phase comparator output Io is output. There are points to consider, such as a longer period.
[0104]
In the sixteenth embodiment of the present invention, the signal whose count value is 0 and the signal whose value is 1 are taken out by the counter CT2, but the difference between those count values may not be 1 and other natural numbers may be used. It may be.
○ Seventeenth embodiment
The seventeenth embodiment of the present invention is a PLL for generating a signal having a frequency obtained by multiplying the frequency of the reference frequency signal fr by a positive real number X which is not necessarily an integer. FIG. 34 is a block diagram of a PLL according to the seventeenth embodiment of the present invention. FIG. 33 shows a block diagram of the phase comparator PD10 in FIG. In the phase comparator according to the seventeenth embodiment of the present invention, the current values of the constant current sources S1 and S2 constituting the charge pump can be set from outside the phase comparator by the current setting values Ic and Id of the constant current sources. It has become. The constant current sources S3 and S4 operate when the phases are greatly shifted.
[00106]
The counter CT1 in the phase comparator PD10 outputs signals indicating that the count value is equal to 0 and P, respectively. Here, P is an integer of 2 or more. When the second signal f2 rises between the time when the count value of the counter CT1 becomes 0 and the time when the count value becomes P, the time until the second signal f2 rises after the count value of the counter CT1 becomes 0 The switch Q2 is turned on only during the period of, and the switch Q1 is turned on only during the period from when the second signal f2 rises to when the count value of the counter CT1 becomes P. Therefore, the phase offset in the phase comparator PD10 is a time obtained by multiplying the cycle of the third signal f1 by P × Id / (Ic + Id). That is, a desired phase offset can be provided by appropriately setting the ratio of the current set values Ic and Id of the constant current source, and the resolution of the phase offset is determined by the resolution of the current set values Ic and Id. A non-integer PLL can be realized by the controller CR11 in FIG. 34 outputting the value of the frequency division number N of the counter CT1 and the current set values Ic, Id appropriately in each cycle.
[00107]
An advantage of the seventeenth embodiment of the present invention over the fifteenth embodiment of the present invention is that the number of constant current sources for which the value of the current has to be set by a signal from outside the phase comparator is small. However, in the seventeenth embodiment of the present invention, since the irregularity of the delay time in the internal circuit affects the accuracy of the phase offset, it is used in the case where the irregularity of the delay time does not cause a problem. In such a case, it is necessary to consider a method of compensating for the irregularity of the delay time in some way. As means for compensating for the irregularity of the delay time in the internal circuit, there are provided two sets such that the time difference between the phase offsets becomes equal to one cycle of the third signal f1 using the method of the sixth embodiment of the present invention. There is a method of calculating the current set values Ic and Id of the constant current source and calculating the current set values Ic and Id for a desired phase offset by primary interpolation.
[00108]
As described above, by using the present invention, a phase comparator having no zero-cross distortion can be realized, and by applying the same, the phase comparator can have a phase offset with high accuracy. Thus, a PLL that performs a non-integer operation such as a fractional PLL can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram of a phase comparator according to a first embodiment of the present invention.
FIG. 2 shows an example of a signal waveform according to the first embodiment of the present invention.
FIG. 3 shows an example of a signal waveform according to the first embodiment of the present invention.
FIG. 4 is a block diagram of a phase comparator according to a second embodiment of the present invention.
FIG. 5 shows an example of a signal waveform according to the second embodiment of the present invention.
FIG. 6 is a block diagram of a PLL device according to a third embodiment of the present invention.
FIG. 7 is a block diagram of a PLL device according to a fourth embodiment of the present invention.
FIG. 8 is a block diagram of a phase comparator according to a fifth embodiment of the present invention.
FIG. 9 is a block diagram of a PLL device according to a fifth embodiment of the present invention.
FIG. 10 is a table showing a phase offset according to the sixth embodiment of the present invention;
FIG. 11 is a block diagram of a PLL device according to a sixth embodiment of the present invention.
FIG. 12 is a table of a phase offset according to the seventh embodiment of the present invention.
FIG. 13 is a block diagram of a phase comparator according to an eighth embodiment of the present invention.
FIG. 14 is a block diagram of a PLL device according to an eighth embodiment of the present invention.
FIG. 15 is a block diagram of a phase comparator according to a ninth embodiment of the present invention.
FIG. 16 is a block diagram of a PLL device according to a ninth embodiment of the present invention.
FIG. 17 is a table showing a phase offset according to the ninth embodiment of the present invention;
FIG. 18 is a block diagram of a phase comparator according to a tenth embodiment of the present invention.
FIG. 19 is a block diagram of a PLL device according to a tenth embodiment of the present invention.
FIG. 20 is a block diagram of a phase comparator according to an eleventh embodiment of the present invention.
FIG. 21 is a block diagram of a PLL device according to an eleventh embodiment of the present invention.
FIG. 22 is a table showing a phase offset according to the eleventh embodiment of the present invention;
FIG. 23 is a block diagram of a phase comparator according to a twelfth embodiment of the present invention.
FIG. 24 is a block diagram of a PLL device according to a twelfth embodiment of the present invention.
FIG. 25 is a block diagram of a phase comparator according to a thirteenth embodiment of the present invention.
FIG. 26 is a block diagram of a PLL device according to a thirteenth embodiment of the present invention.
FIG. 27 is a block diagram of a phase comparator according to a fourteenth embodiment of the present invention.
FIG. 28 is a block diagram of a PLL device according to a fourteenth embodiment of the present invention.
FIG. 29 is a block diagram of a phase comparator according to a fifteenth embodiment of the present invention.
FIG. 30 is a block diagram of a PLL device according to a fifteenth embodiment of the present invention.
FIG. 31 is a block diagram of a phase comparator according to a sixteenth embodiment of the present invention.
FIG. 32 is a block diagram of a PLL device according to a sixteenth embodiment of the present invention.
FIG. 33 is a block diagram of a phase comparator according to a seventeenth embodiment of the present invention.
FIG. 34 is a block diagram of a PLL device according to a seventeenth embodiment of the present invention.
FIG. 35 is an example of a block diagram of a conventional phase comparator.
FIG. 36 shows an example of input / output characteristics of a conventional phase comparator.
[Explanation of symbols]
f1... third signal
f2... a signal giving a second signal or a fourth phase of the second signal
f3... a signal giving a fifth phase of the second signal
fr: Reference frequency signal
fv ···· Voltage controlled oscillator output signal
A, B, C, D, E, P: integer, used for comparison with the count value of counter CT1 or counter CT2
AD: Adjuster
CP: Compensator
CR1, CR2, CR3, CR4, CR5, CR6: Controller CR7, CR8, CR9, CR10, CR11, CR12, CR13: Controller
CT1, CT2 ····· Counter
EOC: One-cycle end signal
I1, I2, I3, I4, I7, I8... S1, S2, S3, S4, S7, S8 output current
Ia, Ib, Ic, Id: current set value of constant current source
Io ... Phase comparator output
N: Number of divisions of counter CT1
PD1, PD2, PD3, PD4, PD5, PD6 ... Phase comparator
PD7, PD8, PD9, PD10, PD11, PD12 ... Phase comparator
Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8 ... switch
QP1, QPM, QN1, QNM ... switch
S1, S2, S3, S4, S5, S6, S7, S8 ... constant current source
SP1, SPM, SN1, SNM ... Constant current source
SW1, SWM ... switching signal
SWP1, SWPM, SWN1, SWNM... Switching signal
VCO ··· Voltage controlled oscillator
X: Frequency setting value, not necessarily an integer
Y: Number of divisions of counter CT2
91... A signal indicating a first phase of the first signal
92... A signal indicating that the count value of the counter CT1 is zero
93... A signal indicating the second phase of the first signal

Claims (24)

A phase comparator for comparing the phase of the first signal with the phase of the second signal, a means for detecting that the first signal has reached the first phase, and the means for detecting that the first signal has reached the second phase Means for detecting that the second signal has reached the third phase, and means for detecting that the first signal has reached the first phase. When the second signal reaches the third phase before reaching the second phase, the output of the phase comparator indicates that the second signal has reached the third phase after the first signal has reached the first phase. And outputs a signal of a second value until the second signal reaches the third phase and then outputs a signal of the second value until the first input reaches the second phase. In other periods, a signal having a value of zero is output, and the time from when the first signal reaches the second phase to when the first signal reaches the first phase is output. Zero cross distortion-free phase comparator using a multi-phase signal, wherein the non-B. 2. The phase comparator according to claim 1, wherein the first phase of the first signal is not equal to the second phase, and the first signal is shifted to the first phase after the first signal reaches the second phase. When the second signal reaches the third phase while the second signal reaches the third phase, the phase comparison is performed until the second signal reaches the third phase and then the first signal reaches the first phase. The output of the phase comparator outputs a signal of a third value, or the output of the phase comparator is from when the first signal reaches the second phase until the second signal reaches the third signal. A zero-cross distortion-free phase comparator which outputs a signal of a fourth value. 3. A signal obtained by inverting the output signal of the phase comparator according to claim 1 or 2 when the average of the output signal of the phase comparator is zero is superimposed on the output of the phase comparator. A phase comparator free of zero-cross distortion. 4. A PLL control method in a PLL device comprising the phase comparator according to claim 1 or claim 2 and a voltage-controlled oscillator, and having a reference frequency signal as an input signal, wherein a first signal is a reference frequency signal. Wherein the second signal is a signal related to an output signal of the voltage controlled oscillator, and wherein the second signal is a signal related to an output signal of the voltage controlled oscillator. 4. A PLL control method in a PLL device comprising the phase comparator according to claim 1 or claim 2 and a voltage-controlled oscillator, and having a reference frequency signal as an input signal. Wherein the second signal is a signal related to the reference frequency signal and the second signal is a signal related to the reference frequency signal. 4. The phase comparator according to claim 1, wherein the first signal is a signal obtained by dividing a third signal by a first counter, and wherein the first signal is a first signal. The detection of the event that has reached the phase is performed by detecting that the value of the first counter has reached the first count value, and the detection of the event that the first signal has reached the second phase is performed by the first counter. A zero-cross distortion-free phase comparator, which is performed by detecting that a value of a counter has reached a second count value. A PLL control method in a PLL device having the phase comparator and the voltage controlled oscillator according to claim 6 and having a reference frequency signal as an input signal, wherein a first signal is a signal related to an output signal of the voltage controlled oscillator, A second signal is a signal related to the reference frequency signal, a ratio between a first value and a second value in the output signal of the phase comparator is a predetermined value, and the frequency division number of the first counter and The phase offset of the phase comparator is sequentially changed by sequentially changing a first count value and a second count value with respect to a preset value as needed, thereby realizing a fractional PLL operation. PLL control method using a zero-cross distortion-free phase comparator. A phase comparator for comparing the phase of the first signal with the phase of the second signal, a means for detecting that the first signal has reached the first phase, and the means for detecting that the first signal has reached the second phase And a means for detecting that the second signal has reached the third phase, and a means for detecting that the second signal has reached the fourth phase. When the first signal reaches the third phase and the first signal reaches the first phase after the first phase is reached and before the first signal reaches the second phase. When the second signal does not reach the fourth phase between the second signal and the third phase, or when the second signal reaches the third phase. From when the first signal reaches the first phase and the second signal reaches the third phase until the second signal reaches the fourth phase. If the first signal does not reach the second phase before the first signal reaches the first phase, the output of the phase comparator indicates that the first signal is the first signal. After reaching the phase and before the second signal reaches the fourth phase, the signal of the first value is superimposed on the output, and after the second signal reaches the third phase, the first input is A second value signal is superimposed on the output until the second phase is reached, and a signal of a zero value is output in other periods, and the first phase and the second phase of the first signal are not equal. , The third phase and the fourth phase of the second signal are not equal, and the time from when the first signal reaches the second phase until it reaches the first phase is not zero, and the second signal Wherein the time from when the signal reaches the fourth phase to when the signal reaches the third phase is not zero. 9. A PLL control method in a PLL device having the phase comparator and the voltage controlled oscillator according to claim 8 and having a reference frequency signal as an input signal, wherein a first signal is a signal related to the reference frequency signal, A signal is a signal related to an output signal of the voltage controlled oscillator, a ratio of a first value and a second value in the output signal of the phase comparator is a predetermined value, and a second signal is output from the phase comparator. Is generated by dividing the fourth signal by the second counter. When the second signal reaches the third phase, the value of the second counter becomes equal to the third count value. Is detected by detecting that the second signal has reached the fourth phase by detecting that the value of the second counter has become equal to the fourth count value. The division number of the counter and the third Zero-cross distortion-free, characterized in that a numerical value and a fourth count value are sequentially changed with respect to a preset value as needed, thereby sequentially changing a phase offset of the phase comparator to realize a fractional PLL operation. A PLL control method using a phase comparator. 10. The PLL control method according to claim 7, wherein a ratio between a first value and a second value in the output signal of the phase comparator is 1: 1, so that 2 is a modulo PLL. A PLL control method using a zero-cross distortion-free phase comparator characterized by realizing an operation. 10. The fractional PLL control method according to claim 7, wherein the ratio of the first value to the second value at the output of the phase comparator is 3 to -5 or 5 to -3, and the modulo value is A PLL control method using a zero-cross distortion-free phase comparator, wherein a fractional PLL operation of 8 is realized. 10. The fractional PLL control method according to claim 7, wherein the ratio of the first value to the second value at the output of the phase comparator is 7: −9 or 9: −7, and the modulo value is: A PLL control method using a zero-cross distortion-free phase comparator, wherein a fractional PLL operation of 16 is realized. In the PLL control system for performing a fractional PLL operation according to claim 7, claim 9, claim 10, claim 11, or claim 12, a ratio between a first value and a second value at the output of the phase comparator is determined. Means for adjusting, and means for detecting an amount related to an average value of the output of the phase comparator over one cycle, and a first count value and a second count value which are equivalent to each other while causing the PLL device to perform an integer PLL operation. It has a function of alternately setting different combinations of the count values, and calibrating the ratio of the first value and the second value in the output of the phase comparator based on the signal of the detected amount at that time. Characteristic PLL control method. In the PLL control system for performing a fractional PLL operation according to claim 7, claim 9, claim 10, claim 11, or claim 12, a ratio between a first value and a second value at the output of the phase comparator is determined. Means for adjusting; means for detecting an amount related to an average value of the output of the phase comparator over one period; and a first product of an inner product of the detected amount and a pre-calculated pattern being an integral multiple of a modulo value. PLL control having means for taking over the period of a signal and having a function of calibrating a ratio between a first value and a second value at the output of the phase comparator based on the value of the inner product or the sign of the value of the inner product method. In the PLL control method, the time from when the value of the first counter reaches the fifth count value to when the value of the first counter reaches the sixth count value is different from the PLL control method according to claim 7. In the meantime, when the second signal reaches the third phase, the time between when the value of the first counter reaches the fifth count value and when the second signal reaches the third phase, A means for superimposing a certain value on the output of the phase comparator, or a means for superimposing a value from the first counter to the fifth count value until the first counter value to the sixth count value. When the second signal reaches the third phase, the phase comparator detects the time from when the second signal reaches the third phase until the value of the first counter reaches the sixth count value. Adding one or more means to superimpose a certain value on the output of PLL control method characterized. 10. The PLL control method according to claim 9, wherein the phase of the first signal reaches a second phase after the second signal reaches a seventh count value with respect to the PLL control method according to claim 9. Means for superimposing a value on the output of the comparator, or the phase comparator from when the first signal reaches the first phase until the value of the second counter reaches the seventh count value. A PLL control method characterized by adding one or more of means for superimposing a certain value on the output of the above, or one of these two kinds of means. 17. The PLL control method according to claim 15, wherein a first value, a second value, and a value of one or more signals superimposed on the phase comparator are output from the phase comparator. the value of the total of three or more signals is, when the number of the signals is n, the ratio of the absolute value of these signals, 2 ^0, 2 ^0, 2 ^1,. . . , 2 ^n-2 , a PLL control method using a zero-cross distortion-free phase comparator. A PLL control system for realizing a fractional PLL operation, comprising: M phase comparators according to claim 1, means for synthesizing output signals of the phase comparators, and a voltage controlled oscillator, wherein a reference frequency signal is input to an input signal. And the first signal is a signal related to the reference frequency signal, the second signal is a signal obtained by dividing the output signal of the voltage controlled oscillator, and the third signal of the second signal for each of the phase comparators Of the output signal of the voltage controlled oscillator are different from each other in the fifth phase and the sixth phase, and the M phase comparators are provided as necessary. Applying a fifth phase as a third phase to a required number of the phase comparators, and applying a sixth phase as a third phase to the remaining phase comparators Zero cross distortion free PLL control method using a phase comparator. A PLL control system for realizing a fractional PLL operation, comprising: M phase comparators according to claim 6, means for synthesizing output signals of the M phase comparators, and a voltage-controlled oscillator, wherein a reference frequency signal is output. The first signal is a signal related to the output signal of the voltage controlled oscillator, the second signal is a signal related to the reference frequency signal, and a first signal of the first signal for each of the phase comparators. Of the output signal of the voltage controlled oscillator are shifted from each other by a P period (P is a natural number), and a first signal to each of the phase comparators is provided. Are two types, a ninth phase and a tenth phase, which are phases shifted from each other by P periods of the output signal of the voltage-controlled oscillator, and the M phase comparators are sequentially provided as necessary. Some of the The seventh phase is applied as the first phase to the phase comparator, the ninth phase is applied as the second phase, and the eighth phase is applied as the first phase to the remaining phase comparators. And a tenth phase as a second phase, and the M phase comparators and a means for synthesizing the output signals of the M phase comparators. A PLL control method using a zero-cross distortion-free phase comparator, wherein a fractional PLL operation is realized by sequentially changing a phase offset. A PLL control method for realizing a fractional PLL operation, comprising: M phase comparators according to claim 6, means for synthesizing output signals of the M phase comparators, and a voltage controlled oscillator, A reference frequency signal as an input signal, a first signal as a signal relating to the output signal of the voltage controlled oscillator, a second signal as a signal relating to the reference frequency signal, and a first signal for each of the phase comparators. The first phase of the signal is two types of a seventh phase and an eighth phase, which are phases shifted from each other by P period (P is a natural number) of the output signal of the voltage controlled oscillator. The second phase of the first signal is set to two types, that is, a ninth phase and a tenth phase, which are phases shifted from each other by P periods of the output signal of the voltage controlled oscillator. Of the phase comparator Applying a seventh phase as a first phase to some of the phase comparators, applying an eighth phase as a first phase to the remaining phase comparators, Applying a ninth phase as a second phase to some of the phase comparators, and applying a tenth phase as a second phase to the remaining phase comparators A fractional PLL operation is realized by sequentially changing the phase offset of one phase comparator comprising M number of the phase comparators and means for synthesizing output signals of the M number of the phase comparators. A PLL control method using a zero-cross distortion-free phase comparator. 7. A PLL control method for realizing a fractional PLL operation, comprising: a first phase comparator, a second phase comparator, and a first phase comparator and a second phase comparator according to claim 6. Means for synthesizing the output signal and a voltage controlled oscillator, having a reference frequency signal as an input signal, and for the first phase comparator and the second phase comparator, converting the first signal into the reference frequency signal. The second signal is a signal related to the output signal of the voltage controlled oscillator, and the third phase of the second signal to the first phase comparator and the second phase comparator is set to the voltage controlled oscillator. Of the output signal of the first phase comparator while maintaining the ratio between the first value and the second value of the output signal of the first phase comparator. Means for changing the first value and the second value; Means for changing the first value and the second value of the output signal of the second phase comparator while maintaining the ratio of the first value to the second value of the force signal; By sequentially setting the ratio of the first value of the output signal to the first value of the output signal of the second phase comparator to a required value, the first phase comparator, the second phase comparator, It is characterized in that the phase offset of one phase comparator comprising means for synthesizing the output signals of the first phase comparator and the second phase comparator is sequentially changed to realize a non-integer PLL operation. A PLL control method using a zero-cross distortion-free phase comparator. In a PLL control method for realizing a fractional PLL operation, the output signals of the third and fourth phase comparators according to claim 6 and the output signals of the third and fourth phase comparators are provided. Means for combining, a voltage controlled oscillator, a reference frequency signal as an input signal, and for a third phase comparator and a fourth phase comparator, a first signal related to an output signal of the voltage controlled oscillator. Signals, the second signal is a signal related to the reference frequency signal, and the first phase of the first signal for each of the phase comparators is changed from the eleventh phase and the eleventh phase to the voltage-controlled oscillator. A twelfth phase, which is a phase delayed by P periods (P is a natural number) of the output signal, and a second phase of the first signal for each of the phase comparators is calculated from a thirteenth phase and a thirteenth phase. Output signal of voltage controlled oscillator The fourteenth phase, which is a phase delayed by P periods, is the first phase of the output signal of the third phase comparator while maintaining the ratio between the first value and the second value of the output signal of the third phase comparator. Means for changing the first and second values of the output signal of the fourth phase comparator while maintaining a ratio of the first and second values of the output signal of the fourth phase comparator. And means for changing the second value, and the ratio of the first value of the output signal of the third phase comparator to the first value of the output signal of the fourth phase comparator is sequentially set to a required value. By doing so, a third phase comparator, a fourth phase comparator, and a means for combining the output signals of the third phase comparator and the phase comparator of the fourth phase comparator are combined. A PLL control using a zero-cross distortion-free phase comparator characterized by realizing a non-integer PLL operation by sequentially changing a phase offset. Formula. 7. The phase comparator according to claim 6, wherein the first value and the second value in the output of the phase comparator can be externally set at any time, and the ratio between the first value and the second value is changed. A zero-cross distortion-free phase comparator having a function of changing a phase offset of the phase comparator. A PLL control method using a zero-cross distortion-free phase comparator, wherein a non-integer PLL operation is realized by using the phase comparator according to claim 21.

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