JP2002026135A - Manufacturing method for capacitor of semiconductor element - Google Patents
Manufacturing method for capacitor of semiconductor elementInfo
- Publication number
- JP2002026135A JP2002026135A JP2001193423A JP2001193423A JP2002026135A JP 2002026135 A JP2002026135 A JP 2002026135A JP 2001193423 A JP2001193423 A JP 2001193423A JP 2001193423 A JP2001193423 A JP 2001193423A JP 2002026135 A JP2002026135 A JP 2002026135A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer
- forming
- oxide film
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 33
- 238000001039 wet etching Methods 0.000 claims abstract description 22
- 238000001312 dry etching Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 8
- 239000002019 doping agent Substances 0.000 claims description 7
- 239000000243 solution Substances 0.000 claims description 6
- 239000011259 mixed solution Substances 0.000 claims description 4
- 229910017855 NH 4 F Inorganic materials 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 230000007423 decrease Effects 0.000 claims description 3
- 229910052733 gallium Inorganic materials 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 230000003247 decreasing effect Effects 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- UOACKFBJUYNSLK-XRKIENNPSA-N Estradiol Cypionate Chemical compound O([C@H]1CC[C@H]2[C@H]3[C@@H](C4=CC=C(O)C=C4CC3)CC[C@@]21C)C(=O)CCC1CCCC1 UOACKFBJUYNSLK-XRKIENNPSA-N 0.000 claims 1
- 230000002950 deficient Effects 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000002265 prevention Effects 0.000 description 3
- 229910008486 TiSix Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000001878 scanning electron micrograph Methods 0.000 description 2
- 229910004491 TaAlN Inorganic materials 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- 229910008482 TiSiN Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Inorganic Chemistry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明が属する技術分野】本発明は、半導体素子のキャ
パシタ製造方法に関し、特に、所定の構造が形成された
半導体基板上部にシード層を形成し、下部膜から上部膜
に行くにつれてウェットエッチング率が低くなる多重層
の酸化膜を形成した後、これらをドライエッチングして
シード層の所定の部分を露出させる第１開口部を形成
し、第１開口部の側面に露出された多重層酸化膜をウェ
ットエッチングして、第１開口部の幅を拡張させつつ、
入口より下部面積が広い第２開口部を形成し、第２開口
部の底面に露出されたシード層上にＥＣＤ（Ｅｌｅｃｔ
ｒｏ−Ｃｈｅｍｉｃａｌ Ｄｅｐｏｓｉｔｉｏｎ）方法
で下部電極を形成することによって、素子の電気的特性
を向上させることのできる半導体素子のキャパシタ製造
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and more particularly, to a method for forming a seed layer on a semiconductor substrate on which a predetermined structure is formed. After forming the multi-layer oxide films to be lowered, these are dry-etched to form a first opening exposing a predetermined portion of the seed layer, and the multi-layer oxide film exposed on the side surface of the first opening is formed. By wet etching, while expanding the width of the first opening,
A second opening having a lower area than the entrance is formed, and an ECD (Elect) is formed on the seed layer exposed at the bottom of the second opening.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, which can improve electrical characteristics of a device by forming a lower electrode by a ro-chemical deposition method.
【０００２】[0002]
【従来の技術】近年、半導体素子の高集積化に伴ってキ
ャパシタ製造工程でサイズを縮小し、静電容量（ｃａｐ
ａｃｉｔａｎｃｅ）を向上させるために、ＥＣＤ方法に
よりＰｔ膜を形成して下部電極に利用する。このために
は、所定の下部構造が形成された半導体基板上部にＰｔ
シード層を形成し、その上部にＰｔシード層を選択的に
露出させる開口部を有する酸化膜パターンを形成した
後、ＥＣＤ方法で開口部の底面のＰｔシード層上にＰｔ
膜を蒸着する。2. Description of the Related Art In recent years, as semiconductor devices have become more highly integrated, the size has been reduced in the capacitor manufacturing process and the capacitance (cap) has been reduced.
In order to improve the activity, a Pt film is formed by an ECD method and used as a lower electrode. For this purpose, a Pt is formed on the semiconductor substrate on which a predetermined lower structure is formed.
A seed layer is formed, and an oxide film pattern having an opening for selectively exposing the Pt seed layer is formed thereon. Then, Pt is formed on the Pt seed layer on the bottom surface of the opening by an ECD method.
Deposit the film.
【０００３】この場合、ドライエッチングにより形成さ
れた酸化膜パターン内の開口部のプロファイル（ｐｒｏ
ｆｉｌｅ）が下部電極のプロファイルを決定することと
なるが、一般的に酸化膜のドライエッチングによる開口
部のプロファイルは、上部より下部の幅が小さくなる。
これによって、図１に示すように、下部電極の下の部分
が上の部分よりその幅が小さく形成されて、以後の誘電
膜蒸着及び上部電極の蒸着工程でステップカバレッジの
不良により素子の電気的特性を低下させるという問題が
あった。In this case, a profile (pro) of an opening in an oxide film pattern formed by dry etching is used.
file) determines the profile of the lower electrode. Generally, the profile of the opening formed by dry etching of the oxide film has a smaller width at the lower portion than at the upper portion.
As a result, as shown in FIG. 1, the lower portion of the lower electrode is formed to have a smaller width than the upper portion. There has been a problem of deteriorating characteristics.
【０００４】[0004]
【発明が解決しようとする課題】そこで、本発明は上記
従来の半導体素子のキャパシタ製造方法における問題点
に鑑みてなされたものであって、本発明の目的は、キャ
パシタ下部電極上に蒸着される誘電膜及び上部電極のス
テップカバレッジの不良を防止し得る半導体素子のキャ
パシタ製造方法を提供することにある。SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above-mentioned problems in the conventional method of manufacturing a capacitor for a semiconductor device, and an object of the present invention is to deposit a film on a capacitor lower electrode. An object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor device, which can prevent a step coverage of a dielectric film and an upper electrode from being defective.
【０００５】[0005]
【課題を解決するための手段】上記目的を達成するため
になされた、本発明による半導体素子のキャパシタ製造
方法は、半導体基板上部にシード（ｓｅｅｄ）層を形成
する第１ステップと、前記シード層上に下部層から上部
層へ行くに従いウェットエッチング率が小さくなる多重
層酸化膜を形成する第２ステップと、前記多重層酸化膜
を選択的にドライエッチングしてその底面に前記シード
層を露出させる第１開口部を形成する第３ステップと、
前記第１開口部側面に露出された前記多重層酸化膜をウ
ェットエッチングして前記第１開口部の幅を拡張させつ
つ下部の幅が上部の幅より広い第２開口部を形成する第
４ステップと、ＥＣＤ（Ｅｌｅｃｔｒｏ−Ｃｈｅｍｉｃ
ａｌ Ｄｅｐｏｓｉｔｉｏｎ）方法により前記第２開口
部底面の前記シード層上に前記第２開口部と同じ形状の
下部電極を形成する第５ステップと、前記多重層酸化膜
をウェットエッチングにより除去してその下部の前記シ
ード層を露出させる第６ステップと、前記露出されたシ
ード層をドライエッチングにより除去する第７ステップ
と、前記下部電極上に誘電膜を形成する第８ステップ
と、前記誘電膜上に上部電極を形成する第９ステップと
を含むことを特徴とする。According to a first aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, comprising the steps of: forming a seed layer on a semiconductor substrate; A second step of forming a multilayer oxide film having a lower wet etching rate from the lower layer to the upper layer, and selectively dry-etching the multilayer oxide film to expose the seed layer on its bottom surface A third step of forming a first opening;
A fourth step of forming a second opening having a lower width larger than an upper width while expanding the width of the first opening by wet etching the multilayer oxide film exposed on the side surface of the first opening; And ECD (Electro-Chemic)
a fifth step of forming a lower electrode having the same shape as that of the second opening on the seed layer on the bottom surface of the second opening by an al deposition method, and removing the lower part of the multi-layer oxide film by wet etching. A sixth step of exposing the seed layer, a seventh step of removing the exposed seed layer by dry etching, an eighth step of forming a dielectric film on the lower electrode, and an upper part on the dielectric film. A ninth step of forming an electrode.
【０００６】[0006]
【発明の実施の形態】次に、本発明による半導体素子の
キャパシタ製造方法の実施の形態の具体例を図面を参照
しながら説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a specific example of an embodiment of a method for manufacturing a capacitor of a semiconductor device according to the present invention will be described with reference to the drawings.
【０００７】まず、図２を参照すると、所定の構造が形
成された半導体基板１１上部に絶縁膜１２及び反射防止
膜１３を形成する。反射防止膜１３は、絶縁膜１２に対
してエッチング選択比の高い物質により形成する。本発
明の実施例では、絶縁膜１２は、酸化膜により形成し、
反射防止膜１３は、酸化窒化膜（ＳｉＯＮ）により形成
する。First, referring to FIG. 2, an insulating film 12 and an antireflection film 13 are formed on a semiconductor substrate 11 on which a predetermined structure is formed. The antireflection film 13 is formed of a material having a high etching selectivity with respect to the insulating film 12. In the embodiment of the present invention, the insulating film 12 is formed by an oxide film,
The antireflection film 13 is formed of an oxynitride film (SiON).
【０００８】次いで、反射防止膜１３及び絶縁膜１２を
選択的にエッチングして半導体基板１１の所定の領域を
露出させるコンタクト孔を形成する。次に、コンタクト
孔形成が完了した全体構造上部に、ポリシリコン膜を５
００Å乃至３０００Åの厚さに形成し、反射防止膜１３
上部面の高さから５００Å乃至２０００Åの深さのコン
タクト孔内にポリシリコン膜が残留するように、全面エ
ッチング工程を実施してポリシリコンプラグ１４を形成
する。Next, a contact hole exposing a predetermined region of the semiconductor substrate 11 is formed by selectively etching the antireflection film 13 and the insulating film 12. Next, a polysilicon film is formed on the entire structure on which the contact holes have been formed.
The anti-reflection film 13 is formed to a thickness of
The entire surface is etched to form a polysilicon plug 14 so that the polysilicon film remains in the contact hole having a depth of 500 to 2000 degrees from the height of the upper surface.
【０００９】次いで、ポリシリコンプラグ１４形成が完
了した全体構造上に、Ｔｉ膜を１００Å乃至３００Åの
厚さに形成した後、急速熱処理工程を実施して、コンタ
クト孔内のポリシリコンプラグ１４とＴｉ膜とを反応さ
せることによって、ＴｉＳｉｘ膜１５を形成した後、反
射防止膜１３上部に残留する未反応Ｔｉ膜をウェットエ
ッチングにより除去する。Next, after a Ti film is formed to a thickness of 100 to 300 mm on the entire structure where the formation of the polysilicon plug 14 is completed, a rapid heat treatment process is performed to form the polysilicon plug 14 and the Ti in the contact hole. After the TiSix film 15 is formed by reacting with the film, the unreacted Ti film remaining on the antireflection film 13 is removed by wet etching.
【００１０】次いで、コンタクト孔が完全に埋め込まれ
るように、全体構造上部に拡散防止膜１６を形成する。
拡散防止膜１６は、ＴｉＮ膜、ＴｉＳｉＮ膜、ＴｉＡｌ
Ｎ膜、ＴａＳｉＮ膜、ＴａＡｌＮ膜の内のいずれか一つ
で形成する。拡散防止膜１６を形成した後、反射防止膜
１３が露出されるまで、ＣＭＰ（ＣｈｅｍｉｃａｌＭｅ
ｃｈａｎｉｃａｌ Ｐｏｌｉｓｈｉｎｇ）工程を実施し
てコンタクト孔内部のみに拡散防止膜１６が存在するよ
うにする。Next, a diffusion preventing film 16 is formed on the entire structure so that the contact hole is completely buried.
The diffusion prevention film 16 is made of TiN film, TiSiN film, TiAl
It is formed of any one of an N film, a TaSiN film, and a TaAlN film. After forming the anti-diffusion film 16, until the anti-reflection film 13 is exposed, CMP (Chemical Me
(Chemical Polishing) process so that the diffusion barrier film 16 exists only inside the contact hole.
【００１１】次いで、反射防止膜１３及び拡散防止膜１
６上に、Ｐｔ膜形成用シード層（ｓｅｅｄ ｌａｙｅ
ｒ）１７を形成する。シード層１７は、５０Å乃至１０
００Åの厚さに形成し、Ｐｔ膜、Ｒｕ膜、Ｉｒ膜、Ｏｓ
膜、Ｗ膜、Ｍｏ膜、Ｃｏ膜、Ｎｉ膜、Ａｕ膜、及びＡｇ
膜の内のいずれか一つで形成する。Next, the antireflection film 13 and the diffusion prevention film 1
6, a seed layer for forming a Pt film (seed layer)
r) Form 17 The seed layer 17 has a thickness of 50 ° to 10 °.
Pt film, Ru film, Ir film, Os
Film, W film, Mo film, Co film, Ni film, Au film, and Ag
It is formed of any one of the films.
【００１２】次に、図３に示すように、シード層１７上
に第１酸化膜１８及び第２酸化膜１９を順に形成する。
本発明の実施例では酸化膜を二重に形成したが、二重層
以上の多重層酸化膜に形成することもできる。Next, as shown in FIG. 3, a first oxide film 18 and a second oxide film 19 are sequentially formed on the seed layer 17.
In the embodiment of the present invention, the oxide film is formed as a double layer. However, the oxide film may be formed as a multilayer oxide film having two or more layers.
【００１３】多重層酸化膜の各層は、同一エッチング剤
に対するウェットエッチング率が下部から上部に行くに
つれて小さくなるように形成する。すなわち、本発明の
実施例でのように、二重層の酸化膜を形成する場合、第
１酸化膜１８のエッチング率が第２酸化膜１９のエッチ
ング率より高くなるように形成する。Each layer of the multi-layer oxide film is formed such that the wet etching rate with respect to the same etching agent decreases from the bottom to the top. That is, when forming a double-layer oxide film as in the embodiment of the present invention, the first oxide film 18 is formed such that the etching rate is higher than that of the second oxide film 19.
【００１４】下部から上部に行くにつれてエッチング率
が小さくなるようにするためには、多重層酸化膜の各層
に添加されるドーパントの濃度を順次、減少させなが
ら、多重層の酸化膜を形成するか、各層の酸化膜に同一
ドーパントを同一濃度で添加して形成する場合、下部か
ら上部に行くにつれて蒸着温度を順次、増加させて形成
する。多重層の酸化膜を形成するためのドーパントに
は、Ｂ、Ｐ、Ａｓ、Ｇａの内の少なくともいずれか一つ
を同時に添加する。本発明の実施例では、多重層酸化膜
の総厚さは５００Å乃至２００００Åとなるようにす
る。In order to decrease the etching rate from the lower part to the upper part, it is necessary to form the multi-layer oxide film while sequentially decreasing the concentration of the dopant added to each layer of the multi-layer oxide film. When the same dopant is added to the oxide film of each layer at the same concentration, the deposition temperature is sequentially increased from the lower part to the upper part. At least one of B, P, As, and Ga is simultaneously added to the dopant for forming the multi-layer oxide film. In an embodiment of the present invention, the total thickness of the multi-layer oxide film is in the range of 500 to 20,000.
【００１５】次いで、ドライエッチング方法で第２酸化
膜１９及び第１酸化膜１８を選択的にエッチングして、
シード層１７を露出させる第１開口部３１を形成する。Next, the second oxide film 19 and the first oxide film 18 are selectively etched by a dry etching method,
A first opening 31 exposing the seed layer 17 is formed.
【００１６】次に、図４に示すように、ウェット工程を
実施してウェットエッチング率の高い第１酸化膜１８が
第２酸化膜１９に比べてより多くエッチングされるよう
にすることによって、第１開口部３１の幅を広くしなが
ら下部の幅が上部の幅より相対的に広い第２開口部３２
を形成する。本発明の実施例では多重層酸化膜のウェッ
トエッチングは、ＨＦ溶液を利用するか、またはＨＦ溶
液にその体積の１０００倍を越えないＨ２０を添加した
混合溶液を利用してウェットエッチングを実施する。ま
たは、ＨＦ体積の５００倍を越えないＮＨ４Ｆを添加し
たＮＨ４Ｆ／ＨＦ混合溶液を利用したウェットエッチン
グを実施する。このようなウェットエッチングは、４℃
乃至８０℃の温度において１秒乃至３６００秒間実施す
る。Next, as shown in FIG. 4, by performing a wet process so that the first oxide film 18 having a high wet etching rate is etched more than the second oxide film 19, The second opening 32 in which the width of the lower portion is relatively larger than the width of the upper portion while increasing the width of the opening 31
To form In the embodiment of the present invention, the wet etching of the multi-layer oxide film is performed by using an HF solution or a mixed solution obtained by adding H 20 not more than 1000 times the volume of the HF solution. I do. Or, performing the wet etching utilizing NH 4 F / HF mixed solution was added NH 4 F which does not exceed 500 times the HF volume. Such wet etching is performed at 4 ° C.
It is performed at a temperature of 乃至 80 ° C. for 1 s to 3600 s.
【００１７】次いで、ＥＣＤ方法を使用して第２開口部
３２の底面のシード層１７上に第１金属膜を３０００Å
乃至１００００Åの厚さに形成した後、パターンニング
して下部電極２０を形成する。第１金属膜は、Ｒｕ膜、
Ｉｒ膜、Ｏｓ膜、Ｗ膜、Ｍｏ膜、Ｃｏ膜、Ｎｉ膜、Ａｕ
膜、またはＡｇ膜の内のいずれか一つで形成し、０．１
ｍＡ／ｃｍ２乃至１０ｍＡ／ｃｍ２の電流密度条件下で
第１金属膜を形成する。Next, a first metal film is formed on the seed layer 17 on the bottom surface of the second opening 32 by using the ECD method at 3000.degree.
After forming the lower electrode 20 to a thickness of about 10,000 °, the lower electrode 20 is formed by patterning. The first metal film is a Ru film,
Ir film, Os film, W film, Mo film, Co film, Ni film, Au
Formed of any one of a film and an Ag film,
The first metal film is formed under a current density condition of mA / cm 2 to 10 mA / cm 2 .
【００１８】第２開口部３２が下部に行くにつれてその
幅が広くなるために、その内部に形成される第１金属膜
も上部より下部が広くなり、下部が上部より広い下部電
極を形成することができる。これの断面図を図７に示
す。Since the width of the second opening 32 becomes lower toward the lower part, the first metal film formed therein also has a lower part wider than the upper part and forms a lower electrode whose lower part is wider than the upper part. Can be. FIG. 7 shows a cross-sectional view of this.
【００１９】次に、図５に示すように、多重層酸化膜、
すなわち、第２酸化膜１９及び第１酸化膜１８を除去し
て、下部のシード層１７を露出させ、下部電極２０間の
絶縁のために、露出されたシード層１７を除去する。Next, as shown in FIG. 5, a multi-layer oxide film,
That is, the second oxide film 19 and the first oxide film 18 are removed to expose the lower seed layer 17, and the exposed seed layer 17 is removed for insulation between the lower electrodes 20.
【００２０】次に、図６に示すように、下部電極２０形
成が完了した全体構造上に誘電膜２１を形成し、誘電特
性を向上させるために、急速熱処理工程を実施する。そ
して誘電膜２１上に第２金属膜、例えば、Ｐｔ膜を形成
した後、パターンニングして上部電極２２を形成する。
本発明の実施例における誘電膜２１は、３００℃乃至６
００℃の温度で１５０Å乃至５００Åの厚さに形成され
たＢＳＴ（（Ｂａ、Ｓｒ）ＴｉＯ３）膜を用いる。ま
た、急速熱処理工程は、５００℃乃至７００℃の窒素雰
囲気下で３０秒乃至１８０秒間実施する。そして、第２
金属膜は、ＣＶＤ方法またはスパッタリング方法を利用
して形成する。Next, as shown in FIG. 6, a dielectric film 21 is formed on the entire structure where the formation of the lower electrode 20 is completed, and a rapid heat treatment process is performed to improve the dielectric characteristics. Then, after forming a second metal film, for example, a Pt film on the dielectric film 21, patterning is performed to form the upper electrode 22.
The dielectric film 21 in the embodiment of the present invention has a temperature of 300 ° C. to 6 ° C.
A BST ((Ba, Sr) TiO 3 ) film formed at a temperature of 00 ° C. and a thickness of 150 ° to 500 ° is used. In addition, the rapid heat treatment process is performed in a nitrogen atmosphere at 500 ° C. to 700 ° C. for 30 seconds to 180 seconds. And the second
The metal film is formed using a CVD method or a sputtering method.
【００２１】尚、本発明は、本実施例に限られるもので
はない。本発明の趣旨から逸脱しない範囲内で多様に変
更実施することが可能である。The present invention is not limited to this embodiment. Various modifications can be made without departing from the spirit of the present invention.
【００２２】[0022]
【発明の効果】上述したように、本発明によれば、所定
の構造が形成された半導体基板上部にシード層を形成
し、下部から上部に行くにつれてウェットエッチング率
が低くなる多重層酸化膜を形成した後、これらをドライ
及びウェットエッチングして多重酸化膜の内部にその下
部が上部より相対的に幅の広い開口部を形成しながら、
開口部の底面のシード層を露出させ、ＥＣＤ方法でシー
ド層上に下部電極を形成することによって、以後の誘電
膜の形成及び上部電極を形成する時、ステップカバレッ
ジ特性を向上させることができるので素子の電気的特性
を向上させることができる。As described above, according to the present invention, a seed layer is formed on an upper portion of a semiconductor substrate on which a predetermined structure is formed, and a multi-layer oxide film having a lower wet etching rate from a lower portion to an upper portion is formed. After formation, these are dry and wet etched to form an opening whose lower part is relatively wider than the upper part inside the multiple oxide film,
By exposing the seed layer on the bottom surface of the opening and forming the lower electrode on the seed layer by the ECD method, the step coverage characteristics can be improved when forming the dielectric film and forming the upper electrode thereafter. The electrical characteristics of the element can be improved.
【図１】従来の方法により製造されたキャパシタ下部電
極の断面形状を示すＳＥＭ画像である。FIG. 1 is an SEM image showing a cross-sectional shape of a capacitor lower electrode manufactured by a conventional method.
【図２】本発明にかかる半導体素子のキャパシタ製造工
程を説明するための断面図である。FIG. 2 is a cross-sectional view illustrating a process of manufacturing a capacitor of a semiconductor device according to the present invention.
【図３】本発明にかかる半導体素子のキャパシタ製造工
程を説明するための断面図である。FIG. 3 is a cross-sectional view illustrating a step of manufacturing a capacitor of a semiconductor device according to the present invention.
【図４】本発明にかかる半導体素子のキャパシタ製造工
程を説明するための断面図である。FIG. 4 is a cross-sectional view illustrating a step of manufacturing a capacitor of a semiconductor device according to the present invention.
【図５】本発明にかかる半導体素子のキャパシタ製造工
程を説明するための断面図である。FIG. 5 is a cross-sectional view illustrating a step of manufacturing a capacitor of a semiconductor device according to the present invention.
【図６】本発明にかかる半導体素子のキャパシタ製造工
程を説明するための断面図である。FIG. 6 is a cross-sectional view illustrating a step of manufacturing a capacitor of a semiconductor device according to the present invention.
【図７】本発明にかかる方法により製造されたキャパシ
タ下部電極の断面形状を示すＳＥＭ画像である。FIG. 7 is an SEM image showing a cross-sectional shape of a capacitor lower electrode manufactured by the method according to the present invention.
１１ 半導体基板 １２ 絶縁膜 １３ 反射防止膜 １４ プラグ １５ ＴｉＳｉｘ膜 １６ 拡散防止膜 １７ シード層 １８ 第１酸化膜 １９ 第２酸化膜 ２０ 下部電極 ２１ 誘電膜 ２２ 上部電極 Reference Signs List 11 semiconductor substrate 12 insulating film 13 antireflection film 14 plug 15 TiSix film 16 diffusion prevention film 17 seed layer 18 first oxide film 19 second oxide film 20 lower electrode 21 dielectric film 22 upper electrode
Claims (13)
を形成する第１ステップと、 前記シード層上に下部層から上部層へ行くに従いウェッ
トエッチング率が小さくなる多重層酸化膜を形成する第
２ステップと、 前記多重層酸化膜を選択的にドライエッチングしてその
底面に前記シード層を露出させる第１開口部を形成する
第３ステップと、 前記第１開口部側面に露出された前記多重層酸化膜をウ
ェットエッチングして前記第１開口部の幅を拡張させつ
つ下部の幅が上部の幅より広い第２開口部を形成する第
４ステップと、 ＥＣＤ（Ｅｌｅｃｔｒｏ−Ｃｈｅｍｉｃａｌ Ｄｅｐｏ
ｓｉｔｉｏｎ）方法により前記第２開口部底面の前記シ
ード層上に前記第２開口部と同じ形状の下部電極を形成
する第５ステップと、 前記多重層酸化膜をウェットエッチングにより除去して
その下部の前記シード層を露出させる第６ステップと、 前記露出されたシード層をドライエッチングにより除去
する第７ステップと、 前記下部電極上に誘電膜を形成する第８ステップと、 前記誘電膜上に上部電極を形成する第９ステップとを含
むことを特徴とする半導体素子のキャパシタ製造方法。1. A first step of forming a seed layer on a semiconductor substrate, and a second step of forming a multi-layer oxide film on the seed layer in which a wet etching rate decreases from a lower layer to an upper layer. A third step of selectively dry-etching the multi-layer oxide film to form a first opening exposing the seed layer on a bottom surface thereof; and a multi-layer exposed on a side surface of the first opening. A fourth step of forming a second opening having a lower width larger than an upper width while expanding the width of the first opening by wet etching the oxide film; and an ECD (Electro-Chemical Depo).
a fifth step of forming a lower electrode having the same shape as the second opening on the seed layer on the bottom surface of the second opening by a position (method), and removing the multi-layer oxide film by wet etching to form a lower electrode. A sixth step of exposing the seed layer, a seventh step of removing the exposed seed layer by dry etching, an eighth step of forming a dielectric film on the lower electrode, and an upper electrode on the dielectric film Forming a capacitor. 9. A method for manufacturing a capacitor of a semiconductor device, comprising:
Ｐｔ膜、Ｒｕ膜、Ｉｒ膜、Ｏｓ膜、Ｗ膜、Ｍｏ膜、Ｃｏ
膜、Ｎｉ膜、Ａｕ膜、またはＡｇ膜の内のいずれか一つ
により形成されることを特徴とする請求項１に記載の半
導体素子のキャパシタ製造方法。2. The method according to claim 1, wherein in the first step, the seed layer comprises:
Pt film, Ru film, Ir film, Os film, W film, Mo film, Co
2. The method according to claim 1, wherein the capacitor is formed of any one of a film, a Ni film, an Au film, and an Ag film.
Ｐｔ膜、Ｒｕ膜、Ｉｒ膜、Ｏｓ膜、Ｗ膜、Ｍｏ膜、Ｃｏ
膜、Ｎｉ膜、Ａｕ膜、またはＡｇ膜の内のいずれか一つ
により形成されることを特徴とする請求項１に記載の半
導体素子のキャパシタ製造方法。3. In the fifth step, the lower electrode comprises:
Pt film, Ru film, Ir film, Os film, W film, Mo film, Co
2. The method according to claim 1, wherein the capacitor is formed of any one of a film, a Ni film, an Au film, and an Ag film.
１ｍＡ／ｃｍ２乃至１０ｍＡ／ｃｍ２の条件下で前記下
部電極を形成することを特徴とする請求項１に記載の半
導体素子のキャパシタ製造方法。4. The method as set forth in claim 5, wherein the current density is equal to 0.
1 mA / cm 2 to a capacitor manufacturing method as claimed in claim 1, wherein the forming the lower electrode under the conditions of 10 mA / cm 2.
の各層に添加されるドーパント（ｄｏｐａｎｔ）の濃度
を順に減少させながら前記多重層酸化膜を形成すること
を特徴とする請求項１に記載の半導体素子のキャパシタ
製造方法。5. The multi-layer oxide film according to claim 1, wherein, in the second step, the multi-layer oxide film is formed while sequentially decreasing the concentration of a dopant added to each layer of the multi-layer oxide film. 13. A method for manufacturing a capacitor of a semiconductor device according to claim 1.
Ｇａの内の少なくともいずれか一つであることを特徴と
する請求項５に記載の半導体素子のキャパシタ製造方
法。6. The method according to claim 5, wherein the dopant is at least one of B, P, As, and Ga.
温度において、１秒乃至３６００秒間、前記ウェットエ
ッチングを実施することを特徴とする請求項１に記載の
半導体素子のキャパシタ製造方法。7. The method of claim 1, wherein in the fourth step, the wet etching is performed at a temperature of 4 ° C. to 80 ° C. for 1 second to 3600 seconds.
たウェットエッチングを実施することを特徴とする請求
項７に記載の半導体素子のキャパシタ製造方法。8. The method of claim 7, wherein wet etching is performed using an HF solution in the fourth step.
記ＨＦ溶液体積の１０００倍を越えないＨ２Ｏを添加し
た混合溶液を利用したウェットエッチングを実施するこ
とを特徴とする請求項８に記載の半導体素子のキャパシ
タ製造方法。9. The method of claim 8, wherein in the fourth step, wet etching is performed using a mixed solution obtained by adding H 2 O not exceeding 1000 times the volume of the HF solution to the HF solution. 13. A method for manufacturing a capacitor of a semiconductor device according to claim 1.
対し５００倍を越えないＮＨ４Ｆを添加したＮＨ４Ｆ／
ＨＦ混合溶液を利用してウェットエッチングを実施する
ことを特徴とする請求項８に記載の半導体素子のキャパ
シタ製造方法。10. In the fourth step, NH 4 was added NH 4 F which does not exceed 500 times the HF solution volume F /
9. The method according to claim 8, wherein the wet etching is performed using an HF mixed solution.
膜の各層に同じドーパントを同じ濃度で添加し、前記多
重層酸化膜の各層の蒸着温度を徐々に増加させながら前
記多重層酸化膜を形成することを特徴とする請求項１に
記載の半導体素子のキャパシタ製造方法。11. In the second step, the same dopant is added to each layer of the multilayer oxide film at the same concentration, and the multilayer oxide film is formed while gradually increasing the deposition temperature of each layer of the multilayer oxide film. The method of claim 1, wherein the capacitor is formed.
はＧａの内の少なくともいずれか一つであることを特徴
とする請求項１１に記載の半導体素子のキャパシタ製造
方法。12. The method of claim 11, wherein the dopant is at least one of B, P, As, and Ga.
の温度において１秒乃至３６００秒間、前記ウェットエ
ッチングを実施することを特徴とする請求項１、１１ま
たは１２に記載の半導体素子のキャパシタ製造方法。13. The method according to claim 4, wherein in the fourth step, 4 ° C. to 80 ° C.
The method according to claim 1, 11 or 12, wherein the wet etching is performed at a temperature of 1 to 3600 seconds.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000036046A KR100580119B1 (en) | 2000-06-28 | 2000-06-28 | Method of manufacturing a capacitor in a semiconductor device |
| KR2000/P36046 | 2000-06-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2002026135A true JP2002026135A (en) | 2002-01-25 |
| JP4087583B2 JP4087583B2 (en) | 2008-05-21 |
Family
ID=19674486
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001193423A Expired - Fee Related JP4087583B2 (en) | 2000-06-28 | 2001-06-26 | Capacitor manufacturing method for semiconductor device |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6383865B2 (en) |
| JP (1) | JP4087583B2 (en) |
| KR (1) | KR100580119B1 (en) |
| DE (1) | DE10134500B4 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100795683B1 (en) * | 2002-04-19 | 2008-01-21 | 매그나칩 반도체 유한회사 | Method of manufacturing a capacitor in semiconductor device |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100422594B1 (en) * | 2001-09-12 | 2004-03-16 | 주식회사 하이닉스반도체 | Capacitor in semiconductor device and method for fabricating the same |
| KR100448852B1 (en) | 2001-12-26 | 2004-09-18 | 주식회사 하이닉스반도체 | Method for manufacturing a capacitor of semiconductor device |
| KR100443361B1 (en) * | 2002-04-26 | 2004-08-09 | 주식회사 하이닉스반도체 | Method for fabricating capacitor using electro chemical deposition |
| US6861355B2 (en) * | 2002-08-29 | 2005-03-01 | Micron Technology, Inc. | Metal plating using seed film |
| KR100866126B1 (en) * | 2002-12-20 | 2008-10-31 | 주식회사 하이닉스반도체 | Method for fabricating capacitor of semiconductor device |
| CN100339953C (en) * | 2003-02-24 | 2007-09-26 | 友达光电股份有限公司 | Method for forming contact hole |
| US7463928B2 (en) * | 2003-04-25 | 2008-12-09 | Medtronic, Inc. | Identifying combinations of electrodes for neurostimulation therapy |
| US8694115B2 (en) * | 2004-07-20 | 2014-04-08 | Medtronic, Inc. | Therapy programming guidance based on stored programming history |
| GB2502306A (en) * | 2012-05-22 | 2013-11-27 | Univ Singapore | Microparticle sensor |
| KR102694259B1 (en) * | 2019-12-12 | 2024-08-13 | 주식회사 원익아이피에스 | Method of forming thin film and Apparatus for treating substrate |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5545585A (en) * | 1996-01-29 | 1996-08-13 | Taiwan Semiconductor Manufacturing Company | Method of making a dram circuit with fin-shaped stacked capacitors |
| US5789320A (en) * | 1996-04-23 | 1998-08-04 | International Business Machines Corporation | Plating of noble metal electrodes for DRAM and FRAM |
| US5677222A (en) * | 1996-10-11 | 1997-10-14 | Vanguard International Semiconductor Corporation | Method for forming a DRAM capacitor |
| DE19643905C1 (en) * | 1996-10-30 | 1998-04-09 | Mosel Vitelic Inc | Charge storage capacitor for dynamic memory device |
| KR100230382B1 (en) * | 1996-11-18 | 1999-11-15 | 윤종용 | fabrication method of fin-type capacitor |
| KR20000001703A (en) * | 1998-06-12 | 2000-01-15 | 윤종용 | Method for forming capacitor of semiconductor device |
| KR100289739B1 (en) * | 1999-04-21 | 2001-05-15 | 윤종용 | Method for manufacturing self-aligned stack capacitor using electroplating method |
| KR20010019578A (en) * | 1999-08-28 | 2001-03-15 | 윤종용 | Method for forming capacitor |
| US6294425B1 (en) * | 1999-10-14 | 2001-09-25 | Samsung Electronics Co., Ltd. | Methods of forming integrated circuit capacitors by electroplating electrodes from seed layers |
-
2000
- 2000-06-28 KR KR1020000036046A patent/KR100580119B1/en not_active IP Right Cessation
-
2001
- 2001-06-22 US US09/886,389 patent/US6383865B2/en not_active Expired - Fee Related
- 2001-06-26 JP JP2001193423A patent/JP4087583B2/en not_active Expired - Fee Related
- 2001-06-28 DE DE10134500A patent/DE10134500B4/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100795683B1 (en) * | 2002-04-19 | 2008-01-21 | 매그나칩 반도체 유한회사 | Method of manufacturing a capacitor in semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| DE10134500B4 (en) | 2009-08-13 |
| US6383865B2 (en) | 2002-05-07 |
| DE10134500A1 (en) | 2002-02-21 |
| KR20020001372A (en) | 2002-01-09 |
| US20020016036A1 (en) | 2002-02-07 |
| JP4087583B2 (en) | 2008-05-21 |
| KR100580119B1 (en) | 2006-05-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100390952B1 (en) | Method of manufacturing a capacitor | |
| US6162671A (en) | Method of forming capacitors having high dielectric constant material | |
| KR100612561B1 (en) | Method of manufacturing a capacitor in a semiconductor device | |
| JP2006173558A (en) | Manufacturing method for capacitor of semiconductor element | |
| KR100533971B1 (en) | Method of manufacturing capacitor for semiconductor device | |
| US6656784B2 (en) | Method for fabricating capacitors | |
| JP4087583B2 (en) | Capacitor manufacturing method for semiconductor device | |
| JP3172832B2 (en) | Method for manufacturing capacitor of semiconductor device | |
| US6444479B1 (en) | Method for forming capacitor of semiconductor device | |
| US6180970B1 (en) | Microelectronic devices including ferroelectric capacitors with lower electrodes extending into contact holes | |
| KR100713065B1 (en) | Method for fabricating semiconductor memory device having cylinder type storage node | |
| KR100436050B1 (en) | Method of fabricating capacitor | |
| US6451666B2 (en) | Method for forming a lower electrode by using an electroplating method | |
| US6159791A (en) | Fabrication method of capacitor | |
| KR100685674B1 (en) | Method of fabrication capacitor | |
| KR100413479B1 (en) | Method for forming capacitor of semiconductor device | |
| KR100190055B1 (en) | White electrode manufacturing method of semiconductor device | |
| KR20020000048A (en) | Method of manufacturing a capacitor in a semiconductor device | |
| KR100403952B1 (en) | Method for fabricating capacitor | |
| KR100414869B1 (en) | Method for fabricating capacitor | |
| KR100275116B1 (en) | Method for forming capacitor of semiconductor device | |
| KR100413478B1 (en) | Method for forming capacitor of semiconductor device | |
| KR100359785B1 (en) | Semiconductor device and method for fabricating the same | |
| KR100646947B1 (en) | Method of manufacturing a capacitor in a semiconductor device | |
| KR20040051070A (en) | Method for fabricating a semiconductor device having metal storage node |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20051108 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20060314 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20080121 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20080129 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20080221 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110228 Year of fee payment: 3 |
|
| R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110228 Year of fee payment: 3 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120229 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130228 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140228 Year of fee payment: 6 |
|
| LAPS | Cancellation because of no payment of annual fees |