KR20020000048A - Method of manufacturing a capacitor in a semiconductor device - Google Patents
Method of manufacturing a capacitor in a semiconductor device Download PDFInfo
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- KR20020000048A KR20020000048A KR1020000033979A KR20000033979A KR20020000048A KR 20020000048 A KR20020000048 A KR 20020000048A KR 1020000033979 A KR1020000033979 A KR 1020000033979A KR 20000033979 A KR20000033979 A KR 20000033979A KR 20020000048 A KR20020000048 A KR 20020000048A
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- oxide layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 239000003990 capacitor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 44
- 230000004888 barrier function Effects 0.000 claims abstract description 17
- 238000009792 diffusion process Methods 0.000 claims abstract description 17
- 239000003292 glue Substances 0.000 claims abstract description 16
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims abstract description 14
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims abstract description 13
- 150000004767 nitrides Chemical class 0.000 claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 11
- 229920005591 polysilicon Polymers 0.000 claims abstract description 11
- 238000003860 storage Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 125000006850 spacer group Chemical group 0.000 claims abstract description 9
- 229910052697 platinum Inorganic materials 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims description 13
- 238000010438 heat treatment Methods 0.000 claims description 6
- 229910004200 TaSiN Inorganic materials 0.000 claims description 4
- 229910010037 TiAlN Inorganic materials 0.000 claims description 4
- 229910008482 TiSiN Inorganic materials 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 claims description 4
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 claims description 4
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 3
- 229910052707 ruthenium Inorganic materials 0.000 claims description 3
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 3
- 229910004491 TaAlN Inorganic materials 0.000 claims description 2
- 229910010413 TiO 2 Inorganic materials 0.000 claims description 2
- 238000004140 cleaning Methods 0.000 claims description 2
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 2
- 238000000137 annealing Methods 0.000 abstract description 2
- 238000000151 deposition Methods 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000010970 precious metal Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
- H01L28/57—Capacitors with a dielectric comprising a perovskite structure material comprising a barrier layer to prevent diffusion of hydrogen or oxygen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
- H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체 소자의 캐패시터 제조 방법에 관한 것으로, 특히 플러그가 형성된 콘택홀 측벽에 알루미늄 산화막으로 스페이서를 형성하여 저장 전극을 형성하기 위한 더미 산화막 패턴 공정에서 플러그의 확산 방지막이 노출되지 않도록 함으로써 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 캐패시터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device. In particular, a diffusion barrier of a plug is not exposed in a dummy oxide pattern process for forming a storage electrode by forming a spacer with an aluminum oxide film on a sidewall of a contact hole having a plug. The present invention relates to a method for manufacturing a capacitor of a semiconductor device capable of improving reliability.
스택형 캐패시터의 제조 공정에서 하부 구조가 형성된 반도체 기판의 소정 영역과 저장 전극을 연결하기 위해 절연막의 소정 영역을 식각하여 콘택홀을 형성한 후 콘택홀 내부에 폴리실리콘, 오믹 콘택층 및 확산 방지막으로 구성된 플러그를 형성한다. 그런데, 캐패시터의 제조 공정은 설계상 플러그 콘택과 저장 전극간에 필연적으로 오정렬이 발생되기 때문에 플러그의 최상부층인 확산 방지막이 노출되는 문제점이 발생된다. 확산 방지막이 노출되면 산소 분위기에서 고유전체막을 증착할 때 확산 방지막이 산화되어 유전체막의 유전율을 저하시키게 되어 캐패시터의 정전 용량을 저하시킨다. 이러한 문제점 때문에 저온에서의 유전체막 증착 및 열처리 공정을 개발하고 있지만, 고유전체막 특유의 높은 유전율을 얻지 못하여 셀당 요구되는 정전 용량을 얻지 못하고 있다. 한편, 스택 구조 이외에 공동 구조의 저장 전극을 형성하여 오정렬을 방지하는 방법을 모색하고 있다. 그러나, 디자인 룰이 감소함에 따라 상대적으로 캐패시터가 차지하는 면적이 증가되어 스택형에 비해 높은 애스펙트비(aspect ratio)를 갖기 때문에 스택형보다 공정 마진이 줄어들고 있다. 또한, 자기정렬 스택 구조를 이용하여 오정렬을 방지하려 하고 있으나, 콘택 플러그와 저장 전극 사이에 정렬 마진의 부족으로 인해 고유전체막이 노출되고, 이로 인해 상기와 같이 산화되어 유전율이 감소하는 문제점이 발생된다.In the manufacturing process of a stacked capacitor, a contact hole is formed by etching a predetermined region of an insulating layer to connect a predetermined region of a semiconductor substrate on which a lower structure is formed with a storage electrode, and then a polysilicon, an ohmic contact layer, and a diffusion barrier layer in the contact hole. Form a configured plug. However, in the manufacturing process of the capacitor, because a misalignment is inevitably generated between the plug contact and the storage electrode, a problem arises in that the diffusion barrier layer, which is the uppermost layer of the plug, is exposed. When the diffusion barrier is exposed, when the high dielectric film is deposited in an oxygen atmosphere, the diffusion barrier is oxidized to lower the dielectric constant of the dielectric layer, thereby lowering the capacitance of the capacitor. Due to these problems, the dielectric film deposition and heat treatment processes are developed at low temperature, but the high dielectric constant peculiar to the high-k dielectric film cannot be obtained, thereby failing to obtain the required capacitance per cell. On the other hand, a method of preventing misalignment by forming a storage electrode having a cavity structure in addition to the stack structure is being sought. However, as the design rule decreases, the area occupied by the capacitor is relatively increased, and thus the process margin is reduced compared to the stacked type because of the higher aspect ratio than the stacked type. In addition, a misalignment is prevented by using a self-aligned stack structure, but a high dielectric film is exposed due to a lack of alignment margin between the contact plug and the storage electrode, which causes oxidation to reduce the dielectric constant as described above. .
따라서, 본 발명은 저장 전극을 형성하기 위한 마스크 및 식각 공정에서 오정렬이 발생되더라도 콘택 플러그의 확산 방지막의 노출을 방지할 수 있는 반도체 소자의 캐패시터 제조 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor device capable of preventing exposure of a diffusion barrier of a contact plug even when misalignment occurs in a mask and an etching process for forming a storage electrode.
상술한 목적을 달성하기 위한 본 발명은 소정의 구조가 형성된 반도체 기판 상부에 제 1 산화막 및 질화막을 형성한 후 상기 질화막 및 제 1 산화막의 소정 영역을 식각하여 상기 반도체 기판의 소정 영역을 노출시키는 콘택홀을 형성하는 단계와, 상기 콘택홀이 완전히 매립되지 않도록 폴리실리콘막, 오믹 콘택층 및 확산 방지막을 순차적으로 형성하는 단계와, 전체 구조 상부에 시드층 및 알루미늄 산화막을 형성한 후 상기 알루미늄 산화막을 전면 식각하여 상기 콘택홀 측벽에 스페이서를 형성하는 단계와, 전체 구조 상부에 글루층 및 제 2 산화막을 순차적으로 형성하는 단계와, 상기 제 2 산화막 및 글루층의 소정 영역을 식각하여 더미 산화막 패턴을 형성하는 단계와, 상기 알루미늄 산화막 스페이서를 제거한 후 상기 더미 산화막 패턴에 백금을 형성하여 저장 전극을 형성하는 단계와, 상기 제 2 산화막, 글루층 및 노출된 시드층을 제거하는 단계와, 전체 구조 상부에 고유전체막을 형성한 후 상부 전극을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.According to the present invention for achieving the above object, a contact for exposing a predetermined region of the semiconductor substrate by forming a first oxide film and a nitride film on the semiconductor substrate having a predetermined structure and then etching a predetermined region of the nitride film and the first oxide film Forming a hole, sequentially forming a polysilicon layer, an ohmic contact layer, and a diffusion barrier layer so that the contact hole is not completely filled, and forming a seed layer and an aluminum oxide layer over the entire structure, and then forming the aluminum oxide layer. Forming a spacer on the sidewalls of the contact hole by etching the entire surface; sequentially forming a glue layer and a second oxide layer on the entire structure; and etching a predetermined region of the second oxide layer and the glue layer to form a dummy oxide pattern. And removing the aluminum oxide spacers and depositing platinum to the dummy oxide pattern. Forming a storage electrode, removing the second oxide film, the glue layer and the exposed seed layer, and forming an upper electrode after forming a high dielectric film over the entire structure. It is done.
도 1(a) 내지 도 1(e)는 본 발명에 따른 반도체 소자의 캐패시터 제조 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.1 (a) to 1 (e) are cross-sectional views of devices sequentially shown to explain a method of manufacturing a capacitor of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11 : 반도체 기판 12 : 제 1 산화막11 semiconductor substrate 12 first oxide film
13 : 질화막 14 : 폴리실리콘막13: nitride film 14: polysilicon film
15 : 티타늄 실리사이드막 16 : 확산 방지막15 titanium silicide film 16 diffusion barrier film
17 : 시드층 18 : 알루미늄 산화막17 seed layer 18 aluminum oxide film
19 : 글루층 20 : 제 2 산화막19: glue layer 20: second oxide film
21 : Pt막 22 : 고유전체막21: Pt film 22: High dielectric film
23 : 상부 전극23: upper electrode
첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.The present invention will be described in detail with reference to the accompanying drawings.
도 1(a) 내지 도 1(e)는 본 발명에 따른 반도체 소자의 캐패시터 제조 방법을 설명하기 위해 순차적으로 도시한 소자의 단면도이다.1 (a) to 1 (e) are cross-sectional views of devices sequentially shown to explain a method of manufacturing a capacitor of a semiconductor device according to the present invention.
도 1(a)를 참조하면, 반도체 소자를 제조하기 위한 소정의 구조가 형성된 반도체 기판(11) 상부에 제 1 산화막(12)을 형성하고, 그 상부에 제 1 산화막(12)과의 식각 선택비가 우수한 질화막(13)을 300∼1000Å의 두께로 형성한다. 질화막(13)과 제 1 산화막(12)의 소정 영역을 식각하여 반도체 기판(11)의 소정 영역을 노출시키는 콘택홀을 형성한다. 콘택홀이 매립되도록 전체 구조 상부에 500∼3000Å 정도의 두께로 폴리실리콘막(14)을 형성한다. 전면 과도 식각 공정을 실시하여 질화막(13) 상부에 형성된 폴리실리콘막(14)이 완전히 제거되고, 콘택홀에 매립된 폴리실리콘막(14)의 일부가 제거되도록 한다. 이때, 콘택홀의 상부로부터 500∼1500Å 정도의 깊이로 폴리실리콘막(14)이 형성되도록 식각 공정을 실시한다. 콘택홀을 포함한 전체 구조 상부에 Ti막을 형성한다. 열처리 공정을 실시하여 폴리실리콘막(14)의 실리콘 원자와 Ti막의 Ti 원자를 반응시켜 오믹 콘택층으로 작용하는 티타늄 실리사이드막(TiSix)(15)을 형성한다. 질화막(13) 상부에 잔류하는 Ti막을 습식 식각 공정으로 제거한다. 콘택홀을 포함한 전체 구조 상부에 확산 방지막(16)을 형성한 후 CMP 공정을 실시하여 평탄화시킨다. 확산 방지막(16)은 TiN막, TiSiN막, TiAlN막, TaSiN막 및 TaAlN막중 어느 하나로 형성한다.Referring to FIG. 1A, a first oxide film 12 is formed on a semiconductor substrate 11 on which a predetermined structure for fabricating a semiconductor device is formed, and an etching selection with the first oxide film 12 is formed thereon. A nitride film 13 having an excellent ratio is formed to a thickness of 300 to 1000 GPa. Predetermined regions of the nitride film 13 and the first oxide film 12 are etched to form contact holes for exposing the predetermined regions of the semiconductor substrate 11. The polysilicon film 14 is formed in the thickness of about 500-3000 micrometers on the whole structure so that a contact hole may be filled. The entire over-etching process is performed to completely remove the polysilicon film 14 formed on the nitride film 13 and to remove a part of the polysilicon film 14 embedded in the contact hole. At this time, an etching process is performed such that the polysilicon film 14 is formed to a depth of about 500 to 1500 Å from the top of the contact hole. A Ti film is formed over the entire structure including the contact hole. The heat treatment process is performed to form a titanium silicide film (TiSi x ) 15 that serves as an ohmic contact layer by reacting the silicon atoms of the polysilicon film 14 with the Ti atoms of the Ti film. The Ti film remaining on the nitride film 13 is removed by a wet etching process. The diffusion barrier layer 16 is formed on the entire structure including the contact hole and then planarized by performing a CMP process. The diffusion barrier 16 is formed of any one of a TiN film, a TiSiN film, a TiAlN film, a TaSiN film, and a TaAlN film.
도 1(b)를 참조하면, 질화막(13)과 식각 선택비가 높은 화학 가스, 예를들어 CF4를 이용한 건식 식각 공정에 의해 콘택홀내의 확산 방지막(16)을 소정 두께로 식각한다. 전체 구조 상부에 시드층(seed layer)(17)을 형성한 후 알루미늄 산화막(Al2O3)(18)을 형성한다. 알루미늄 산화막(18)을 전면 식각하여 콘택홀 내에 스페이서를 형성한다. 시드층(17)은 Pt 또는 Ru를 50∼1000Å의 두께로 증착하여 형성한다.Referring to FIG. 1B, the diffusion barrier layer 16 in the contact hole is etched to a predetermined thickness by a dry etching process using a nitride gas 13 and a chemical gas having a high etching selectivity, for example, CF 4 . After forming a seed layer 17 on the entire structure, an aluminum oxide layer (Al 2 O 3 ) 18 is formed. The entire surface of the aluminum oxide layer 18 is etched to form a spacer in the contact hole. The seed layer 17 is formed by depositing Pt or Ru to a thickness of 50 to 1000 GPa.
도 1(c)를 참조하면, 전체 구조 상부에 글루층(glue layer)(19) 및 제 2 산화막(20)을 형성한다. 글루층(19)은 TiN막, TiAlN막, TaN막, TaSiN막, TiSiN막, Al2O3막 및 TiO2막중 어느 하나를 50∼500Å의 두께로 증착하여 형성하고, 제 2 산화막(20)은 5000∼10000Å의 두께로 형성한다. 마스크 및 식각 공정을 실시하여 제 2 산화막(20) 및 글루층(19)의 소정 영역을 제거하여 더미 산화막 패턴을 형성한다.Referring to FIG. 1C, a glue layer 19 and a second oxide film 20 are formed on the entire structure. The glue layer 19 is formed by depositing any one of a TiN film, a TiAlN film, a TaN film, a TaSiN film, a TiSiN film, an Al 2 O 3 film, and a TiO 2 film to a thickness of 50 to 500 GPa, and the second oxide film 20 Is formed to a thickness of 5000 to 10000 Pa. A mask and an etching process are performed to remove predetermined regions of the second oxide film 20 and the glue layer 19 to form a dummy oxide film pattern.
도 1(d)를 참조하면, 1∼50%의 HCl 또는 H2SO4를 이용한 세정 공정을 실시하여 알루미늄 산화막 스페이서(18)를 제거한다. 더미 산화막 패턴에 스택형 저장 전극을 형성하기 위한 Pt막(21)을 전기 도금법을 이용하여 3000∼10000Å의 두께로 형성한다. 전기도금법은 DC 또는 펄스 방법을 이용하며, 이때의 전류 밀도는 0.1∼10㎃/㎠이다. 제 2 산화막(20)을 습식 식각 공정으로 제거하고, 글루층(19) 및 노출된 시드층(17)을 건식 식각 공정으로 제거한다.Referring to FIG. 1 (d), the aluminum oxide spacer 18 is removed by a cleaning process using 1 to 50% HCl or H 2 SO 4 . A Pt film 21 for forming a stacked storage electrode in the dummy oxide film pattern is formed to have a thickness of 3000 to 10000 kPa using an electroplating method. The electroplating method uses a DC or pulse method, and the current density at this time is 0.1 to 10 mA / cm 2. The second oxide layer 20 is removed by a wet etching process, and the glue layer 19 and the exposed seed layer 17 are removed by a dry etching process.
도 1(e)를 참조하면, 전체 구조 상부에 BST, PZT, SBT등의 고유전체막(22)을 형성한 후 결정화를 증가시켜 유전 특성을 확보하기 위해 급속 열처리 공정을 실시한다. 전체 구조 상부에 귀금속층을 형성하고 패터닝하여 상부 전극(23)을 형성한다. 고유전체막(22)은 400∼600℃의 온도에서 150∼500Å의 두께로 형성하며, 급속 열처리 공정은 500∼700℃의 질소 분위기에서 30∼180초동안 실시한다. 또한, 상부 전극(23)은 Pt, Ru, SRO등의 귀금속으로 형성한다.Referring to FIG. 1 (e), after forming a high dielectric film 22 such as BST, PZT, SBT, etc. on the entire structure, a rapid heat treatment process is performed to increase the crystallization to secure dielectric properties. The upper electrode 23 is formed by forming and patterning a noble metal layer on the entire structure. The high dielectric film 22 is formed to a thickness of 150 to 500 kPa at a temperature of 400 to 600 占 폚, and the rapid heat treatment process is performed for 30 to 180 seconds in a nitrogen atmosphere of 500 to 700 占 폚. In addition, the upper electrode 23 is made of precious metals such as Pt, Ru, and SRO.
한편, 본 발명의 또다른 실시예로서 알루미늄 산화막을 먼저 형성한 후 확산 방지막이 노출되도록 전면 식각하여 스페이서를 형성하고, 시드층을 전체 구조 상부에 형성한다. 그리고난 후 상기와 같은 공정을 실시하면, 저장 전극을 형성하고, 제 2 산화막, 글루층 및 시드층을 제거하면 알루미늄 산화막 스페이서가 콘택홀 측벽에 잔류하게 된다. 이 상태에서 고유전체막 및 상부 전극을 형성한다.Meanwhile, as another embodiment of the present invention, an aluminum oxide film is first formed, and then a front surface is etched to expose the diffusion barrier, thereby forming a spacer, and a seed layer is formed on the entire structure. After the above process, the storage electrode is formed, and when the second oxide layer, the glue layer, and the seed layer are removed, the aluminum oxide spacers remain on the contact hole sidewalls. In this state, a high dielectric film and an upper electrode are formed.
상술한 바와 같이 고유전 캐패시터를 형성하면 오정렬이 발생하였어도 확산 방지막이 노출되지 않아 고유전체막의 고온 어닐링 공정이 가능하여 신뢰성있는 캐패시터를 제조할 수 있을 뿐만 아니라 0.1㎛ 이하의 디바이스에서도 높은 정전 용량을 갖는 캐패시터를 제조할 수 있다.As described above, when the high dielectric capacitor is formed, the diffusion barrier layer is not exposed even when misalignment occurs, thereby enabling high temperature annealing process of the high dielectric layer, thereby producing a reliable capacitor, and having a high capacitance even in a device having a thickness of 0.1 μm or less. Capacitors can be manufactured.
Claims (16)
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| KR1020000033979A KR20020000048A (en) | 2000-06-20 | 2000-06-20 | Method of manufacturing a capacitor in a semiconductor device |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100408742B1 (en) * | 2001-05-10 | 2003-12-11 | 삼성전자주식회사 | Capacitor in integrated circuits device and method therefor |
| KR100646947B1 (en) * | 2000-06-29 | 2006-11-17 | 주식회사 하이닉스반도체 | Method of manufacturing a capacitor in a semiconductor device |
| KR100676534B1 (en) * | 2000-06-28 | 2007-01-30 | 주식회사 하이닉스반도체 | Method of manufacturing a capacitor in a semiconductor device |
| CN116110635A (en) * | 2021-11-11 | 2023-05-12 | 西安交通大学苏州研究院 | Ohmic contact electrode structure based on silicon substrate and preparation method thereof |
| KR20230143855A (en) | 2022-04-06 | 2023-10-13 | 김정필 | Prefabricated injection tube for nozzle, block assembly thereof, and application products including the same |
-
2000
- 2000-06-20 KR KR1020000033979A patent/KR20020000048A/en not_active Application Discontinuation
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100676534B1 (en) * | 2000-06-28 | 2007-01-30 | 주식회사 하이닉스반도체 | Method of manufacturing a capacitor in a semiconductor device |
| KR100646947B1 (en) * | 2000-06-29 | 2006-11-17 | 주식회사 하이닉스반도체 | Method of manufacturing a capacitor in a semiconductor device |
| KR100408742B1 (en) * | 2001-05-10 | 2003-12-11 | 삼성전자주식회사 | Capacitor in integrated circuits device and method therefor |
| CN116110635A (en) * | 2021-11-11 | 2023-05-12 | 西安交通大学苏州研究院 | Ohmic contact electrode structure based on silicon substrate and preparation method thereof |
| KR20230143855A (en) | 2022-04-06 | 2023-10-13 | 김정필 | Prefabricated injection tube for nozzle, block assembly thereof, and application products including the same |
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