GB2317270A - Forming a layer on a pre-stressed semiconductor wafer - Google Patents
Forming a layer on a pre-stressed semiconductor wafer Download PDFInfo
- Publication number
- GB2317270A GB2317270A GB9718654A GB9718654A GB2317270A GB 2317270 A GB2317270 A GB 2317270A GB 9718654 A GB9718654 A GB 9718654A GB 9718654 A GB9718654 A GB 9718654A GB 2317270 A GB2317270 A GB 2317270A
- Authority
- GB
- United Kingdom
- Prior art keywords
- wafer
- layer
- stressed
- forming
- semiconductor wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 15
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 238000005452 bending Methods 0.000 claims description 7
- 235000012431 wafers Nutrition 0.000 abstract description 32
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
- H01L21/6833—Details of electrostatic chucks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Jigs For Machine Tools (AREA)
Abstract
A method of forming a layer 15 on a semiconductor wafer 13 comprises applying tensile stress to the wafer, depositing the layer on the wafer, and releasing the wafers from the stressed condition. A seed layer 14 is deposited on the wafer before the wafer is stressed by means of an electrostatic chuck 10 with a convex surface 11. The layer 15 is then deposited on the wafer and allowed to harden or set. On release from the chuck, the wafer flattens to compress the layer 15 and prevent the formation of cracks.
Description
2317270 A Method of Forming a Layer This invention relates to a method of
forming a layer on a semiconductor wafer.
In a number of manufacturing processes involving semi- s conductor wafers, it is known to deposit a generally liquid layer on to the surface of the wafJ and there is then a need to remove moisture from that layer, before further layers can be deposited or other processing steps carried out. Examples of such process are the spin-on glass process or planarisation processes such as the one described in International Patent Application No. PCT/GB93/01368. The layers (which -term includes films) are generally tensile layers and the resultant internal forces often lead to the layers becoming cracked as the moisture is removed, unless is great care is taken. Sometimes other processing steps have to take place, for example the deposition of a water permeable capping layer prior to any drying process.
From one aspect the present invention consists in a method of forming a layer on a semi-conductor wafer, comprising applying tensile stress to the wafer, depositing a tensile layer on the stressed wafer and releasing the wafer from the stressed condition.
The result of the release of the wafer from the stressed condition will be to create a compressive stress within the layer which will serve to counterbalance the tensile nature of the layer and hence remove or reduce the 2 likelihood of cracking.
In a preferred embodiment the wafer is stressed by bending and this may, for example, be achieved by clamping the wafer to an electrostatic chuck having a convex curved support surface.
Preferable the layer is allowed to harden or is hardened or set in some other way prior to the release o.E the stress. It is particularly preferred that a seed layer is deposited on the wafer prior to the wafer being stressed.
The invention also consists in apparatus for bending a wafer includinc an electrostatic chuck having a convex curved support surface.
Although the invention has been defined above, it is to be understood ha"t it includes any inventive combination of is the features set out above or in the following description.
The invention may be performed in various ways and specific embodiments will now be described, by way of example, with reference to the accompanying drawing which is a schematic cross section through a wafer clamped to an electrostatic chuck.
In the figure, an electrostatic chuck 10 has a convex upper surface 11 and is powered from power source 12. The general dperation of an electrostatic chuck is well known and is, conveniently summarised in an article by Larry D Hartsough in Solid State Technology which appears on,pdje" 8-7" of the January 1993 issue. More detailed constructions and operations are described in the references to that article and they and the article are hereby incorporated by refer- 3 ence. The normal purpose of such chucks is to create an electrostatic distribution on the top of a dielectric support so that the wafer is held flat relative to the support so that a gas heat transfer medium trapped between the two can create a uniform heat transfer over the entire surface of the wafer. However, in this case the upper surface 11 is clearly convex so that when the wafer 13 is clamped to the chuck 10 it is subjected to tensile stress.
Preferable, prior to the wafer being so stressed, a seed layer 14 is deposited on the wafer 13. Once the wafer 13 is stressed, a tensile film or layer 15 is deposited using the appropriate techniques, such as those mentioned above. The layer 15 is then hardened or allowed to harden or set or partially set. When it is in the desired condi- is tion, the wafer 11 is released from the chuck 10 and it returns to its normally flat condition. In doing so it places the layer 15 under a compressive load and this serves to resist the tensile forces within the layer 15, which would otherwise cause it to crack as moisture is removed from it. Traditionally precautions taken during the moisture removing steps can therefore either be reduced or dispensed-with altogether.
It will be understood that other methods of bending the wafer maybe used; the attraction of the electrostatic chuck is that it avoids the need for any engagement of the upper surface of the wafer 13. It will be further understood that the operation may occur on a number of occasions as the semi-conductor device is built up on the wafer by oper- 4 ations, but care may need to be taken that subsequent bending of the wafer does not cause damage to layers deposited earlier. It may, for example, be desirable to use chucks with successively shallower curves as the device 5 builds up.
Claims (8)
1. A method of forming a layer on a semiconductor wafer, comprising, applying tensile stress to the wafer,depositing a tensile layer on the stressed wafer and releasing the 5 wafer from the stressed condition.
2. A method as claimed in claim 1 wherein the wafer is stressed by bending.
3. A method as claimed in claim 2 wherein the wafer is stressed by clamping the wafer to an electronic chuck having a convex curved support surface.
4. A method as claimed in any one of the preceding claims wherein the layer is allowed to harden or is hardened or set prior to the release of the stress.
5. A method as claimed in any one of the preceding claims wherein a seed layer is deposited on the wafer prior to the wafer being stressed.
6. A method of forming a layer on a semiconductor wafer substantially as herein before described with reference to the accompanying drawings.
7. Apparatus for bending a semiconductor wafer including an electrostatic chuck having a convex support surface.
6
8. Apparatus for bending a semiconductor wafer substantially as herein before described.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GBGB9618620.0A GB9618620D0 (en) | 1996-09-06 | 1996-09-06 | A method of forming a layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9718654D0 GB9718654D0 (en) | 1997-11-05 |
| GB2317270A true GB2317270A (en) | 1998-03-18 |
Family
ID=10799521
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GBGB9618620.0A Pending GB9618620D0 (en) | 1996-09-06 | 1996-09-06 | A method of forming a layer |
| GB9718654A Withdrawn GB2317270A (en) | 1996-09-06 | 1997-09-04 | Forming a layer on a pre-stressed semiconductor wafer |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GBGB9618620.0A Pending GB9618620D0 (en) | 1996-09-06 | 1996-09-06 | A method of forming a layer |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPH10177938A (en) |
| KR (1) | KR19980024318A (en) |
| DE (1) | DE19737825A1 (en) |
| GB (2) | GB9618620D0 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6413583B1 (en) | 1998-02-11 | 2002-07-02 | Applied Materials, Inc. | Formation of a liquid-like silica layer by reaction of an organosilicon compound and a hydroxyl forming compound |
| US6800571B2 (en) | 1998-09-29 | 2004-10-05 | Applied Materials Inc. | CVD plasma assisted low dielectric constant films |
| US6858153B2 (en) | 1998-02-11 | 2005-02-22 | Applied Materials Inc. | Integrated low K dielectrics and etch stops |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6184157B1 (en) * | 1998-06-01 | 2001-02-06 | Sharp Laboratories Of America, Inc. | Stress-loaded film and method for same |
| AT411856B (en) * | 2000-10-16 | 2004-06-25 | Datacon Semiconductor Equip | METHOD FOR PRODUCING AN ADHESIVE CONNECTION FROM A DISC-SHAPED SEMICONDUCTOR SUBSTRATE TO A FLEXIBLE ADHESIVE TRANSPORT CARRIER, AND DEVICE FOR CARRYING OUT THIS METHOD |
| GB0029570D0 (en) * | 2000-12-05 | 2001-01-17 | Trikon Holdings Ltd | Electrostatic clamp |
| KR100809335B1 (en) | 2006-09-28 | 2008-03-05 | 삼성전자주식회사 | Semiconductor device and method of fabricating the same |
| US20080116521A1 (en) | 2006-11-16 | 2008-05-22 | Samsung Electronics Co., Ltd | CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities and Methods of Forming Same |
| US7534678B2 (en) | 2007-03-27 | 2009-05-19 | Samsung Electronics Co., Ltd. | Methods of forming CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein and circuits formed thereby |
| US7902082B2 (en) | 2007-09-20 | 2011-03-08 | Samsung Electronics Co., Ltd. | Method of forming field effect transistors using diluted hydrofluoric acid to remove sacrificial nitride spacers |
| US7923365B2 (en) | 2007-10-17 | 2011-04-12 | Samsung Electronics Co., Ltd. | Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5275683A (en) * | 1991-10-24 | 1994-01-04 | Tokyo Electron Limited | Mount for supporting substrates and plasma processing apparatus using the same |
-
1996
- 1996-09-06 GB GBGB9618620.0A patent/GB9618620D0/en active Pending
-
1997
- 1997-08-29 DE DE19737825A patent/DE19737825A1/en not_active Withdrawn
- 1997-09-04 GB GB9718654A patent/GB2317270A/en not_active Withdrawn
- 1997-09-04 KR KR1019970045688A patent/KR19980024318A/en not_active Application Discontinuation
- 1997-09-05 JP JP24095197A patent/JPH10177938A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5275683A (en) * | 1991-10-24 | 1994-01-04 | Tokyo Electron Limited | Mount for supporting substrates and plasma processing apparatus using the same |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6413583B1 (en) | 1998-02-11 | 2002-07-02 | Applied Materials, Inc. | Formation of a liquid-like silica layer by reaction of an organosilicon compound and a hydroxyl forming compound |
| US6858153B2 (en) | 1998-02-11 | 2005-02-22 | Applied Materials Inc. | Integrated low K dielectrics and etch stops |
| US7227244B2 (en) | 1998-02-11 | 2007-06-05 | Applied Materials, Inc. | Integrated low k dielectrics and etch stops |
| US6800571B2 (en) | 1998-09-29 | 2004-10-05 | Applied Materials Inc. | CVD plasma assisted low dielectric constant films |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9718654D0 (en) | 1997-11-05 |
| KR19980024318A (en) | 1998-07-06 |
| DE19737825A1 (en) | 1998-03-12 |
| GB9618620D0 (en) | 1996-10-16 |
| JPH10177938A (en) | 1998-06-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |