GB2186468A - Improvements relating to data transmission systems - Google Patents

Abstract

A data transmission system in which a train of rectangular data pulses of logic 0 and/or logic 1 significance is produced in synchronism with a train of rectangular timing signals and in which the baud rate of the timing signals is measured by timing signal sampling means and the degree of steepness of the leading and trailing edges of the data pulses is automatically adjusted in dependence upon the measured baud rate. <IMAGE>

Description

SPECIFICATION Improvements relating to data transmission systems This invention relates to data transmission systems in which trains of data pulses of logic 0 and/or logic 1 significance are transmitted over serial data links.

In data transmission systems handling secure data, serial data links may constitute a potential source of inadvertent data leakage due to information radiation resulting from square-wave char acteristics of the transmitted data pulses. For the avoidance of such data leakage, it is necessaryfor the steepness of the leading and trailing edges ofthe data pulses to be reduced in dependence upon the baud rateofthe data to be transmitted overtheserial link.

According to the present invention there is provided a data transmission system in which a train of rectangular data pulses of logic 0 and/or logic 1 significance is produced in synchronism with a train of rectangulartiming signals and in which the baud rate ofthetiming signals is measured by timing signal sampling means and the degree of steepness ofthe leading and trailing edges of the data pulses is automatically adjusted in dependence upon the measured baud rate.

In carrying outthe present invention the timing signal sampling meansmaycompriseabinarycounterwhich may be stepped during the positive excursion of each timing signal by clock pulses having a relatively high repetition frequency compared to the frequency of the timing signals. An output from the binary counter at the end ofthe positive excursion of atimingsignal maybearrangedtoproducethe selective operation of switching means for the adjustment of the capacitance of a wave-shaping circuit in orderto shape, as required, the data pulses to be transmitted over a data transmission serial link or channel.The switching means may be operated by the outputs from flipJlop means connected tore- spective outputterminals of the binary counter and these flip-flop means may be arranged to be latched by the trailing or negative-going edge of each timing signal as sampling takes place, thereby allowing the binary counterto be re-set in readiness for sampling the next timing signal.

By way of example the present invention will now be described with reference to the accompanying drawings in which: Figure I shows part of a data transmission system including a wave-shaping circuit capable of being automatically adjusted in accordance with the baud rate of data pulses to be transmitted over a serial link or channel; Figure 2 shows the wave-shaping of data pulses having different baud rates, as weli as a counttable for the binary counter ofthe system of Figure 1; and, Figure 3 shows specific detail relating to the waveshaping of the data pulses, as well as a table indicating the switch operation that takers place in the wave-shaping circuit of Figure 1.

In operation of the data transmission system shown in part in the drawings, a train of rectangular timing signals TP1 , TP2 orTP3 are produced having a baud rate of 2,400, 300 or 75 (see Figure 2) which may be preselected by computer software means (not shown) in accordance with the characterofthetransmission line or channel TLto be used for data transmission purposes. The timing signals, such as the signals TP1,are applied to a gate IC1 which is opened by the positive-going edge of a timing signal to allow a binary counter IC2 to be stepped by clocking pulses derived from an oscillator Xl having a high frequency (e.g. 230KHz) compared to the frequency or baud rateofthetiming signalsTP1,TP2 orTP3.

At the end of the positive excursion of a timing signal, the binary counterwill be providing specific logic 1 and/or logic 0 outputs at the counter output terminals Q9 and Q11 (See table in Figure 2) and these outputs are stored in bistable devices IC5 and IC6, respectively, as they become latched bythetrailing or negative-going edge of the positive excursion of a timing signal received over line L.This trailing edge also causes monostable switching-means comprising devices IC3 and IC4to be triggered for providing outputs for resetting the binary counter IC2 in readinessfor commencement of the next counting operation at the beginning ofthe positive half-cycle ofthe next timing signal. The bistable device IC5 produces a logic 1 or logic 0 output corresponding to that ofoutputterminal Q9 of the binary counter whilstthe bistable device IC6 produces complementary logic outputs the upper of which, as viewed in Figure 1, corresponds to that of the output terminal QI 1 of the binary counter.Exemplary logic outputs from the binary counter, including the outputs from terminals Q9 and Ql 1 for different baud rates of timing signals are shown in the counttable embodied i n in Figure2ofthedrawings.

The logic outputfrom the bistable device IC5 and the complementary count logic output from the bistable device 106 are applied to an AND gate IC7. The output from this AND gate and the logic count output from the bistable IC6 are applied to analogue switching means 51 to S4 of a wave-shapi ng circuit including capacitors C1 to C6 of which the capacitors C1 to C4 are arranged to be selectively connected, or disconnected, by the analogue switching means 51 to S4 into or out of circuit with a line driver LDfor shaping data pulses DP1 which are synchronised with the timing signals TP1 having a period "t" and which are applied to the input of the line driver LD.

After shaping, the data pulses SDP1 are transmitted overthetransmission channel TL.

As will be appreciated, the device IC6 and the AND gate IC7 produce mutually exclusive outputs. Consequently, when the switches S1 and S2 are closed the switches S3 and S4 are open and vice versa. In the absence of a logic 1 output from the gate IC7 or the device IC6 all switches S1 to S4 are open and the baud rate of 2400 is selected. It will also be apprecia tedthatto prevent spurious outputs from low order counter outputs the lowest baud rate (i.e. highest count) outputs inhibit other high baud rate outputs by means of the gate IC7.

The selective operation of the analogue switching means S1 to S4for producing the requisite shaping of the data pulses of the respective baud rates of 2,400,300 and 75 is shown in the table of Figure 3. By referring to the binary counter output table in Figure 2 itwill readily be seen that the logic 0 and/or 1 outputs at terminals Q9 and Q1 1 forthe respective baud rates will produce the switch operations shown in Figure 3.

The pulse widths and rise times for the shaped data pulses atthethree baud rates concerned are shown in Figures 2 and 3.

As will be appreciated from the foregoing, during transmission of data pulses the incoming timing signals will be continuously sampled by the clock binary counter IC2 and a change in baud rate of these timing signals will produce a different binary count output at terminals Q9 and Q1 1 at the end of a positive excursion of timing signal which in turn will produce modification of the capacitive wave-shaping circuit to vary, as appropriate, the shaping of the data pulsesfortransmission overthe data transmission line or channel TL.

It will of course be appreciated thatthe circuit arrangement described may readily be modified to provide for an extended range of baud rates (e.g. 75, 150,300,600,1,200 and 2,400,4,800 or9,600 orsubsets thereof).

Claims (7)

1. A data transmission system in which a train of rectangular data pulses of logic 0 and/or logic 1 significance is produced in synchronism with a train of rectangulartiming signals and in which the baud rate ofthetiming signals is measured by timing signal sampling means and the degree of steepness of the leading and trailing edges of the data pulses is automatically adjusted in dependence upon the measured baud rate.

2. Adatatransmission system as claimed in claim 1, in which the timing signal sampling means comprises a binary counterwhich is stepped by clock pulses having a relatively high repetition frequency compared to the frequency of the timing signals.

3. Adatatransmission system as claimed in claim 2, in which the binary counter is stepped by the clock pulses during the positive excursion of each timing signal.

4. A data transmission system as claimed in claim 3, in which an outputfrom the binary counter atthe end of the positive excursion of a timing signal produces selective operation of switching meansfor the adjustment ofthe effective capacitance of a wave-shaping circuit in order to shape the data pulses to be transmitted over the serial linktransmission path.

5. Adata transmission system as claimed in claim 4, in which the switching means is operated by outputs from flip-flop means connected to respective outputterminals of the binary counter.

6. A data transmission system as claimed in claimS, in which the flip-flop means are arranged to be latched by the trailing edge of each timing signal during sampling, thereby aliowing the binary counterto be re-set in readiness for sampling the next timing signal.

7. A data transmission system substantially as hereinbefore described with reference to the accompanying drawings.