EP1870903A2 - Über einen temperaturgesteuerten Impuls programmierte Speicherzelle - Google Patents
Über einen temperaturgesteuerten Impuls programmierte Speicherzelle Download PDFInfo
- Publication number
- EP1870903A2 EP1870903A2 EP07011897A EP07011897A EP1870903A2 EP 1870903 A2 EP1870903 A2 EP 1870903A2 EP 07011897 A EP07011897 A EP 07011897A EP 07011897 A EP07011897 A EP 07011897A EP 1870903 A2 EP1870903 A2 EP 1870903A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- memory cell
- current
- phase change
- memory
- applying
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0078—Write using current through the cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0092—Write characterized by the shape, e.g. form, length, amplitude of the write pulse
Definitions
- Resistive memory utilizes the resistance value of a memory element to store one or more bits of data.
- a memory element programmed to have a high resistance value may represent a logic "1" data bit value
- a memory element programmed to have a low resistance value may represent a logic "0" data bit value.
- the resistance value of the memory element is switched electrically by applying a voltage pulse or a current pulse to the memory element.
- resistive memory is phase change memory. Phase change memory uses a phase change material in the resistive memory element.
- Phase change memories are based on phase change materials that exhibit at least two different states.
- Phase change material may be used in memory cells to store bits of data.
- the states of phase change material may be referred to as amorphous and crystalline states.
- the states may be distinguished because the amorphous state generally exhibits higher resistivity than does the crystalline state.
- the amorphous state involves a more disordered atomic structure, while the crystalline state involves a more ordered lattice.
- Some phase change materials exhibit more than one crystalline state, e.g. a face-centered cubic (FCC) state and a hexagonal closest packing (HCP) state.
- FCC face-centered cubic
- HCP hexagonal closest packing
- Phase change in the phase change materials may be induced reversibly.
- the memory may change from the amorphous state to the crystalline state and from the crystalline state to the amorphous state in response to temperature changes.
- the temperature changes to the phase change material may be achieved in a variety of ways.
- a laser can be directed to the phase change material, current may be driven through the phase change material, or current can be fed through a resistive heater adjacent the phase change material.
- controllable heating of the phase change material causes controllable phase change within the phase change material.
- a phase change memory including a memory array having a plurality of memory cells that are made of phase change material may be programmed to store data utilizing the memory states of the phase change material.
- One way to read and write data in such a phase change memory device is to control a current and/or a voltage pulse that is applied to the phase change material.
- the level of current and/or voltage generally corresponds to the temperature induced within the phase change material in each memory cell.
- a phase change memory cell can store multiple bits of data.
- Multi-bit storage in a phase change memory cell can be achieved by programming the phase change material to have intermediate resistance values or states. Cells in such intermediate states have a resistance that lies between the fully crystalline state and the fully amorphous state. If the phase change memory cell is programmed to one of three different resistance levels, 1.5 bits of data per cell can be stored. If the phase change memory cell is programmed to one of four different resistance levels, two bits of data per cell can be stored, and so on.
- the description in this disclosure is substantially focused on four different resistance levels or states and two bits of data per cell. This is for illustrative purposes only, however, and not intended to limit the scope of the invention. In principle it is possible to store three or more states.
- the amount of crystalline material coexisting with amorphous material and hence the cell resistance is controlled via a suitable write strategy.
- the amount of crystalline material coexisting with amorphous material should be precisely controlled to ensure consistent resistance values for multi-bit storage. Consistent resistance values having a narrow distribution of the different resistance levels ensure that a sufficient sensing margin can be obtained.
- the memory device includes a phase change memory cell and a circuit.
- the circuit is for programming the memory cell to a selected one of more than two states by applying a temperature controlled set pulse to the memory cell.
- FIG. 1 is a block diagram illustrating one embodiment of a memory device 100.
- Memory device 100 includes a write circuit 102, a distribution circuit 104, memory cells 106a, 106b, 106c, and 106d, and a sense circuit 108.
- Each of the memory cells 106a-106d is a phase change memory cell that stores data based on the amorphous and crystalline states of phase change material in the memory cell.
- each of the memory cells 106a-106d can be programmed into more than two states by programming the phase change material to have intermediate resistance values.
- the amount of crystalline material coexisting with amorphous material - and hence the cell resistance - is controlled via a suitable write strategy.
- Memory device 100 is configured to program memory cells 106a-106d by controlling the amount of crystallized material by monitoring the memory cell temperature and/or resistance. At the correct temperature, the amount of crystallized phase change material can be controlled by time. In addition, the phase change memory cell resistance provides an indication of the memory cell temperature. Therefore, by controlling the length of a write pulse at a specified temperature as measured by the resistance of the memory cell, each phase change memory cell 106a-106d is programmed to a selected state of more than two possible states.
- electrically coupled is not meant to mean that the elements must be directly coupled together and intervening elements may be provided between the “electrically coupled” elements.
- Write circuit 102 is electrically coupled to distribution circuit 104 through signal path 110.
- Distribution circuit 104 is electrically coupled to each of the memory cells 106a-106d through signal paths 112a-112d.
- Distribution circuit 104 is electrically coupled to memory cell 106a through signal path 112a.
- Distribution circuit 104 is electrically coupled to memory cell 106b through signal path 112b.
- Distribution circuit 104 is electrically coupled to memory cell 106c through signal path 112c.
- Distribution circuit 104 is electrically coupled to memory cell 106d through signal path 112d.
- distribution circuit 104 is electrically coupled to sense circuit 108 through signal path 114, and sense circuit 108 is electrically coupled to write circuit 102 through signal path 116.
- Each of the memory cells 106a-106d includes phase change material (i.e., a phase change element) that may be changed from an amorphous state to a crystalline state or from a crystalline state to an amorphous state under the influence of temperature change.
- phase change material i.e., a phase change element
- the amount of crystalline material coexisting with amorphous material in the phase change material of one of the memory cells 106a-106d thereby defines more than two states for storing data within memory device 100. In the amorphous state, a phase change material exhibits significantly higher resistivity than in the crystalline state. Therefore, the more than two states of memory cells 106a-106d differ in their electrical resistivity.
- the more than two states can be three states and a trinary system can be used, wherein the three states are assigned bit values of "0", “1", and "2". In one embodiment, the more than two states are four states that can be assigned multi-bit values, such as "00", "01", “10", and "11". In other embodiments, the more than two states can be any suitable number of states in the phase change material of a memory cell.
- Write circuit 102 provides pulses to memory cells 106a-106d and programs one of the more than two resistance levels or states into the phase change material of each of the memory cells 106a-106d.
- write circuit 102 provides voltage pulses to distribution circuit 104 through signal path 110 and distribution circuit 104 controllably directs the voltage pulses to memory cells 106a-106d through signal paths 112a-112d.
- distribution circuit 104 includes a plurality of transistors that controllably direct voltage pulses to each of the memory cells 106a-106d.
- write circuit 102 provides current pulses to distribution circuit 104 through signal path 110 and distribution circuit 104 controllably directs the current pulses to memory cells 106a-106d through signal paths 112a-112d.
- Sense circuit 108 senses the state of each memory cell and provides signals that indicate the state of the resistance of each memory cell. Sense circuit 108 reads each of the more than two states of memory cells 106a-106d through signal path 114.
- Distribution circuit 104 controllably directs read signals between sense circuit 108 and memory cells 106a-106d through signal paths 112a-112d.
- distribution circuit 104 includes a plurality of transistors that controllably direct read signals between sense circuit 108 and memory cells 106a-106d.
- write circuit 102 resets the phase change material in a target memory cell 106a-106d.
- a reset operation includes heating the phase change material of the target memory cell above its melting temperature and quickly cooling the phase change material to thereby achieve a substantially amorphous state.
- This amorphous state is one of the more than two states of each of the memory cells 106a-106d and is the highest resistance state.
- write circuit 102 programs a selected one of the more than two states into the target memory cell.
- Write circuit 102 provides a signal to the target memory cell to crystallize part of the phase change material and thereby lower the resistance of the target memory cell.
- write circuit 102 sets the phase change material in a target memory cell 106a-106d.
- a set operation includes heating the phase change material of the target memory cell above its crystallization temperature (but usually below its melting temperature) to thereby achieve a substantially crystalline state.
- This crystalline state is one of the more than two states of each of the memory cells 106a-106d and is the lowest resistance state.
- write circuit 102 programs a selected one of the more than two states into the target memory cell.
- Write circuit 102 provides a signal to the target memory cell to transition a portion of the phase change material to an amorphous state and thereby raise the resistance of the target memory cell.
- FIG. 2 is a diagram illustrating one embodiment of a memory cell 202 in four different states at 200a, 200b, 200c, and 200d.
- Memory cell 202 includes a phase change material 204 that is situated in insulation material 206.
- memory cell 202 can have any suitable geometry including phase change material 204 in any suitable geometry and insulation material 206 in any suitable geometry.
- Phase change material 204 is electrically coupled at one end to a first electrode 208 and at the other end to a second electrode 210. Pulses are provided to memory cell 202 via first electrode 208 and second electrode 210. The current path through phase change material 204 is from one of the first electrode 208 and second electrode 210 to the other one of the first electrode 208 and second electrode 210. In one embodiment, each of the memory cells 106a-106d is similar to memory cell 202. Memory cell 202 provides a storage location for storing bits of data.
- Insulation material 206 can be any suitable insulator, such as SiO 2 , fluorinated silica glass (FSG), or boro-phosphorous silicate glass (BPSG).
- First electrode 208 and second electrode 210 can be any suitable electrode material, such as TiN, TaN, W, Al, Ti, Ta, TiSiN, TaSiN, TiAlN, TaAlN, or Cu.
- Phase change material 204 may be made up of a variety of materials in accordance with the present invention. Generally, chalcogenide alloys that contain one or more elements from group VI of the periodic table are useful as such materials.
- phase change material 204 of memory cell 202 is made up of a chalcogenide compound material, such as GeSbTe, SbTe, GeTe, or AgInSbTe.
- phase change material 204 is chalcogen free, such as GeSb, GaSb, InSb, or GeGaInSb.
- phase change material 204 is made up of any suitable material including one or more of the elements Ge, Sb, Te, Ga, As, In, Se, and S.
- Phase change material 204 is programmed into one of four states to store two bits of data.
- a selection device such as an active device like a transistor or diode, is coupled to first electrode 208 to control the application of pulses to phase change material 204.
- the pulses reset phase change material 204 and program one of the other three states into phase change material 204.
- a small fraction 212 of phase change material 204 has been programmed to change the resistance through phase change material 204 and memory cell 202.
- a medium sized fraction 214 of phase change material 204 has been programmed to change the resistance through phase change material 204 and memory cell 202.
- a large fraction 216 which is substantially all of phase change material 204, has been programmed to change the resistance through phase change material 204 and memory cell 202.
- the size of the programmed fraction is related to the resistance through phase change material 204 and memory cell 202.
- the three different phase change fractions at 200b-200d plus the initial state at 200a provide four states in phase change material 204, and memory cell 202 provides a storage location for storing two bits of data.
- the state of memory cell 202 at 200a is a "00”
- the state of memory cell 202 at 200b is a "01”
- the state of memory cell 202 at 200c is a "10”
- the state of memory cell 202 at 200d is a "11".
- phase change material 204 is reset to a substantially amorphous state.
- a reset pulse is selectively enabled by the selection device and sent through first electrode 208 and phase change material 204.
- the reset pulse heats phase change material 204 above its melting temperature and phase change material 204 is quickly cooled to achieve the substantially amorphous state at 200a.
- phase change material 204 includes crystalline state phase change material at 218 and 220, and amorphous state phase change material at 222.
- the substantially amorphous state at 200a is the highest resistance state of memory cell 202.
- a temperature controlled set pulse is provided via a write circuit, such as write circuit 102.
- a temperature controlled set pulse is provided to program the small volume fraction 212 into a crystalline state.
- the crystalline state is less resistive than the amorphous state and memory cell 202 at 200b has a lower resistance than memory cell 202 in the substantially amorphous state at 200a.
- the partially crystalline and partially amorphous state at 200b is the second highest resistance state of memory cell 202.
- a temperature controlled set pulse is provided to program the medium volume fraction 214 into a crystalline state. Since the crystalline fraction 214 is larger than the crystalline faction 212 and the crystalline state is less resistive than the amorphous state, memory cell 202 at 200c has a lower resistance than memory cell 202 at 200b and memory cell 202 in the amorphous state at 200a. The partially crystalline and partially amorphous state at 200c is the second lowest resistance state of memory cell 202.
- a temperature controlled set pulse is provided to program substantially all of the phase change material 216 into the crystalline state. Since the crystalline state is less resistive than the amorphous state, memory cell 202 at 200d has a lower resistance than memory cell 202 at 200c, memory cell 202 at 200b, and memory cell 202 in the amorphous state at 200a.
- the substantially crystalline state at 200d is the lowest resistance state of memory cell 202.
- memory cell 202 can be programmed into any suitable number of resistance values or states.
- memory cell 202 can be set to a substantially crystalline state and reset pulses can be used to program memory cell 202 to the desired resistance value or state.
- Figure 3 is a graph 230 illustrating one embodiment of the crystallization of phase change material based on temperature and time.
- Graph 230 includes the log of time on x-axis 232 and temperature on y-axis 234.
- T MELT indicated at 240
- the phase change material liquefies.
- Tx indicated at 238 up until a minimum time (T MIN ) indicated at 236, the phase change material remains amorphous.
- T MIN the phase change material begins to crystallize.
- approximately 1% of the phase change material is crystallized.
- phase change material After a second period as indicated at 244, approximately 50% of the phase change material is crystallized, and after a third period as indicated at 246, approximately 99% of the phase change material is crystallized. Therefore, by controlling the temperature of the phase change material and the length of time at that temperature, the amount of crystallized phase change material can be controlled.
- Figure 4 is a graph 260 illustrating one embodiment of the relationship between resistance and temperature for phase change material.
- Graph 260 includes temperature in Kelvin (K) on x-axis 262 and resistance in kiloohms (k ⁇ ) on y-axis 264.
- K Kelvin
- k ⁇ resistance in kiloohms
- the relationship between the temperature of the phase change material during programming and the resistance is illustrated by curve 266.
- the resistance of the phase change material is approximately 5.6k ⁇ .
- higher programming temperatures, such as 1000K the resistance of the phase change material is approximately 1.5k ⁇ . Therefore, by determining the resistance of the phase change material during programming, the temperature of the phase change material can be determined.
- Figure 5 is a graph 300 illustrating one embodiment of a temperature controlled set pulse for programming a phase change memory cell.
- Graph 300 includes time on x-axis 302, current and voltage on axis 304, and resistance on axis 306. Voltage versus time is indicated by curve 318, current versus time is indicated by curve 320, and resistance verses time is indicated by curve 316.
- the temperature controlled set pulse includes four phases indicated at 308, 310, 312, and 314.
- a small current is applied to a memory cell to reach the threshold voltage of the phase change material as indicated at 322 of voltage curve 318.
- the current is increased until the desired temperature of the memory cell is reached.
- the temperature is determined by monitoring the resistance of the memory cell. The desired temperature as indicated by the resistance is reached at 324 of resistance curve 316.
- the current and voltage applied to the memory cell are maintained at constant values for a set period to crystallize a desired portion of the phase change material.
- the desired portion of phase change material crystallized determines the programmed state of the memory cell.
- the desired portion of phase change material has been crystallized.
- the current is ramped down to zero. In this way, the phase change memory cell is programmed to a desired state based on the temperature of the phase change material and the length of the write pulse in the third phase at 312.
- write circuit 102 includes a current pulse generator to provide a current pulse on a bit line coupled to a selected memory cell.
- the bit line current and the bit line voltage are monitored to determine the memory cell resistance and hence the temperature of the memory cell.
- write circuit 102 includes a voltage source to apply a voltage to a bit line coupled to a selected memory cell.
- a voltage is applied to a word line, which controls an access device coupled to the selected memory cell, to provide a current pulse from the access device to the selected memory cell.
- the word line and bit line voltages are monitored to determine the memory cell resistance and hence the temperature of the memory cell.
- other methods of generating the current pulse are used. In any case, the current pulse is temperature controlled to program the selected memory cell to a desired resistance state.
- FIG. 6 is a graph 350 illustrating one embodiment of temperature controlled set pulses for programming a phase change memory cell to one of multiple states.
- Graph 350 includes time on x-axis 352 and current on y-axis 354.
- Temperature controlled set pulse 356 programs a memory cell to a first state such as state 200b of memory cell 202 illustrated in Figure 2.
- Temperature controlled set pulse 358 which provides a greater current than temperature controlled set pulse 356, programs a memory cell to a second state, such as state 200c of memory cell 202 illustrated in Figure 2.
- Temperature controlled set pulse 360 which provides a greater current than temperature controlled set pulse 358, programs a memory cell to a third state, such as state 200d of memory cell 202 illustrated in Figure 2.
- Temperature controlled set pulses 356, 358, and 360 all have the same pulse length but they have different target temperatures and hence current level plateaus for programming a memory cell to different states.
- Figure 7 is a flow diagram illustrating one embodiment of a method 400 for programming a phase change memory cell.
- write circuit 102 resets a selected memory cell 106a-106d to an amorphous state or substantially amorphous state, such as the substantially amorphous state 200a of memory cell 202 illustrated in Figure 2.
- a target temperature/resistance to maintain during the pulse application and a pulse length is selected.
- the memory cell resistance is evaluated during the application of the current pulse and the current pulse plateau level is adjusted based on the resistance.
- the pulse is held for a predetermined time to program the phase change memory cell to the desired state.
- the pulse is shut off and the programming of the memory cell is finished.
- Figure 8 is a flow diagram illustrating another embodiment of a method 450 for programming a phase change memory cell.
- write circuit 102 resets a selected memory cell 106a-106d to an amorphous state or substantially amorphous state, such as the substantially amorphous state 200a of memory cell 202 illustrated in Figure 2.
- a target temperature to maintain during the pulse application and a pulse length is selected.
- the current is ramped up while monitoring the phase change element (PCE) voltage of the memory cell to evaluate the phase change element resistance.
- PCE phase change element
- the resistance of the phase change element provides an indication of the temperature of the phase change element.
- the ramp up of the current is stopped and the current and voltage levels are maintained at constant levels.
- the pulse is applied for the predetermined pulse length to program the phase change memory cell to the desired state.
- the pulse is shut off and the programming of the memory cell is complete.
- Embodiments of the present invention provide a temperature controlled set pulse for programming a phase change memory cell to one of more than at least two resistance level or states.
- the temperature controlled set pulse is based on the temperature of the memory cell as determined by monitoring the resistance of the memory cell during the set pulse and on a crystallization time of the memory cell at that temperature. In this way, precise control over the programming of memory cells to intermediate resistance values for multi-bit storage applications is possible.
Landscapes
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
- Read Only Memory (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/455,340 US7457146B2 (en) | 2006-06-19 | 2006-06-19 | Memory cell programmed using a temperature controlled set pulse |
Publications (3)
Publication Number | Publication Date |
---|---|
EP1870903A2 true EP1870903A2 (de) | 2007-12-26 |
EP1870903A3 EP1870903A3 (de) | 2008-11-19 |
EP1870903B1 EP1870903B1 (de) | 2013-05-01 |
Family
ID=38457994
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP07011897.1A Not-in-force EP1870903B1 (de) | 2006-06-19 | 2007-06-18 | Über einen temperaturgesteuerten Impuls programmierte Speicherzelle |
Country Status (5)
Country | Link |
---|---|
US (1) | US7457146B2 (de) |
EP (1) | EP1870903B1 (de) |
JP (2) | JP2008059736A (de) |
KR (1) | KR20070120455A (de) |
CN (1) | CN101093723B (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2012067660A1 (en) | 2010-11-19 | 2012-05-24 | Hewlett-Packard Development Company, L.P. | Method and circuit for switching a memristive device |
Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7085154B2 (en) * | 2003-06-03 | 2006-08-01 | Samsung Electronics Co., Ltd. | Device and method for pulse width control in a phase change memory device |
US7423901B2 (en) * | 2006-03-03 | 2008-09-09 | Marvell World Trade, Ltd. | Calibration system for writing and reading multiple states into phase change memory |
KR100825777B1 (ko) * | 2006-09-26 | 2008-04-29 | 삼성전자주식회사 | 상 변화 메모리 장치의 파이어링 방법 및 상 변화 메모리장치 |
US7564710B2 (en) * | 2007-04-30 | 2009-07-21 | Qimonda North America Corp. | Circuit for programming a memory element |
JP5503102B2 (ja) * | 2007-07-04 | 2014-05-28 | ピーエスフォー ルクスコ エスエイアールエル | 相変化メモリ装置 |
KR100919565B1 (ko) * | 2007-07-24 | 2009-10-01 | 주식회사 하이닉스반도체 | 상 변화 메모리 장치 |
US7997791B2 (en) * | 2007-07-24 | 2011-08-16 | Qimonda Ag | Temperature sensor, integrated circuit, memory module, and method of collecting temperature treatment data |
KR100944343B1 (ko) * | 2007-08-10 | 2010-03-02 | 주식회사 하이닉스반도체 | 상 변화 메모리 장치 |
KR100934851B1 (ko) * | 2007-08-10 | 2010-01-06 | 주식회사 하이닉스반도체 | 상 변화 메모리 장치 및 그 동작방법 |
KR100919582B1 (ko) * | 2007-08-10 | 2009-10-01 | 주식회사 하이닉스반도체 | 상 변화 메모리 장치 |
KR101390337B1 (ko) * | 2007-09-13 | 2014-04-29 | 삼성전자주식회사 | 멀티-레벨 상변환 메모리 장치, 그것의 프로그램 방법,그리고 그것을 포함한 메모리 시스템 |
KR20090075539A (ko) * | 2008-01-04 | 2009-07-08 | 삼성전자주식회사 | 단일 조성의 반금속 박막을 이용한 상변화 메모리 |
JP5223005B2 (ja) * | 2009-07-06 | 2013-06-26 | 株式会社日立製作所 | 半導体記憶装置およびその製造方法 |
US8441847B2 (en) * | 2009-09-23 | 2013-05-14 | International Business Machines Corporation | Programming multi-level phase change memory cells |
US8289762B2 (en) * | 2009-10-30 | 2012-10-16 | Intel Corporation | Double-pulse write for phase change memory |
CN101901632B (zh) * | 2010-08-11 | 2015-12-02 | 上海华虹宏力半导体制造有限公司 | 监控位线电压的监控电路及监控方法 |
US8971091B2 (en) * | 2010-11-19 | 2015-03-03 | Hewlett-Packard Development Company, L.P. | Method and circuit for switching a memristive device in an array |
US9021227B2 (en) * | 2011-06-22 | 2015-04-28 | Intel Corporation | Drift management in a phase change memory and switch (PCMS) memory device |
PL3002657T3 (pl) * | 2012-09-11 | 2017-07-31 | Philip Morris Products S.A. | Urządzenie i sposób sterowania elektrycznym ogrzewaczem celem ograniczania temperatury |
WO2015195141A1 (en) * | 2014-06-20 | 2015-12-23 | Hewlett-Packard Development Company, L. P. | Memristive memory cell resistance switch monitoring |
US9343149B2 (en) * | 2014-07-10 | 2016-05-17 | Micron Technology, Inc. | Enhancing nucleation in phase-change memory cells |
TWI649748B (zh) * | 2015-01-14 | 2019-02-01 | 財團法人工業技術研究院 | 電阻式隨機存取記憶體與其控制方法 |
US9583187B2 (en) | 2015-03-28 | 2017-02-28 | Intel Corporation | Multistage set procedure for phase change memory |
US9792986B2 (en) * | 2015-05-29 | 2017-10-17 | Intel Corporation | Phase change memory current |
FR3041807B1 (fr) * | 2015-09-24 | 2017-12-08 | Stmicroelectronics Rousset | Procede de controle d'un cycle d'ecriture de memoire de type eeprom et dispositif correspondant |
CN106571160A (zh) * | 2015-10-13 | 2017-04-19 | 中芯国际集成电路制造(上海)有限公司 | 一种相变存储器的处理方法 |
US10998044B2 (en) | 2017-01-20 | 2021-05-04 | Hefei Reliance Memory Limited | RRAM write using a ramp control circuit |
KR102614852B1 (ko) | 2018-11-14 | 2023-12-19 | 삼성전자주식회사 | 메모리 장치, 메모리 셀 및 메모리 셀 프로그래밍 방법 |
US11631462B2 (en) * | 2020-02-10 | 2023-04-18 | International Business Machines Corporation | Temperature assisted programming of flash memory for neuromorphic computing |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030123277A1 (en) * | 2001-12-28 | 2003-07-03 | Tyler Lowrey | Method and apparatus to program a phase change memory |
EP1450373A1 (de) * | 2003-02-21 | 2004-08-25 | STMicroelectronics S.r.l. | Phasenwechselspeicheranordnung |
US20040228159A1 (en) * | 2003-05-13 | 2004-11-18 | Kostylev Sergey A. | Method of eliminating drift in phase-change memory |
EP1557841A2 (de) * | 2004-01-20 | 2005-07-27 | Sony Corporation | Resistiver Multibitspeicher und Schreib-Lösch-Verfahren zu dessen Anwendung |
US20060109707A1 (en) * | 2004-11-23 | 2006-05-25 | Infineon Technologies North America Corp. | Energy adjusted write pulses in phase-change memories |
EP1755126A1 (de) * | 2005-08-15 | 2007-02-21 | Qimonda AG | Speichervorrichtung, die mehr als zwei Zustände in eine Speicherzelle programmiert |
EP1865512A2 (de) * | 2006-06-09 | 2007-12-12 | Qimonda North America Corp. | Verwendung von Strom aus einer Zugangsvorrichtung zur Programmierung einer Speicherzelle |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3530441A (en) * | 1969-01-15 | 1970-09-22 | Energy Conversion Devices Inc | Method and apparatus for storing and retrieving information |
US5536947A (en) * | 1991-01-18 | 1996-07-16 | Energy Conversion Devices, Inc. | Electrically erasable, directly overwritable, multibit single cell memory element and arrays fabricated therefrom |
US5296716A (en) * | 1991-01-18 | 1994-03-22 | Energy Conversion Devices, Inc. | Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom |
US6141241A (en) * | 1998-06-23 | 2000-10-31 | Energy Conversion Devices, Inc. | Universal memory element with systems employing same and apparatus and method for reading, writing and programming same |
US6075719A (en) * | 1999-06-22 | 2000-06-13 | Energy Conversion Devices, Inc. | Method of programming phase-change memory element |
US6570784B2 (en) * | 2001-06-29 | 2003-05-27 | Ovonyx, Inc. | Programming a phase-change material memory |
US6487113B1 (en) * | 2001-06-29 | 2002-11-26 | Ovonyx, Inc. | Programming a phase-change memory with slow quench time |
US6512241B1 (en) * | 2001-12-31 | 2003-01-28 | Intel Corporation | Phase change material memory device |
US6759267B2 (en) * | 2002-07-19 | 2004-07-06 | Macronix International Co., Ltd. | Method for forming a phase change memory |
US6768665B2 (en) * | 2002-08-05 | 2004-07-27 | Intel Corporation | Refreshing memory cells of a phase change material memory device |
JP4094006B2 (ja) | 2002-09-11 | 2008-06-04 | オヴォニクス,インコーポレイテッド | 相変化材料メモリにプログラムする方法 |
KR100546322B1 (ko) * | 2003-03-27 | 2006-01-26 | 삼성전자주식회사 | 비휘발성 메모리와 휘발성 메모리로 선택적으로 동작할 수있는 상 변화 메모리 장치 및 상 변화 메모리 장치의 동작방법 |
KR100564567B1 (ko) * | 2003-06-03 | 2006-03-29 | 삼성전자주식회사 | 상 변화 메모리의 기입 드라이버 회로 |
US7085154B2 (en) * | 2003-06-03 | 2006-08-01 | Samsung Electronics Co., Ltd. | Device and method for pulse width control in a phase change memory device |
KR100558548B1 (ko) * | 2003-11-27 | 2006-03-10 | 삼성전자주식회사 | 상변화 메모리 소자에서의 라이트 드라이버 회로 및라이트 전류 인가방법 |
JP4567963B2 (ja) * | 2003-12-05 | 2010-10-27 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
TW200527656A (en) * | 2004-02-05 | 2005-08-16 | Renesas Tech Corp | Semiconductor device |
TWI288931B (en) * | 2004-06-19 | 2007-10-21 | Samsung Electronics Co Ltd | Phase-change memory element driver circuits using measurement to control current and methods of controlling drive current of phase-change memory elements using measurement |
KR100650098B1 (ko) | 2005-03-11 | 2006-11-28 | 오보닉스, 아이엔씨. | 상변화 재료 메모리를 프로그램하는 방법 |
-
2006
- 2006-06-19 US US11/455,340 patent/US7457146B2/en not_active Expired - Fee Related
-
2007
- 2007-06-18 JP JP2007159775A patent/JP2008059736A/ja not_active Withdrawn
- 2007-06-18 EP EP07011897.1A patent/EP1870903B1/de not_active Not-in-force
- 2007-06-19 CN CN2007101115657A patent/CN101093723B/zh not_active Expired - Fee Related
- 2007-06-19 KR KR1020070059789A patent/KR20070120455A/ko not_active Application Discontinuation
-
2010
- 2010-11-12 JP JP2010254001A patent/JP2011060418A/ja active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030123277A1 (en) * | 2001-12-28 | 2003-07-03 | Tyler Lowrey | Method and apparatus to program a phase change memory |
EP1450373A1 (de) * | 2003-02-21 | 2004-08-25 | STMicroelectronics S.r.l. | Phasenwechselspeicheranordnung |
US20040228159A1 (en) * | 2003-05-13 | 2004-11-18 | Kostylev Sergey A. | Method of eliminating drift in phase-change memory |
EP1557841A2 (de) * | 2004-01-20 | 2005-07-27 | Sony Corporation | Resistiver Multibitspeicher und Schreib-Lösch-Verfahren zu dessen Anwendung |
US20060109707A1 (en) * | 2004-11-23 | 2006-05-25 | Infineon Technologies North America Corp. | Energy adjusted write pulses in phase-change memories |
EP1755126A1 (de) * | 2005-08-15 | 2007-02-21 | Qimonda AG | Speichervorrichtung, die mehr als zwei Zustände in eine Speicherzelle programmiert |
EP1865512A2 (de) * | 2006-06-09 | 2007-12-12 | Qimonda North America Corp. | Verwendung von Strom aus einer Zugangsvorrichtung zur Programmierung einer Speicherzelle |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2012067660A1 (en) | 2010-11-19 | 2012-05-24 | Hewlett-Packard Development Company, L.P. | Method and circuit for switching a memristive device |
EP2641331A4 (de) * | 2010-11-19 | 2017-07-26 | Hewlett-Packard Enterprise Development LP | Verfahren und schaltung zum umschalten einer memresistiven vorrichtung |
Also Published As
Publication number | Publication date |
---|---|
CN101093723B (zh) | 2012-01-04 |
CN101093723A (zh) | 2007-12-26 |
KR20070120455A (ko) | 2007-12-24 |
EP1870903A3 (de) | 2008-11-19 |
US7457146B2 (en) | 2008-11-25 |
EP1870903B1 (de) | 2013-05-01 |
JP2008059736A (ja) | 2008-03-13 |
JP2011060418A (ja) | 2011-03-24 |
US20070297221A1 (en) | 2007-12-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP1870903B1 (de) | Über einen temperaturgesteuerten Impuls programmierte Speicherzelle | |
US7539050B2 (en) | Resistive memory including refresh operation | |
US7571901B2 (en) | Circuit for programming a memory element | |
US7719886B2 (en) | Multi-level resistive memory cell using different crystallization speeds | |
US7426134B2 (en) | Sense circuit for resistive memory | |
US7593255B2 (en) | Integrated circuit for programming a memory element | |
US7626858B2 (en) | Integrated circuit having a precharging circuit | |
US7615770B2 (en) | Integrated circuit having an insulated memory | |
US7623401B2 (en) | Semiconductor device including multi-bit memory cells and a temperature budget sensor | |
US7372725B2 (en) | Integrated circuit having resistive memory | |
US7292466B2 (en) | Integrated circuit having a resistive memory | |
EP1858093A2 (de) | Speicherzelle mit dotiertem Phasenwechselmaterial | |
US7577023B2 (en) | Memory including write circuit for providing multiple reset pulses | |
US7929336B2 (en) | Integrated circuit including a memory element programmed using a seed pulse | |
US7692949B2 (en) | Multi-bit resistive memory | |
US7564710B2 (en) | Circuit for programming a memory element | |
US20080165573A1 (en) | Memory including two access devices per phase change element | |
US7551476B2 (en) | Resistive memory having shunted memory cells | |
US7031181B1 (en) | Multi-pulse reset write scheme for phase-change memories | |
US20090027943A1 (en) | Resistive memory including bidirectional write operation |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC MT NL PL PT RO SE SI SK TR |
|
AX | Request for extension of the european patent |
Extension state: AL BA HR MK YU |
|
PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
|
AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC MT NL PL PT RO SE SI SK TR |
|
AX | Request for extension of the european patent |
Extension state: AL BA HR MK RS |
|
17P | Request for examination filed |
Effective date: 20090518 |
|
17Q | First examination report despatched |
Effective date: 20090622 |
|
AKX | Designation fees paid |
Designated state(s): DE FR GB |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: QIMONDA AG |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R079 Ref document number: 602007030113 Country of ref document: DE Free format text: PREVIOUS MAIN CLASS: G11C0016020000 Ipc: G11C0013000000 |
|
RIC1 | Information provided on ipc code assigned before grant |
Ipc: G11C 11/56 20060101ALI20121008BHEP Ipc: G11C 13/00 20060101AFI20121008BHEP |
|
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
GRAS | Grant fee paid |
Free format text: ORIGINAL CODE: EPIDOSNIGR3 |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): DE FR GB |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R081 Ref document number: 602007030113 Country of ref document: DE Owner name: INFINEON TECHNOLOGIES AG, DE Free format text: FORMER OWNER: QIMONDA NORTH AMERICA CORP., CARY, N.C., US Ref country code: DE Ref legal event code: R081 Ref document number: 602007030113 Country of ref document: DE Owner name: POLARIS INNOVATIONS LTD., IE Free format text: FORMER OWNER: QIMONDA NORTH AMERICA CORP., CARY, N.C., US |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R096 Ref document number: 602007030113 Country of ref document: DE Effective date: 20130627 |
|
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
26N | No opposition filed |
Effective date: 20140204 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R097 Ref document number: 602007030113 Country of ref document: DE Effective date: 20140204 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20140723 Year of fee payment: 8 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R081 Ref document number: 602007030113 Country of ref document: DE Owner name: INFINEON TECHNOLOGIES AG, DE Free format text: FORMER OWNER: QIMONDA AG, 81739 MUENCHEN, DE Ref country code: DE Ref legal event code: R081 Ref document number: 602007030113 Country of ref document: DE Owner name: POLARIS INNOVATIONS LTD., IE Free format text: FORMER OWNER: QIMONDA AG, 81739 MUENCHEN, DE |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 9 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 20150618 Year of fee payment: 9 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 20150619 Year of fee payment: 9 |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: 732E Free format text: REGISTERED BETWEEN 20150827 AND 20150902 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R081 Ref document number: 602007030113 Country of ref document: DE Owner name: POLARIS INNOVATIONS LTD., IE Free format text: FORMER OWNER: INFINEON TECHNOLOGIES AG, 85579 NEUBIBERG, DE |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R119 Ref document number: 602007030113 Country of ref document: DE |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: TP Owner name: INFINEON TECHNOLOGIES AG, DE Effective date: 20160212 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: DE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20160101 |
|
GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20160618 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: ST Effective date: 20170228 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20160630 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20160618 |