EP0525985B1 - Interface de liaison bidirectionnelle de données à haute vitesse - Google Patents

Interface de liaison bidirectionnelle de données à haute vitesse Download PDF

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Publication number
EP0525985B1
EP0525985B1 EP92305979A EP92305979A EP0525985B1 EP 0525985 B1 EP0525985 B1 EP 0525985B1 EP 92305979 A EP92305979 A EP 92305979A EP 92305979 A EP92305979 A EP 92305979A EP 0525985 B1 EP0525985 B1 EP 0525985B1
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EP
European Patent Office
Prior art keywords
data
transmit
receive
fifo buffer
transmit data
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EP92305979A
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German (de)
English (en)
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EP0525985A2 (fr
EP0525985A3 (fr
Inventor
Robert J. Galuszka
Andrew J. Walton
Stewart F. Bryant
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Cabletron Systems Inc
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Cabletron Systems Inc
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Priority to EP01204235A priority Critical patent/EP1198105A3/fr
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Publication of EP0525985A3 publication Critical patent/EP0525985A3/fr
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Publication of EP0525985B1 publication Critical patent/EP0525985B1/fr
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
    • H04L69/324—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/40—Network security protocols

Definitions

  • the present invention is directed to data communications in a computer network and, more particularly, to a high performance data link interface.
  • computers and other processing and operating devices are often coupled to one another in a network so that messages, typically in the form of data packets, can be transmitted between computers of the network.
  • Data transmission services are utilized for the physical transmission of data between nodes of the network, i.e. between points of the network where computers or other devices or systems are physically and electrically coupled to the network.
  • Network protocols have been developed to control the transmission of data between the nodes of a computer network.
  • Each protocol is typically defined in terms of a number of layers, with each layer relating to a certain aspect of the functionality required for data transmissions throughout a network.
  • the first three layers are defined as a physical layer, a data link layer and a network layer.
  • the physical layer is directed to the physical and electrical specifications of a physical link, such as the data transmission service or bus that couples the nodes of a network to one another.
  • the physical layer controls bit transmission through the link so that a series of bits of a data packet can be communicated from one node to another node on the network.
  • the physical layer sets the voltage levels for logical ones and zeros, the timing of stable bit information on the link and so on, as necessary to transmit the bits of a data packet over the physical link.
  • the data link layer is directed to packaging or framing of bits of a data transmission into a defined framed packet that is free of transmission errors.
  • the data link layer creates and recognizes boundaries between bits to define bit fields. The boundaries provide structure and meaning to the bits of a data transmission.
  • the data transmission when framed according to a data link protocol, can include a start frame byte to indicate the beginning of a framed data packet, a header comprising n bits to indicate source and destination information, the length of the data packet in bytes, the network layer protocol being used and so on.
  • the header can be followed by framed bytes of the actual data packet being communicated from a source device to a destination device, an end byte to indicate the end of the particular data transmission frame and cyclic redundancy check (CRC) code bytes for use in checking the integrity of a data transmission.
  • CRC cyclic redundancy check
  • the network layer is directed to the control of routing information required to direct a message from the source device to the destination device on the network.
  • the network layer information is included in one of the bit fields of a frame defined by the data link layer, as e.g., in the header.
  • Each protocol will define the length and content of the network layer information to uniquely identify each source and destination of data in the network and also the processing scheme for routing data frames through the network.
  • a data link interface is required at each node of the network to receive and transmit serial bits from and to the respective data transmission service and to frame the serial bits for processing at the node.
  • the data link interface will support the electrical and physical specification of the data transmission service coupled to the node and process serial bits received at the node to frame the constituent bytes of a data transmission according to the data link protocol utilized in the network.
  • the data link interface can then transmit the framed data transmission to, e.g., a data link and network layer processor at the node for processing of the frame according to the content of the frame and the protocol utilized in the network.
  • US 5,007,051 describes a method and device for controlling transmission across a data link.
  • the device comprises a receive port connected the receive data path of the transmission line and a receive controller, and a transmit port connected to the transmit data path of the transmission line.
  • Incoming signals are processed and validated by the receive controller. If an error signal is detected the transmitter is caused to send a reject frame back to the remote location from which it was transmitted.
  • US 5,016,248 discloses a buffer memory device and method for fixed length packet data. However, there is no disclosure in this document of a device have separate receive and transmit data line interfaces.
  • the invention provides a new and improved data link interface for coupling a node of a computer network to a high speed, synchronous data transmission service such as a T1 line.
  • the architecture for the data link interface includes separate receive and transmit data framing paths to fully utilize the separate receive and transmit data paths implemented in full duplex communication links such as T1 lines.
  • the use of separate receive and transmit framing paths permits logical parallel receive and transmit data framing for efficient data link processing of data transmissions received at or transmitted from the respective node of the computer network.
  • a dual port RAM is coupled between the receive and transmit data framing paths for transfer of messages between the data paths.
  • the messages can include, e.g., acknowledgement messages for transmission by the transmit data path in respect of data received at the receive data path and acknowledgement messages received by the receive data path in respect of data being transmitted by the transmit data path.
  • each of the receive and transmit framing paths can operate to perform the respective receive and transmit functions required by the protocol and also communicate with the opposite transmitting or receiving node of the computer network via the communication facility provided by the dual port RAM for full implementation of the data link layer of the protocol used in the network.
  • certain standard signals such as, e.g., the CCITT standard data set signals, used to indicate a proper communication channel over the data transmission service are coupled directly to each of the receive and transmit framing components of the interface.
  • CCITT Consulting committee-International Telephone Networky
  • the framing of each particular frame is provided so that the detection of transmission errors (i.e. the negation of CCITT signals) can be directly correlated to a particular frame to facilitate a rapid and efficient transmission error recovery.
  • the framing components can be controlled to delay responding to the detection of a transmission error for a predetermined period of time to prevent an error recovery operation when the negation of the CCITT signals is only a glitch and does not indicate a disconnection on the link.
  • the predetermined delay will "smooth" the operation of the data link interface so that an error recovery operation is performed only when there is a true error on the line, as will be explained in more detail below.
  • Additional standard signals such as, e.g., the CCITT standard line count signals, are coupled through the line interface to a processor at the respective node.
  • the processor receives line speed information for use in scheduling events and the performance of operations required in the processing of data transmissions.
  • Data transmission services such as T1 lines can be operated at any one of a plurality of line speeds within a predetermined range of line speeds.
  • the processor can configure itself for operation at the particular line speed being utilized in a particular data transmission.
  • each of the receive and transmit framing paths is provided with a First-in-First-out (FIFO) buffer to buffer receive and transmit data between the line interface and a processor or processors at the respective node of the computer system.
  • the transmit FIFO buffer can be operated to release data bytes of a frame to the framing component of the transmit framing path for transmission on the link only after a predetermined number of bytes are stored in the FIFO buffer.
  • Modern high speed data transmission services can operate at line speeds fast enough to transmit bits as fast as a high performance processor at the respective node can load bytes into the transmit FIFO buffer.
  • a processor performing data link processing for a data transmission will require more time to process a certain number of bytes at the beginning of a frame, as e.g., the header, than the remaining bytes of the transmission.
  • the predetermined number of bytes required before the transmit FIFO buffer releases data for transmission permits a synchronization of the loading of data into the transmit FIFO buffer by the processor with the transmission of bits onto the transmit path of the link.
  • the predetermined number of bytes can be set, e.g., so that at least the header of a data frame is loaded into the transmit FIFO buffer before release of data from the buffer for transmission. Thereafter, the high performance processor will be able to load the transmit FIFO buffer at a speed commensurate with the line speed of the link.
  • the above described features of the line interface of the present invention provide an efficient and high speed line interface between a node and a data transmission service.
  • the line interface takes full advantage of the separate receive and transmit data paths provided in transmission services such as T1 lines and also implements an advantageous use of standard control signals such as CCITT data set and line count signals for efficient transmission error recovery and flexible configurability of the node for operation at any number of line speeds.
  • Fig. 1 is a block diagram of a high speed synchronous transmission line interface card according a preferred embodiment of the present invention.
  • Fig. 2 is a block diagram of the line interface unit of the line interface card of Fig. 1.
  • the line interface card 20 includes two ports 25, 27.
  • Each port 25, 27 is adapted to be coupled to a synchronous line operating at a line speed of e.g., from 56K bps to 2.048M bps and is user configured to support the electrical and physical specifications of one of the standard line interfaces, such as one of the RS422/449, V.35 and X.21 standard leased telephone lines.
  • Each of the ports 25, 27 is coupled to a line interface 22 that is, in turn, coupled to a processor 24.
  • the processor 24 is coupled to a bus interface 26 so that the processor 24 can transmit and receive data packets to and from a bus 15.
  • the line interface card 20 couples the ports 25, 27 to the bus 15 to provide a communication link between components coupled to the bus (not illustrated) and the T1 data transmission lines.
  • the line interface 22 comprises two separate line interface units 29, 31, each coupled to one of the ports 25, 27 respectively. Moreover, each line interface unit 29, 31 is coupled to a transmit processing bus 33, 35 and a receive processing bus 37, 39, respectively.
  • the line interface units 29, 31 support the HDLC data link protocol to receive or transmit serial bit streams and provide the necessary byte framing interface to the processor 22.
  • the processor 24 comprises four TMS320C25 processors 41, 43, 45, 47.
  • the processors 41, 45 are each dedicated to the processing of data packets to be transmitted out of one of the ports 25, 27, respectively, and are each coupled to a respective transmit processing bus 33, 35.
  • the processors 43, 47 are each dedicated to the processing of data packets received at one of the ports 25, 27, respectively, and are each coupled to a respective receive processing bus 37, 39.
  • the buses 33, 37, 35, 39 are all coupled to the interface 26 of the line interface card 20 for acquisition and control of the bus 15 by any one of the processors 41, 43, 45, 47.
  • the processors 41, 43, 45, 47 can perform data link and network layer processing for each data packet and individually participate in appropriate bus transactions to transmit data packets to the components coupled to the line interface card 20 via the bus 15.
  • a line interface 49 is coupled to the respective port 25, 27 to serially receive or transmit the bits of data packets and to receive or transmit appropriate control signals required by the physical layer of the transmission service utilized on the transmission line, as e.g., CCITT standard signals.
  • the interface 49 couples all of the serial bits received at the respective port 25, 27 to a receive framing device 51 that operates according to the HDLC data link protocol to frame the received serial bits into bytes of a framed data packet.
  • the framed bytes are stored in a receive FIFO buffer memory 53.
  • the bytes stored in the FIFO buffer 53 are read by a receive processor interface 55 and transmitted to the respective receive processor 43, 47 over the appropriate receive processing bus 37, 39.
  • the interface 49 is coupled to a transmit framing device 57 that generates a serial bit stream for transmission by the interface 49 out of the port 25, 27.
  • the transmit framing device 57 is coupled to a transmit FIFO buffer memory 59 that contains framed bytes of data packets to be transmitted.
  • the transmit framing device 57 also operates according to the HDLC data link protocol to accept the framed data packets stored in the transmit FIFO 59 and produce a corresponding bit stream for transmission by the interface 49.
  • the transmit FIFO 59 is coupled to a transmit interface 61 that is, in turn, coupled to a respective transmit processor 41, 45 by the appropriate transmit processing bus 33, 35.
  • the transmit interface 61 stores framed data packets received from the transmit processor 41, 45 in the transmit FIFO 59 for subsequent transmission.
  • the separate receive and transmit framing paths provided by the receive framing and transmit framing devices 51, 57 and the use of separate receive and transmit processors 41, 45, 43, 47 permit parallel, concurrent transmit and receive data packet processing in each of the line interface units 29, 31 of the line interface card 20.
  • the parallel transmit/receive, concurrent processing architecture for the line interfaces takes full advantage of the separate transmit and receive paths utilized in full duplex communication links that are provided by the commercially available leased telephone lines.
  • the transmit interface 61 is also coupled to the receive FIFO 53 so that the line interface 29, 31 can operate utilizing only one of the processors, through the transmit interface 61.
  • a dual port RAM 63 is coupled to each of the receive and transmit interfaces 55, 61 to provide a communication channel between the transmit and receive processors 41, 45, 43, 47.
  • the RAM 63 is divided into three sections.
  • Each of the transmit and receive processors 41, 45, 43, 47 share read and write access to a first section of the RAM 63 so that semaphores can be passed between the processors for communication.
  • the semaphores can include, e.g., a message from the receive processor 43, 47 to the transmit processor 41, 45 requesting the transmit processor 41, 45 to send a message to the component of the network to which the line interface card 20 is linked, to retransmit frames that were not properly received.
  • a protocol can be implemented in each of the processors to control the updating of the semaphore locations of the first section.
  • read and write access to the dual port RAM 63 can be controlled by a hardware mechanism.
  • a second section of the RAM 63 can only be written to by the transmit processor 41, 45 but read by the receive processor 43, 47 and a third section of the RAM 63 can only be written to by the receive processor 43, 47 but read by the transmit processor 41, 45.
  • the second and third sections of the dual port RAM 63 are used to communicate values such as acknowledgement numbers between the transmit and receive processors 41, 45, 43, 47.
  • the other component of the network receiving the packet will return acknowledgement messages pursuant to, e.g., the data link protocol of the transmission line.
  • the acknowledgement messages are received by the receive processor 43, 45 through the receive side of the line interface 29, 31.
  • the receive processor 43, 45 will extract a preselected portion of each acknowledgement message, as, e.g., the frame sequence number contained in the acknowledgement message, and write the preselected portion of each acknowledgement message to its read/write section of the dual port RAM 63.
  • the transmit processor 41, 45 can then read the preselected portions of the acknowledgement messages from that section of the dual port RAM 63.
  • a line 65 couples the line interface 49 to the receive framing device 51 so that the line interface 49 can transmit data set signals received by the line interface 49 to the receive framing device 51.
  • the data set signals are transmitted by the component of the network that is transmitting to the line interface card 20 and indicate that a proper communication channel exists between the transmitting component and the line interface 49.
  • the data set signals include the CCITT standard 109 (data channel received line signal detector) and CCITT standard 107 (data set ready) signals. Accordingly, the receive framing device 51 can utilize the data set signals to directly monitor the connection with the transmitting component.
  • the receive framing device 51 will only store data byte frames in the receive FIFO 53 when the data set signals are asserted. If the data set signals are negated during the processing of any byte, the receive framing device 51 will stop processing the current frame and place a status indicator in the receive FIFO 53 to indicate to the respective receive processor 43, 47 that a transmission error has occurred. Thus, the receive framing device 51 will not frame and store corrupted data that may appear at the port 25, 27 after the connection with the transmitting component has failed.
  • the receive processor 43, 47 when the receive processor 43, 47 receives the bytes and status indicator from the receive FIFO 53, it will know that there was a transmission error during the forwarding of the current frame and that the completed frames contained in the receive FIFO 53 were stored while the data set signals were asserted. Accordingly, the receive processor 43, 47 can send a message to the transmit processor 41, 45 via the dual port RAM 63 to request the transmitting component to resend the corresponding frame.
  • a line 67 couples the line interface 49 to the transmit framing device 57 so that the line interface 49 can likewise transmit data set signals received by the line interface 49 to the transmit framing device 57.
  • the data set signals include CCITT standard 106 (clear to send) or CCITT standard 107 (data set ready) signals. Accordingly, the transmit framing device 57 can also directly monitor the connection with the component of the network meant to receive the data being transmitted by the line interface 49.
  • the transmit framing device 57 will terminate processing and transmission after the current byte with an abort sequence.
  • the transmit framing device will also transmit an error status message to the respective transmit processor 41, 45.
  • the transmit framing device 57 will also flush the transmit FIFO 59 and not permit the storing of any further bytes in the transmit FIFO 59 by the transmit interface 61 until the transmit processor 41, 45 has acknowledged the error status message.
  • the transmit framing device 59 knows that the transmit processor 41, 45 will now be operating in a manner suitable to correct the transmission error, by e.g., transmitting a message to the component of the network meant to receive the data packet, to prompt the component to send a message indicating what data was received by the component. In this manner, the transmit processor 41, 45 will know what data has to be retransmitted.
  • the component will have, of course, received the abort sequence from the transmit framing device 59 and the message for retransmission by the component will be received by the respective receive processor 43, 47.
  • the receive processor 43, 47 will store a preselected portion of the message as a value in the dual port RAM 63, and that value is read by the transmit processor 41, 45.
  • the transmit framing device 59 Since the transmit framing device 59 maintains the transmit FIFO 59 flushed until it knows that the transmit processor 41, 45 has become aware of the transmission error, there will not be any out of sequence frames in the transmit FIFO 59 that were sent to the transmit FIFO 59 after negation of the data set signals but before the transmit processor 41, 45 received the error message. In this manner, the transmit framing device 59 avoids wasting bandwidth on the line by only transmitting frames stored in the transmit FIFO 59 after the acknowledgement of the error condition and a reassertion of data set signals.
  • the direct monitoring of the data set signals by the receive and transmit framing devices 51, 57 provides a straightforward scheme for the efficient detection and correction of transmission errors.
  • the framing devices interlock detection of data set signals with data being received or transmitted so that the FIFO's 53, 59 can be rapidly loaded with data with error detection being directly associated with a specific frame.
  • the processing of frames is terminated by the respective framing device 51, 57 upon the detection of a negation of the data set signals and appropriate status messages are generated at that time by the framing device 51, 57 for initiation of retransmission of specific frames identified at the occurrence of a transmission error without any waste of bandwidth.
  • the receive and transmit framing devices 51, 57 do not necessarily terminate processing immediately upon the detection of the negation of the data set signals. Rather, the framing device 51, 57 can be controlled to wait a predetermined fixed period of time after negation of the data set signals and will proceed to terminate processing only if the data set signals remain negated at the end of the fixed period of time. This will "smooth" out the operation of the framing device 51, 57 to prevent the termination of processing when the negation of the data set signals is merely a glitch or is proper, as, e.g., at the end of a transmission, but is detected by the framing device 51, 57 while data is still arriving.
  • a modem may drop the data set signals when it transmits the last "flag" byte of a frame.
  • a slight shift in the time relationship between the dropping of the data set signals and the transmission of the last byte may result in the framing device 51, 57 detecting the negation of the data set signals prior to reception of the last byte causing the framing device 51, 57 to treat the negation of the data set signals as a transmission error.
  • the wait time period prevents this from happening.
  • the framing devices 51, 57 will, however, immediately commence processing upon detection of the assertion of the data set signals.
  • the transmit framer 57 During the operation of the transmit framer 57, bytes are continuously transmitted to the port 25, 27 so long as there are bytes in the transmit FIFO 59. If the transmit FIFO 59 becomes empty, the transmit framer 57 will commence an abort sequence. As described above, the port 25, 27 is coupled to a high speed transmission line that may be able to transmit data as fast as the transmit processor 41, 45 can send data to the transmit FIFO 59. The time required to process the first several bytes of a data packet by the processor 41, 45 can be longer than the transmit time for those bytes. Thus, at times, the transmit framer 57 may be able to empty the transmit FIFO 59 faster than the transmit processor 41, 45 can store bytes into the transmit FIFO 59.
  • a programmable threshold is set by the transmit processor 41, 45 and communicated to the respective transmit FIFO 59.
  • the transmit FIFO 59 will not start the transmission of bytes to the transmit framing device 57 until the number of bytes in the transmit FIFO 59 is at least equal to the threshold value.
  • the threshold is set by the transmit processor 41, 45 to a value equal to the number of bytes for which its processing time is greater than the transmit time. After that number of bytes, the transmit processor 41, 45 will be able to send bytes to the transmit FIFO 59 as fast as they can be transmitted over the line.
  • the transmit FIFO 59 will therefore buffer at least the threshold number of bytes to provide the transmit processor with sufficient time to reach the transmission speed of the line.
  • the transmit framing device 57 will thus always have bytes available for transmission in the transmit FIFO 59.
  • the transmit FIFO 59 will then override the threshold and release the bytes to the transmit framing device 57.
  • the transmit processor 41, 45 sends a command byte to the transmit FIFO 59 for each framed data packet.
  • the command byte is stored in the transmit FIFO 59 when all of the data bytes of the corresponding frame are stored in the transmit FIFO 59.
  • An override indication for the transmit FIFO 59 can comprise the command byte associated with a frame that is smaller in size than the threshold value. When the transmit FIFO 59 sees a command byte it will send the frame to the transmit framing device 57 regardless of the threshold value.
  • the transmit FIFO 59 counts the number of command bytes in the transmit FIFO 59. The count is incremented whenever a new command byte is stored in the transmit FIFO 59 and is decremented whenever a complete frame is transmitted out of the transmit FIFO 59. As long as there are multiple commands in the transmit FIFO 59, the FIFO 59 will override the threshold since the presence of multiple commands indicates that several complete data packets are stored in the transmit FIFO 59 and available for transmission.
  • CRC cyclical redundancy checking
  • the framing device 51 will accumulate both 16 bit and 32 bit CRC blocks.
  • the receive framing device 51 will check both the CRC code that is expected, i.e. one of the 16 bit or 32 bit blocks and the other CRC code. The checking of each CRC code can be performed in parallel. If the expected CRC code is not correct, and the other CRC code is correct, the receive framing device 51 will send a message to the receive processor 43, 47 indicating that the expected CRC code is incorrect but that the other CRC code is correct. The receive processor 43, 47 can then take appropriate action to reconfigure the link if necessary to change the expected CRC code.
  • the transmit processor 41, 45 can dynamically indicate to the transmit framing device 57 whether or not to generate and add a CRC code to a packet being transmitted.
  • the CRC of a data packet passed through the bridge is not meant to be altered inasmuch as in a bridge, the ultimate destination of the packet performs CRC checking of the original CRC code.
  • the transmit processor 41, 45 will indicate to the transmit framing device 57 in the command byte that the CRC code should not be appended.
  • the CCITT standard transmit line clock signal 114 is transmitted from the line interface 49 over a line 75 to a transmit line counter 77.
  • the transmit line counter 77 will use the CCITT signal 114 to determine the line speed being utilized on the link coupled to the respective port 25, 27 and transmit line speed information to the transmit interface 61 via a line 78.
  • the line speed information is made available to the transit processor 45, 47. This will enable the transmit processor 45, 47 to directly utilize line speed information to configure itself for the scheduling of events and the performance of operations required in the processing of data according to the actual line speed of the link.
  • the transmit processor 45, 47 can use the transmission of the line speed information as an indication that a link exists with another component of the computer network.
  • the receive processor 41, 43 is provided with line speed information contained in the CCITT 115 receive line clock signal via the receive line counter 80 and the lines 81, 82.
  • a receive status register 90 is coupled between the receive FIFO buffer 53 and the receive interface 55 and a transmit status register 92 is coupled between the transmit FIFO buffer 59 and the transmit interface 61.
  • the status registers are each loaded by the respective FIFO buffer 53, 59 to indicate the operating state of the FIFO, e.g. normal or error condition.
  • Each of the receive and transmit processors 41, 43 and 45, 47, respectively, can periodically poll the respective status register 90, 92 to determine the state of the corresponding FIFO buffer.
  • a zero value stored in the respective status register 90, 92 indicates a normal operating state for the respective FIFO buffer 53, 59 with either space available for storage of additional bytes, in the case of the transmit FIFO buffer 59, or bytes stored in the FIFO for reading, in the case of the receive FIFO buffer 53.
  • each of the processors 41, 43, 45 and 47 need only perform a simple test for a zero value in the respective status register 90, 92 during each polling operation to determine that the state of the corresponding FIFO is normal and reading or writing of bytes should proceed.

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  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Computer And Data Communications (AREA)
  • Small-Scale Networks (AREA)

Claims (11)

  1. Interface de liaison de données (29,31) à utiliser dans un réseau de transmission de données, l'interface (29,31) étant propre à être couplée à une ligne de transmission de données synchrone en duplex intégral, et comprenant :
    un dispositif d'interface de ligne de données de réception et un dispositif d'interface de ligne de données d'émission, chacun propre à être couplé aux chemins de données d'émission et de réception (65 et 67) respectivement de la ligne de transmission de données synchrone
       caractérisée en ce que
    l'interface de liaison de données (29,31) comprend en outre une mémoire vive à double accès (63) couplée à chacun dudit dispositif d'interface de ligne de données de réception et dudit dispositif d'interface de ligne de données d'émission pour transmettre des messages entre eux et ledit dispositif d'interface de ligne de données d'émission peut fonctionner pour produire un signal d'accusé de réception à transmettre par le chemin de données d'émission par rapport à des données reçues au niveau du chemin de données de réception.
  2. Interface de liaison de données suivant la revendication 1, comprenant en outre un processeur de données de réception (43,47) couplé audit dispositif d'interface de liaison de données de réception et un processeur de données d'émission (41,45) couplé audit dispositif d'interface de liaison de données d'émission.
  3. Interface de liaison de données (29,31) suivant la revendication 1, dans laquelle ledit dispositif d'interface de ligne de données de réception comprend un dispositif de délimitation des données de réception (51) pour délimiter des données série reçues du chemin de données de réception de la ligne de transmission de données synchrone en trames de réception, une mémoire tampon FIFO de données de réception (53) couplée audit dispositif de délimitation des données de réception (51) pour mémoriser les trames de réception et un dispositif d'interface de données de réception (55) couplé à ladite mémoire tampon FIFO de données de réception (53) et propre à être couplé à un processeur de données de réception (37,39) pour la transmission des trames de réception au processeur de données de réception (43,47), dans laquelle en outre ledit dispositif d'interface de ligne de données d'émission comprend un dispositif de délimitation des données d'émission (57) pour transmettre des trames sous la forme de données série au chemin de données d'émission de la ligne de transmission de données synchrone, une mémoire tampon FIFO de données d'émission (59), couplée audit dispositif de délimitation des données d'émission (57), pour mémoriser des trames d'émission et un dispositif d'interface de données d'émission (61) couplé à ladite mémoire tampon FIFO de données d'émission (59) et propre à être couplé à un processeur d'émission (41,45) pour recevoir des trames d'émission du processeur d'émission (41,45) à mémoriser dans ladite mémoire tampon FIFO de données d'émission (59).
  4. Interface de liaison de données suivant la revendication 3, dans laquelle ledit dispositif de délimitation des données de réception (51) est propre à recevoir un signal modem de la ligne de transmission de données synchrone pour contrôler la connexion à un dispositif distant sur la ligne de transmission de données synchrone, le dispositif de délimitation des données de réception (51) fonctionnant pour former et mémoriser des parties d'une trame dans ladite mémoire tampon FIFO de paquet de données de réception (53) lorsque le signal modem indique une connexion et pour abandonner la formation et la mémorisation des parties d'une trame et pour produire et mémoriser un message d'état d'erreur dans la mémoire tampon FIFO de données de réception (53) lorsque le signal modem n'indique pas une connexion.
  5. Interface de liaison de données suivant la revendication 3, dans laquelle ledit dispositif de délimitation des données d'émission (57) est propre à recevoir un signal modem de la ligne de transmission de données synchrone pour contrôler la connexion à un dispositif distant sur la ligne de transmission de données synchrone, le dispositif de délimitation des données d'émission (57) fonctionnant pour produire et transmettre des données d'une trame mémorisée dans ladite mémoire tampon FIFO de données d'émission (59) lorsque le signal modem indique une connexion et pour abandonner la transmission desdites données, vider ladite mémoire tampon FIFO de données d'émission (59) et produire et transmettre un message d'état d'erreur au processeur de données d'émission (41,43) lorsque le signal modem n'indique pas une connexion.
  6. Interface de liaison de données suivant la revendication 4, dans laquelle ledit dispositif de délimitation des données de réception (51) abandonne la formation et la mémorisation des parties d'une trame une période de temps prédéterminée après que le signal modem indique pour la première fois l'absence de connexion.
  7. Interface de liaison de données suivant la revendication 6, dans laquelle ledit dispositif de délimitation des données de réception (51) est commandé pour abandonner de manière sélective la formation et la mémorisation des parties d'une trame une période de temps prédéterminée après que le signal modem indique pour la première fois l'absence de connexion.
  8. Interface de liaison de données suivant la revendication 3, dans laquelle ledit dispositif de délimitation des données d'émission (57) abandonne la transmission de données série une période de temps prédéterminée après que le signal modem indique pour la première fois l'absence de connexion, dans laquelle ledit dispositif de délimitation des données d'émission (57) est commandé pour abandonner de manière sélective la transmission de données série une période de temps prédéterminée après que le signal modem indique pour la première fois l'absence de connexion, dans laquelle en outre ledit dispositif de délimitation des données d'émission (57) transmet des données de ladite mémoire tampon FIFO de données d'émission (57) lorsqu'un nombre d'octets de données mémorisées dans ladite mémoire tampon FIFO de données d'émission (57) dépasse une valeur seuil.
  9. Interface de liaison de données suivant la revendication 8, dans laquelle ledit dispositif de délimitation des données d'émission (57) transmet des données de ladite mémoire tampon FIFO de données d'émission (59) lorsque le nombre d'octets de données mémorisés dans ladite mémoire tampon FIFO de données d'émission (59) est inférieur à la valeur seuil et les octets mémorisés dans la mémoire tampon FIFO de données d'émission (59) comprennent au moins une trame complète à transmettre.
  10. Interface de liaison de données suivant la revendication 2, dans laquelle ledit dispositif d'interface de ligne de données de réception traite chacun d'un premier code CRC prévu et d'un deuxième code CRC imprévu pour des données de réception, et produit et transmet un message au processeur de données de réception (43,47) lorsque le premier code CRC prévu est incorrect et le deuxième code CRC imprévu est correct, dans laquelle ledit dispositif d'interface de ligne de données d'émission est commandé de manière dynamique pour annexer des informations de code CRC aux données d'émission, dans laquelle en outre l'interface de liaison de données couple les informations de signal de comptage de ligne provenant de la ligne de transmission de données à chacun du processeur de données de réception (43,47) et du processeur de données d'émission (41,45).
  11. Interface de liaison de données suivant la revendication 3, comprenant en outre un registre d'état couplé entre la mémoire tampon FIFO de données de réception (53) et le dispositif d'interface de données de réception, le registre d'état étant commandé pour mémoriser une valeur zéro pour indiquer un fonctionnement normal de la mémoire tampon FIFO de données de réception (53), des données étant mémorisées dans la mémoire tampon FIFO de données de réception (53), l'interface de liaison de données comprenant en outre un registre d'état couplé entre la mémoire tampon FIFO de données d'émission (59) et le dispositif d'interface de données d'émission, le registre d'état étant commandé pour mémoriser une valeur zéro pour indiquer un fonctionnement normal pour la mémoire tampon FIFO de données d'émission (59), de l'espace étant disponible dans la mémoire tampon FIFO de données d'émission (59).
EP92305979A 1991-06-28 1992-06-29 Interface de liaison bidirectionnelle de données à haute vitesse Expired - Lifetime EP0525985B1 (fr)

Priority Applications (1)

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EP01204235A EP1198105A3 (fr) 1991-06-28 1992-06-29 Interface de ligne de transmission à grande vitesse

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US722684 1985-04-12
US07/722,684 US5301186A (en) 1991-06-28 1991-06-28 High speed transmission line interface

Related Child Applications (1)

Application Number Title Priority Date Filing Date
EP01204235A Division EP1198105A3 (fr) 1991-06-28 1992-06-29 Interface de ligne de transmission à grande vitesse

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EP0525985A2 EP0525985A2 (fr) 1993-02-03
EP0525985A3 EP0525985A3 (fr) 1994-10-12
EP0525985B1 true EP0525985B1 (fr) 2002-05-22

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EP92305979A Expired - Lifetime EP0525985B1 (fr) 1991-06-28 1992-06-29 Interface de liaison bidirectionnelle de données à haute vitesse

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US (2) US5301186A (fr)
EP (2) EP1198105A3 (fr)
JP (1) JPH05204804A (fr)
DE (1) DE69232613T2 (fr)
IE (1) IE922105A1 (fr)

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Also Published As

Publication number Publication date
JPH05204804A (ja) 1993-08-13
DE69232613T2 (de) 2003-01-30
US5301186A (en) 1994-04-05
US5519693A (en) 1996-05-21
DE69232613D1 (de) 2002-06-27
EP0525985A2 (fr) 1993-02-03
EP1198105A2 (fr) 2002-04-17
IE922105A1 (en) 1992-12-30
EP0525985A3 (fr) 1994-10-12
EP1198105A3 (fr) 2005-09-14

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