EP0221786A2 - LED matrix display panel - Google Patents

LED matrix display panel Download PDF

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Publication number
EP0221786A2
EP0221786A2 EP86401754A EP86401754A EP0221786A2 EP 0221786 A2 EP0221786 A2 EP 0221786A2 EP 86401754 A EP86401754 A EP 86401754A EP 86401754 A EP86401754 A EP 86401754A EP 0221786 A2 EP0221786 A2 EP 0221786A2
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EP
European Patent Office
Prior art keywords
memories
display panel
clock
frequency
diodes
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Granted
Application number
EP86401754A
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German (de)
French (fr)
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EP0221786B1 (en
EP0221786A3 (en
Inventor
Jean Flinois
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CENTRE D'AUTOMATISMES ET DE RECHERCHES ELECTRONIQUES CENTAURE SARL
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CENTRE D'AUTOMATISMES ET DE RECHERCHES ELECTRONIQUES CENTAURE SARL
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Priority to AT86401754T priority Critical patent/ATE74225T1/en
Publication of EP0221786A2 publication Critical patent/EP0221786A2/en
Publication of EP0221786A3 publication Critical patent/EP0221786A3/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2085—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/04—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions
    • G09G3/06—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions using controlled light sources
    • G09G3/12—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions using controlled light sources using electroluminescent elements
    • G09G3/14—Semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the invention relates to a display panel with a matrix of light-emitting diodes, typically forming a luminous newspaper, and it relates more particularly to such a panel which is both more economical and brighter than known analogous systems, while allowing more fast.
  • a conventional luminous journal consists of a matrix of light-emitting diodes, a corresponding number of memories (typically bi-stable flip-flops) interposed between said diodes and a shift register in which the information representative of an image to be displayed circulates. .
  • This information is delivered at the rate of a clock by a control unit associated with a program memory.
  • the control unit and the program memory are generally located in a separate box from the panel and connected to the latter by a strand of conductive wires. This arrangement is advantageous when the diode panel is intended to be placed outside and subjected to the weather. In this case, the most fragile components, contained in the control unit, can be placed in a sheltered place and more easily accessible for the modification or updating of the messages to be reproduced.
  • the invention makes it possible in particular to solve this problem.
  • the basic principle of the invention results from the search for a better adaptation between the available integrated circuits, constituting the memories and the light-emitting diodes usually used for such an application.
  • By analyzing the characteristics of recent integrated circuits of rapid CMOS technology it has thus been found that the manufacturers of these integrated circuits designed for high-speed digital computing applications, had been led to lower the supply voltage, while admitting a higher current, so that the circuits can be driven at a higher clock frequency.
  • One of the features of the invention is to propose a new application of this type of component, for directly supplying a light-emitting diode.
  • the invention therefore essentially relates to a display panel with a matrix of light-emitting diodes, for example of the light journal type, each diode being supplied by means of a memory, characterized in that the memories are made of fast CMOS technology, in that the diodes are directly connected to the outputs of their respective memories, and in that the supply voltage of said memories is chosen to fix the value of the current in said diodes.
  • Another problem solved by the invention relates to the very structure of the display panels. This involves efficiently transmitting the high-frequency clock to all the circuits, despite the large dimensions of the diode array. Indeed, it is not possible to provide a clock common to all the integrated circuits. The parasitic capacities which would result therefrom would not allow the transfer of information at the chosen frequency, that is to say of the order of 2 MHz. It is therefore necessary to provide, step by step, means for amplifying or regenerating the clock signal, which can desynchronize the various circuits of the shift register. According to another aspect of the invention, means are provided for the shift register to function correctly without the clock signal being actually synchronized at all points of the register.
  • the display panel defined above is also characterized in that the stages of the shift register are arranged in groups of stages adjacent to each other, in that a means of amplification and reset in form is interposed in the clock link between any two adjacent groups and in that a delay means is interposed between the data output and the data output of these same adjacent groups.
  • Another feature of the invention consists in supplying the display panel with a reduced frequency clock and in regenerating the high frequency clock in the display panel itself, which makes it possible to have a length of conductive cable. more important between the control unit and the high-frequency clock proper, and the display panel.
  • each memory is composed of a bi-stable flip-flop and, according to the invention, the corresponding diode 11 is directly connected to its output, that is to say in particular without series resistance.
  • There are two possibilities of connecting the diode relative to the flip-flop either by using the transistor of channel N, the diode being connected between the output of the memory and the mass (fig. 2), or by using the transistor of the channel P, the diode being connected, this time, to the power supply terminal (fig. 3).
  • the memories 12 are connected to be loaded by the outputs of a shift register of the serial type, that is to say with serial data inputs and parallel outputs, the latter being connected to the inputs for loading the memories 12.
  • the progression of the information in the register takes place at the rate of a high-frequency clock, applied by a clock link 14.
  • the transfer of information from the inputs to the outputs of the memories 12 is controlled when the information train corresponding to a complete image has reached the last stage of the shift register 13. At this time, a control signal is applied on a loading BUS 15 common to all the memories 12.
  • control system for the diode array 11 will advantageously be implemented by cascading a suitable number of integrated circuits of the 74 HC 4094 B type incorporating the times of stages 13a of the shift register and a corresponding number (eight in the example) of memories 12 connected to the outputs of these stages of register.
  • the accessible outputs of said memories 12 are connected directly to light-emitting diodes 11, respectively; according to the assembly of Figure 2 or that of Figure 3.
  • the output of the last stage of the register of a given integrated circuit is connected to the input of the first stage of another integrated circuit of the same type, located nearby.
  • each flip-flop forming memory 12 is sufficient to optimally supply the light-emitting diode, which typically requires a current of the order of 25 mA. Indeed, this integrated circuit admits to being supplied with a lower voltage than the other MOS type circuits and this can vary within fairly wide limits. This feature is therefore used to adjust or determine the current flowing in the diodes, by choosing the supply voltage accordingly.
  • the voltage is chosen around 4 V, to obtain a current of the order of 25 mA in each diode. For this current value, the voltage across the diode is close to 1.8 V.
  • the power dissipated in each memory is therefore of the order of 0.062 W.
  • the maximum power dissipated by said integrated circuit is 0.5 W, which corresponds to the power admissible by this type of integrated circuit. If we assume a diode utilization rate of around 35%, the average power dissipated by each circuit is therefore in fact only 0.175 W.
  • the stages 13a of the shift register are arranged in groups of stages adjacent to each other (that is to say topologically neighboring on the display panel) and a means d amplification and fitness 18 is interposed in the clock link between any two such adjacent groups, while a delay means 19 is interposed between the data output and data input from these same adjacent groups.
  • the high-frequency clock signal can still be used from one end to the other of the display panel, despite the parasitic capacities distributed over the entire distance, by means 18 arranged gradually.
  • the resulting desynchronization is inconsequential thanks to the delay brought simultaneously in the transfer of information, from group to group.
  • the delay between two groups must be greater than the delay of the clock between these same groups.
  • each amplifier can be produced by two cascade inverters, for example available in integrated circuits of the same category, bearing the reference 74 HCU 04.
  • Self-timer means 19 are also available in each integrated circuit of type 74 HC 4094 B containing registers and memories.
  • an amplifier 18 and a delay means 19 associated with each integrated circuit that is to say for eight diodes, have been represented for the sake of simplification. In fact, it will be possible to "space" them much more, the number of stages in each group possibly being between ten and forty and preferably close to thirty.
  • the device of FIG. 4 connected to the output of the high-frequency clock generator, therefore at a distance from the panel, supplies a signal whose frequency is reduced by half. It consists of a flip-flop 20 looped back to its input by an inverter 21 whose output signal is amplifying 22 before being applied to the clock line.
  • the device in Figure 5 is a frequency multiplier designed to double the frequency of the signal it receives. It consists of an amplifier 24 distributing its output signal to two monostables 25, 26, mounted in parallel and phase shifted by an inverter 27. The outputs of the two monostables are connected to the two inputs of an OR gate 28 whose output is output the original frequency.
  • the system which has just been described allows the display of successive images at very high speed, up to a thousand images per second. These performances can be taken advantage of for the continuous display of a still image comprising diodes lit with different light levels, obtained by rapid and successive switching on and off of these diodes. For example, for a minimum frequency of twenty images per second, one can obtain up to fifty different light levels.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of El Displays (AREA)
  • Illuminated Signs And Luminous Advertising (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electric Clocks (AREA)

Abstract

LED display panel for forming a luminous journal. <??>The LEDs (11) which are arranged in a matrix are controlled via flip-flops forming a high-speed CMOS technology memory (12) able to deliver to them a current of sufficient intensity. The diodes are connected directly to the outputs of these memories and the current crossing them is determined by the supply voltage for the memories (12). <??>The memories are loaded by a shift register (13) of serial type. <IMAGE>

Description

L'invention se rapporte à un panneau d'affichage à matrice de diodes électroluminescentes, formant typiquement un journal lumineux et elle concerne plus particulièrement un tel panneau à la fois plus écono­mique et plus lumineux que les systèmes analogues connus, tout en permet­tant un affichage plus rapide.The invention relates to a display panel with a matrix of light-emitting diodes, typically forming a luminous newspaper, and it relates more particularly to such a panel which is both more economical and brighter than known analogous systems, while allowing more fast.

Un journal lumineux classique se compose d'une matrice de diodes électroluminescentes, d'un nombre correspondant de mémoires (typiquement des bascules bi-stables) intercalées entre lesdites diodes et un registre à décalage dans lequel circulent les informations représentatives d'une image à afficher. Ces informations sont délivrées au rythme d'une horloge par une unité de commande associée à une mémoire programme. L'unité de commande et la mémoire programme sont généralement situées dans un boîtier séparé du panneau et reliées à ce dernier par un toron de fils conducteurs. Cet agencement est avantageux lorsque le panneau de diodes est destiné à être placé à l'extérieur et soumis aux intempéries. Dans ce cas, les com­posants les plus fragiles, contenus dans l'unité de commande, peuvent être placés dans un endroit abrité et plus facilement accessibles pour la modi­fication ou l'actualisation des messages à reproduire. Jusqu'à présent, il a été assez difficile d'adapter les caractéristiques des mémoires à cel­les des diodes électroluminescentes. On a ainsi cherché à alimenter les diodes à travers des résistances de charge, mais ce type de circuit a l'in­convénient d'une consommation de puissance dans les résistances, non di­rectement utile pour l'affichage. Le prix de revient est par ailleurs élevé, non seulement en raison du nombre de résistances nécessaire, mais aussi du coût de main-d'oeuvre pour leur câblage. On a tenté d'alimenter les diodes électroluminescentes directement par le courant délivré par les mémoires, mais cela aboutit généralement à faire travailler lesdites mé­moires hors des caractéristiques prévues par le constructeur de ces circuits intégrés. Un tel mode de réalisation est, à la limite, concevable pour l'affichage de messages défilants, car les diodes ne sont utilisées que pendant une faible partie du temps. Ceci devient plus difficile à envisa­ger pour l'affichage de messages fixes, notamment des graphismes, où cer­taines diodes peuvent être allumées en permanence pendant des intervalles de temps relativement longs, d'où des conditions de fonctionnement beaucoup plus défavorables pour les mémoires qui les alimentent.A conventional luminous journal consists of a matrix of light-emitting diodes, a corresponding number of memories (typically bi-stable flip-flops) interposed between said diodes and a shift register in which the information representative of an image to be displayed circulates. . This information is delivered at the rate of a clock by a control unit associated with a program memory. The control unit and the program memory are generally located in a separate box from the panel and connected to the latter by a strand of conductive wires. This arrangement is advantageous when the diode panel is intended to be placed outside and subjected to the weather. In this case, the most fragile components, contained in the control unit, can be placed in a sheltered place and more easily accessible for the modification or updating of the messages to be reproduced. Up to now, it has been quite difficult to adapt the characteristics of the memories to those of light-emitting diodes. We have thus sought to supply the diodes through load resistors, but this type of circuit has the drawback of consuming power in the resistors, which is not directly useful for the display. The cost price is also high, not only because of the number of resistors required, but also because of the labor cost for their wiring. Attempts have been made to supply the light-emitting diodes directly with the current delivered by the memories, but this generally results in making said memories work outside the characteristics provided by the manufacturer of these integrated circuits. Such an embodiment is, ultimately, conceivable for the display of scrolling messages, since the diodes are used only for a small part of the time. This becomes more difficult to envisage for the display of fixed messages, in particular graphics, where certain diodes can be permanently lit for relatively long time intervals, hence much more unfavorable operating conditions for the memories which supply them. .

L'invention permet notamment de résoudre ce problème. Le principe de base de l'invention résulte de la recherche d'une meilleure adaptation entre les circuits intégrés disponibles, constituant les mémoires et les diodes électroluminescentes habituellement utilisées pour une telle appli­cation. En analysant les caractéristiques de circuits intégrés récents de la technologie CMOS rapide, on a ainsi constaté que les constructeurs de ces circuits intégrés conçus pour des applications de calcul numérique à grande vitesse, avaient été amenés à en abaisser la tension d'alimenta­tion, tout en admettant un courant plus important, pour que les circuits puissent être pilotés à une fréquence horloge plus élevée. L'une des par­ticularités de l'invention est de proposer une nouvelle application de ce type de composants, pour alimenter directement une diode électrolumines­cente.The invention makes it possible in particular to solve this problem. The basic principle of the invention results from the search for a better adaptation between the available integrated circuits, constituting the memories and the light-emitting diodes usually used for such an application. By analyzing the characteristics of recent integrated circuits of rapid CMOS technology, it has thus been found that the manufacturers of these integrated circuits designed for high-speed digital computing applications, had been led to lower the supply voltage, while admitting a higher current, so that the circuits can be driven at a higher clock frequency. One of the features of the invention is to propose a new application of this type of component, for directly supplying a light-emitting diode.

Dans cet esprit, l'invention concerne donc essentiellement un pan­neau d'affichage à matrice de diodes électroluminescentes, par exemple du type journal lumineux, chaque diode étant alimentée par l'intermédiaire d'une mémoire, caractérisé en ce que les mémoires sont réalisées en tech­nologie CMOS rapide, en ce que les diodes sont directement connectées aux sorties de leurs mémoires respectives, et en ce que la tension d'alimen­tation desdites mémoires est choisie pour fixer la valeur du courant dans lesdites diodes.With this in mind, the invention therefore essentially relates to a display panel with a matrix of light-emitting diodes, for example of the light journal type, each diode being supplied by means of a memory, characterized in that the memories are made of fast CMOS technology, in that the diodes are directly connected to the outputs of their respective memories, and in that the supply voltage of said memories is chosen to fix the value of the current in said diodes.

Un autre problème résolu par l'invention est lié à la structure même des panneaux d'affichage. Il s'agit de transmettre efficacement l'horloge haute-fréquence à tous les circuits, malgré les dimensions im­portantes de la matrice de diodes. En effet, il n'est pas possible de prévoir une horloge commune à tous les circuits intégrés. Les capacités parasites qui en résulteraient ne permettraient pas le transfert des in­formations à la fréquence choisie, c'est-à-dire de l'ordre de 2 MHz. On est donc amené à prévoir, de proche en proche, des moyens d'amplification ou de régénération du signal d'horloge, lesquels peuvent désynchroniser les différents circuits du registre à décalage. Selon un autre aspect de l'invention, on prévoit des moyens pour que le registre à décalage fonction­ne correctement sans que le signal d'horloge soit réellement synchronisé en tous les points du registre.Another problem solved by the invention relates to the very structure of the display panels. This involves efficiently transmitting the high-frequency clock to all the circuits, despite the large dimensions of the diode array. Indeed, it is not possible to provide a clock common to all the integrated circuits. The parasitic capacities which would result therefrom would not allow the transfer of information at the chosen frequency, that is to say of the order of 2 MHz. It is therefore necessary to provide, step by step, means for amplifying or regenerating the clock signal, which can desynchronize the various circuits of the shift register. According to another aspect of the invention, means are provided for the shift register to function correctly without the clock signal being actually synchronized at all points of the register.

Dans ce but, le panneau d'affichage défini ci-dessus est aussi ca­ractérisé en ce que les étages du registre à décalage sont agencés en grou­pes d'étages adjacents les uns des autres, en ce qu'un moyen d'amplifica­tion et de remise en forme est intercalé dans la liaison d'horloge entre deux groupes adjacents quelconques et en ce qu'un moyen retardateur est intercalé entre la sortie de données et la sortie de données de ces mêmes groupes adjacents.For this purpose, the display panel defined above is also characterized in that the stages of the shift register are arranged in groups of stages adjacent to each other, in that a means of amplification and reset in form is interposed in the clock link between any two adjacent groups and in that a delay means is interposed between the data output and the data output of these same adjacent groups.

Une autre particularité de l'invention consiste à alimenter le panneau d'affichage avec une horloge de fréquence réduite et à régénérer l'horloge de fréquence élevée dans le panneau d'affichage même, ce qui permet de disposer d'une longueur de câble conducteur plus importante en­tre l'unité de commande et l'horloge haute-fréquence proprement dite, et le panneau d'affichage.Another feature of the invention consists in supplying the display panel with a reduced frequency clock and in regenerating the high frequency clock in the display panel itself, which makes it possible to have a length of conductive cable. more important between the control unit and the high-frequency clock proper, and the display panel.

L'invention apparaîtra plus clairement à la lumière de la descrip­tion qui va suivre, donnée uniquement à titre d'exemple et faite en réfé­rence au dessin annexé, dans lequel :

  • - la figure 1 illustre partiellement un schéma de principe de l'ensemble des mémoires et du registre à décalage associé aux diodes électroluminescentes;
  • - la figure 2 est un schéma de branchement possible entre une diode électroluminescente et sa mémoire;
  • - la figure 3 est une variante de branchement;
  • - la figure 4 présente le schéma d'un circuit réducteur de fré­quence d'horloge; et
  • - la figure 5 représente le schéma d'un circuit multiplicateur de fréquence d'horloge
The invention will appear more clearly in the light of the description which follows, given solely by way of example and made with reference to the appended drawing, in which:
  • - Figure 1 partially illustrates a block diagram of all memories and the shift register associated with light emitting diodes;
  • - Figure 2 is a possible connection diagram between a light emitting diode and its memory;
  • - Figure 3 is an alternative connection;
  • - Figure 4 shows the diagram of a clock frequency reducing circuit; and
  • - Figure 5 shows the diagram of a clock frequency multiplier circuit

En se reportant au dessin, on a représenté une partie d'un panneau d'affichage de diodes électroluminescentes 11, respectivement connectées à des mémoires 12 réalisées en technologie CMOS rapide, aujourd'hui commer­cialisées sous la référence HCMOS par la plupart des constructeurs de semi­conducteurs. Chaque mémoire est composée d'une bascule bi-stable et, selon l'invention, la diode 11 correspondante est directement connectée à sa sortie, c'est-à-dire notamment sans résistance série. Il existe deux possibilités de branchement de la diode par rapport à la bascule, soit en utilisant le transistor du canal N, la diode étant branchée entre la sor­tie de la mémoire et la masse (fig. 2), soit en utilisant le transistor du canal P, la diode étant raccordée, cette fois, à la borne d'alimentation (fig. 3).Referring to the drawing, there is shown a part of a display panel of light-emitting diodes 11, respectively connected to memories 12 produced in rapid CMOS technology, today marketed under the reference HCMOS by most semiconductor manufacturers. . Each memory is composed of a bi-stable flip-flop and, according to the invention, the corresponding diode 11 is directly connected to its output, that is to say in particular without series resistance. There are two possibilities of connecting the diode relative to the flip-flop, either by using the transistor of channel N, the diode being connected between the output of the memory and the mass (fig. 2), or by using the transistor of the channel P, the diode being connected, this time, to the power supply terminal (fig. 3).

En se reportant à nouveau à la figure 1, on voit que les mémoires 12 sont connectées pour être chargées par les sorties d'un registre à dé­calage de type série, c'est-à-dire à entrées de données série et sorties parallèles, ces dernières étant reliées aux entrées de chargement des mé­moires 12. La progression des informations dans le registre se fait au rythme d'une horloge haute-fréquence, appliqué par une liaison d'horloge 14. Le transfert des informations des entrées vers les sorties des mémoi­res 12 est commandé lorsque le train d'informations correspondant à une image complète est parvenu jusqu'au dernier étage du registre à décalage 13. A ce moment, un signal de commande est appliqué sur un BUS de charge­ment 15 common à toutes les mémoires 12. Pratiquement, on réalisera avan­tageusement le système de pilotage de la matrice de diodes 11 par un mon­tage en cascade d'un nombre convenable de circuits intégrés du type 74 HC 4094 B incorporant à la fois des étages 13a du registre à décalage et un nombre correspondant (huit dans l'exemple) de mémoires 12 reliées aux sorties de ces étages de registre. Les sorties accessibles desdites mémoires 12 sont reliées directement à des diodes électroluminescentes 11, respectivement; selon le montage de la figure 2 ou celui de la figure 3. La sortie du dernier étage du registre d'un circuit intégré donné est re­lié à l'entrée du premier étage d'un autre circuit intégré du même type, situé à proximité. Le courant de chaque bascule formant mémoire 12 est suffisant pour alimenter de façon optimale la diode électroluminescente, laquelle nécessite typiquement un courant de l'ordre de 25 mA. En effet, ce circuit intégré admet d'être alimenté sous une tension plus faible que les autres circuits de type MOS et celle-ci peut varier dans des limites assez larges. On met donc à profit cette particularité pour régler ou déterminer le courant circulant dans les diodes, en choisissant la tension d'alimentation en conséquence. Typiquement, avec le type de circuit in­tégré mentionné plus haut, la tension est choisie aux environs de 4 V, pour obenir un courant de l'ordre de 25 mA dans chaque diode. Pour cette va­leur de courant, la tension aux bornes de la diode est voisine de 1,8 V. La puissance dissipée dans chaque mémoire est donc de l'ordre de 0,062 W. Comme chaque circuit intégré contient huit mémoires, la puissance maximum dissipée par ledit circuit intégré (correspondant à huit diodes allumées) est de 0,5 W, ce qui correspond à la puissance admissible par ce type de circuit intégré. Si on admet un taux d'utilisation des diodes de l'ordre de 35 %, la puissance moyenne dissipée par chaque circuit n'est donc en fait que de 0,175 W.Referring again to FIG. 1, it can be seen that the memories 12 are connected to be loaded by the outputs of a shift register of the serial type, that is to say with serial data inputs and parallel outputs, the latter being connected to the inputs for loading the memories 12. The progression of the information in the register takes place at the rate of a high-frequency clock, applied by a clock link 14. The transfer of information from the inputs to the outputs of the memories 12 is controlled when the information train corresponding to a complete image has reached the last stage of the shift register 13. At this time, a control signal is applied on a loading BUS 15 common to all the memories 12. In practice, the control system for the diode array 11 will advantageously be implemented by cascading a suitable number of integrated circuits of the 74 HC 4094 B type incorporating the times of stages 13a of the shift register and a corresponding number (eight in the example) of memories 12 connected to the outputs of these stages of register. The accessible outputs of said memories 12 are connected directly to light-emitting diodes 11, respectively; according to the assembly of Figure 2 or that of Figure 3. The output of the last stage of the register of a given integrated circuit is connected to the input of the first stage of another integrated circuit of the same type, located nearby. The current of each flip-flop forming memory 12 is sufficient to optimally supply the light-emitting diode, which typically requires a current of the order of 25 mA. Indeed, this integrated circuit admits to being supplied with a lower voltage than the other MOS type circuits and this can vary within fairly wide limits. This feature is therefore used to adjust or determine the current flowing in the diodes, by choosing the supply voltage accordingly. Typically, with the type of integrated circuit mentioned above, the voltage is chosen around 4 V, to obtain a current of the order of 25 mA in each diode. For this current value, the voltage across the diode is close to 1.8 V. The power dissipated in each memory is therefore of the order of 0.062 W. As each integrated circuit contains eight memories, the maximum power dissipated by said integrated circuit (corresponding to eight lit diodes) is 0.5 W, which corresponds to the power admissible by this type of integrated circuit. If we assume a diode utilization rate of around 35%, the average power dissipated by each circuit is therefore in fact only 0.175 W.

Selon une autre caractéristique importante de l'invention, les étages 13a du registre à décalage sont agencés en groupes d'étages adja­cents les uns des autres (c'est-à-dire topologiquement voisins sur le panneau d'affichage) et un moyen d'amplification et de remise en forme 18 est intercalé dans la liaison d'horloge entre deux tels groupes adjacents quelconques, tandis qu'un moyen retardateur 19 est intercalé entre la sortie de données et l'entrée de données de ces mêmes groupes adjacents. Ainsi, le signal d'horloge haute-fréquence est toujours exploitable d'une extrémité à l'autre du panneau d'affichage, malgré les capacités parasites réparties sur toute la distance, grâce aux moyens 18 disposés de proche en proche. La désynchronisation qui en résulte est sans conséquence grâce au retard apporté simultanément dans le transfert des informations, de groupe en groupe. Le retard entre deux groupes devra être supérieur au retard de l'horloge entre ces mêmes groupes. Pratiquement, chaque am­plificateur pourra être réalisé par deux inverseurs en cascade, par exem­ple disponibles dans des circuits intégrés de la même catégorie, portant la référence 74 HCU 04. Des moyens retardateurs 19 sont en outre disponi­bles dans chaque circuit intégré de type 74 HC 4094 B renfermant les re­gistres et les mémoires. Dans l'exemple de la figure 1, on a représenté par souci de simplification un amplificateur 18 et un moyen retardateur 19 associé à chaque circuit intégré, c'est-à-dire pour huit diodes. En fait, on pourra les "espacer" beaucoup plus, le nombre d'étage de chaque groupe pouvant être compris entre dix et quarante et de préférence voisin de trente. Enfin, comme mentionné précédemment, on prévoit de transmettre le signal d'horloge sous une fréquence réduite dans le toron de fils con­ducteurs reliant le panneau d'affichage et son unité de commande renfer­mant le générateur d'horloge haute-fréquence, non représenté. Ainsi, le dispositif de la figure 4 connecté à la sortie du générateur d'horloge haute-fréquence, donc à distance du panneau, fournit un signal dont la fréquence est réduite de moitié. Il se compose d'une bascule 20 rebouclée sur son entrée par un inverseur 21 dont le signal de sortie est amplifiant 22 avant d'être appliqué à la ligne d'horloge. Le dispositif de la figu­re 5 est un multiplicateur de fréquence conçu pour doubler la fréquence du signal qu'il reçoit. Il se compose d'un amplificateur 24 distribuant son signal de sortie à deux monostables 25, 26, montés en parallèles et dé­phasés par un inverseur 27. Les sorties des deux monostables sont reliées aux deux entrées d'une porte OU 28 dont la sortie restitue la fréquence originale.According to another important characteristic of the invention, the stages 13a of the shift register are arranged in groups of stages adjacent to each other (that is to say topologically neighboring on the display panel) and a means d amplification and fitness 18 is interposed in the clock link between any two such adjacent groups, while a delay means 19 is interposed between the data output and data input from these same adjacent groups. Thus, the high-frequency clock signal can still be used from one end to the other of the display panel, despite the parasitic capacities distributed over the entire distance, by means 18 arranged gradually. The resulting desynchronization is inconsequential thanks to the delay brought simultaneously in the transfer of information, from group to group. The delay between two groups must be greater than the delay of the clock between these same groups. In practice, each amplifier can be produced by two cascade inverters, for example available in integrated circuits of the same category, bearing the reference 74 HCU 04. Self-timer means 19 are also available in each integrated circuit of type 74 HC 4094 B containing registers and memories. In the example of FIG. 1, an amplifier 18 and a delay means 19 associated with each integrated circuit, that is to say for eight diodes, have been represented for the sake of simplification. In fact, it will be possible to "space" them much more, the number of stages in each group possibly being between ten and forty and preferably close to thirty. Finally, as mentioned above, provision is made to transmit the clock signal at a reduced frequency in the strand of conductive wires connecting the display panel and its control unit containing the high-frequency clock generator, not shown. Thus, the device of FIG. 4 connected to the output of the high-frequency clock generator, therefore at a distance from the panel, supplies a signal whose frequency is reduced by half. It consists of a flip-flop 20 looped back to its input by an inverter 21 whose output signal is amplifying 22 before being applied to the clock line. The device in Figure 5 is a frequency multiplier designed to double the frequency of the signal it receives. It consists of an amplifier 24 distributing its output signal to two monostables 25, 26, mounted in parallel and phase shifted by an inverter 27. The outputs of the two monostables are connected to the two inputs of an OR gate 28 whose output is output the original frequency.

Le système qui vient d'être décrit permet l'affichage d'images successives à très grande vitesse, jusqu'à mille images par seconde. Ces performances peuvent être mises à profit pour l'affichage en continu d'une image fixe comportant des diodes allumées avec des niveaux lumineux différents, obtenus par allumage et extinction rapide et successive de ces diodes. A titre d'exemple, pour une fréquence minimale de vingt images par seconde, on peut obtenir jusqu'à cinquante niveaux lumineux différents.The system which has just been described allows the display of successive images at very high speed, up to a thousand images per second. These performances can be taken advantage of for the continuous display of a still image comprising diodes lit with different light levels, obtained by rapid and successive switching on and off of these diodes. For example, for a minimum frequency of twenty images per second, one can obtain up to fifty different light levels.

Claims (6)

1. Panneau d'affichage à matrice de diodes électroluminescentes (11), par exemple du type journal lumineux, chaque diode étant alimentée par l'intermédiaire d'une mémoire (12), caractérisé en ce que les mémoires sont réalisées en technologie CMOS rapide, en ce que les diodes (11) sont directement connectées aux sorties de leurs mémoires respectives et en ce que la tension d'alimentation desdites mémoires est choisie pour fixer la valeur du courant dans lesdites diodes.1. Display panel with a matrix of light-emitting diodes (11), for example of the light journal type, each diode being supplied by means of a memory (12), characterized in that the memories are produced in rapid CMOS technology , in that the diodes (11) are directly connected to the outputs of their respective memories and in that the supply voltage of said memories is chosen to fix the value of the current in said diodes. 2. Panneau d'affichage selon la revendication 1, caractérisé en ce que lesdites mémoires (12) sont réalisées à partir de circuits intégrés de la série HCMOS, de préférence à partir de circuits du type 74 HC 4094 B.2. Display panel according to claim 1, characterized in that said memories (12) are produced from integrated circuits of the HCMOS series, preferably from circuits of type 74 HC 4094 B. 3. Panneau d'affichage selon la revendication 1 ou 2, caractéri­sé en ce que chaque mémoire (12) est connectée pour être chargée par un étage (13a) correspondant d'un registre à décalage (13) de type série, recevant pour chaque image une succession d'informations générées par une unité de commande au rythme d'une horloge, une liaison de chargement (15) étant commune à toutes les mémoires.3. Display panel according to claim 1 or 2, characterized in that each memory (12) is connected to be loaded by a stage (13a) corresponding to a shift register (13) of series type, receiving for each image a succession of information generated by a control unit at the rate of a clock, a loading link (15) being common to all the memories. 4. Panneau d'affichage selon la revendication 3, caractérisé en ce que les étages (13a) du registre à décalage sont agencés en groupes d'étages adjacents les uns des autres, en ce qu'un moyen d'amplification et de remise en forme (18) est intercalé dans la liaison d'horloge entre deux groupes adjacents quelconques et en ce qu'un moyen retardateur (19) est intercalé entre la sortie de données et l'entrée de données de ces mêmes groupes adjacents.4. Display panel according to claim 3, characterized in that the stages (13a) of the shift register are arranged in groups of stages adjacent to each other, in that a means of amplification and restoration form (18) is interposed in the clock link between any two adjacent groups and in that a delay means (19) is interposed between the data output and the data input of these same adjacent groups. 5. Panneau d'affichage selon la revendication 4, caractérisé en ce que le nombre d'étages de chaque groupe est compris entre dix et qua­rante, de préférence voisin de trente.5. Display panel according to claim 4, characterized in that the number of stages of each group is between ten and forty, preferably close to thirty. 6. Panneau d'affichage selon l'une des revendications 3 à 5, dans lequel l'horloge précitée est située à distance et reliée à la matrice de diodes par une liaison d'une certaine longueur, caractérisé en ce que ladite horloge est associée à un circuit réducteur de fréquence (figure 4) pour émettre un signal d'horloge de fréquence réduite et en ce que ladite matrice de diodes électroluminescentes est associée à un multiplicateur de fréquence (figure 4) recevant ledit signal d'horloge de fréquence ré­duite et susceptible de régénérer un signal d'horloge haute-fréquence.6. Display panel according to one of claims 3 to 5, wherein the above clock is located at a distance and connected to the diode array by a link of a certain length, characterized in that said clock is associated a frequency reducing circuit (FIG. 4) for transmitting a clock signal of reduced frequency and in that said matrix of light-emitting diodes is associated with a frequency multiplier (FIG. 4) receiving said clock signal of reduced frequency and capable of regenerating a high-frequency clock signal.
EP86401754A 1985-09-30 1986-08-05 Led matrix display panel Expired - Lifetime EP0221786B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT86401754T ATE74225T1 (en) 1985-09-30 1986-08-05 DISPLAY PANEL WITH LIGHT EMITTING DIODES.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8514475A FR2588112B1 (en) 1985-09-30 1985-09-30 LIGHT EMITTING DIODE ARRAY DISPLAY PANEL
FR8514475 1985-09-30

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EP0221786A2 true EP0221786A2 (en) 1987-05-13
EP0221786A3 EP0221786A3 (en) 1989-03-22
EP0221786B1 EP0221786B1 (en) 1992-03-25

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EP (1) EP0221786B1 (en)
AT (1) ATE74225T1 (en)
DE (1) DE3684556D1 (en)
FR (1) FR2588112B1 (en)
NO (1) NO863528L (en)

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EP0755041A1 (en) * 1995-07-17 1997-01-22 Siemens Integra Verkehrstechnik Ag Signalling device

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GB0110802D0 (en) * 2001-05-02 2001-06-27 Microemissive Displays Ltd Pixel circuit and operating method
CN107226016A (en) * 2017-07-05 2017-10-03 上海小糸车灯有限公司 Automobile tail lamp circuit based on Communication Control

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4117889A1 (en) * 1991-05-31 1992-12-03 Diehl Gmbh & Co Digital display control circuit for electric hot plates - transfers data using multiplexer and grey code to seven-segment converter, controlled by CPU and oscillator
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EP0755041A1 (en) * 1995-07-17 1997-01-22 Siemens Integra Verkehrstechnik Ag Signalling device

Also Published As

Publication number Publication date
NO863528D0 (en) 1986-09-03
DE3684556D1 (en) 1992-04-30
NO863528L (en) 1987-03-31
FR2588112A1 (en) 1987-04-03
US4982182A (en) 1991-01-01
EP0221786B1 (en) 1992-03-25
FR2588112B1 (en) 1989-12-29
ATE74225T1 (en) 1992-04-15
EP0221786A3 (en) 1989-03-22

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