EP0221786A2 - Anzeigetafel mit Leuchtdioden - Google Patents

Anzeigetafel mit Leuchtdioden Download PDF

Info

Publication number
EP0221786A2
EP0221786A2 EP86401754A EP86401754A EP0221786A2 EP 0221786 A2 EP0221786 A2 EP 0221786A2 EP 86401754 A EP86401754 A EP 86401754A EP 86401754 A EP86401754 A EP 86401754A EP 0221786 A2 EP0221786 A2 EP 0221786A2
Authority
EP
European Patent Office
Prior art keywords
memories
display panel
clock
frequency
diodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP86401754A
Other languages
English (en)
French (fr)
Other versions
EP0221786B1 (de
EP0221786A3 (en
Inventor
Jean Flinois
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CENTRE D'AUTOMATISMES ET DE RECHERCHES ELECTRONIQUES CENTAURE SARL
Original Assignee
CENTRE D'AUTOMATISMES ET DE RECHERCHES ELECTRONIQUES CENTAURE SARL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CENTRE D'AUTOMATISMES ET DE RECHERCHES ELECTRONIQUES CENTAURE SARL filed Critical CENTRE D'AUTOMATISMES ET DE RECHERCHES ELECTRONIQUES CENTAURE SARL
Priority to AT86401754T priority Critical patent/ATE74225T1/de
Publication of EP0221786A2 publication Critical patent/EP0221786A2/de
Publication of EP0221786A3 publication Critical patent/EP0221786A3/fr
Application granted granted Critical
Publication of EP0221786B1 publication Critical patent/EP0221786B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2085—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/04—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions
    • G09G3/06—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions using controlled light sources
    • G09G3/12—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions using controlled light sources using electroluminescent elements
    • G09G3/14—Semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the invention relates to a display panel with a matrix of light-emitting diodes, typically forming a luminous newspaper, and it relates more particularly to such a panel which is both more economical and brighter than known analogous systems, while allowing more fast.
  • a conventional luminous journal consists of a matrix of light-emitting diodes, a corresponding number of memories (typically bi-stable flip-flops) interposed between said diodes and a shift register in which the information representative of an image to be displayed circulates. .
  • This information is delivered at the rate of a clock by a control unit associated with a program memory.
  • the control unit and the program memory are generally located in a separate box from the panel and connected to the latter by a strand of conductive wires. This arrangement is advantageous when the diode panel is intended to be placed outside and subjected to the weather. In this case, the most fragile components, contained in the control unit, can be placed in a sheltered place and more easily accessible for the modification or updating of the messages to be reproduced.
  • the invention makes it possible in particular to solve this problem.
  • the basic principle of the invention results from the search for a better adaptation between the available integrated circuits, constituting the memories and the light-emitting diodes usually used for such an application.
  • By analyzing the characteristics of recent integrated circuits of rapid CMOS technology it has thus been found that the manufacturers of these integrated circuits designed for high-speed digital computing applications, had been led to lower the supply voltage, while admitting a higher current, so that the circuits can be driven at a higher clock frequency.
  • One of the features of the invention is to propose a new application of this type of component, for directly supplying a light-emitting diode.
  • the invention therefore essentially relates to a display panel with a matrix of light-emitting diodes, for example of the light journal type, each diode being supplied by means of a memory, characterized in that the memories are made of fast CMOS technology, in that the diodes are directly connected to the outputs of their respective memories, and in that the supply voltage of said memories is chosen to fix the value of the current in said diodes.
  • Another problem solved by the invention relates to the very structure of the display panels. This involves efficiently transmitting the high-frequency clock to all the circuits, despite the large dimensions of the diode array. Indeed, it is not possible to provide a clock common to all the integrated circuits. The parasitic capacities which would result therefrom would not allow the transfer of information at the chosen frequency, that is to say of the order of 2 MHz. It is therefore necessary to provide, step by step, means for amplifying or regenerating the clock signal, which can desynchronize the various circuits of the shift register. According to another aspect of the invention, means are provided for the shift register to function correctly without the clock signal being actually synchronized at all points of the register.
  • the display panel defined above is also characterized in that the stages of the shift register are arranged in groups of stages adjacent to each other, in that a means of amplification and reset in form is interposed in the clock link between any two adjacent groups and in that a delay means is interposed between the data output and the data output of these same adjacent groups.
  • Another feature of the invention consists in supplying the display panel with a reduced frequency clock and in regenerating the high frequency clock in the display panel itself, which makes it possible to have a length of conductive cable. more important between the control unit and the high-frequency clock proper, and the display panel.
  • each memory is composed of a bi-stable flip-flop and, according to the invention, the corresponding diode 11 is directly connected to its output, that is to say in particular without series resistance.
  • There are two possibilities of connecting the diode relative to the flip-flop either by using the transistor of channel N, the diode being connected between the output of the memory and the mass (fig. 2), or by using the transistor of the channel P, the diode being connected, this time, to the power supply terminal (fig. 3).
  • the memories 12 are connected to be loaded by the outputs of a shift register of the serial type, that is to say with serial data inputs and parallel outputs, the latter being connected to the inputs for loading the memories 12.
  • the progression of the information in the register takes place at the rate of a high-frequency clock, applied by a clock link 14.
  • the transfer of information from the inputs to the outputs of the memories 12 is controlled when the information train corresponding to a complete image has reached the last stage of the shift register 13. At this time, a control signal is applied on a loading BUS 15 common to all the memories 12.
  • control system for the diode array 11 will advantageously be implemented by cascading a suitable number of integrated circuits of the 74 HC 4094 B type incorporating the times of stages 13a of the shift register and a corresponding number (eight in the example) of memories 12 connected to the outputs of these stages of register.
  • the accessible outputs of said memories 12 are connected directly to light-emitting diodes 11, respectively; according to the assembly of Figure 2 or that of Figure 3.
  • the output of the last stage of the register of a given integrated circuit is connected to the input of the first stage of another integrated circuit of the same type, located nearby.
  • each flip-flop forming memory 12 is sufficient to optimally supply the light-emitting diode, which typically requires a current of the order of 25 mA. Indeed, this integrated circuit admits to being supplied with a lower voltage than the other MOS type circuits and this can vary within fairly wide limits. This feature is therefore used to adjust or determine the current flowing in the diodes, by choosing the supply voltage accordingly.
  • the voltage is chosen around 4 V, to obtain a current of the order of 25 mA in each diode. For this current value, the voltage across the diode is close to 1.8 V.
  • the power dissipated in each memory is therefore of the order of 0.062 W.
  • the maximum power dissipated by said integrated circuit is 0.5 W, which corresponds to the power admissible by this type of integrated circuit. If we assume a diode utilization rate of around 35%, the average power dissipated by each circuit is therefore in fact only 0.175 W.
  • the stages 13a of the shift register are arranged in groups of stages adjacent to each other (that is to say topologically neighboring on the display panel) and a means d amplification and fitness 18 is interposed in the clock link between any two such adjacent groups, while a delay means 19 is interposed between the data output and data input from these same adjacent groups.
  • the high-frequency clock signal can still be used from one end to the other of the display panel, despite the parasitic capacities distributed over the entire distance, by means 18 arranged gradually.
  • the resulting desynchronization is inconsequential thanks to the delay brought simultaneously in the transfer of information, from group to group.
  • the delay between two groups must be greater than the delay of the clock between these same groups.
  • each amplifier can be produced by two cascade inverters, for example available in integrated circuits of the same category, bearing the reference 74 HCU 04.
  • Self-timer means 19 are also available in each integrated circuit of type 74 HC 4094 B containing registers and memories.
  • an amplifier 18 and a delay means 19 associated with each integrated circuit that is to say for eight diodes, have been represented for the sake of simplification. In fact, it will be possible to "space" them much more, the number of stages in each group possibly being between ten and forty and preferably close to thirty.
  • the device of FIG. 4 connected to the output of the high-frequency clock generator, therefore at a distance from the panel, supplies a signal whose frequency is reduced by half. It consists of a flip-flop 20 looped back to its input by an inverter 21 whose output signal is amplifying 22 before being applied to the clock line.
  • the device in Figure 5 is a frequency multiplier designed to double the frequency of the signal it receives. It consists of an amplifier 24 distributing its output signal to two monostables 25, 26, mounted in parallel and phase shifted by an inverter 27. The outputs of the two monostables are connected to the two inputs of an OR gate 28 whose output is output the original frequency.
  • the system which has just been described allows the display of successive images at very high speed, up to a thousand images per second. These performances can be taken advantage of for the continuous display of a still image comprising diodes lit with different light levels, obtained by rapid and successive switching on and off of these diodes. For example, for a minimum frequency of twenty images per second, one can obtain up to fifty different light levels.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of El Displays (AREA)
  • Illuminated Signs And Luminous Advertising (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electric Clocks (AREA)
EP86401754A 1985-09-30 1986-08-05 Anzeigetafel mit Leuchtdioden Expired - Lifetime EP0221786B1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT86401754T ATE74225T1 (de) 1985-09-30 1986-08-05 Anzeigetafel mit leuchtdioden.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8514475A FR2588112B1 (fr) 1985-09-30 1985-09-30 Panneau d'affichage a matrice de diodes electroluminescentes
FR8514475 1985-09-30

Publications (3)

Publication Number Publication Date
EP0221786A2 true EP0221786A2 (de) 1987-05-13
EP0221786A3 EP0221786A3 (en) 1989-03-22
EP0221786B1 EP0221786B1 (de) 1992-03-25

Family

ID=9323389

Family Applications (1)

Application Number Title Priority Date Filing Date
EP86401754A Expired - Lifetime EP0221786B1 (de) 1985-09-30 1986-08-05 Anzeigetafel mit Leuchtdioden

Country Status (6)

Country Link
US (1) US4982182A (de)
EP (1) EP0221786B1 (de)
AT (1) ATE74225T1 (de)
DE (1) DE3684556D1 (de)
FR (1) FR2588112B1 (de)
NO (1) NO863528L (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4117889A1 (de) * 1991-05-31 1992-12-03 Diehl Gmbh & Co Ansteuerschaltung fuer eine digitale anzeigeeinheit
EP0755041A1 (de) * 1995-07-17 1997-01-22 Siemens Integra Verkehrstechnik Ag Signalisierungsvorrichtung

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5459479A (en) * 1993-10-15 1995-10-17 Marcum Enterprises Incorporated Solid state depth locator having liquid crystal display
GB0110802D0 (en) * 2001-05-02 2001-06-27 Microemissive Displays Ltd Pixel circuit and operating method
CN107226016A (zh) * 2017-07-05 2017-10-03 上海小糸车灯有限公司 基于通讯控制的汽车尾灯电路

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2277389A1 (fr) * 1974-07-01 1976-01-30 Ibm Panneau d'affichage de caracteres mobiles a decalage de phase optique

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3541543A (en) * 1966-07-25 1970-11-17 Texas Instruments Inc Binary decoder
US4014013A (en) * 1975-04-07 1977-03-22 Texas Instruments Incorporated Direct drive display system for mos integrated circuits using segment scanning
US4247925A (en) * 1978-07-13 1981-01-27 Joseph Meshi Game microcomputer
US4426766A (en) * 1981-10-21 1984-01-24 Hughes Aircraft Company Method of fabricating high density high breakdown voltage CMOS devices
JPS59111197A (ja) * 1982-12-17 1984-06-27 シチズン時計株式会社 マトリクス型表示装置の駆動回路
US4656469A (en) * 1983-11-17 1987-04-07 Oliver Earl H Activated work and method of forming same
US4682162A (en) * 1984-09-14 1987-07-21 Trans-Lux Corporation Electronic display unit
US4669424A (en) * 1985-06-07 1987-06-02 Bianco Frank J Apparatus for and method of repelling pests such as fleas and ticks
US4689504A (en) * 1985-12-20 1987-08-25 Motorola, Inc. High voltage decoder
US4725993A (en) * 1987-03-20 1988-02-16 Elexis Corporation Device including battery-activated oscillator

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2277389A1 (fr) * 1974-07-01 1976-01-30 Ibm Panneau d'affichage de caracteres mobiles a decalage de phase optique

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IEEE ELECTRO, vol. 7, mai 1982, pages 1-11, New York, US; R. BROOMFIELD et al.: "ISO-CMOS technology in the microprocessor interface" *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4117889A1 (de) * 1991-05-31 1992-12-03 Diehl Gmbh & Co Ansteuerschaltung fuer eine digitale anzeigeeinheit
DE4117889C5 (de) * 1991-05-31 2006-06-22 Diehl Stiftung & Co.Kg Ansteuerschaltung für eine digitale Anzeigeeinheit
EP0755041A1 (de) * 1995-07-17 1997-01-22 Siemens Integra Verkehrstechnik Ag Signalisierungsvorrichtung

Also Published As

Publication number Publication date
NO863528D0 (no) 1986-09-03
DE3684556D1 (de) 1992-04-30
NO863528L (no) 1987-03-31
FR2588112A1 (fr) 1987-04-03
US4982182A (en) 1991-01-01
EP0221786B1 (de) 1992-03-25
FR2588112B1 (fr) 1989-12-29
ATE74225T1 (de) 1992-04-15
EP0221786A3 (en) 1989-03-22

Similar Documents

Publication Publication Date Title
EP0645888B1 (de) Digitale Verzögerungsleitung
EP0709254B1 (de) Elektronisches Informationsübertragungssystem auf stromführenden Leitungen, insbesonders für ein Kraftfahrzeug
EP0506567B1 (de) Schnell wiederkonfigurienbare lichtwellenlänge Multiplexer
FR2705844A1 (fr) Procédé et dispositif de modulation en amplitude d'un signal radiofréquence.
EP0631240A1 (de) Schaltungsanordnung zur Datenübertragung
FR2694828A1 (fr) Bus d'ordinateur à transfert de paquets.
EP0221786B1 (de) Anzeigetafel mit Leuchtdioden
EP0194177B1 (de) Teilnehmerschnittstellenschaltung mit Überwachungsbetrieb bei verringerter Speisung
EP0695112A1 (de) Lumineszenzdiodenvorrichtung
FR2774536A1 (fr) Procede de detection d'un ou plusieurs canaux libres dans un multiplex temporel optique, un dispositif de mise en oeuvre et une application du dispositif
EP0053214B1 (de) Verteilungssystem für digitale Signale
FR2552575A1 (fr) Circuit de commande d'un panneau a plasma de type alternatif
FR2767976A1 (fr) Dispositif d'aide au demarrage pour une pluralite de sources de courant
FR2531791A1 (fr) Circuit d'adressage pour equipement de test automatique
EP0961207B1 (de) Gerät zur Kommunikation zwischen einem Neuronalen Netzwerk und einem Benutzersystem über einen Bus
FR2760914A1 (fr) Circuit convertisseur de niveaux analogiques
EP0016677A1 (de) Vorrichtung zur digitalen Übertragung
FR2584520A1 (fr) Dispositif d'affichage comportant un reseau matriciel de sources lumineuses
FR2666922A1 (fr) Chaine de mesure et de commande d'une pluralite d'elements constituant l'equipement de bateaux de plaisance.
FR2550867A1 (fr) Installation de commande, notamment pour une decoration lumineuse
EP0760180B1 (de) Verfahren und einrichtung für pseudozufallsschalten
FR2667959A1 (fr) Circuit de gestion de sorties pour automate programmable.
WO2004051446A1 (fr) Circuit integre comportant des sous-ensembles connectes en serie
EP0383666B1 (de) Modulare Interface-Schaltung und Teilnehmeranordnung für ein digitales Netz
EP1331737B1 (de) Pulsgeneratorschaltung und entsprechendes mikroelektronisches Bauelement

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE CH DE GB IT LI LU NL SE

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): AT BE CH DE GB IT LI LU NL SE

17P Request for examination filed

Effective date: 19890727

17Q First examination report despatched

Effective date: 19910604

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT BE CH DE GB IT LI LU NL SE

REF Corresponds to:

Ref document number: 74225

Country of ref document: AT

Date of ref document: 19920415

Kind code of ref document: T

REF Corresponds to:

Ref document number: 3684556

Country of ref document: DE

Date of ref document: 19920430

ITF It: translation for a ep patent filed
GBT Gb: translation of ep patent filed (gb section 77(6)(a)/1977)
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
EPTA Lu: last paid annual fee
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: LU

Payment date: 19940801

Year of fee payment: 9

Ref country code: GB

Payment date: 19940801

Year of fee payment: 9

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: SE

Payment date: 19940816

Year of fee payment: 9

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: AT

Payment date: 19940817

Year of fee payment: 9

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: BE

Payment date: 19940822

Year of fee payment: 9

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: CH

Payment date: 19940829

Year of fee payment: 9

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: NL

Payment date: 19940831

Year of fee payment: 9

Ref country code: DE

Payment date: 19940831

Year of fee payment: 9

EAL Se: european patent in force in sweden

Ref document number: 86401754.6

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19950805

Ref country code: GB

Effective date: 19950805

Ref country code: AT

Effective date: 19950805

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Effective date: 19950806

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LI

Effective date: 19950831

Ref country code: CH

Effective date: 19950831

Ref country code: BE

Effective date: 19950831

BERE Be: lapsed

Owner name: CENTRE D'AUTOMATISMES ET DE RECHERCHES ELECTRONIQU

Effective date: 19950831

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Effective date: 19960301

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 19950805

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

NLV4 Nl: lapsed or anulled due to non-payment of the annual fee

Effective date: 19960301

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Effective date: 19960501

EUG Se: european patent has lapsed

Ref document number: 86401754.6

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED.

Effective date: 20050805