DE2248238C3 - Flip-flop circuit arrangement - Google Patents

Description

The invention relates to a flip-flop circuit arrangement with MIS transistors, consisting of a first and second transistor, each having the input working electrode of one transistor connected to the Control electrode of the other transistor is connected, the output working electrodes with means for connecting these electrodes to ground reference potential are connected and the output signals are tapped from the input working electrodes, these Input working electrodes are connected to switching means for connection to a supply voltage source, furthermore consisting of a third and fourth transistor, whose input working electrode each over Switching means are connected to the input working electrodes of the first and second transistors, respectively.

Various embodiments of single-channel MIS binary flip-flop circuits are described, for example, in US Pat. Nos. 3,573,507 and 63 115. However, the circuit complexity in these known circuit arrangements is considerable and therefore unsatisfactory for reasons of cost. In particular, there is the disadvantage that a Clock signal source and a further signal source are required, the further signal source being inverse Outputs signals to the clock signal source, it does not matter whether the inverse signal in the same Flip-flop circuit is generated or externally

is fed. In US Patent 35 55 307 a flip-flop circuit is shown in which only one timing signal source is required. In this circuit are however, complementary MlS transistors are required, which are also available in large numbers.

The object of the present invention is to design a single-channel binary flip-flop so that one relatively small number of components is required and that still only a single timing signal source is necessary without the need to blow Control signals to form inverse signals. This task is performed for a flip-flop circuit arrangement of the initially specified type solved by the use of a fifth and sixth transistor whose respective output working electrode is connected to the control electrode of the fourth or third Transistor and its respective input working electrode is connected to the control electrode of the first or second transistor, the control electrode of the fifth and sixth transistor being connected to a voltage pulse source, the pulses of which are connected to these Control transistors conductive, and at the same time the output working electrodes of the third and fourth Apply transistor.

The invention is explained in more detail below with reference to the drawings

F i g. 1 a known flip-flop circuit,

Fig.2 shows a known compared to the circuit according to FIG. 1 modified flip-flop circuit,

3 shows a flip-flop circuit according to the invention,

F i g. 4 a further embodiment according to the invention,

Fig. 5 shows a frequency divider circuit using preparation of the flip-flop according to the invention.

In the following description, it is assumed that MOS devices are used because they are on can be used most economically in integrated circuits. In the same way, of course M IS components are also used.

F i g. 1 shows the most widely used flip-flop circuit using single-channel MIS transistors with no timing signal source. The circuit shows transistors 71 and T ₂ , whose control electrodes and input working electrodes are connected together and connected to a potential source - Vdd. The output working electrodes of 71 and T ₂ are connected to the Q ' and Q outputs. The output working electrode of Γι is also connected to the input working electrode of a transistor T ₃ , the control electrode of which is connected to an input terminal /. The output working electrode of T ₃ is at the ground reference potential. The output working electrode Γι is also connected to the input bar electrode of a transistor T ₄ , whose output working electrode is also at ground reference potential. The control electrode of T ₄ is connected to the output working electrode of Tz . The output working electrode of T ₂ is connected to the input working electrode of Ti, the control electrode of which is connected to the input terminal K. The output working electrode of Ti is also at ground reference potential. The output working electrode of T ₂ is also connected to the input working electrode of a transistor Tb. Its control electrode is connected to the output working electrode of T \ , while the output working _{electrode of T 6 is} also at ground reference potential. The switching states that occur are as follows:

State

a b c d

0 0

1 1

It is assumed that the logical value "1"

ίο represents the state in which the two input signals applied to / and K are sufficiently negative that the transistors of the circuit become conductive. For easier understanding it is assumed that the logical value "1" is equivalent - Vdd is during the logical value »0« corresponds to the ground reference potential. The same symbols also apply to the logical output values Q.

In state a, an input signal with the logical value "0" is applied to the / terminal and thus to the Control electrode of transistor T ₃ . T ₃ is blocked and point A is separated from the ground reference potential. Furthermore, the value "0" is at K. The switching state of each of the transistors T ₄ and T ₆ remains unchanged since the points A and B have no potential experience change when the signal values »0« are applied to inputs / and K. This also means that the output ^ remains unchanged

In switching state b, the value for / is changed to »1« while input K remains unchanged at »0« This means that T ₃ becomes conductive and point A now has ground reference potential, T ₆ is now blocked, as is T ₅ , so that the potential -V _DD is at point β, which corresponds to the logical value "1"

In switching state c, input J has the value "0", while input K has the value "1". This means that there is now ground reference potential at point B , whereby Ts is conductive and T ^ is blocked. Since the input / is at »0«, point A shows the potential - Vdd so that Q ' now has the value "1"

Point B remains at "0" since both T ₅ and T _{6 are} conductive

so that the output Q has the value "0" having.

Both inputs / and K am are in switching state d

logical value "1" lying. This means that Ts and T _{5 are} conductive, so that both points A and B are at ground reference potential. If the signals with the logical value "1" are now removed from / and K , points A and B can float because they are now from the ground reference point are tial separated, so that now the flip-flop one which can assume stable states, at which Q either "0" and "1" is however indefinite, which of these states is assumed.

In the circuit of Figure 2 is between the

Output working electrode of the transistor T ₃ and the ground reference potential, a transistor T ₇ and a switch Sio are connected. The control electrode of T ₁ is connected to the output Q ' via a switch S \ . In a corresponding manner, a transistor is T% and a Switch Si 2 connected between the output working electrode of transistor T ₅ and ground reference potential. The control electrode of the transistor 7J is connected to the output Q _{via a switch S 2} . In switching state c according to the table above, where at J

b5 the value "0" and K the value "1" and accordingly Q equals "0", the switches Si and S _{2 are} open and the switches S _{] o} ut.d S, _{2 are} closed. The circuit now assumes the switching state according to d, where

J changes to the logical value "1". This makes Ti conductive, but no current can flow because Ti is blocked (switch Si is open). The switch Si is now closed and the switch S _{10 is} opened at the same time. Since there is A-Voo at the point, this potential reaches the control electrode of Ti and is stored there. (.-r T ₁ , however, no current can flow because the switch Sw is open, which is why A remains at the potential - VpD , while Si is closed and the control electrode is charged by Ti . If Si is now opened and Sio is closed at the same time, this has the effect it now sets the charge on the gate of T ₇ that T conducts ₇ and at point a now has Ti, Ti and S \ o ground reference potential lie ;. the point a therefore assumes the logic value "0" a. Considering the point collar one assumes that 5, and Si are gciriggcrt simultaneously, which also applies to Sio and S12, results from the above table that the switching state of the output Q at the logic value of c was "0". Since the on the control electrode of T ₈ lying potential corresponds to the logic value "0" (ground reference potential), when S2 is closed, Tg does not conduct, so that the transistors Ti and 7g and the switches Sj and Sn do not contribute to the determination of the potential at point B during the transition from the switching state c to Sc have hold state d according to the previous table. If point A now assumes the logic value "0", T _{6 is} blocked and since S2 is open at this point in time, there is no current connection from the output working _{electrode of transistor T 2} to the ground reference potential. Point B and thus the output <? Thus have the logical value "1". In this way, output Q in state c has changed to output Q ' in state d. If one considers the cases in which there is a transition from state b to state d or from state a to state d, one sees that Q changes each time after Q ' , where Q' is the alternating, binary logical value of Q ' In the circuit according to FIG. 2 the following switching states occur:

State In K _n <? _n +1 a 0 0 Qn b 1 0 1 C. 0 1 0 d 1 1 Qn

Q _n + 1 represents the output Q after n + \ pulses of the switches Si, S ₂ , Sio and S12 . Q _n corresponds to the exit ** · »« · ** ^ n £ ch i? ~! ^{Ni rl} üls £ n this ScG2l * ^ ^r l *** practical embodiment, the switches Si and S ₂ are normally triggered by the timing pulses while the switches Sn and Sio are triggered by inverse signals of these pulses. As mentioned above, this flip-flop circuit requires both a timing signal source and a source of inverse signals, which means that an extra circuit is required and also a relatively complex circuit is required in order to obtain the required operating speed and correspondingly clear output signals will. The aforementioned Schahimg according to US Pat. No. 3,555,307 eliminates the need for an inverse Zetttaktsignalquelle, but there complicated circuits with complementary MIS transistors are required. According to the present invention, single-channel components are used, the circuit being designed so that inverse clock signals are not required, but that only a clock signal source is required, the pulses of which change between a modulating signal and ground reference potential.

The F i g. 3 shows a basic circuit arrangement in which the switching components which are identical to those according to FIG. t and 2 have the same designation. Compared to the circuit arrangement according to FIG. 1 are used in the circuit according to FIG. 3 only four more transistors Ti, Te, T> and 7I _{0 are} required. The control electrode of the transistor T ₁ is connected to the output electrode of the transistor Γιο. Furthermore, the F. input electrode of Tw is connected to the output Q '. In a corresponding manner, the control electrode of transistor 7s is connected to the output electrode of T ₉ , the input electrode of which is connected to output Q. The control electrodes of T ₉ and T10 and the output working _{electrodes of T 7} and T ₈ are each connected to a clock signal source C. Their signals have a control potential for the transistors T> and Ti0 and a ground reference potential for the transistors Ti and T ₈ .

The table for the F i g. 2 is valid in the same way for the circuit arrangement according to FIG. 3, however, Q _n + \ the state of the output Q n + 1 after full time pulses represent. Q _n corresponding to the state of the output Q to η full clock pulses. Q ' is always the alternating binary logical value of Q.

First, consider the transition from state a to state b according to the table. Q _n + 1 is in state a at Q _n . Assuming that Q _{n changes} the logic value "1", T ₃ becomes conductive. At this point in time, the clock signal C has ground reference potential, at which T ₉ and T _{10 are} blocked . Therefore T ₇ is also blocked. Since point B has the potential "1" , T, is open at this point in time , Q ' is at "0" and T ₆ is blocked. Terminal K is at "0", which is why Ts is blocked

If a clock pulse C now occurs, the output working electrodes of T ₇ and T _{8 are} separated from the ground reference potential and T ₉ and T _t0 become conductive. Terminal A has the value "0" so that no current flows through Tio to open T ₇ . Point B, on the other hand, is at the value "1", so that a current flows through T ₉ and charges the control electrode of T ₁ As mentioned, the output working _{electrode of T 8 is} separated from the ground reference potential when the pulse C occurs so that sufficient time is available to fully charge the control electrode of T _8. The potential at C now returns to ground reference potential and the charge at the control electrode of T ₈ causes T " to remain open. However, since T _{5 is} blocked when iT is the logic value" 0, no current can flow through _{T 8, and} the output Q therefore remains at the logical value "1". In the following it is assumed that in state a Q _{m has} the logical value "0" An / the value "1" is applied, whereby T ₃ becomes conductive. Due to the potential at point Λ, T _{6 is} conductive and holds point B at the logical value "0". As a result of a pulse C becomes T ₉ and sliding Since point A has the logical value "1", a current flows through Τ "and charges the control electrode of T ₁ . Since the point B at »0« Begt bfefct T »is blocked. The clock signal C now becomes the ground reference potential, a current flows through 3a and 7J and the point A assumes the ground reference potential, ie the logical value "0",

whereby T _{b is} blocked. Since point B is now separated from the ground reference potential, it assumes the potential - V _m , ie the logical value "I". This means that no matter which binary value is present for Q _n in state a, the logical value "1" is always assumed in state b.

If one now looks at the transition from state b to state c, it must be assumed that point A is at the value "0" and point B at the value "I" in the state. The signal at input / now changes to the logical value "0", while input K now has the value "1". In this way, Tt is blocked and Γ _{5 is} opened. If a pulse C occurs, the control electrode is charged _{from Γ 8} to the potential at point B. 7} remains blocked. If C now goes back to ground reference potential, T ₅ and Γ _{Β become} conductive and point B takes on the value “0”, whereby T _{t is} blocked at the same time. Therefore the logical value "1" is now at point A.

The transition from state c to state d is considered below. In state d, the logic values "1" are present at the input connections J and K. whereby Γ ₃ and Tj become conductive. Since the value "1" is at point A in state c , T _{b is} conductive and 7 " _{4 is} blocked. If a pulse C now occurs, T" and Fio become conductive and the control electrode of Ti is brought to the potential of point A. If C now goes back to ground potential, Ti and 7? Are conductive and point A assumes the value "0", whereby T _{b is} blocked. Therefore point B assumes the logic value "1." As in the circuit according to F. 2 it can be clearly seen that with each transition from state a, b or c to state d there is an output ζ) which is equal to the alternating binary output value of the previous output Q. In state d, this means that Q _n + \ = <? '"Is.

The example according to FIG. 3 can therefore be taken from that the / - / C flip-flop shown there is the same Has operation like the circuit according to FIG. 2. However, there is an inverter for the timing signal is not required. as is required in the known circuits. This advantage is achieved without the need for complementary transistors.

In Fig. 4 is a flip-flop according to FIG. 3, in which additional input connections CLEAR and SET are provided. An additional transistor Tw is provided, the input working electrode of which is connected to the control electrode of Tt, the output working electrode of which is interconnected with the output working electrode of T ₁ and the control electrode of which is connected to the terminal CLEAR . The output working electrode of T _u is also connected to the input working electrode of a transistor Γι 3, the output working electrode of which is connected to the control electrode of Ti. The control electrode of 7 ~ u is connected to the control electrode of Tw. Furthermore, a transistor T \ 2 is provided, whose input working electrode is connected to the control electrode of T _b , whose output working electrode is connected to the output working electrode of T _b and whose control electrode is connected to the SE7 "terminal. The output working electrode of Tn is also connected to the input working electrode of a transistor 7" i4, whose Output working electrode is connected to the control electrode of transistor 7s. The control electrode of Tu is connected to the control electrode of T \ 2-

It is assumed that the point A is at the logical value "1" and the point Asia is at the logical value "0". A SFT pulse makes the transistors 7m and Tn conductive. Point A therefore takes on the logical value "1", ie its potential corresponds to the ground reference potential, at the same time point B is brought to the logical value "1". Any charge on the control electrode of Ti that would cause Tu to become conductive, which would bring point B to ground reference potential (K = "1", ie Γ ₅ is conductive) is _{diverted to ground via Γ, 4} , whereby 7 « remains locked. Terminal A is now at the value "0" and terminal B at the value "1". A Ci- £ / 4 /? - signal at the control electrodes of Tw and Γη acts in an analogous manner to a S £ T signal and causes the point ß to return to the value "0" and point A to the value "1" by placing point B via Tw and discharging the control electrode from Τη via Γι3 to ground reference potential.

The F i g. FIG. 5 shows a frequency dividing circuit which represents a special case of the circuit of FIG. 3, where the inputs ] and K are both at the logic value "1" and the transistors Tj and Γ5 are therefore omitted. It is assumed that point B has the logical value "1" and point A has the logical value "0". If a pulse C occurs, a current flows through Tq and charges the control electrode of Γ "conductive, the point to B assumes ground reference potential, the transistor 7i is blocked and the point A assumes the logical value" 1 ". If a pulse C occurs again, the potentials at points A and B are reversed again.

If the impulses C occur with a frequency f, signals with the frequency / 72 appear at the outputs Q and Q ' , which change between "0" and "1".

In the circuits described here, MOS transistors with a P-channel and a silicon control electrode were described. It goes without saying , however, that corresponding transistors with an N-channel can also be used, in which case the supply voltage source then naturally has an inverted polarity of + "Vdd

1 sheet of drawings

Claims (7)

Patent claims: 1. Flip-flop circuit arrangement with MIS transistors, consisting of a first and a second transistor, the input working electrode of one transistor being connected to the control electrode of the other transistor, the output working electrodes being connected to means for connecting these electrodes to ground reference potential and from the input working electrodes, the output signals are tapped, these input working electrodes are connected to switching means for connection to a supply voltage source, further consisting of a third and is fourth transistor, the input working electrode of which, however, switching means are connected to the input working electrodes of the first and second transistor, respectively, characterized by the Use of a fifth and sixth transistor (T% 71ο), whose respective output working electrode is connected to the control electrode of the fourth or third transistor (Tt. T ₁ ) and their respective input working electrode ode is connected to the control electrode of the first and second transistor (T ₄ , T ₆ ), the control electrode of the fifth and sixth transistor (Ti7io) being connected to a voltage pulse source, the pulses of which control these transistors conductively, and which simultaneously control the output working electrodes of the apply the third and fourth transistor (T ₁ , Tg) . 2. Circuit arrangement according to claim 1, characterized in that the respective input working electrode of the first and second transistor (T ₄ , T ₆ ) is connected to the supply voltage source via a load transistor (T \, T ₂ ) , this input working electrode in each case with the output working electrode of this Transistors fl \. Ti) , whose input working electrodes are connected to the supply voltage source. 3. Circuit arrangement according to claim 1 or 2, characterized in that the transistors MOS transistors with a silicon gate are. 4. Circuit arrangement according to claim 1, characterized in that the switching means for connecting the input working electrode of the third transistor (Tj) to the input working electrode of the first transistor (T ₄ ) consists of a ninth transistor (T ₃ ) , the input working electrodes of the first and of the ninth transistor (T ₄ , Tt) are interconnected and the output working electrode of the ninth transistor (T ₃ ) is connected to the input working electrode of the third transistor (T ₇ ) and that the switching means for connecting the input working electrode of the fourth transistor (Ts) to the input working electrode of the second transistor (T ₆ ) consists of a tenth transistor (T ₅ ) , the input working electrodes of the second and the tenth transistor t> o (T ₆ , T ₅ ) being connected together and the output working electrode of the tenth transistor (T $) being connected to the Input working electrode of the fourth transistor (Ti) is connected. 5. Circuit arrangement according to claim 4, characterized in that the control electrode of the ninth transistor (T ₃ ) is connected to a signal source emitting binary signals, the first and emits second input signals for opening and blocking the ninth transistor (T ₃ ) and that the control electrode of the tenth transistor (T ₅ ) is connected to a further signal source emitting binary signals, the first and second input signals for opening and blocking the tenth transistor ^ T ₅ ) gives up 6. Circuit arrangement according to claim 1, characterized in that an eleventh and twelfth transistor (Tu, T13) are provided, the input working electrode of the eleventh transistor (Tu) with the control electrode of the first transistor (T ₄ ) and the output working electrode of the eleventh transistor ( Tu) are connected to ground reference potential, the input working electrode of the twelfth transistor (T ₁₃ ) is also connected to ground reference potential, and its output working electrode is connected to the control electrode of the third transistor (Π) and the control electrodes of both transistors (Tu, 7b) are connected together and on one CL £ 4W connection. , 7. Circuit arrangement according to claim 1, characterized in that a thirteenth and fourteenth transistor (Tu, T _i4 ) are provided, the input working electrode of the thirteenth transistor (Tn) with the control electrode of the second transistor (T ₆ ) and the output arbsitselectrode of the thirteenth transistor (Tu) are connected to ground reference potential, the input working electrode of the fourteenth transistor (Tt ₄ ) is also connected to ground reference potential and its output working electrode is connected to the control electrode of the fourth transistor (T%) and the control electrodes of both transistors (T \ ₂ , 7Ή) are connected together and connected to an SE7 "connector.