DE2248238A1 - FLIP-FLOP CIRCUIT ARRANGEMENT - Google Patents

Description

Augsburg 31. P.O. Box 242
Rehlingenstrasse 8

Postal checking account: Munich Nf. 74539

6l23 / 12 / Ch / gn

Microsystems International Limited
800 Dorchester Blvd., ¥.
Montreal 101, Quebec, Canada

Flip-flop circuit arrangement

Various embodiments of single channel MIS binary flip-flops are described, for example, in U.S. Patents 3,573,507 and US Pat
3 363 115 · The circuit complexity in these known circuit arrangements is considerable and therefore unsatisfactory for reasons of cost. In particular, the disadvantage is that a timing signal source and a further signal source are required, the further signal source emitting inverse signals to the timing signal source, regardless of whether the inverse signal is generated in the same flip-flop circuit or supplied from the outside
will. In U.S. Patent 3,355,307 there is shown a flip-flop circuit which has only one source of timing signal
is required. In this circuit, however, are
Complementary MIS transistors required, which are also available in large numbers.

l - t

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The object of the present invention is to provide a train single-channel binary flip-flop so that one relatively small number of components is required and that still only a single timing signal source is necessary without it being necessary to form signals inverse to these control signals.

According to the present invention, a single-channel MIS-Fl ip-flop circuit arrangement is proposed in which a first and a second MIS transistor are provided, each having a continuous, an input and an output working electrode, the input working electrode of the first transistor is connected to the control electrode of the second transistor, the input electrode of the second transistor is connected to. the control electrode of the first transistor, the output working electrode of the two transistors are connected to switching means that establish a connection with the ground reference potential, the input working electrodes of the two transistors are each connected to switching means that serve to pick up a first and a second output signal, the input working tseltiktrode are also connected to switching means for connection to a voltage source, furthermore a third and a fourth MIS transistor are provided, with switching means Lu for connecting the input working electrode of the third or fourth transistor to the input working electrode of the first or second transistor , furthermore with a fifth and sixth MIS transistor, whose output tse 1 t; k electrodes are connected with <) to control I ek trodes fourth and third transistor and the input

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working electrode of the fifth or sixth
The transistor is connected to the control electrode of the first or second transistor, furthermore connections are provided which are connected to a pulse potential source, which is between a potential that makes the fifth and sixth transistor conductive when it is applied to their control electrodes and changes to ground reference potential, these terminals being connected to the control electrodes of the fifth and sixth transistors and the output working electrodes of the third and fourth transistors.

The invention is explained in more detail below with reference to the drawings. It show the

Fig. 1 shows a known flip-flop circuit

Fig. 2 shows a known compared to the

Circuit according to FIG. 1 modified flip-flop circuit.

3 shows a flip-flop circuit according to the invention.

Fig. ^ I a further embodiment according to the invention.

Fig. 5 shows a frequency divider circuit below Use the flip-flop as per the invention.

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In the following description it is assumed that MOS components are used because they are most economical in integrated circuits can be used. MIS components can of course also be used in the same way.

Fig. 1 shows the most widely used flip-flop circuit using single-channel MIS transistors with no timing signal source. The circuit shows transistors T ₁ and T ₀ , whose control electrodes and input working electrodes are connected together and connected to a potential source -V _n ..... The output working electrodes of T ₁ and T "are connected to the outputs Q ¹ and Q". The output working electrode of T is also connected to the input working electrode of a transistor T-, the control electrode of which is connected to an input terminal J. The output working electrode of T is connected to the ground reference potential. The output working electrode T is furthermore connected to the input working electrode of a transistor T. whose output working electrode is also connected to the reference potential. The control electrode of T. is connected to the output working electrode of T ". The output working electrode of T ₀ is connected to the input working _{electrode of T r} , the control electrode of which is connected to the input terminal K. The output working electrode of T_ is also at the reference potential. The output working electrode of T_ is also connected to the input working electrode of a transistor IV. Its control electrode is connected to the output working electrode of T ₁ , while the output working electrode of T / - is also connected

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is at ground reference potential. The switching states that occur are as follows:

State J K Q a ' 0 0 Q b 1 0 1 C. 0 1 0 d 1 1 9

It is assumed here that the logic value "1" represents the state in which the two input signals applied to J and K are sufficiently negative that the transistors of the circuit become conductive. For easier understanding it is assumed that the logical value "1" is equivalent to -V " _nn , while the logical value" 0 "corresponds to the ground reference potential. The same symbols also apply to the logical output values Q.

In state a, an input signal with the logic value "0" is present at terminal J and thus the control electrode of the transistor T ". T is by it locked and point A separated from the ground reference potential. Furthermore, the value "0" is present at K. Of the Switching state of each of the transistors T. and IV remains unchanged, since the points A and B experience no change in potential when the inputs J and K die Signal values "0" are applied. This also means that the output Q remains unchanged.

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In switching state b, the value at J is changed to "1", while input K remains unchanged at "O" remain. This means that T_ becomes conductive and point Λ now has ground reference potential. IV is now as well as T blocked, so that the potential -V is at point B, which corresponds to the logical value "1" is equivalent to.

In switching state c, input J has the value "0", while input K has the value "1". This means that there is now ground reference potential at point D, with T _{r being} conductive and T. being blocked as a result. Since the input J is at "0", the point A has the potential -V , so that Q ¹ now has the value "1". The point B remains at "0", since both IV and IV are conductive, so that the output Q thus has the value "0".

In switching state d, both single-series J and K are lying on the logical value "1". This means that T "and T-conductive, so that both points A and B are at ground reference potential. Are the signals now with the logical value "1" removed from J and K, the points A and U can float because they are now from the ground reference potential are separated so that now the flip-flop can assume one of the stable states, at which Q is either "0" and "1", but it is indefinite which of these states is assumed.

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In the circuit according to FIG. 2, a transistor T and a switch S _{1n are} connected between the output working electrode of the transistor T "and the ground reference potential. The control electrode of T_ is connected to the output Q ^{1 via a switch S.} In a corresponding manner, a transistor To and a switch S _{12 are connected} between the output working electrode of transistor T_ and the ground reference potential. The control electrode of the transistor Tn is connected to the output Q _{via a switch S 0.} In switching state c according to the table above, where 'at J * is the value "0" and K is the value "1" and accordingly Q is equal to "0", the switches S. and S _{0 are} open and the switches S._ and S, _o closed. The circuit now assumes the switching state according to d, with J changing to the logical value "1". This makes T “conductive, but no current can flow because T_ is blocked (switch S. is open). The switch S. is now closed and the switch _{S.n is} opened at the same time. Since the point A is -V _nr , this potential reaches the control electrode of T ₇ and is stored there. However, no current can flow via T because switch S _{n is} open, which is why A _{remains at the potential -V nn} while S _{1 is} closed and the control electrode of T_ is charged. If S ₁ is now opened and S is closed at the same time, the charge on the control electrode of T causes T_ to conduct and at point A now lies above T, T and S ₁ ground reference potential. Point A therefore assumes the logical value ¹¹ O ". If one now considers point B and one assumes that S ₄ and S _{0 are} triggered simultaneously, which also applies to S _in and S, the table above shows that that in switching state c the output Q was at the logical value "O ^lr . Since the potential at the control electrode of Tg corresponds to the logical

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See value "O" (ground reference potential) corresponds when S _{0 is} closed, Tg does not conduct, so that therefore the transistors T_ and T «and the switches S ₀ and S ₁₉ do not contribute to the determination of the potential at point D at the transition from Have switching status c to switching status d according to the previous table. If point A now ^{assumes the logical value 11} O ", ΊΥ is blocked and since S _{9 is} open at this point in time, there is no current connection from the output _{working electrode of transistor T 0} to the ground reference potential In this way, output Q in state c has changed to output Q ¹ in state D. If one considers the cases in which a transition from state b to state d or from state a to state d takes place, one sees that Q changes each time after Q ¹ , where Q * is the alternating, binary logic value of Q ^1. In the circuit according to FIG. 2, the following switching states occur:

State J
η K
η 0 + 1 a O O Q _n b 1 O 1 C. O 1 0 d 1 1 0

Q +1 represents the output Q after η + 1 pulses of the switches S., S ₀ , S- _o and Sp. Q corresponds to the output Q after n-pulses of these switches. In the practical exemplary embodiment, switches S ₁ and S are normally triggered by clock pulses »

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while the switches S._ and S _{HO are} triggered by inverse signals of these pulses. As already mentioned above, this flip-flop circuit requires both a timing signal source and a source of inverse signals, which means that an extra circuit is required and also relatively complex circuitry is required so that the required operating speed and correspondingly clear output signals can be obtained. The aforementioned circuit of US Pat. No. 3,555 eliminates the need for an inverse timing signal source, but requires complicated circuits with complementary MIS transistors. According to the present invention, single-channel components are used, the circuit being designed so that inverse clock signals are not required, but that only a clock signal source is required, the pulses of which change between a modulating signal and ground reference potential.

3 shows a basic circuit arrangement in which the switching components which are identical to those according to FIGS. 1 and 2 have the same characteristics. Compared to the circuit arrangement according to FIG. 1, only four further transistors T_., Tn ₁ T and T are required in the circuit according to FIG. The control electrode of the transistor T is connected to the output electrode of the transistor T. Furthermore, the input electrode of T is connected to the output Q '. In a corresponding manner, the control electrode of the transistor To is connected to the output electrode of T _Q , the input electrode of which is connected to the output Q. The control electrodes of T and T and the output working electrodes

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of T and Tn are each connected to a timing signal source C. Their signals have a control potential for the transistors T _c and T. and a ground reference potential for the transistors T_ and

T _n on.
ο

The table for FIG. 2 is equally valid for the circuit arrangement according to FIG. 3, but Q +1 represents the state of output Q after n + 1 complete clock pulses. Q corresponds to the state of output Q after η complete clock pulses. Q ¹ is always the alternating binary logical value of Q.

First, consider the transition from state a to state b according to the table. 0 + 1 is in state a at Q. It is assumed that 0 has the logic word ' ¹ I ". If J changes to the logic value" J ", T becomes conductive. At this point in time, the clock signal C has ground reference potential , at which T and T. are blocked. Therefore T is also blocked. Since point D has the potential "1", Ti is open at this point in time, Q ¹ is at "0" and 'IV is blocked is at "0", which is why T _{r is} blocked.

If a clock pulse C now occurs, the output working electrodes of T_ and To are separated from the ground reference potential and T and T become conductive. Terminal A has the value ¹ D ", so that no current flows through T to open T_. Point B, on the other hand, has the value" 1 ", so that a current flows through T" and

- 11 -

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charges the control electrode of To. As mentioned, the output working electrode of Tq is disconnected from the ground reference potential when the pulse C occurs, so that sufficient time is available to fully charge the control electrode of Tn. The potential at C now returns to ground reference potential and the charge on the control electrode. Von T *, causes Tr, to remain open. However, since T _{r is} blocked when the logic value ¹¹ O "is applied to K, no current can flow via Tn, and the output Q therefore remains at the logic value" l ^1t . In the following it is assumed that in the state a Q has the logical value "0" · The value "I ^{11" is} applied to J, whereby T. becomes conductive. As a result of the potential at point A, TV is conductive and keeps point B at the logical value ' ¹ O ". As a result of a pulse C, T and T become conductive. Since point A has the logical value ¹¹ I ¹ ', a current flows through' f. and charges the control electrode of T. Since the point B is at "O ¹¹ , Tn remains blocked. The clock signal C now becomes the ground reference potential, a current flows through T and T" and the point A assumes the ground reference potential, ie the logical value ¹ O ", whereby T, - is blocked. Since the point B is now separated from the ground reference potential, it takes the potential - ^ _ηη a "i ie the logical value ¹¹ I ¹ '* This means that whatever binary value is in state a for Q, always in state b the logical value "1" is assumed.

If we now consider the transition from state b to state c, it must be assumed that in state d the point A at the value "O ^11" and the point B at the value "1"

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lies. The signal at input J now changes to the logical value "0", while at input K there is now a value of "1". In this way, T is blocked and T _{r is} opened. If a pulse C occurs, the control electrode of Tn is charged to the potential at point B. T_ remains blocked. If C now goes back to ground reference potential, T _r and Tn become conductive and point D assumes the value "0", whereby T. is blocked at the same time. Therefore, the logical value "1" is now at point Λ.

The transition from state c to state d is considered below. In state d, the logic values "1" are present at the input terminals J and K, as a result of which T and T become conductive. Since the value "1" is at point a in state c, T ^ is conductive and T i is blocked. If a pulse C now occurs, T and T become conductive and the control electrode of T_ is brought to the potential of point A. If C now goes back to ground potential, T_ and T "are conductive and point A takes the value" 0 ", whereby T _{r is} blocked. Therefore, the point B takes the logical value "1". As in the circuit according to FIG. 2, it is clear that Ii c Ii shows that with each transition from state a, b or c to state d there is an output Q which is equal to the alternating binary output value of the previous output Q.

In state d, this means that Q +1 = Q ¹ .

η η

It can thus be seen from the example according to FIG. 3 that the J-K flip-flop shown there is the same It works like the hold according to FIG. 2, but with an inverting stage for the Zei.ttaktsignal

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is not required, as is required in the known circuits. This benefit will achieved without the need for complementary transistors will.

FIG. K shows a flip-flop according to FIG. 3, in which additional input connections CIjEAR and SET are provided. An additional transistor T 'is provided, the input working electrode of which is connected to the control electrode of T; , whose output working electrode is interconnected with the output working electrode 'of T ^ and whose control electrode is connected to the terminal CLEAR. The output working _{electrode of T 1} .. is also connected to the input working electrode of a transistor T. "whose output working electrode is connected to the control electrode of T. The control electrode of T ₁ ~ is connected to the control electrode of T ... «Furthermore, a transistor Τ., _ Is provided, the input working electrode of which is connected to the control electrode of T / -, the output working electrode of which is connected to the output working electrode of T ^ and whose control electrode is connected to the SET connection. The output working _{electrode of T 12} is also connected to the input working electrode of a transistor T. ^, whose output working electrode is connected to the control electrode of transistor To «The control electrode of T / is connected to the control electrode of T. ^,»

It is assumed that point A is at the logical Value "1" and the point B is at the logical value "Q" are located. A SET-Irap.itIs. leaves the transistors

- th -

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T. and T _{0 become} conductive. Point A therefore assumes the logical value "1", ie its potential corresponds to the ground reference potential, at the same time point B is brought to the logical value "1". Any charge on the control electrode of T «, which would cause T to become conductive, whereby the point FJ would be brought to ground reference potential (K = ¹¹ I", ie _Tr is conductive) is discharged to ground via T., Whereby To is blocked Terminal A is now at the value "0" and terminal B is at the value "1." A CLEAR signal on the control electrodes of T and T. "acts in an analogous manner to a SET signal and causes point B to return to the value "0" and point A to the value ^{! r} l ", in that point B is connected to ground via T and the discharge of the control electrode from T_ via T to ground reference potential.

FIG. 5 shows a frequency divider circuit which represents a special case of the circuit according to FIG. 3, the inputs J and K both being at the logic value "1" and the transistors T and T _r therefore coming into wogfall. It is assumed that the point B has the logical value "1" and the point A has the logical value "0". If a pulse C occurs, a current flows through T and charges the control electrode of Tq. If the pulse C goes back to the ground reference potential, To becomes conductive, the point to B assumes the ground reference potential, the transistor Tj is blocked and the point A assumes the logic value "1". If a pulse C occurs again, the potentials at points A and B are reversed again

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If the pulses C occur with a frequency f, ^{signals with the frequency f / 2 appear at the outputs Q and Q 1} , which change between "O" and ¹¹ I ".

In the circuits described here, > MOS transistors with a P-channel and a silicon control electrode were described. It goes without saying, however, that corresponding transistors with an N-channel can also be used, in which case the supply voltage source then of course has an inverted polarity of + V.

- 16 CLAIMS

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Claims (6)

6l23 / l2 / Ch / gn - l6 - September 26th EXPECTATIONS y. Flip-flop circuit arrangement with MIS transistors, consisting of a first and a second transistor, the input working electrode of one transistor being connected to the control electrode of the other transistor, the output working electrodes being connected to means for connecting these electrodes to ground reference potential and from the input working electrodes the output signals are tapped, these input working electrodes being connected to switching means for connection to a supply voltage source, further consisting of a third and fourth transistor, the input working electrode of which is connected via switching means to the input working electrodes of the first and second transistor, characterized by the use a fourth and fifth transistor (T, T ...) whose respective output working electrode is connected to the control electrode of the fourth and third transistor (Tn, T) and their respective input working electrode is connected to the control electrode of the first or »second transistor (Ti ₁ T ^ -), the control electrode of the fifth and sixth transistor (T _Q » T ₁₀ ) are connected to a voltage pulse source whose pulses cause these transistors to open, which simultaneously act on the output working electrodes of the third and fourth transistors (T-, Tg). 2. Circuit arrangement according to claim 1, characterized in that g e that the respective input working electrode of the first and second L-th transistor - 17 - 3 0 9 8 2 4/1037 6l23 / l2 / Ch / gn - 17-26 September 1,972 (T /, Ί \ -) is connected _{to the supply voltage source via a load transistor (T, T 0} ), this input working electrode being connected to the output working electrode of these transistors (T, T ₀ ), the input working electrodes of which are connected to the supply voltage source. 3. Circuit arrangement according to claim 1 or 2, characterized characterized in that the transistors MOS transistors with a silicon gate are. 4. Circuit arrangement according to claim 1, characterized in that the switching means for connecting the input working electrode of the third transistor (T) to the input working electrode of the first transistor (Ti) consists of a ninth transistor T, the input working electrodes of the first and the ninth transistor (T ., T) are interconnected and the output working electrode of the ninth transistor (T) is connected to the input working electrode of the third transistor (T ^) and that the switching means for connecting the input working electrode of the fourth transistor (Tn) to the input working electrode of the second transistor (T ^) consists of a tenth transistor (T _r ), the input working electrodes of the second and the tenth transistor (T ^, T_) are connected together and the output working electrode of the longed transistor (T _r ) is connected to the input working electrode of the fourth transistor (T ") is. - 18 - 309824/1037 6l23 / l2 / Ch / gn - l8 - September 26, 1972 5. Circuit arrangement according to claim h, characterized in that the control electrode of the ninth transistor (T ") is connected to a signal source emitting binary signals, emits the first and second input signals for opening and blocking the ninth transistor (T) and that the control electrode of the tenth transistor (T_) with a further signal source emitting binary signals is connected, which emits first and second input signals for opening and blocking the tenth transistor (T ₅ ). 6. Circuit arrangement according to claim 1, characterized in that an eleventh and twelfth transistor (T ..., T ") are provided, wherein the input working electrode of the eleventh transistor (T.) The control electrode of the first transistor (T ₁ ) and the output working electrode of the eleventh transistor (T ..) are connected to ground reference potential, the input working electrode of the twelfth transistor (T) is also connected to ground reference potential, and its output working electrode is connected to the control electrode of the third transistor (T ",) and the control electrodes of both transistors (T, T) are interconnected and connected to a CLEAR connection. 7 · Circuit arrangement according to claim 1, dadurcli g e markzej chnet that a thirteenth and a fourteenth transistor (T, Ti) are provided, being the input working electrode of the thirteenth - 19 - 309824/1037 6l23 / l2 / Ch / gn - 19-26 September 1972 The transistor (T _o ) is connected to the control electrode of the second transistor (IV) and the output working electrode of the thirteenth transistor (T. _) is connected to ground reference potential, the input working _{electrode of the fourteenth transistor (T;} ) is also connected to the ground reference potential and its output working electrode is connected to the control electrode of the fourth transistor (Tn) is connected and the control electrodes of both transistors (T._, T ..) are connected together and are connected to a SET terminal. 309824/1037