DE102020118108A1 - Boost converter for a power supply for an electrical load, and power supply and method for boosting the input voltage in a power supply for an electrical load - Google Patents

Abstract

The invention relates to a step-up converter for a power supply unit with two step-up converter stages (HSa, HSb), with one inductor (L1a, L1b) being provided for each step-up converter stage, with the inductor being connected to one pole of the AC voltage source (ACin) and to a node ( P1a, P1b) between two semiconductor switches (S1a, S2a; S1b, S2b). According to the invention, the first semiconductor switch (S1a, S1b) is connected in series with a measuring resistor (R1a, R1b). The step-up converter has a signal generation unit (110) for generating drive signals for the two semiconductor switches per step-up converter stage, with the first semiconductor switch (S1a) being closed and the second semiconductor switch (S2a) being opened to step-up the input voltage when the input voltage (Vin) is positive drive a current through the inductor (L1a) to magnetize the inductor (L1a). For demagnetization, the first semiconductor switch (S1a) is opened and the second semiconductor switch (S2a) is closed and the filter capacitor (C1) is charged accordingly. The current through the measuring resistor (R1) is recorded with a means. According to the invention, the signal generation unit (110) has a drive unit (113a, 113b) which drives the step-up converter stages offset from one another with a selected phase shift and regulates the period of the drive signals in one step-up converter stage (HSa, HSb) and in the at least one other step-up converter stage ( HSa, HSb) keeps constant or vice versa. This step-up converter (100) is used, for example, as a power factor pre-regulator in power supplies.

Description

The present invention relates to a step-up converter for a power supply for supplying an electrical load. The invention further relates to a power supply comprising a boost converter according to the invention. In this case, the step-up converter can be used in particular as a power factor pre-regulator in a switched-mode power supply. The invention also relates to a method for step-up conversion of the input voltage in a power supply of an electrical consumer.

Power supplies are required for a wide range of areas and purposes. Since the term power supply is used in many ways, the term converter is used below. Their job is to control the flow of current between the power source and the load, or to convert it from one type of current to another. They belong to the sub-area of power electronics within electrical engineering. There are the following types of power converters: rectifiers, inverters, DC converters and AC converters. These different power converters also include the power supply units, which are also referred to as power supply units. They have the task of supplying electronic equipment with direct current. A distinction is made between linear power supplies and switched-mode power supplies. The switched-mode power supplies also belong to the regulated power supplies.

the 1 shows the basic structure of a switched-mode power supply. It consists of the components rectification 10, DC converter 20, power transmission stage 30, smoothing 40, control stage 50, electrical isolation 60 and control 70. The mains voltage from the public power supply network is present at the input of the switched-mode power supply. The AC voltage with an effective value of 230 V and a mains frequency of 50 Hz is given as an example. The following three components can be present in the rectifier stage 10: mains filter 1, rectifier 2 and filter capacitor 3. A high DC voltage is present at the output of the rectifier stage 10, which relates to the voltage value 400 V, for example. This DC voltage is chopped up by the DC converter 20 into a square-wave signal. It contains a power transistor, eg bipolar transistor 4, MOSFET transistor corresponding to Metal Oxide Semiconductor Field Effect Transistor, thyristor or IGBT, corresponding to Insulated Gate Bipolar Transistor, which generates the square-wave signal by switching operations. By changing the duty cycle of the square-wave signal, different voltages and currents and thus also different power levels can be set. Pulse width modulation (PWM) and pulse train modulation (PFM) techniques are mainly used to control the circuit breakers.

For power supply units that are designed for power ranges of 75 W and more, it is mandatory that they be equipped with PFC technology, corresponding to power factor correction, in order to avoid repercussions on the power supply network through the generation of harmonics. This is also defined in the European standard EN61000-3-2. An active PFC circuit is often used for this. This consists of a kind of additional switched-mode power supply, which is connected upstream of the actual one and ensures that the current drawn corresponds to the sinusoidal mains voltage. As a result, the current follows a course that would be caused by a resistance in the current mains voltage. In this way, if the mains voltage is not exactly sinusoidal, as is often the case in power grids, the actual progression - not the idealized one - of the mains voltage is traced. The power factor remains close to unity and there are fewer harmonics. Otherwise, they could "build up" and overload the power grid. The power factor indicates the ratio of active power to apparent power. If the phase shift between current and voltage is zero, real power and apparent power are equal and the power factor remains at unity. When there is a noticeable phase difference between voltage and current, power flows back to the utility and the power factor drops below unity. Active PFC circuits usually consist of a rectifier with a step-up converter connected directly downstream, which charges a large-capacitance capacitor 3 to a voltage above the peak voltage of the AC mains voltage, e.g. 400 V. This is then used to supply the actual consumer (switched-mode power supply or e.g. electronic ballast for fluorescent lamps). A step-up converter is also referred to as a step-up converter. It is a flyback converter in which an inductor drives a current through the load when the switching transistor is off.

the 2 shows the basic circuit diagram of a step-up converter that can be used in such an active PFC circuit. By operating step-up converter circuits in the so-called boundary conduction mode, low-loss switching of the MOSFET semiconductor switches S that are usually used is achieved. In this case, the step-up converter 100 is operated near the gap limit of the inductor _{current I L in} such a way that both currentless switching on, so-called “zero current switching” (ZCS) and voltage-free switching on, so-called “zero voltage switching” (ZVS) of the switch S is made possible . The inductor L1 of the step-up converter 100 and the output capacitance of the semiconductor _switch C Osc form a series resonant circuit. This oscillating circuit is charged within half the period of its natural frequency, so that when the sign of the inductor _{current I L changes,} the output _{capacitance C Osc is charged} to double the value of the step-up converter input voltage V _in minus the step-up converter output voltage Vout. As a result, when the semiconductor switch S is switched on again, the switching voltage and the inrush current and thus the switching losses are reduced. Such switching losses occur when the semiconductor switch S is current-carrying. According to Ohm's law, P = U*I. The power loss P, which is converted into heat in the semiconductor switch S, is therefore dependent on how high the voltage that is applied is.

$$t_{Off}=\frac{V_{in}}{V_{out}-V_{in}}\ast t_{On}$$

$$t_{Res}=\pi \ast \sqrt{L\ast C_{Osc}}$$

Dabei bedeuten P_in die Eingangsleistung und L die Induktivität der Drosselspule L1. Um ein möglichst verlustfreies Schalten des Halbleiterschalters zu gewährleisten, darf die Periodendauer T_s eines Schaltzyklus nicht kürzer sein als: $$T_{smin}=t_{On}+t_{Off}+t_{Res}.$$

So ist es dann gewährleistet, dass die Transistorkapazität des Halbleiterschalters S für ein verlustfreies Schalten entladen werden kann.In the 3 voltage and current curves over a complete switching period of the semiconductor switch S are shown. The current profile I _L is triangular. During the switch-on phase t _On , the current through the inductor L1 increases linearly. During the switch-off phase toff, the current through the inductor L1 drops linearly. In the phase t _Res , which corresponds to half the period of the resonant frequency of the resonant circuit consisting of the inductor L1 and the capacitance of the semiconductor switch S, the direction of the current even changes. The chronological relationships are as follows: $$t_{On}=\frac{P_{in}\ast 2\ast L}{{\mathrm{<figure-callout\; id="2"\; label="V\; i\; n"\; filenames="DE102020118108A1\_0008.png,DE102020118108A1\_0009.png"\; state="\{\{state\}\}">V</figure-callout>}}_{in}{}^2}$$

$$t_{Off}=\frac{V_{in}}{V_{O\mathrm{and}t}-V_{in}}\ast t_{On}$$

$$t_{Res}=\pi \ast \sqrt{L\ast C_{Osc}}$$

P _{in is} the input power and L is the inductance of the choke coil L1. In order to ensure that the semiconductor switch switches with as little loss as possible, the period T _{s of} a switching cycle must not be shorter than: $$T_{smin}=t_{On}+t_{Off}+t_{Res}.$$

It is then ensured in this way that the transistor capacitance of the semiconductor switch S can be discharged for lossless switching.

In particularly loss-optimized applications, instead of a conventional step-up converter acc. 2 a half-bridge PFC circuit with at least two active semiconductor switches S1, S2 is used. This is in 4 shown. The diode D goes out 2 replaced by another semiconductor switch S2.

The temporal relationships that acc. 2 apply are in the US patent U.S. 8,766,605 B2 explained in relation to the use of a half-bridge PFC circuit. The term half-bridge PFC circuit expresses the fact that both the positive and the negative half-wave are upconverted by the same semiconductor switch branch. However, this requires a polarity reversing circuit that closes the circuit.

In the 5 shows the time sequence of the drive signals of the semiconductor switches S1 and S2 for a positive input voltage V _in . The control signals are generated by setting current thresholds I _h and I _l. For this purpose, the current must be measured and compared with specified values.

In this case, the condition for switching off S1 and switching on S2 is that the current threshold I _{h of} the inductor _{current I L is} exceeded. The current threshold I _h for the respective operating point is specified by a current controller. In this case, the condition for switching off S2 and switching on S1 is that the inductor _{current I L falls below the current threshold I L} . The current threshold I _l is statically predetermined and its position ensures complete _{charge reversal} from the capacitance C Osc of the semiconductor switch S1.

In contrast to the circuit in 2 , in which the diode D determines the recharging process, the switch S2 is switched on until the capacitance C _{Osc has been} completely recharged to 0 V. Then the semiconductor switch S1 is switched on and the semiconductor switch S2 is switched off at the same time, so that the current I _L can commutate from S2 to S1 and the direction of the current I _{L changes} again. A new cycle begins with the magnetization of the choke coil.

Details on this control method are in the following documents US20070109822A1 and US8026704B2 described in more detail.

An alternative method for generating the control signals for the semiconductor switches S1 and S2 is from the doctoral thesis ""Current Mode Control structure: Current-Mode Control: Modeling and Digital Application", by Jian Li, April 14, 2009, Blacksburg, Virginia Polytechnic Institute and State University known. In this case, to generate the switching times t _onS1 and t _{onS2 of} the semiconductor switches, switches S1 and S2 are used, which _{compare the voltage drop caused by the current I L} in a measuring resistor with voltage threshold values.

From the document "LED Application Design Using BCM Power Factor Correction (PFC) Controller for 100W Lightning System"; AN-9731, 02011 Fairchild Semiconductor Corporation Rev. 1.0.0, 3/24/11 a circuit design for a PFC circuit that is operated in the so-called “boundary conduction mode” (BCM) is known.

When using a step-up converter circuit for power factor correction (PFC), a two-stage variant is used if greater power is required. Such step-up converters are interesting for higher power classes from about 1 kW power. This so-called "interleaved" PFC circuit can also be implemented as a bridgeless topology, as in the patent specification U.S. 8,363,434 B2 is shown. There are two step-up converter stages that charge the filter capacitor. One problem here is the "ripple currents" that arise as a result of the switching processes in both step-up converter stages. They would increase if the two step-up converter stages were allowed to work in common mode.

It is therefore the object of the invention to provide a step-up converter for power supplies which enables the two step-up converter stages to be operated in such a way that the resulting ripple currents, which are taken together from the network, are as small as possible. In addition, both step-up converter stages should switch with as little loss as possible. Likewise, a current measurement that is as favorable as possible using only one measuring resistor in the current path per step-up converter stage with little additional circuitry should be sufficient for detecting the current.

This object is achieved by a boost converter according to claim 1, a power supply for an electrical load according to claim 14 and a method for boosting the input voltage in a power supply according to claim 16.

The dependent claims contain advantageous developments and improvements of the invention according to the following description.

In order to solve this problem, it is proposed according to the invention to control the switching cycle of the at least one second stage offset from the first stage by a selected phase shift. At the same time, the magnetization time in the first stage is kept constant during a half-wave of the input voltage, and the demagnetization time is adjusted in order to achieve the desired sinusoidal current curve in the inductance. In contrast, in the at least one second stage, the period duration is kept constant and the magnetization time is adjusted. It is thus possible to achieve low-loss switching in the at least two step-up converter stages and to compensate for the ripple currents from the at least two step-up converter stages, which are taken together from the network.

In a general embodiment, the invention relates to a step-up converter for a power supply of an electrical consumer, which is equipped with at least two step-up converter stages. In this case, the step-up converter has a bridgeless rectifier circuit and a filter capacitor. An inductor is provided for each step-up converter stage, with the inductor being connected to one pole of the AC voltage source and to a node between two semiconductor switches. In this case, the first semiconductor switch per step-up converter stage is connected in series with a measuring resistor. The step-up converter is equipped with a signal generation unit that generates control signals for the two semiconductor switches per step-up converter stage, with the first semiconductor switch being closed and the second semiconductor switch being opened for step-up conversion of the input voltage when the input voltage is positive for each step-up converter stage in order to drive a current through the inductance for magnetization the inductance. To demagnetize the inductance in the step-up converter stages, the first semiconductor switch is opened and the second semiconductor switch is closed, and the filter capacitor is charged accordingly. In a preferred embodiment, the first semiconductor switch per step-up converter stage is connected in series with a measuring resistor to measure the current flowing through the first semiconductor switch. The signal generation unit has a means for detecting the current through the respective measuring resistor of the respective step-up converter stage. In an advantageous embodiment, the current through the measuring resistor is detected advantageously at the end of the phase for demagnetizing the inductance. The invention offers the advantage that it is possible to switch the semiconductor switches with as little loss as possible. The capacitance of the semiconductor switch in the step-up converter stages is particularly disruptive for lossless switching. It causes a voltage during the switching process which, together with the remaining current flow in the semiconductor switch, leads to power loss. In order to switch without losses, the capacitance of the semiconductor switch must be discharged as completely as possible. A current measurement is required for this. A particular advantage of the circuit according to the invention is that a simple measuring resistor is sufficient for measuring the current. A particularly advantageous measure is that the signal generation unit has a control unit that is designed for this is to control the step-up converter stages with a selected phase shift offset from one another. With two step-up converter stages, for example, a phase shift of 180° is optimal. This ensures that the ripple currents (also known as ripple current), which are drawn from the mains by both stages in the control cycles, compensate as well as possible, so that only a small residual ripple remains in the resulting current consumption. At the same time, the drive unit is designed to regulate the period of the drive signals in one step-up converter stage and to keep it constant in the at least one other step-up converter stage, and to regulate the magnetization time in the at least one other step-up converter stage and to keep it constant in the first step-up converter stage. This has the advantage that the desired phase shift between the drive signals for minimizing the ripple currents is retained and lossless switching in the at least two step-up converter stages is made possible.

An extended embodiment of the invention consists in the step-up conversion of the AC input voltage when the input voltage is negative for each step-up converter stage, the first semiconductor switch is opened and the second semiconductor switch is closed in order to drive a current through the inductance to magnetize the inductance and to demagnetize the inductance of the first semiconductor switch is closed and the second semiconductor switch is opened. In the demagnetization phase, the filter capacitor is charged accordingly. For this configuration, the current through the measuring resistor is advantageously detected at the end of the phase for demagnetizing the inductance. This variant of the invention enables lossless switching of the semiconductor switches by adapting the drive signals of the semiconductor switches even when the negative half-cycle of the AC input voltage is present. In this way, the invention enables high power values without full-bridge rectification, which leads to a pulsating mains current with a high harmonic content.

For switching with as little loss as possible, it is also advantageous if the control unit has a calculation unit that precalculates the control cycle time for the phases for magnetization and demagnetization per control cycle as a function of the input voltage and output voltage. A control cycle consists of the phases for magnetization and demagnetization. The signal generation unit also has a control stage that calculates a correction value for the control cycle time based on the difference between the measured current value through the measuring resistor and a current reference value. In this way, various factors that would be required for a more accurate calculation of the control cycle time can be ignored. Some factors, such as component scatter, are unavoidable and could only be recorded with great effort. Also, some factors could be age-related, which requires even more effort to account for.

It is particularly advantageous for lossless switching if the correction value is used in a first timer unit of the signal generation unit for the subsequent control cycle, so that the timer unit correspondingly shortens or lengthens the control cycle time. The duration of the control cycle is determined with the first timer unit.

It is also advantageous that the signal generation unit has a further control stage, which calculates a magnetization time from the difference between the specified output voltage and the measured output voltage, which is used in the at least one first step-up converter stage. This corresponds to a voltage regulator that outputs a controlled variable to keep the output voltage constant.

For a step-up converter with two step-up converter stages, an advantageous measure is that the calculation unit is still designed based on the difference between the measured current value through the measuring resistor in the first step-up converter stage and the measured current value through the measuring resistor in the second step-up converter stage, a correction value for the magnetization time to be calculated, which is used in the second step-up converter stage. The control cycle time for the first and second step-up converter stage is set with the first timer. In order to achieve the 180° phase shift between the two step-up converter stages, the drive signal for the second stage is reset when half the value of the set timer is reached and the drive signal for the first stage only at the end of the programmed timer value. If you left it at that, the phase shift would exist, but it would not be guaranteed that the inductor current in the second step-up converter stage would have the same lower threshold value as the current in the first step-up converter stage. Loss-free switching of the same quality would then not be possible for this step-up converter stage. Since the control method of the first step-up converter stage influences the period of the switching cycle (ie the demagnetization time) and the 180° phase shift is controlled via this, it is therefore advantageous to use the control method for the second high Modify the converter stage in such a way that the magnetization time is controlled and the control cycle time is kept constant. In this way, the same lower threshold value for the current can be maintained as in the first step-up converter stage, and at the same time the desired phase difference can be maintained.

To generate the control signals for the semiconductor switches, it is advantageous if the signal generation unit has a second timer unit to which the calculated magnetization time is forwarded, in which the calculated magnetization time is used for a number of subsequent control cycles for the first step-up converter stage. The control signals are generated in the form of PWM signals. The duty cycle of the PWM signals can be set variably due to the separate timer units.

In this regard, it is also advantageous if the signal generation unit has a third timer unit to which the corrected magnetization time is forwarded, in which the corrected magnetization time for the subsequent control cycle for the second step-up converter stage is applied.

In this case, an advantageous variant consists in the number of control cycles for which the calculated magnetization time is used being valid for one half-wave of the input AC voltage. The magnetization time is advantageously kept constant in the control cycles over a half-cycle of the AC input voltage, while the demagnetization time is adjusted. This causes the current through the inductor to also become sinusoidal when the AC input voltage is sinusoidal.

It is also advantageous for the signal generation unit to be equipped with an input AC voltage detection unit, which is set up to determine the phase position of the input AC voltage, and the information about the phase position, in particular whether the positive half-cycle or negative half-cycle of the input AC voltage is present, to a configuration unit of the Signal generation unit supplies. The mode of operation of the step-up converter according to the invention is different for the positive and negative half-wave of the AC input voltage. Therefore, detecting the polarity of the AC input voltage is advantageous.

In this regard, a further advantageous variant is that the configuration unit is set up to configure a number of the components of the signal generation unit for operation with a positive input voltage or with a negative input voltage, depending on what the information about the polarity of the AC input voltage indicates. It is common to configure the various components via register entries, which can be done by the configuration unit.

To detect the current when the capacitance of the semiconductor switch is discharged, it is advantageous to connect the measuring resistor in the at least first and second step-up converter stage between the first semiconductor switch and the return line to the input AC voltage source to which the inductance is not connected.

A choke coil is typically used as an inductance in step-up converters. This can be precisely adjusted by the number of turns and stretches or compression and geometric design.

In a further embodiment, the invention consists in a power supply for an electrical consumer, which has a step-up converter according to the invention. The step-up converter according to the invention can be used particularly advantageously as a step-up converter for power factor pre-regulation in the power supply.

Such power factor pre-regulation stages can be used particularly advantageously in switched-mode power supplies.

In a further embodiment, the invention relates to a method for step-up conversion of the input voltage in a power supply of an electrical consumer, which has a multi-stage step-up converter with at least two step-up converter stages. A rectifier circuit and a filter capacitor are provided. In this case, an inductor is provided for each step-up converter stage, with the inductor being connected to one pole of the AC voltage source and to a node between two semiconductor switches. Furthermore, the first semiconductor switch per step-up converter stage is connected in series with a measuring resistor. Control signals for the two semiconductor switches per step-up converter stage are generated by a signal generation unit, with the first semiconductor switch being closed for step-up conversion of the input voltage when the input voltage is positive for each step-up converter stage, and the second semiconductor switch being opened in order to drive a current through the inductance to magnetize the inductance. To demagnetize the inductance, the first semiconductor switch is opened and the second semiconductor switch is closed and the filter capacitor is charged accordingly. The current through the respective measuring resistor is recorded by the signal generation unit. The method is characterized in that the signal generation unit has a drive unit, by which the step-up converter stages are driven offset with respect to one another with a selected phase shift, the period of the drive signals in one step-up converter stage being controlled by the drive unit and kept constant in the at least one other step-up converter stage is, and the magnetization time is regulated in the at least one other step-up converter stage and is kept constant in the first step-up converter stage.

In this regard, there is a particular advantage that, with this method, the current through the measuring resistor is measured at predetermined times that are predetermined by the precalculated control cycle time and corrected by the correction value. For the invention it is sufficient to measure the current only at these points in time, which is possible with inexpensive AD converters.

• 1 ein Prinzipschaltbild eines Schaltnetzgerätes;
• 2 ein Prinzipschaltbild einer Halbbrücken-PFC-Schaltung mit einem Halbleiterschalter;
• 3 den Stromverlauf durch die Induktivität der Halbbrücken-PFC-Schaltung gem. 2 und den durch die Drain-Source-Kapazität des Halbleiterschalters S bedingten Spannungsverlauf am Halbleiterschalter S bei Ansteuerung des Halbleiterschalter S bei Erreichen von Stromschwellen im Stromverlauf;
• 4 ein Prinzipschaltbild einer Halbbrücken-PFC-Schaltung mit zwei Halbleiterschaltern;
• 5 den Stromverlauf durch die Induktivität der Halbbrücken-PFC-Schaltung gem. 4 und den durch die Drain-Source-Kapazität des Halbleiterschalters S1 bedingten Spannungsverlauf am Halbleiterschalter S1 bei Ansteuerung der Halbleiterschalter S1 und S2 bei Erreichen von Stromschwellen im Stromverlauf;
• 6 ein Prinzipschaltbild einer zweistufigen Halbbrücken-PFC-Schaltung mit jeweils zwei Halbleiterschaltern pro Hochsetzstellerstufe und Polwende-Schaltung;
• 7 ein Prinzipschaltbild einer zweistufigen Halbbrücken-PFC-Schaltung mit jeweils zwei Halbleiterschaltern, wobei die Polwende-Schaltung mit Dioden realisiert wird;
• 8 ein Blockschaltbild einer Signalerzeugungseinheit der Halbbrücken-PFC-Schaltung;
• 9 die Art der Ansteuersignalerzeugung der Halbbrücken-PFC-Schaltung gem. 7 bei positiver Halbwelle der Eingangsspannung; und
• 10 die Art der Ansteuersignalerzeugung der Halbbrücken-PFC-Schaltung gem. 7 bei negativer Halbwelle der Eingangsspannung.

Several exemplary embodiments of the invention are explained in more detail below with reference to the figures shown in the drawings. Show it:

• 1 a schematic diagram of a switching power supply;
• 2 a schematic diagram of a half-bridge PFC circuit with a semiconductor switch;
• 3 the current flow through the inductance of the half-bridge PFC circuit acc. 2 and the voltage curve at the semiconductor switch S caused by the drain-source capacitance of the semiconductor switch S when the semiconductor switch S is driven when current thresholds are reached in the current curve;
• 4 a schematic diagram of a half-bridge PFC circuit with two semiconductor switches;
• 5 the current flow through the inductance of the half-bridge PFC circuit acc. 4 and the voltage curve at the semiconductor switch S1 caused by the drain-source capacitance of the semiconductor switch S1 when the semiconductor switches S1 and S2 are driven when current thresholds are reached in the current curve;
• 6 a basic circuit diagram of a two-stage half-bridge PFC circuit with two semiconductor switches per step-up converter stage and polarity reversal circuit;
• 7 a basic circuit diagram of a two-stage half-bridge PFC circuit, each with two semiconductor switches, the polarity reversing circuit being implemented with diodes;
• 8th a block diagram of a signal generation unit of the half-bridge PFC circuit;
• 9 the type of drive signal generation of the half-bridge PFC circuit acc. 7 with a positive half-cycle of the input voltage; and
• 10 the type of drive signal generation of the half-bridge PFC circuit acc. 7 in the case of a negative half-cycle of the input voltage.

This description illustrates the principles of the inventive disclosure. It is thus understood that those skilled in the art will be able to conceive various implementations which, while not explicitly described herein, embody principles of the inventive disclosure and are intended to be protected within their scope.

As described, there is the approach of operating a PFC circuit in Boundary Conduction Mode (BCM). The time t _on for the repeated magnetization of the inductance L is kept constant over a sine half-wave of the mains AC voltage. This time is proportional to the instantaneous power output of the switched-mode power supply and is specified by a voltage regulator, which is intended to keep the output voltage of the circuit, ie 400 V, for example, constant.

In addition, the time for demagnetizing the inductance L must be set. According to the solution according to a parallel patent application by the applicant P-2020-0136-DE, this occurs in that the point in time at which the second current switch is to switch off is precalculated and the time for demagnetization is set accordingly.

Da die Berechnung durch Bauteil-Toleranzen und andere Faktoren, wie Verzögerungen bei der Generierung der Ansteuersignale in Treiberstufen, etc. abweichen kann, wird geprüft werden, ob mit der berechneten Off-Zeit auch der gewünschte Stromwert in der Induktivität L erreicht wurde. Dazu wird die erforderliche Information des Stroms aus dem Pfad des ersten Halbleiterschalter S1 gewonnen. Dazu ist in dem Strompfad ein Strommesswiderstand (Shunt) geschaltet, mit dem eine Messspannung erzeugt wird, die proportional zum Storm durch den Halbleiterschalter S1 ist. Dieser Messwert wird als Istwert einem Regler zugeführt, der einen Korrekturwert ausgibt, der die Berechnung der Abmagnetisierungszeit beeinflusst.The demagnetization time (off time) during which the first current switch S1 is open and the second S2 is closed is calculated as follows from the time t _on for magnetization: $$t_{Off}=\frac{V_{in}}{V_{O\mathrm{and}t}-V_{in}}\ast t_{On}.$$

Since the calculation can deviate due to component tolerances and other factors, such as delays in the generation of the control signals in the driver stages, etc., it is checked whether the desired current value in the inductance L was also reached with the calculated off time. To do this, the necessary information about the current is obtained from the path of the first semiconductor switch S1. For this purpose, a current measuring resistor (shunt) is connected in the current path, with which a measuring voltage is generated which is proportional to the current through the semiconductor switch S1. This measured value is fed to a controller as an actual value, which performs a correction value that influences the calculation of the demagnetization time.

This solution must be adapted for a multi-stage active PFC circuit. Because, as explained at the outset, there is the problem that the ripple currents would increase if the step-up converter stages are switched with the same drive signals without a phase difference.

the 6 shows a basic circuit diagram of a two-stage half-bridge PFC circuit according to the invention with pole reversing circuit. The sinusoidal mains voltage with 230 V effective value and 50 Hz mains frequency is present at the AC _in input. This circuit contains two step-up converter stages HSa and HSb. An inductor and two semiconductor switches and a measuring resistor are provided for each step-up converter stage. The first step-up converter stage HSa consists of an inductor L1a, a first semiconductor switch S1a and a second semiconductor switch S2a and a measuring resistor R1a. The second step-up converter stage HSb consists of an inductor coil L1b, a first semiconductor switch S1b and a second semiconductor switch S2b and a measuring resistor R1b. In the example, the choke coils L1a and L1b each have an inductance of 64 μH. In the example, the measuring resistors R1a and R1b each have a resistance value of 20 mΩ. The line into which the choke coil L1a is connected goes to a node P1a which is connected on the one hand to the drain output of the second semiconductor switch S2a. On the other hand, the node P1a is connected to the source input of the first semiconductor switch S1a. Both semiconductor switches S1a and S2a are designed as field effect transistors of the nMOSFET type. They serve to rectify and chop the input signal. To do this, they are switched at a relatively high frequency, eg 100 kHz. The drive signal CTRLA1 is applied to the gate of the field effect transistor S1a. The drive signal CTRLA2 is applied to the gate of the field effect transistor S2a.

The line into which the choke coil L1b is connected goes to a node P1b which is connected on the one hand to the drain output of the second semiconductor switch S2b. On the other hand, the node P1b is connected to the source input of the first semiconductor switch S1b. These semiconductor switches S1b and S2b are also in the form of field effect transistors of the nMOSFET type. Instead, other semiconductor switches, such as bipolar transistors, thyristors or IGBTs, could be used for all or selected semiconductor switches. The drive signal CTRLB1 is applied to the gate of the field effect transistor S1b. The drive signal CTRLB2 is applied to the gate of the field effect transistor S2b. The exact timing of these drive signals is calculated in a digital circuit that is 6 is not shown, but which is explained in more detail below.

At the output of the half-bridge PFC circuit 100, a filter capacitor C1 is connected, which is charged during the switching phase of the semiconductor switches S1a and S1b and provides the subsequent DC converter of the switched-mode power supply with a high voltage of 400 V, for example. The filter capacitor C1 has a capacitance of 600 μP, for example. The current, which flows in the opposite direction to discharging the transistor capacitance of semiconductor switches S2a and S2b when the semiconductor switches S1a and S1b are open, flows through the measuring resistor R1a and R1b, which is provided in the lower switching branch of the series connection of the two semiconductor switches S1a, S2a and S1b, S2b . With this current flow, the transistor capacitance of the lower semiconductor switch S2a, S2b contained in a step-up converter stage HSa, HSb is discharged, which is necessary for switching with as few losses as possible. In order to achieve this, it is first necessary to measure the current flow. Therefore, the voltage drop across the measuring resistor R1a is recorded. This is done in such a way that the voltages at the node points P3a and P4a are fed to inputs of a signal conditioning circuit MEa. In the signal conditioning circuit, the measurement signals are amplified and filtered, and the difference voltage is formed via a voltage divider, which is then fed to an A/D input of the digital circuit 110 . The voltage drop across the measuring resistor R1b of the second step-up converter stage HSb is recorded in exactly the same way. A pole-changing circuit consists of the two semiconductor switches S3 and S4. These are, for example, also nMOS field effect transistors. Node P2, to which both transistors are connected, is connected to the return line to the AC input voltage source _{AC in .} Both semiconductor switches S3 and S4 are used to reverse the polarity of the circuit. For the positive half-cycle of the input voltage, S4 is blocked and S3 is switched on. For the negative half cycle of the input voltage, S3 is blocked and S4 is switched on. The switching signals CTRL3 and CTRL4 are therefore generated with the 50 Hz mains frequency. The incoming AC input voltage is also recorded. The signal adjustment circuit ME1 is used for signal adjustment. The difference signal is fed to a further A/D input of the signal generation unit 110 . The boosted output voltage Vout is also detected. The signal adjustment circuit ME2 is used for signal adjustment. The metrologically adapted output voltage Vout is fed to a further A/D input of the signal generation unit 110 .

the 7 shows another variant of this half-bridge PFC circuit, in which the two semiconductor switches S3 and S4 are replaced by diodes D1 and D2. These have the advantage that they do not require dedicated switching signals. The diodes are self-locking and show the desired polarity reversal behavior even without control signals. The other components in 7 , which have the same reference numbers as in 6 , denote the same components.

With the circuit acc. 7 an approach for a single-stage active PFC circuit is further developed, which was already presented in the applicant's parallel patent application P-2020-0136 DE.

The time Ton, which is set at approx. 100 kHz for chopping the input voltage, is kept constant over a sine half wave of the mains voltage. This time corresponds to the time required to magnetize the inductance L per control process. As described, the PFC circuit contains a current control loop which has the task of _{keeping the instantaneous value of the input current I L} (t) (choke current) proportional to the instantaneous value of the input voltage V _in (t). This is done by varying the control cycle time. In this way, the power factor can then be kept close to one. This time is proportional to the power and is specified by a voltage regulator, which is intended to keep the output voltage of the circuit constant at 400 V, for example.

In order to set the time for demagnetizing the choke coil L, the time at which the first semiconductor switch S1a, S1b is to switch off is precalculated in the applicant's parallel patent application and this calculation is corrected with the aid of an additional current control process. This pre-calculation and correction can be carried out based on the positive input voltage (positive half-cycle) or the negative input voltage (negative half-cycle), because the necessary information to be able to correct the current thresholds is contained in both cases.

However, the solution in the parallel patent application relates only to a step-up converter with a step-up converter stage.

In the case of the single-stage boost converter, the magnetization time and the demagnetization time are precalculated in the integrated circuit 110 . The control cycle time of the step-up converter stage is then only adjusted in order to reach the lower current threshold of the current peak value. The pre-calculated values can therefore be used for both step-up converter stages.

In order to minimize the ripple current, it is necessary to allow the step-up converter stages to work at different times. In a two-stage boost converter circuit, it is best to operate the switching cycle of the second stage 180° out of phase with the first boost converter stage HSa. A master timer is used for this, which specifies the control cycle times for both stages. This can be done in such a way that when half the timer value is reached, the switching signal CTRL_B1 for switching on the first semiconductor switch S1b of the second stage HSb is reset and for the first step-up converter stage HSb the switching signal CTRL_A1 is only reset at the end of the master timer value. If you left it at that, the phase shift of 180° between the switching cycles would exist, but it would not be guaranteed that the inductor current in the boost converter stage HSb would have the same lower threshold value as the inductor current in the boost converter stage HSa. Since the control method of the first step-up converter stage HSa influences the period of the switching cycle (or demagnetization time) and the 180° phase shift in the activation of the semiconductor switches is controlled via this, the control method for the second step-up converter stage HSb is therefore modified according to the invention.

The signal detection and the type of control of the second stage are identical to the first step-up converter stage HSa. In the second step-up converter stage HSb, however, in order to regulate the same lower threshold value of the inductor coil current, it is not the period duration that is influenced, but rather the magnetization time of this stage. So the output variable of the controller for the step-up converter stage HSb is added to or subtracted from the precalculated magnetization time for this stage, depending on the sign of the controlled variable of the controller. The lower threshold value can also be reached in this way without adjusting the control cycle time.

8th shows a block diagram of the signal generation unit 110 with which the control signals CTRL_A1, CTRL_A2 and CTRL_B1, CTRL_B2 for the semiconductor switches of the step-up converter stages HSa, HSb are generated. It is an integrated circuit with which this type of control is implemented. The integrated circuit can be implemented in the form of a DSP (digital signal processor), FPGA (field programmable gate array), or ASIC (application specific integrated circuit) or using a standard microcontroller and appropriate software. The variant shown applies to the case that the positive input voltage (half-wave) of the AC input voltage is applied. However, the controller architecture is for operation with both half-waves of the input change designed for voltage. However, this requires the components of the controller architecture to be reconfigured.

berechnet werden, die bereits eingangs erläutert wurde. Diese Formel gilt immer dann, wenn der Stromverlauf durch die Drosselspule L an der Lückgrenze betrieben wird. Diese Regelungsstufe 112 arbeitet mit der Eingangsinformation über die Differenz zwischen gewünschter Zwischenkreisspannung von z.B. 400 V und der tatsächlich gemessenen Zwischenkreisspannung. Die Differenz wird von der Subtraktionsstufe 111a geliefert.The control signals CTRL_A1 and CTRL_A2 for the semiconductor switches S1a and S2a of the first boost converter stage HSa and CTRL_B1 and CTRL_B2 for the semiconductor switches S1b and S2b of the second boost converter stage HSb 100 are generated with the controller. The block diagram contains the following components: The reference number 111 designates three subtraction stages. In the first subtraction stage 111, the output voltage Vout is subtracted from the reference _voltage V Out_Ref. The output voltage should be kept as constant as possible at the value of 400 V. The deviation from the desired value is thus determined in the first subtraction stage 111 . Depending on the load on the switched-mode power supply, the intermediate circuit voltage can vary from 400 V and must be readjusted. In the second subtraction stage 111, the currently measured current I _{b_neg} through the measuring resistor R1b is subtracted _{from the specified current threshold reference value I Neg_Ref.} The current is always measured at the precalculated and corrected points in time. No further current measurement values need to be recorded. Thus, in this subtraction stage 111, the respective deviation I _err from the desired value I _{ref is} determined. This is the essential information for the subsequent control stage 113b, in which the correction T _{P_Offset} for the precalculated period T _{P of} the respective control cycle is calculated. A PI controller or PID controller can be used for this, for example. Depending on the requirement as to how quickly the difference should be corrected, a different controller can also be used. The control stage 113b outputs the correction _value T P_Offset to the downstream master timer unit 116 . In addition, the information about the calculated control cycle time T _{P is also} supplied to the master timer unit 116 . This is calculated in the calculation unit 114, which is also for the calculated magnetizing T _on to fed. This information T _on is supplied by the control stage 112. This time T _on is kept constant for the positive half-wave. It is therefore a control stage that readjusts the manipulated variable only relatively slowly. It has been shown that even a 10 Hz PI controller is sufficient for this. The magnetization time T _on can be calculated using the formula $$t_{On}=\frac{P_{in}\ast 2\ast L}{V_{in}{}^2}$$

are calculated, which has already been explained at the outset. This formula always applies when the current flow through the choke coil L is operated at the gap limit. This control stage 112 works with the input information about the difference between the desired intermediate circuit voltage of, for example, 400 V and the actually measured intermediate circuit voltage. The difference is provided by the subtractor 111a.

die sich aus der Zeit für die Gesamtlänge von Aufmagnetisierungszeit T_on und der Abmagnetisierungszeit Toff zusammensetzt. Der erste Teil der Formel entspricht dabei der Formel für die Berechnung der Abmagnetisierungszeit, die eingangs erwähnt wurde.The calculation unit 114 calculates the control cycle time according to the formula $$T_P=\frac{V_{in}}{V_{O\mathrm{and}t}-V_{in}}\ast T_{On}+T_{On}$$

which is made up of the time for the total length of the magnetization time T _on and the demagnetization time Toff. The first part of the formula corresponds to the formula for calculating the demagnetization time that was mentioned at the beginning.

The master timer unit 116 corresponds to a programmable timer unit which outputs an event after the set times have elapsed. The event could also be output in the form of a generated signal. In digital technology, the event can also be issued in the form of a software event, which, similar to a software-generated interrupt, calls a specific program routine. A timer is set in the master timer unit 116, with which the control cycle time for the switching processes in the two step-up converter stages HSa and HSb is formed. At the same time, the offset of 180° phase difference between the controls of the semiconductor switches in the two step-up converter stages HSa and HSb is also controlled with this timer.

A controlled variable is calculated by the control stage 113a, which corresponds to _{the correction T On_Offset of} the magnetization time T _{on .} This correction is also recalculated per control cycle, ie with a frequency of approx. 100 kHz.

A timer is set in the timer unit 115b, which timer determines the magnetization time T _on for the step-up converter stage HSb. This timer is also reset per control cycle, i.e. with approx. 100 kHz. A timer is set in the timer unit 115a, which timer determines the magnetization time for the step-up converter stage HSa. This timer is reset per control cycle, i.e. with approx. 100 kHz. The setting of this timer differs from the setting of the timer in the timer unit 115b because the magnetization time is adjusted instead of the control cycle time in order to regulate the lower current threshold. For this purpose, the difference between the magnetization time T _on and the correction _{value T on_Offset is formed} in a further subtraction stage 111.

The actual signal generation for the control signals CTRL_A1, CTRL_A2 and CTRL_B1, CTRL_B2 takes place in the PWM signal generation unit 119.

The state of the input voltage is detected with the state machine 117 . This is sampled with a time grid of 25 kHz. The state machine 117 determines whether the positive half cycle or the negative half cycle of the input voltage is present. The status determined is forwarded to a configuration unit 118 which makes corresponding register settings for the various blocks of the integrated circuit 110 depending on the status. At least the PWM signal generation unit 119 has to be reconfigured, since the functions of the semiconductor switches S1 and S2 are reversed when the input voltage is negative.

the 9 shows the current control process with a positive input voltage, i.e. with the positive half-wave of the input AC voltage. The control signals for the semiconductor switches of the two step-up converter stages HSa are formed with the aid of the three different timer units 116, 115a and 115b. For these, the history of the timer statuses is given for three control cycles. In addition, the timing of the drive signals for the semiconductor switches in the step-up converter stages HSa and HSb is specified. The course of the timer value is plotted along the ordinate in the timer diagrams. The time t is plotted along the abscissa. The timer values run up linearly by incrementing up to a set maximum value, at which point they are reset again.

The master timer unit 116 is set to the maximum value T _P +T _{P_Offset} per control cycle. When half of this value is reached, the demagnetization time for the first step-up converter stage HSa ends. When the maximum value is reached, the demagnetization time for the second boost converter stage HSb ends. Both step-up converter stages work offset by 180°.

The timer unit 115a determines the times of the switching operations for magnetizing the inductor coil L1a in the step-up converter stage HSa during the positive half-cycle of the AC input voltage AC _in . The drive signal with which the semiconductor switch S2a is switched for the magnetization phase is in 9 also referred to as CTRL_A2. For this purpose, the semiconductor switch S2a is opened and the semiconductor switch S1a is closed. The timer of the timer unit 115a is started after the master timer unit 116 has completed the demagnetization time for the step-up converter stage HSa. In addition, there is a short waiting time delay2. This serves to ensure that the switching processes in the semiconductor switches are completed before the next magnetization phase begins. The control signal CTRL_A2 is started when the timer value CMP1=delay is reached and terminated _{when the programmed timer value CMP3=T on} +T _{On_Offset is reached.} The delay values are fixed for the sake of simplicity. If necessary, they could also be set variably. The correction _{value T On_A_Offset} depends on the measured current value through the measuring resistor R1, which is newly recorded per control cycle. The measurement of current is carried through the measuring resistor R1 at the time CMP4 = T _P + T _{P_Offset} - ADC_preTime However, based on the count of the timer of the timer unit 115a. The current through the measuring resistor R2 is measured at the time
CMP4=T _P +T _{P_Offset} -ADC_preTime, however, related to the count of the timer of the timer unit 115b. The respective AD converter is triggered at the pre-calculated and corrected points in time for measured value acquisition. The time ADC_preTime ensures that the current is not measured during a switching process. As a result, the recording times are offset from one another. The measured values serve as actual values for the calculations for the next control cycle.

The calculated timer value CMP3= T _on +T _{On_Offset also} takes into account the time delay. The time delay1 is awaited between switching off the magnetization phase and starting the demagnetization phase. The demagnetization phase serves to demagnetize the choke coil L1a and to discharge the transistor capacitance of the semiconductor switch S2a with the precalculated value. The demagnetization phase is also variable because the duration of the control cycle time is predetermined and the magnetization time is variable. The demagnetization phase is determined by generating the control signal CTRL_A1.

The timer unit 115b determines the times of the switching processes for magnetizing the inductor coil L1b in the step-up converter stage HSb. The boost converter stage HSb is operated as explained in the parallel patent application. The magnetization time is calculated in advance and remains constant during the time when the positive half-wave of the AC input voltage is present. The lower current threshold is regulated by varying the demagnetization time. The magnetization phase is started when the timer value CMP1=delay is reached. The control signal CTRL_B2 is started here. When the pre-calculated value CMP3= T _on is reached, the Aufmagneti phase ended. Then the waiting time delay3 is awaited before the demagnetization phase is started by switching on the control signal CTRL_B1. This demagnetization phase is terminated variably by the master timer unit 116 terminating the control cycle time variably. The correction value is used here, by which the time T _P per control cycle calculated in advance after the previous control process is corrected. After the activation signal CTRL_B1 has been switched off, the waiting time delay4 is awaited before the timer of the timer unit 115b is reset. To determine the magnetization phase, the control signal CTRL_B2 is generated as shown.

10 shows the corresponding control processes with a negative input voltage at the end of the current edge. The same reference numbers again designate the same components as previously explained. However, it is noted that the semiconductor switches in the step-up converter stages HSa and HSb each swap roles. The timer unit 115a determines the times of the switching processes for demagnetizing the inductor coil L1a in the step-up converter stage HSa during the negative half-cycle of the AC input voltage AC _in . The master timing unit 116 determines the end of the magnetization phase to obtain the 180° phase offset. The timing unit 115b determines the times of the switching processes for magnetizing the inductor L1b in the step-up converter stage HSb during the negative half-cycle of the AC input voltage AC _in . The time for demagnetization is determined by the master timer unit 116 .

The disclosure is not limited to the exemplary embodiments described here. There is room for various adaptations and modifications that those skilled in the art would contemplate based on their skill in the art as well as belonging to the disclosure.

Reference List

1

line filter

2

rectifier

3

filter capacitor

4

switching stage

5

transmitter

6

controller

7

optocoupler

10

rectification stage

20

DC chopper

30

power transfer stage

40

smoothing level

50

control level

60

electrical isolation

70

steering

100

boost converter

110

signal generation unit

111

subtraction levels

112

voltage regulation stage

113a

1. Current control level

113b

2. Current control level

114

calculation unit

115a

1. Timer unit

115b

2. Timer unit

116

master timer unit

117

AC input voltage detection unit

118

configuration unit

119

PWM signal generation unit

C1

filter capacitor

CTRL_A1, CTRL_A2

Control signals boost converter stage A

CTRL_B1, CTRL_B2

Control signals boost converter stage B

D

diode

D1, D2

rectifier diode

DSP

digital signal processor

delay, delay1, delay2, delay3, delay4

waiting times

Cosc

transistor capacitance

HSa, HSb

boost converter stages

Ib

measured current

Ia_sense, Ib_sense

Lines for current measurement

IL

coil current

L1a, L1b

choke coils

ME1, ME2, MEa, MEb

signal conditioning unit

P1a, P1b, P2, P3a, P3b

nodes

R1a, R1b

measuring resistor

S1a, S2a, S1b, S2b

semiconductor switch

SNG

switching power supply

ton, ton

magnetization time

tOff

demagnetization time

tRes

resonant vibration time

TOn_A_Offset

Correction value magnetization time

TP_Offset

Correction value demagnetization time

TP

control cycle time

vintage

input voltage

Vout

output voltage

Vout_ref

Output voltage reference value

QUOTES INCLUDED IN DESCRIPTION

This list of the documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent Literature Cited

• US 8766605 B2 [0008]
• US20070109822A1[0012]
• US 8026704 B2 [0012]
• US 8363434 B2 [0015]

Non-patent Literature Cited

• "Current Mode Control structure: Current-Mode Control: Modeling and Digital Application", by Jian Li, April 14, 2009, Blacksburg, Virginia Polytechnic Institute and State University [0013]
• "LED Application Design Using BCM Power Factor Correction (PFC) Controller for 100W Lightning System"; AN-9731, 02011 Fairchild Semiconductor Corporation Rev.1.0.0, 3/24/11 [0014]

Claims (16)

Step-up converter for a power supply of an electrical consumer with at least two step-up converter stages (HSa, HSb), having a bridgeless rectifier circuit (D1, D2; S3, S4) and a filter capacitor (C1), with one inductor (L1a, L1b) being provided for each step-up converter stage, wherein the inductor (L1a, L1b) is connected to one pole of the AC voltage source (AC _in ) and to a node (P3a, P3b) between two semiconductor switches (S1a, S2a; S1b, S2b), the first semiconductor switch (S1a, S1b ) is connected in series with a measuring resistor (R1a, R1b) per step-up converter stage (HSa, HSb), with a signal generation unit (110), the control signals for the two semiconductor switches (S1a, S2a; S1b, S2b) per step-up converter stage (HSa, HSb) generated, the first semiconductor switch (S1a, S1b) being closed and the second for step-up conversion of the input voltage when the input voltage (V _{in ) is positive for each step-up converter stage (HSa, HSb).} Semiconductor switch (S1a, S1b) is opened in order to drive a current through the inductor (L1a) to magnetize the inductor (L1a), the first semiconductor switch (S1a, S1b) and the second semiconductor switch being opened to demagnetize the inductor (L1a). (S2a, S2b) is closed and the filter capacitor (C1) is charged accordingly, the signal generation unit (110) having means for detecting the current through the respective measuring resistor (R1a, R1b), characterized in that the signal generation unit (110) has a control unit (113a, 113b) which drive the step-up converter stages (HSa, HSb) offset with respect to one another with a selected phase shift, the drive unit (113b) being designed to regulate the period of the drive signals in one step-up converter stage (HSb) and in the at least one other step-up converter stage (HSa) constant, and the magnetization time in the at least one other high to regulate step-up converter stage (HSa) and to keep it constant in the first step-up converter stage (HSb). boost converter after claim 1 Wherein, the first semiconductor switch (S1a, S1b) is opened to the up-conversion of the input AC voltage at a negative input voltage (V _in) per boost converter stage (HSa, HSb) and the second semiconductor switches (S2a, S2b) is closed by a current through the inductor (L1a, L1b) for magnetizing the inductor (L1a, L1b), with the first semiconductor switch (S1a, S1b) being closed and the second semiconductor switch (S2a, S2b) being opened and the filter capacitor ( C1) is charged accordingly, and the signal generation unit (110) has means for detecting the current through the measuring resistor (R1a, R1b) at the end of the phase for demagnetizing the inductance (L1a, L1b). boost converter after claim 1 or 2 , wherein the signal generation unit (110) has a calculation unit (114) which precalculates the control cycle time (T _P ) for the phases for magnetization and demagnetization per control cycle as a function of the input voltage (V _in ) and output voltage (V _out ), and the signal generation unit (110) further comprises a control stage (113b), which based on the difference between the measured current value (I _b) through the measuring resistor (R 1b) in the first up converter stage (HSB) and a current reference value (Iref) a correction value (T _{P_Offset} ) for the control cycle time (T _P ). boost converter after claim 3 , the correction _value (T P_Offset ) being used in a first timer unit (116) of the signal generation unit (110) for the subsequent control cycle, so that the first timer unit (116) shortens or lengthens _{the control cycle time (T P ) accordingly.} boost converter after claim 4 , wherein the signal generation unit (110) has a further control stage (112) which calculates a magnetization time (T _{On ) from the difference between the specified output voltage (V Out_ref} ) and the measured output voltage (V _Out ), which is calculated in the at least first and second step-up converter stage ( HSa, HSb) is used. Boost converter after one of claims 3 until 5 , wherein the signal generation unit (110) has a further control stage (113a) which is based on the difference between the measured current value (I _b ) through the measuring resistor (R1b) in the first step-up converter stage (HSb) and the measured current value (I _a ). the measuring resistor (R1a) in the second step-up converter stage (HSa) calculates a correction _value (T On_A_Offset ) for the magnetization time (T _On ), which is used in the second step-up converter stage (HSa). Boost converter after one of Claims 4 until 6 , wherein the signal generation unit (110) has a second timer unit (115b) to which the calculated magnetization time (T _On ) is forwarded, in which the magnetization time (T _On ) for a number of subsequent control cycles for the first step-up converter stage (HSb) is used . boost converter after claim 7 , wherein the signal generation unit (110) has a third timer unit (115a) to which the corrected magnetization time (T _{On_A_offset} ) is forwarded, in which the corrected magnetization time (T _{On_A_Offset} ) for the subsequent control cycle for the second step-up converter stage (HSa) is applied. boost converter after claim 7 or 8th , where the number of control cycles for which the calculated magnetization time (T _On ) for the first step-up converter stage (HSb) is used is valid for one half cycle of the AC input voltage. Boost converter according to one of the preceding claims, wherein the signal generation unit (110) is equipped with an input AC voltage detection unit (117) which is set up to determine the phase position of the input AC voltage, and the information about the phase position, in particular whether the positive half-wave or negative half-wave of the AC input voltage is present, to a configuration unit (118) of the signal generation unit (110). boost converter after claim 10 , wherein the configuration unit (118) is set up to configure a number of the components of the signal generation unit (110) for operation with a positive input voltage or with a negative input voltage, depending on what the information about the phase position of the AC input voltage indicates. Boost converter according to one of the preceding claims, wherein the measuring resistor (R1a, R1b) in the at least first and second step-up converter stage (HSa, HSb) in each case between the first semiconductor switch (S1a, S1b) and the return line to the input AC voltage source (AC _in ) to which the Inductance (L1, L2) is not connected, is connected. Boost converter according to one of the preceding claims, wherein the at least first and second step-up converter stage (HSa, HSb) has a choke coil (L1a, L1b) as inductance. Power supply for an electrical consumer, characterized in that the power supply (SNG) has a step-up converter (100) according to one of the preceding claims, the step-up converter (100) being used for power factor pre-regulation in the power supply. power supply after Claim 14 , whereby the power supply (SNG) is designed as a switching power supply. Method for step-up conversion of the input voltage in a power supply of an electrical consumer, which has a multi-stage step-up converter (100) with at least two step-up converter stages (HSa, HSb), with a rectifier circuit (D1, D2; S3, S4) and a filter capacitor (C1), wherein one inductance (L1a, L1b) is provided for each step-up converter stage (HSa, HSb), the inductance (L1a, L1b) being connected to one pole of the AC voltage source (AC _in ) and to a node (P3a, P3b) between two semiconductor switches ( S1a, S2a; S1b, S2b), wherein the first semiconductor switch (S1a, S1b) per step-up converter stage (HSa, HSb) is connected in series with a measuring resistor (R1a, R1b), with a signal generation unit (110) from the control signals for the two Semiconductor switches (S1a, S2a; S1b, S2b) per step-up converter stage (HSa, HSb) are produced, with step-up conversion of the input voltage given a positive input voltage (V _in ) per step-up step eller stage (HSa, HSb) the first semiconductor switch (S1a, S1b) is closed and the second semiconductor switch (S1a, S1b) is opened in order to drive a current through the inductor (L1a, L1b) to magnetize the inductor (L1a, L1b) , the first semiconductor switch (S1a, S1b) being opened and the second semiconductor switch (S2a, S2b) being closed and the filter capacitor (C1) being charged accordingly in order to demagnetize the inductance (L1a, L1b), the current flowing through the respective measuring resistor ( R1a, R1b) is detected by the signal generation unit (110), characterized in that the signal generation unit (110) has a drive unit (113a, 113b) by which the step-up converter stages (HSa, HSb) are driven offset with a selected phase shift relative to one another, wherein the period of the drive signals in one step-up converter stage (HSb) is controlled by the drive unit (113b) and in the at least one other step-up controller stage (HSa) is kept constant, and the magnetization time in the at least one other step-up converter stage (HSa) is regulated and in the first step-up converter stage (HSb) is kept constant.

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