CN220189651U

CN220189651U - Semiconductor device structure and image sensor

Info

Publication number: CN220189651U
Application number: CN202321621681.4U
Authority: CN
Inventors: 许书洋; 万皓
Original assignee: SmartSens Technology Shanghai Co Ltd
Current assignee: SmartSens Technology Shanghai Co Ltd
Priority date: 2023-06-25
Filing date: 2023-06-25
Publication date: 2023-12-15
Anticipated expiration: 2033-06-25

Abstract

The utility model provides a semiconductor device structure and an image sensor, wherein the semiconductor device structure is suitable for the image sensor and comprises the following components: the semiconductor substrate comprises a plurality of chip areas and cutting areas positioned at the periphery of the chip areas; the cutting area comprises an interface blocking cutting area, and the chip area comprises an auxiliary cutting area; the auxiliary cutting area is adjacent to the cutting area, and the cutting outer edge corresponds to the interface separation cutting area and has a distance with the auxiliary cutting area. Through the design of the utility model, the influence of the cutting process on the chip core area in the process of cutting and acquiring the chip can be effectively relieved.

Description

Semiconductor device structure and image sensor

Technical Field

The utility model belongs to the technical field of image acquisition, and particularly relates to a semiconductor device structure and an image sensor.

Background

The image sensor is an important component constituting the digital camera. Two major classes, CCD (charge coupled device) and CMOS (metal oxide semiconductor device), are classified according to the device. With the continuous development of CMOS integrated circuit manufacturing processes, particularly CMOS Image Sensor (CIS) design and manufacturing processes, CMOS Image sensors have gradually become the mainstream in place of CCD Image sensors. Compared with the CMOS image sensor, the CMOS image sensor has the advantages of higher industrial integration level, lower power and the like.

The existing image sensor often has the phenomenon of interference imaging or tearing (chipping) in the chip segmentation process, so that the core area of the chip is damaged to different degrees, and the performance of the image sensor and the imaging effect of the image sensor are directly affected. Thus, improvement of the chip dicing process is a highly-needed problem.

Therefore, it is necessary to provide a semiconductor device structure, an image sensor, a method for manufacturing the same, and an electronic device for solving the above-mentioned problems in the prior art.

It should be noted that the foregoing description of the technical background is only for the purpose of providing a clear and complete description of the technical solution of the present utility model and for the convenience of understanding by those skilled in the art. The above-described solutions cannot be considered to be known to the person skilled in the art simply because they are set forth in the background section.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present utility model is to provide a semiconductor device structure and an image sensor, which are used for solving the problems of the prior art that the chip core area is affected during the chip dividing process of the image sensor.

To achieve the above and other related objects, the present utility model provides a semiconductor device structure adapted for an image sensor, comprising:

The semiconductor substrate comprises a plurality of chip areas and a cutting area positioned at the periphery of the chip areas;

the cutting area comprises an interface blocking cutting area, and the chip area comprises an auxiliary cutting area;

the auxiliary cutting area is adjacent to the cutting area, and the cutting outer edge corresponds to the interface separation cutting area and is spaced from the auxiliary cutting area.

Optionally, the dicing area further includes a peripheral functional area, the interface blocking dicing area is located between the peripheral functional area and the chip area, the peripheral functional area includes a first material structure and a second material structure with different materials, and the interface blocking dicing area and/or the auxiliary dicing area includes a crack relieving material layer located on the same structural layer as the interface of the two.

Optionally, the peripheral functional area includes a plurality of chip detection structures, and a first buffer area is arranged between the chip detection structures and the interface blocking cutting area on the adjacent side;

optionally, a second buffer region is provided between adjacent chip detection structures along a direction in which the chip region and the dicing region are arranged.

Optionally, the first material structure is a metal, the second material structure is an interlayer dielectric, and the crack mitigating material layer is an interlayer dielectric.

Optionally the plurality of chip detection structures form at least one detection structure band, the first buffer region being located between the detection structure band and the adjacent interface barrier cut region; when the number of the detection structure belts is at least two, the second buffer areas are positioned between the adjacent detection structure belts, and different sides of the cutting outer edge are corresponding to the interface blocking cutting areas or the interface blocking cutting areas and the second buffer areas respectively.

Optionally, the semiconductor substrate includes a stacked semiconductor substrate and an interconnection structure layer, the chip region includes a chip body region, the auxiliary dicing region is located between the chip body region and the dicing region, and the interconnection structure layer includes a first clearance region corresponding to the interface blocking dicing region and/or a second clearance region corresponding to the auxiliary dicing region.

Optionally, the interconnection structure layer further includes a virtual wiring region corresponding to the auxiliary cutting region, the second clearance region is adjacent between the cutting region and the virtual wiring region, the virtual wiring region includes at least one of a wiring buffer structure region and a guard ring structure region, and when both are present, the wiring buffer structure region is disposed close to the second clearance region.

Optionally, the guard ring structure region includes a plurality of guard ring structures, and the plurality of guard ring structures are annularly disposed on the periphery of the chip body region.

Optionally, the wiring buffer structure region includes a plurality of wiring buffer structures, and the plurality of wiring buffer structures form a plurality of buffer structure rows and/or buffer structure columns at the periphery of the chip body region.

Optionally, the width of the first clearance area is greater than or equal to 4 μm.

Optionally, the width of the second clearance area is greater than or equal to 3 μm.

Optionally, a sum of widths of the wiring buffer structure region and the second clearance region is greater than or equal to 18 μm.

Optionally, a distance between the cut outer edge and the guard ring structure region near the side is greater than or equal to 20 μm.

Optionally, the semiconductor substrate includes a virtual active region corresponding to the auxiliary cutting region, the virtual active region is located between the cutting region and the chip body region, and the virtual active region corresponds to at least the second headroom region.

Optionally, the virtual active area includes a headroom release area and an evaluation buffer groove area, where the headroom release area is adjacent to the cutting area and is disposed corresponding to the second headroom area, and the evaluation buffer groove area is adjacent to the chip main body area.

Optionally, a virtual device transition region is further arranged between the headroom release region and the evaluation buffer slot region, and covers the boundary of the second headroom region and the virtual wiring region when the second headroom region and the virtual wiring region are adjacent; and/or the evaluation buffer groove area is provided with an evaluation buffer groove, and a spacing structure layer is arranged between the bottom and the wiring buffer structure area.

Optionally, the transition region of the virtual device is provided with a trench isolation structure, and the trench isolation structure comprises a plurality of sub isolation structures arranged in an array or a single trench isolation structure with hollowed-out parts; and/or the interval structure layer comprises a single interval structure or a plurality of interval blocks arranged in an array, and the interval structure or the interval blocks are exposed at the bottom of the evaluation buffer groove.

Optionally, the included angle between the line center line of each line of the wiring buffer structure and the cutting line is set in an acute angle trend, and the included angle between the column center line of each column of the wiring buffer structure and the cutting line is set in an acute angle trend.

Optionally, the included angle between the line center line of each line of the trench isolation structure and the cutting line is set in an acute angle trend, and the included angle between the column center line of each column of the trench isolation structure and the cutting line is set in an acute angle trend.

Optionally, the wiring buffer structure is vertically arranged in at least two layers, and a space is arranged between centers of the wiring buffer structures at corresponding positions of adjacent layers.

Optionally, the semiconductor device structure further includes at least one stacking substrate stacked with the semiconductor substrate, and each region of the stacking substrate is disposed vertically corresponding to each region of the semiconductor substrate.

Optionally, the peripheral functional area of the semiconductor substrate is electrically connected with the peripheral functional area of the stacked substrate through an interlayer interconnection structure, and the same structural layer of the interlayer interconnection structure corresponds to the auxiliary cutting area and the interface blocking cutting area.

The utility model also provides an image sensor, which comprises a chip area, wherein the chip area is obtained by cutting along the cutting area based on the semiconductor device structure according to any one of the schemes.

The utility model also provides electronic equipment comprising the image sensor according to any one of the schemes.

The utility model also provides a preparation method of the image sensor according to any one of the schemes, which comprises the following steps:

providing the semiconductor device structure;

performing first cutting along the outer cutting edge to obtain an intermediate cutting structure;

And performing second cutting on the intermediate cutting structure corresponding to the cutting area to obtain separated chip areas, wherein the width of a cutting knife for second cutting is smaller than that of the cutting knife for first cutting.

Optionally, in the dicing direction, a dicing bottom of the first dicing exceeds a depth of the peripheral functional region of the semiconductor device structure.

As described above, the semiconductor device structure and the image sensor of the present utility model can effectively alleviate the influence on the chip area in the dicing process based on the configuration design of each region on the semiconductor device structure, and are beneficial to preventing the generation of cracks (dicing) in the dicing process, and also beneficial to preventing the interface cracks and the direct tearing of the substrate. The size of the cutting tool can be flexibly configured, the influence of the cutting process on the chip can be further relieved based on the combined configuration of the cutting tool, and the imaging quality is improved.

Drawings

Fig. 1 is a block diagram showing the basic structure of an image sensor system.

Fig. 2 shows a schematic diagram of a pixel circuit of an image sensor.

Fig. 3 is a schematic top view of a semiconductor structure according to an embodiment of the utility model.

Fig. 4 is a cross-sectional view of the semiconductor device structure of fig. 3 taken along the i-ii position.

Fig. 5 is a schematic cross-sectional view showing an example of a structure corresponding to the dashed-line box of fig. 4.

Fig. 6 shows a top view of an example of the structure corresponding to fig. 5.

Fig. 7 shows a top view of another exemplary structure corresponding to fig. 5.

Fig. 8 is a schematic cross-sectional view showing another example of the structure corresponding to the dashed-line frame of fig. 4.

Fig. 9 is a plan view showing an example of the structure corresponding to fig. 8.

Fig. 10 illustrates a partial area distribution of interconnect structure layers of a semiconductor device structure in accordance with an embodiment of the present application.

Fig. 11 shows a semiconductor substrate portion partitioning distribution of a semiconductor device structure in accordance with one embodiment of the present application.

Fig. 12 is a schematic diagram showing an arrangement of a wiring buffer structure according to an embodiment of the present application.

Fig. 13 is a schematic diagram illustrating an arrangement of trench isolation structures according to an embodiment of the application.

Fig. 14 is a flowchart showing the preparation of an image sensor according to an embodiment of the application.

Fig. 15 is a schematic diagram showing an intermediate dicing structure in the manufacture of an image sensor according to an embodiment of the present application.

Description of element reference numerals

100. Semiconductor device structure

101a, 101b, 101c, 101d chip area

102a, 102b cutting region

1012. Auxiliary cutting area

1013. Second headroom region

1014. Virtual wiring area

1015. Wiring buffer structure region

1016. Guard ring structure region

1017. Virtual active area

1018. Headroom releasing zone

1019. Virtual device transition region

1020. Evaluating a buffer sector

1020a evaluation buffer slot

1021. Peripheral functional area

1022. 1023 interface separation cutting area

201. First cutting tool

202. Second cutting tool

300. Chip detection structure area

301a and 301b chip detection structure

302. 303 first buffer

304. Second buffer area

Detailed Description

Other advantages and effects of the present utility model will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present utility model with reference to specific examples. The utility model may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present utility model.

It should be emphasized that the term "comprises/comprising" when used herein is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps or components.

Features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments in combination with or instead of the features of the other embodiments.

As described in detail in the embodiments of the present utility model, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present utility model. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.

For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present.

In the context of the present utility model, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present utility model by way of illustration, and only the components related to the present utility model are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

The present utility model will be described in detail with reference to the accompanying drawings.

Fig. 1 is a block diagram showing the basic structure of an image sensor system. The image sensor comprises a reading circuit and a control circuit which are connected to the pixel array, the functional logic unit is connected to the reading circuit, and the reading circuit and the control circuit are connected to the state register to realize reading control of the pixel array. The pixel array includes a plurality of pixels (P1, P2, P3) arranged in rows (R1, R2, R3 … Ry) and columns (C1, C2, C3 … Cx), and pixel signals output from the pixel array are output to the readout circuit via the column lines. In one embodiment, after each pixel acquires image data, the image data is read out using a read mode specified by a status register and then transferred to a functional logic unit. In particular applications, the readout circuitry may include analog-to-digital conversion (ADC) circuitry, among others.

In some applications, the status register may include a programmable selection system for determining whether the readout system is to read out by a rolling exposure mode (rolling shutter) or a global exposure mode (global shutter). The functional logic may store only image data or image data applied or processed by an image effect. In particular applications, the readout circuitry may read out one row of image data at a time along the readout column lines, or may read out the image data in various other ways. The operation of the control circuit may be determined by the current setting of the status register, e.g., the control circuit generates a shutter signal for controlling image acquisition, which in some applications may be a global exposure signal such that all pixels of the pixel array acquire their image data simultaneously through a single acquisition window. In some other applications, the shutter signal may be a rolling exposure signal such that the pixels of each pixel row of the pixel array are consecutively read through the acquisition window.

Fig. 2 is a schematic diagram showing connection of a pixel circuit in the image sensor. As shown in fig. 2, each pixel circuit includes a photoelectric conversion element (e.g., photodiode) and a pixel circuit (shown as a transistor within a dashed box). The photodiode may be a buried photodiode (PPD) applied in the current image sensor. In an application example, the pixel circuit includes a reset transistor (RST), a source follower transistor (SF), and a pixel selection transistor (RS), which are connected to a transfer Transistor (TX) and a photodiode as shown in the drawing. In another stacked structure application, not shown, the pixel circuit includes a reset transistor, a source follower transistor, and a pixel select transistor disposed on one circuit chip, which are connected to a photodiode in another chip based on a transfer transistor. In operation, the photoelectric conversion element generates photo-charges in response to incident light during exposure, and the transfer transistor is connected to a transfer signal that controls the transfer transistor to transfer charges accumulated in the photoelectric conversion element to a floating diffusion region (FD). In one embodiment, the transfer transistor may be a MOSFET (metal oxide semiconductor field effect transistor), the reset transistor being connected between VDD and the floating diffusion region, the reset transistor being responsive to a reset signal to reset the sensor pixel circuit (e.g., discharge or charge the floating diffusion region and photodiode to a present voltage), the floating diffusion region being connected to the gate of the source follower transistor, the source follower transistor being connected between VDD and the pixel select transistor to respond to and output the potential of the floating diffusion region, the pixel select transistor being connected to the source follower transistor and the pixel circuit bit line, the pixel select readout being effected in response to the pixel select control signal and output it to the readout column.

With the progress of semiconductor process nodes, the wafer packaging technology is rapidly advancing. Especially, the CMOS image sensor applied to the camera of the consumer electronic product such as the mobile phone/tablet has higher and higher requirements on the packaging technology, the CMOS image sensor currently mainly applied to the camera of the consumer electronic product such as the mobile phone/tablet generally adopts the pure knife cutting technology, the laser (l aser) cutting of the main flow is not iterated with the technology until that, the l aser cutting is accompanied with high temperature, the melt of silicon is easy to be generated, the melt is easy to peel off in the service life cycle of the product or the product falling process, the high probability can fall in the imaging area of the CMOS image sensor, the normal work of the CMOS image sensor chip is interfered, and the problem is that the terminal customer can see the problem, and the customer complaint is extremely easy to be caused.

However, the pure knife cutting the cutting location does not produce a melt of silicon, and such problems can be avoided. The silicon chip is easy to peel off when the pure knife is used for cutting, if special design is not carried out on the cutting channel, unacceptable yield loss can be generated when the pure knife is used for cutting, the problems that the existing image sensor chip is damaged in the cutting process and the like are difficult to effectively solve, and the semiconductor device structure can effectively solve the problems.

Embodiment one:

referring to fig. 3 and 4, the present embodiment provides a semiconductor device structure 100, which is suitable for an image sensor, and includes: a semiconductor substrate W1, the semiconductor substrate W1 including a plurality of chip regions 101a, 101b, 101c, 101d and dicing regions 102a, 102b located at the periphery of the chip regions; the semiconductor device structure 100 of the present embodiment is described below by taking the chip region 101b and the dicing region 102a as an example:

in this embodiment, the dicing area 102a includes the interfacial barrier dicing areas 1022, 1023, and the interfacial barrier dicing area 1022 is taken as an example for illustration, it can be understood that the interfacial barrier dicing area 1023 is further between the dicing area 102a and the chip area 100a adjacent to the other side, and in addition, the chip area 101b includes the auxiliary dicing area 1012; wherein the auxiliary cutting area 1012 is disposed adjacent to the cutting area 102a, and the cutting outer edge corresponds to the interfacial barrier cutting area 1022 and has a space with the auxiliary cutting area 1012. In this embodiment, the cutting edge may be an edge of the first cutting tool 201, such as an edge of a cutting blade, as shown in fig. 4, with a right edge of the cutting edge corresponding to the interface barrier cutting region 1022 and a space between the right edge of the cutting edge and the auxiliary cutting region 1012 during cutting. Through the design, the area cut by the cutting outer edge can fall on the interface blocking cutting area 1022 and has a certain distance from the chip area 101b, so that the influence of the extension of the cutting crack formed in the cutting process on the chip area 101b can be relieved based on the interface blocking cutting area 1022 and the auxiliary cutting area 1012, and the influence of the cutting outer edge on the chip area 101b when falling on other areas of the cutting area 102a can be relieved by the interface blocking cutting area 1022. For example, in one implementation, the interfacial barrier cut region 1023 and the auxiliary cut region 1012 may each be selected as a single layer of material, and further, may be selected as a material composition that is easily cut relative to other materials of the cut region, such as silicon oxide, or as a material that is selected to form a relatively weak interface stress effect even if an interface is present. It will be appreciated by those skilled in the art that other material layers that are necessary or necessary to form in the preparation of the existing image sensor may also be present in the corresponding region, and are not strictly limited to only one material, as long as the crack formation and stress propagation that relieve the peripheral functions proposed by the present application can be solved.

Referring to fig. 4, 10 and 11, in one embodiment, the dicing area 102a further includes a peripheral functional area 1021, and the interface blocking dicing area 1022 is located between the peripheral functional area 1021 and the chip area 101b, wherein the peripheral functional area 1021 includes a first material structure and a second material structure with different materials, and an interface is formed between the two material structures, for example, the first material structure may be a metal material structure, such as Gu, W, etc., and the second material structure may be an insulating dielectric material structure, such as silicon oxide, etc.

In this embodiment, the interface barrier cut region 1022 may be designed to include a layer of crack mitigating material, or the auxiliary cut region 1012 may be designed to include a layer of crack mitigating material, or both, wherein the material of the crack mitigating material layer includes, but is not limited to, silicon oxide. In addition, the interfaces of the crack relieving material layer, the first material structure and the second material structure are located in the same structural layer, and it is understood that the crack relieving material layer and the first material structure are located in the same depth interval, and the crack relieving material layer covers the interfaces in a side view. Based on the design, in the cutting process, the cutting edge falls into the crack relieving material layer area, so that the interface of different material structures is prevented from being cut, the interface easy to tear is prevented from being torn, the stress in the tearing process is further prevented from extending to the chip area, the crack diffusion is prevented, and the protection of the chip core area in the chip area is facilitated. The crack relieving material layer may be a single material structure layer, or may be a structure layer comprising multiple materials, where the interface formed by the multiple material structure layers is not easy to crack or has relatively weak stress.

With continued reference to fig. 4, 10, and 11, the peripheral functional region 102a includes a plurality of chip detecting structures 301a and 301b, wherein a first buffer region 302 is disposed between the chip detecting structure 301b and the adjacent interface blocking and cutting region 1022, and it can be appreciated that the other side may be further provided with a first buffer region 303; alternatively, a second buffer 304 is provided between adjacent chip detection structures 301a, 301b in the direction in which the chip region 101b and the dicing region 102a are arranged; alternatively, the peripheral function region 102a may be provided with a first buffer region and a second buffer region, where each buffer region is configured to facilitate further implementation of the cutting stress buffering. In this example, the plurality of chip detection structures 301a, 301b may be understood as a first material structure in the above example, and the surrounding insulating dielectric material layer may be understood as a corresponding second material structure, and the crack mitigating material layer may utilize the surrounding insulating dielectric material layer, and may not include a metal material, to mitigate crack formation and propagation.

In a further example, a plurality of chip-test structures form at least one test structure strip 305, 306, the plurality of chip-test structures forming a chip-test structure zone 300, wherein a first buffer zone 302 is located between the test structure strip 306 and an adjacent interface barrier cut zone 1022; when the number of the detection structural bands is at least two, such as detection structural bands 305 and 306, and the second buffer region 304 is located between adjacent detection structural bands 305 and 306, in this embodiment, different sides of the cutting outer edge may each correspond to the interface blocking cutting regions 1022 and 1023, or different sides of the cutting outer edge may respectively correspond to the interface blocking cutting region 1022 and the second buffer region 304, at this time, the second buffer region 304 serves as the interface blocking cutting region 1022, that is, may cut based on the second buffer region 304, the cutting outer edge may fall on the second buffer region 304, and no interface of different material structures is cut during the cutting process, or the stress is weaker, so that the same effect as the effect of relieving the stress when cutting in the foregoing example may be achieved. Of course, in other embodiments, when two second buffers 304 are present, the edges of the cutting blade may fall in the area of the second buffers 304. According to the design, the cutting tool can be correspondingly configured according to the actual size, and the odd number of the detection structure belts can be correspondingly cut by the middle belt.

Specifically, the chip test structures 301a and 301b may be test structures (test keys) disposed in the scribe line region for chip test, but may also be other process monitor structures mark, pads for process measurement and electrical connection, and so on. The first buffer areas 302, 303 and the second buffer area 304 may be areas formed by dielectric materials (such as silicon oxide) commonly used in the fabrication of the wiring structure of the image sensor. In this embodiment, the cutting edge of the cutting tool falls on the interface blocking cutting areas 1022 and 1023 or falls on the second buffer area 304, so that the edge of the cutting knife is not in contact with the interface formed by different materials, and cutting in a single material layer is beneficial to alleviating the phenomenon that the edge of the cutting knife is easy to crack when falling on the interface of different materials.

Referring to fig. 4, in one embodiment, a semiconductor substrate W1 includes a stacked semiconductor substrate a and an interconnect structure layer M, a chip region 101b includes a chip body region 1011, an auxiliary dicing region 1012 is located between the chip body region 1011 and the dicing region 102a, and the interconnect structure layer M includes a first clearance area K1 corresponding to the interface blocking dicing region 1022 and/or a second clearance area K2 corresponding to the auxiliary dicing region 1012.

Specifically, the semiconductor device structure 100 may be a structure that is prepared on a wafer correspondingly in the preparation process of the image sensor, may be a structure that has not been cut after the device is prepared, and the semiconductor substrate a may be any structure used for preparing each functional area of the image sensor in the field of the image sensor. In addition, the interconnect structure layer M may be an interconnect structure layer of a device fabricated on the semiconductor substrate a, and may include a metal interconnect structure and an insulating dielectric material layer to achieve electrical connection between devices of the image sensor.

For example, a photosensitive element, individual control transistors, wirings, and the like of a CMOS image sensor are prepared based on a semiconductor substrate. The semiconductor substrate may be a structure formed by a single-layer material layer, including but not limited to a silicon substrate, in which elements in each region are prepared, and may be single crystal silicon, single crystal germanium, polycrystalline silicon, amorphous silicon, a silicon germanium compound, or the like. In addition, the semiconductor substrate can also be a laminated structure formed by two or more material layers, and each region is prepared in any required layer. For example, a semiconductor substrate including a silicon substrate and an epitaxial layer (EP I) formed on the silicon substrate, in which a photoelectric conversion element, a transistor element (including a charge transfer element, for example) and the like are prepared, a back-illuminated image sensor can be prepared based on the above-described structure. In addition, the semiconductor substrate may be silicon on insulator SO I. In addition, the semiconductor substrate can be a region with N-type doping or P-type doping so as to meet the functional requirement of the device.

In this embodiment, the interconnect structure layer M includes a first clearance area K1 corresponding to the interface barrier cut region 1022, or the interconnect structure layer M includes a second clearance area K2 corresponding to the auxiliary cut region 1012, or the interconnect structure layer M includes the first clearance area K1 and the second clearance area K2, it is understood that the first clearance area K1 and the second clearance area K2 may be a part of the interconnect structure layer M, such as formed by a dielectric layer thereof, to form a crack mitigating material layer for mitigating the occurrence and propagation of a cutting crack. The propagation of cracks in the horizontally corresponding structural layer can be prevented based on the first and second clearance areas K1 and K2. In addition, for the interconnect structure layer M, the corresponding interfacial barrier cutting area 1022 is the first clearance area K1, and the layer may further include the corresponding first buffer area and second buffer area, and may be formed by the dielectric layer thereof.

With continued reference to fig. 4, the interconnect structure layer M further includes a dummy wiring region 1014 corresponding to the auxiliary cutting region 1012, the second clearance region 1013 is adjacent between the cutting region 102a and the dummy wiring region 1014, the dummy wiring region 1014 includes at least one of a wiring buffer structure region 1015 and a guard ring structure region 1016, and when both are present, the wiring buffer structure region 1015 is disposed close to the second clearance region 1013. Based on the above design, the relief of the dicing crack can be further realized by the second clearance area K2, and the blocking of the crack propagation can be facilitated by the wiring buffer structure region 1015 and the guard ring structure region 1016 provided.

Specifically, with reference to the description of the foregoing embodiment, for the interconnect structure layer M, the corresponding auxiliary cutting region 1012 may sequentially include a corresponding second clearance region 1013 (a region indicated by K2 in the layer), a wiring buffer structure region 1015, and a guard ring structure region 1016, where the second clearance region 1013 may be formed by a dielectric layer of the interconnect structure layer M, the wiring buffer structure region 1015 may be a virtual metal structure, and the guard ring structure region 1016 may be a guard ring (sealing ring) made of a metal structure.

As an example, the width K1 of the first clearance area is 4 μm or more, for example, may be 5 μm, 6 μm; the width K2 of the second clearance area 1013 is 3 μm or more, for example, may be 3.5 μm or 4.5 μm; as an example, the sum of the widths of the wiring buffer structure region 1015 and the second clearance region 1013 is 15 μm or more, for example, 18 μm, 20 μm, 22 μm may be used. As an example, a distance between the cut outer edge closest to the chip body region 1011 and the guard ring structure region 1016 on the near side is 20 μm or more. For example, 21 μm, 22 μm, 25 μm. The above dimensions may be set according to the actual chip size and requirements.

With continued reference to fig. 4, in one embodiment, guard ring structure region 1016 includes a plurality of guard ring structures disposed annularly about the periphery of chip body region 1011. The periphery of the chip body region 1011 may be provided with a ring-shaped guard ring structure, or may be provided with a plurality of ring-shaped guard ring structures, which are shown as 3 ring-shaped guard ring structures in fig. 4, and the single guard ring structure may be a closed ring structure or may be a ring structure surrounded by a plurality of spaced guard rings.

In one embodiment, the wiring buffer structure region 1015 includes a plurality of wiring buffer structures forming a number of buffer structure rows and/or buffer structure columns at the periphery of the chip body region 1011. The wiring buffer structure may be a metal block, and the plurality of metal blocks are arranged in an array according to rows and columns.

With continued reference to fig. 4, the semiconductor substrate a includes a virtual active region 1017 corresponding to the auxiliary cutting region 1012, the virtual active region 1017 being located between the cutting region 102a and the chip body region 1011, and the virtual active region 1017 corresponding to at least the second clearance region 1013. It is understood that the dummy active region 1017 is located in a semiconductor substrate where the core imaging device of the actual image sensor is not prepared, for example, a pixel circuit device of the image sensor such as a photoelectric conversion element, a charge transfer element, a floating diffusion active region, a signal output transistor, etc. is prepared in the semiconductor substrate horizontally on the same layer as the region and corresponding to the position of the chip main body region 1011, whereas an active region corresponding to the dummy active region 1017 may not be prepared.

With continued reference to fig. 4, in one embodiment, the virtual active area 1017 includes a headroom release area 1018 and an evaluation buffer notch area 1020, the headroom release area 1018 being disposed adjacent to the dicing area 102a and corresponding to the second headroom area 1013, the evaluation buffer notch area 1020 being disposed adjacent to the die body area 1011. The headroom releasing region 1018 may be an active region belonging to the layer in the semiconductor substrate, that is, may be a P-type silicon substrate, and the headroom releasing region 1018 of the virtual active region AA may be beneficial to defining an edge of the chip di e; the evaluation buffer pocket 1020 may be a trench structure fabricated by a back side process of a semiconductor substrate.

In a further example, a virtual device transition region 1019 is further provided between the headroom relief region 1018 and the evaluation buffer slot region 1020, the virtual device transition region 1019 covering the boundary of the second headroom region 1013 and the virtual wiring region 1014 when they are contiguous. The dummy device transition region 1019 may be based on an active region of the semiconductor substrate that belongs to the layer, may be provided with the isolation structure 105, and in other examples may be provided with the dummy device 106, etc.

Referring to fig. 4 and fig. 5-9, in one embodiment, an evaluation buffer area 1020 is provided with an evaluation buffer 1021, and a spacer structure layer is provided between the bottom of the evaluation buffer 1021 and the wiring buffer 1015. The evaluation buffer slot 1021 may be a trench structure prepared by a back surface process of a semiconductor substrate, however, in other embodiments, other materials including but not limited to silicon oxide may be filled in the evaluation buffer slot 1021, so that stress may be relieved, and in addition, the spacer structure layer includes but not limited to a silicon oxide layer. The evaluation buffer 1021 may be used to stop the silicon peeling, and secondly, the evaluation buffer 1021 may be used to evaluate whether the silicon peeling will cause failure, the silicon peeling degree is slightly and severely divided, and the silicon peeling is not more than the circle of grooves and can be regarded as good products, and the silicon peeling is not more than the circle of grooves and can be regarded as invalid products.

As an example, referring to fig. 5-7, the spacer structure layer is a single spacer structure 103, and the bottom of the evaluation buffer 1021 reveals the single spacer structure 103. As another example, referring to fig. 8 and 9, the spacer structure layer is a plurality of spacer blocks 104 arranged in an array, and the bottom of the evaluation buffer 1021 exposes the spacer blocks 104. The single spacer structure 103 and the spacer block 104 may be both manufactured together in the process of manufacturing the device isolation structure by the chip body region 1011, for example, may be manufactured by a shallow trench isolation structure ST I process based on an image sensor, and the materials include, but are not limited to, silicon oxide, so that the process can be simplified. The formation of the spacer structure layer is also beneficial to realizing the compatibility of the preparation and opening process of the evaluation buffer slot 1021 and the bonding pad (pad) of the device, and the evaluation buffer slot 1021 and the bonding pad opening can be simultaneously formed based on the same process, and the bonding pad opening can be a TSV hole exposing a metal layer (such as a first metal layer) to prevent over etching of a bonding pad area.

With continued reference to fig. 4 and fig. 5-9, in one embodiment, the dummy device transition region 1019 is provided with a trench isolation structure 105, where the trench isolation structure 105 includes a plurality of sub-isolation structures arranged in an array, as shown in fig. 7 and fig. 9, or has a hollowed-out single trench isolation structure, as shown in fig. 6, and in this embodiment, it is preferably designed to have a hollowed-out single trench isolation structure, and the hollowed-out space region is the active area AA of the square. The single trench isolation structure with the hollowed-out structure and the plurality of sub isolation structures can be prepared together in the process of preparing the device isolation structure by the chip main body region 1011, for example, the shallow trench isolation structure ST I based on an image sensor can be prepared by a process, and materials include but are not limited to silicon oxide, so that the process can be simplified.

Referring to fig. 4, 10 and 12, the included angles between the line center lines of the wiring buffer structures 1015a of each line and the cutting lines are set in an acute trend, and the included angles between the column center lines of the wiring buffer structures of each column and the cutting lines are set in an acute trend; the wiring buffer structure 1015a is disposed obliquely along the cutting line, which is advantageous for realizing buffering of cutting stress. It should be noted that the acute angle trend here may be a regular acute angle, or may be an acute angle formed by a loose ray, and the aim is to relieve the stress of the knife cutting by the trend design. The cutting line here refers to a line corresponding to a trace horizontally struck by the cutter.

Referring to fig. 4, 11 and 13, the included angles between the line center lines of the trench isolation structures of each line and the cutting lines are set in an acute trend, and the included angles between the column center lines of the trench isolation structures of each column and the cutting lines are set in an acute trend; the trench isolation structure is obliquely arranged along the cutting line, so that the buffer of cutting stress is realized. It should be noted that, herein, the line center line of the trench isolation structure may be understood as a center line formed by the center of each sub-isolation structure when the trench isolation structure includes a plurality of sub-isolation structures arranged in an array, and at this time, a virtual active area structure, a virtual device (such as including a virtual polysilicon structure) and the like may be formed between each sub-isolation structure; in addition, when the trench isolation structure 105 is a single trench isolation structure with a hollow out, the line center line of the trench isolation structure may be understood as a center line formed by the hollow out centers of each array arrangement, and at this time, each hollow out area may be formed with a virtual active area structure, a virtual device, or the like, or may not be formed with other devices, and may be formed only with an active area material based on a semiconductor substrate.

Further, referring to fig. 4 and fig. 10-13, the wiring buffer structures are arranged vertically in at least two layers, and a space is provided between centers of the wiring buffer structures at corresponding positions of adjacent layers. In this example, in two structure layers corresponding up and down, the up and down centers are not corresponding, for example, in the second layer of wiring buffer structure, the center of a certain wiring buffer structure (such as a metal block) is in the vertical direction, and the projections of the first layer of wiring buffer structure layer and the third layer of wiring buffer structure layer are not coincident with the centers of the wiring buffer structures, for example, the projections may fall in a space region (such as formed by an insulating medium material) surrounded by adjacent wiring buffer structures.

Referring to fig. 4, in one embodiment, the semiconductor device structure further includes at least one stacking substrate W2 stacked with the semiconductor substrate W1, and each region of the stacking substrate W2 is disposed vertically corresponding to each region of the semiconductor substrate W1. It should be noted that this embodiment provides a stack (stack) structure of an image sensor, in which at least the photosensitive element is fabricated on the first wafer (the semiconductor substrate W1), and at least the peripheral circuit, such as the analog-to-digital conversion circuit ADC, is fabricated on the second wafer (the stack substrate W2), and of course, the device distribution in the specific image sensor may be selected according to the actual implementation. Of course, in other embodiments, three or more wafers may be included to complete the image sensor fabrication by stacking.

With continued reference to fig. 4, in one embodiment, the peripheral functional region 1021 of the semiconductor substrate W1 and the peripheral functional region of the stacked substrate W2 are electrically connected by an interlayer interconnection structure, and the same structural layer of the interlayer interconnection structure corresponds to the auxiliary cutting region 1012 and the interfacial barrier cutting region 1022. In this embodiment, the auxiliary cutting region 1012 and the interfacial barrier cutting region 1022 extend in two substrates, for example, it may be understood that the same material of the region corresponding to the upper and lower two substrates extends at the interface where the two substrates are bonded, so that the crack propagation formed at the bonding interface of the two substrates during the cutting process may be further alleviated based on the interface formed by the same material layer corresponding to the different material structure in the overlying inter-layer interconnect structure in the lateral direction.

Embodiment two:

the present utility model also provides an image sensor including a chip region, the chip region of the image sensor of this embodiment being cut along the cutting region 102a based on the semiconductor device structure as described in any one of the above embodiments. That is, the chip area of the image sensor of this embodiment includes a chip body region 1011.

The utility model also provides electronic equipment comprising the image sensor according to any one of the schemes. The image sensor can be a CMOS image sensor, the electronic equipment can be security monitoring equipment, vehicle-mounted electronic equipment, a mobile phone camera, machine vision equipment and the like, and the image sensor can acquire high-quality image information.

Embodiment III:

referring to fig. 3, fig. 4, fig. 14 and fig. 15, the present embodiment further provides a method for manufacturing an image sensor according to any one of the above schemes, including:

s1: providing a semiconductor device structure, as shown in fig. 4;

s2: performing a first cut along the cut outer edge to obtain an intermediate cut structure, as shown in fig. 13;

s3: the second dicing is performed on the intermediate dicing structure corresponding to the dicing area 102a, resulting in separated individual chip areas 101b, and the width of the dicing blade 202 for the second dicing is smaller than the width of the dicing blade 201 for the first dicing.

Specifically, in this embodiment, the obtaining of the chip area is achieved by adopting the two-time cutting manner, and the formation of the cutting crack and the influence on the chip can be further reduced based on the use of the second cutting blade with smaller width. Of course, in other embodiments, since the embodiment of the present application has been effectively improved in a pair of semiconductor device structures, the formation and the influence of the dicing crack can be effectively alleviated by using a single dicing method.

With continued reference to fig. 15, the dicing bottom of the first dicing extends beyond the depth of the peripheral functional region of the semiconductor device structure in the dicing direction.

Specifically, in this embodiment, in the first dicing process, the dicing depth of the dicing blade exceeds the depth of the peripheral functional region, for example, the dicing blade may exceed the depth of the underlying interconnect structure layer M, and in the structure having the stacked substrate W2 and the semiconductor substrate W1 which are stacked, the dicing blade may extend from the semiconductor substrate W1 to the stacked substrate W2, and further, the dicing blade may extend beyond the interconnect structure layer of the stacked substrate W2, and the problem of dicing crack may be solved based on the configuration of the semiconductor device in the present utility model.

In one embodiment, the cutting areas 102a, 102b may be provided with a width D between 100 μm and 200 μm, for example 120 μm, 150 μm, 180 μm, and in addition the first cutting tool 201 may have a width between 105 μm and 120 μm, for example 110 μm, 115 μm; the width of the second cutting tool 202 is between 80 μm and 100 μm, such as 85 μm, 90 μm.

In summary, the semiconductor device structure, the image sensor, the preparation method and the electronic device of the utility model can effectively relieve the influence on the chip area in the cutting process based on the configuration design of each region on the semiconductor device structure, are beneficial to preventing the generation of cracks (chipping) in the cutting process, and are also beneficial to preventing interface cracks and direct tearing of the substrate. The size of the cutting tool can be flexibly configured, the influence of the cutting process on the chip can be further relieved based on the combined configuration of the cutting tool, and the imaging quality is improved. Therefore, the utility model effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present utility model and its effectiveness, and are not intended to limit the utility model. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the utility model. Accordingly, it is intended that all equivalent modifications and variations of the utility model be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims

1. A semiconductor device structure adapted for use in an image sensor, comprising:

2. The semiconductor device structure of claim 1, wherein the dicing region further comprises a peripheral functional region, the interfacial barrier dicing region is located between the peripheral functional region and the chip region, the peripheral functional region comprises a first material structure and a second material structure of different materials, and the interfacial barrier dicing region and/or the auxiliary dicing region comprises a crack mitigating material layer at the same structural layer as the interface of the two.

3. The semiconductor device structure of claim 2, wherein the peripheral functional region comprises a plurality of chip detection structures, a first buffer region being disposed between the chip detection structures and the interface barrier cut region on an adjacent side; and/or, in the direction along which the chip area and the cutting area are arranged, a second buffer area is arranged between the adjacent chip detection structures; and/or the first material structure is metal, the second material structure is interlayer dielectric, and the crack mitigating material layer is interlayer dielectric.

4. The semiconductor device structure of claim 3, wherein the plurality of chip test structures form at least one test structure strip, the first buffer region being located between the test structure strip and the adjacent interface barrier cut region; when the number of the detection structure belts is at least two, the second buffer areas are positioned between the adjacent detection structure belts, and different sides of the cutting outer edge are corresponding to the interface blocking cutting areas or the interface blocking cutting areas and the second buffer areas respectively.

5. The semiconductor device structure of claim 1, wherein the semiconductor base comprises a stacked semiconductor substrate and an interconnect structure layer, the chip region comprises a chip body region, the auxiliary dicing region is located between the chip body region and the dicing region, and the interconnect structure layer comprises a first clearance region corresponding to the interface-blocking dicing region and/or a second clearance region corresponding to the auxiliary dicing region.

6. The semiconductor device structure of claim 5, wherein the interconnect structure layer further comprises a dummy wire region corresponding to the auxiliary scribe line region, the second headroom region being adjacent between the scribe line region and the dummy wire region, the dummy wire region comprising at least one of a wire buffer structure region and a guard ring structure region, the wire buffer structure region being disposed proximate the second headroom region when both are present.

7. The semiconductor device structure of claim 6, wherein the guard ring structure region comprises a plurality of guard ring structures disposed annularly about the periphery of the chip body region; and/or the wiring buffer structure region comprises a plurality of wiring buffer structures, and the plurality of wiring buffer structures form a plurality of buffer structure rows and/or buffer structure columns at the periphery of the chip main body region; and/or the width of the first clearance area is greater than or equal to 4 μm; the width of the second clearance area is more than or equal to 3 mu m; the sum of the widths of the wiring buffer structure region and the second clearance region is greater than or equal to 18 μm; the distance between the cut outer edge and the guard ring structure region near the side is 20 μm or more.

8. The semiconductor device structure of claim 5, wherein the semiconductor substrate includes a virtual active region corresponding to the auxiliary dicing region, the virtual active region being located between the dicing region and the chip body region, and the virtual active region corresponding to at least the second headroom region.

9. The semiconductor device structure of claim 8, wherein the dummy active region comprises a headroom relief region disposed adjacent to the dicing region and corresponding to the second headroom region, and an evaluation buffer tub region disposed adjacent to the die body region.

10. The semiconductor device structure of claim 9, wherein a virtual device transition region is further provided between the headroom relief region and the evaluation buffer tub region, the virtual device transition region covering a boundary of the second headroom region and the virtual wire region when there is an adjoining therebetween; and/or the evaluation buffer slot area is provided with an evaluation buffer slot, and when a virtual wiring area exists and comprises a wiring buffer structure area, a spacing structure layer is arranged between the bottom of the evaluation buffer slot and the wiring buffer structure area.

11. The semiconductor device structure of claim 10, wherein the dummy device transition region is provided with a trench isolation structure comprising a plurality of sub-isolation structures arranged in an array or a single trench isolation structure with a hollowed-out shape; and/or the interval structure layer comprises a single interval structure or a plurality of interval blocks arranged in an array, and the interval structure or the interval blocks are exposed at the bottom of the evaluation buffer groove.

12. The semiconductor device structure of claim 11, wherein a line center line of the wiring buffer structure of each line is disposed at an acute angle with respect to a dicing line; and/or the included angle between the line central line of the groove isolation structure of each line and the cutting line is in an acute angle trend, and the included angle between the column central line of the groove isolation structure of each column and the cutting line is in an acute angle trend; and/or the wiring buffer structures are vertically arranged in at least two layers, and a space is reserved between the centers of the wiring buffer structures at the corresponding positions of the adjacent layers.

13. The semiconductor device structure of any of claims 1-12, further comprising at least one stacking base disposed in a stack with the semiconductor base, each region of the stacking base being disposed in a top-to-bottom correspondence with each region of the semiconductor base.

14. The semiconductor device structure of claim 13, wherein the peripheral functional region of the semiconductor substrate and the peripheral functional region of the stacked substrate are electrically connected by an interlayer interconnect structure, and the same structural layer of the interlayer interconnect structure corresponds to the auxiliary dicing region and the interfacial barrier dicing region.

15. An image sensor comprising a chip region cut along the dicing region based on the semiconductor device structure according to any one of claims 1 to 14.