CN217385736U - MCU's ATE equipment and system thereof - Google Patents
MCU's ATE equipment and system thereof Download PDFInfo
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- CN217385736U CN217385736U CN202220986383.4U CN202220986383U CN217385736U CN 217385736 U CN217385736 U CN 217385736U CN 202220986383 U CN202220986383 U CN 202220986383U CN 217385736 U CN217385736 U CN 217385736U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The utility model discloses ATE equipment of an MCU. The ATE equipment is used for testing a chip to be tested and comprises a power management module, a testing machine table, a communication module and a testing board. The testing board comprises a main control board, and the chip to be tested is arranged on the main control board for testing. The power management module is connected with the testing machine table and the testing board and used for providing corresponding power sources, excitation signals and voltages. The communication module is arranged between the testing machine table and the testing board, and data exchange is carried out between the testing machine table and the testing board through the communication module. The utility model further discloses an ATE system of the MCU of the ATE equipment comprising the MCU. According to the ATE equipment and the ATE system, the chip detection efficiency can be improved, and the detection cost can be reduced.
Description
Technical Field
The utility model relates to a chip test equipment, concretely relates to MCU's ATE equipment and system thereof.
Background
The MCU chip is an aggregate including a plurality of chips, and when a user tests such chips, each component thereof needs to be tested to achieve an expected effect, i.e., different test programs need to be used to test the corresponding component. ATE (Automatic Test Equipment) is an aggregate of high-performance computer-controlled Test instruments, which are combined with computers. Typically, a computer tests a chip by running instructions of a test program. Semiconductor chip test equipment is an important device for testing the integrity of the function and performance of an integrated circuit and ensuring the quality of the integrated circuit in the production and manufacturing process of the integrated circuit. The most basic requirements of the ATE equipment of the MCU are to ensure the rapidity, reliability and stability of the test function. In addition, in the chip testing process, the testing universality is very important, and when different types of chips are tested, the flow needs to be changed every time when one chip is tested, only one chip can be tested at a time, the testing efficiency is low, and the universality is not high.
SUMMERY OF THE UTILITY MODEL
According to the utility model discloses an aspect provides a MCU's ATE equipment for test the chip that awaits measuring, include: the device comprises a power management module, a test machine, a communication module and a test board; the test board comprises a main control board, and the chip to be tested is arranged on the main control board for testing; the power management module is connected with the test board and used for providing corresponding power, excitation signals and voltage; the communication module is arranged between the test machine platform and the test board, and the test machine platform and the test board carry out data communication through the communication module. This ATE equipment can improve the efficiency that the chip detected, reduces and detects the cost.
The utility model discloses an on the other hand, communication module includes serial ports communication interface, the test board sets up sends the TX pin and receives the RX pin, send the TX pin and receive the RX pin and be connected with the receipt RX pin, the transmission TX pin of the chip that awaits measuring respectively.
The utility model discloses an on the other hand, serial ports communication interface is the UART mouth.
The utility model discloses an on the other hand, communication module includes and mouthful communicates interface, be equipped with a plurality of chips that await measuring on the main control board, the main control board passes through and mouthful communicates interface is right a plurality of chips that await measuring carry out independent test. The arrangement of the parallel port communication interface can make the ATE device compatible with various types of general MCUs on the market and can simultaneously test a plurality of chips.
The utility model discloses an on the other hand, parallel port communication interface is the GPIO mouth.
The utility model discloses an on the other hand, the test board includes the computer.
The utility model discloses an on the other hand, be provided with the socket seat on the main control board, the chip that awaits measuring is placed on the socket seat, through the socket seat with the main control board electricity is connected.
The utility model discloses an on the other hand still provides a MCU's ATE system, including as above MCU's ATE equipment and detecting element.
The utility model discloses an on the other hand, MCU's ATE system still includes detecting element, detecting element connects between main control board and the chip that awaits measuring for detect the consumption of the chip that awaits measuring.
The utility model discloses an on the other hand, detecting element is handheld universal meter.
Drawings
Fig. 1 is a schematic diagram of an embodiment of an ATE apparatus of an MCU according to the present invention;
FIG. 2 is a schematic diagram of another embodiment of the ATE device of the MCU for data transmission;
FIG. 3 is a schematic diagram illustrating the operation of another embodiment of the ATE device with the MCU;
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
Implementation mode one
Fig. 1 schematically shows an ATE device of an MCU according to an embodiment of the present invention. As shown in fig. 1, the ATE device of the MCU may be a power consumption testing device of a general-purpose chip, and the chip may be an MCU (micro control unit). Specifically, the ATE device of the MCU includes a power management module 1, a tester table 2, a communication module 3, and a test board 4. The test board 4 includes a main control board 5, and the main control board 5 is a circuit board for embedded system development, and includes a series of hardware components such as a central processing unit, a memory, an input device, an output device, a data path/bus, and an external resource interface. The chip 6 to be tested is installed on the main control board 5 for detection, and the chip 6 to be tested is electrically connected with the main control board 5. Specifically, a socket seat may be disposed on the main control board 5, and the chip 6 to be tested is placed on the socket seat, that is, the chip 6 to be tested is electrically connected to the main control board 5 through the socket seat. The test machine 2 comprises an upper computer for controlling the test of the chip; the upper computer can be a computer which directly sends out a control command; the communication module 3 is disposed between the test board 2 and the test board 4, and is configured to perform data communication with the chip 6 to be tested, such as sending a test program to the chip 6 to be tested, or receiving test data returned by the chip 6 to be tested. The power management module 1 is connected with the test board 2 and the test board 4, supplies power to the test board 2, the main control board 5 and the chip 6 to be tested, and provides power, excitation signals and voltage for the MCU ATE equipment.
When the chip is tested, the upper computer sends test data, test programs and the like to the chip 6 to be tested on the main control board 5 through the communication module 3. And the chip 6 to be tested obtains test result data after running the test program, and the test result data is returned to the test machine through the communication module 3 to complete the chip test.
Second embodiment
As shown in fig. 2, the communication module 3 includes a serial communication interface. Specifically, the tester 2 communicates with the chip 6 through the UART port. The test machine 2 and the chip 6 to be tested are respectively provided with independent sending TX and receiving RX pins, the sending TX pin of the test machine 2 is connected with the receiving RX pin of the chip 6 to be tested, and the receiving RX pin of the test machine 2 is connected with the sending TX pin of the chip 6 to be tested. The test machine 2 is a communication initiator, the test machine 2 sends an instruction, the instruction is sent to the receiving RX pin of the chip 6 to be tested through the sending TX pin of the test machine 2, after the chip 6 to be tested receives the instruction, the test machine 2 is responded and a test command is executed, and a test result is sent to the receiving RX pin of the test machine 2 through the sending TX pin of the chip 6 to be tested to be received. The serial port communication interface has high compatibility and can cover various serial chip products.
Third embodiment
The communication module 3 includes a parallel port communication interface, such as a GPIO parallel port interface. The main control board 5 can be provided with a plurality of chips, and the main control board 5 can control the plurality of chips to perform function test and obtain a test result through the GPIO parallel port. Software of the upper computer controls the main control board 5 to obtain function test results of the plurality of test chips under different environmental temperatures and different working voltages, and the main control board can independently test the plurality of chips. The main control board 5 can be compatible with the test of various types of general MCU in the market through GPIO parallel port interface, and can simultaneously test a plurality of chips.
Example IV
Fig. 3 is a schematic diagram of the working principle of an ATE system of the ATE device including the MCU, and as shown in fig. 3, the ATE system of the MCU further includes a detection unit, which may be a handheld multimeter 7 (e.g., a UT61D handheld multimeter) for testing the peripheral power consumption of the chip 6 to be tested.
The main control board 5 can be the singlechip (for example F407 singlechip), the main control board 5 is connected through serial ports 1 and the serial port instrument of computer and is carried out the transmission of instruction and data, the main control board 5 passes through serial ports 2 and to the chip 6 transmission instruction that awaits measuring, it provides reset signal to the RST reset pin of the chip 6 that awaits measuring through the GPIO port, the chip 6 that awaits measuring passes through the port and is connected with handheld universal meter 7, the data of handheld universal meter 7 change behind the TTL with transmit to the serial ports 3 of main control board 5 through RS 232. Therefore, the handheld multimeter can detect the port current of the chip to be detected.
The process of using the handheld multimeter to detect the peripheral power consumption of the chip to be detected comprises the following steps:
1) sending an automatic test instruction to a main control board through a serial port tool of a computer;
2) the main control board analyzes the command received by the serial port 1;
3) if the test command is an automatic test command, the main control board executes the following actions:
a) pulling down a GPIO port connected with a RST reset pin of the chip to be tested for 100ms to reset the chip to be tested;
b) sending a basic power consumption instruction to a chip to be tested through a serial port 2, enabling the chip to be tested to enter a sleep mode, and enabling all peripheral clocks of the chip to be tested to be in a closed state;
c) reading the current readings of the handheld multimeter at the moment through the serial port 3, recording the current readings as data 1, processing and storing the data 1, and taking the data 1 as basic power consumption;
d) repeating the step a;
e) sending a power consumption instruction for detecting a first peripheral to a chip to be detected through a serial port 2, enabling the chip to be detected to enter a sleep mode, and enabling the chip to be detected to have and only the peripheral to be in an open state;
f) reading the current indication of the multimeter at the moment through the serial port 3, recording the current indication as data 2, processing and storing the data 2, wherein the data 2 is the basic power consumption plus the power consumption of the first peripheral, so that the data 3 is data 2-data 1 to obtain the power consumption of the peripheral;
g) and (e) continuously repeating the steps a-f and testing the power consumption of the peripheral equipment, wherein the instruction address of the step e is automatically accumulated until the power consumption test instruction of the last peripheral equipment is completed.
4) The main control board outputs data to a serial port tool of the computer through the serial port 1 and displays the data in the computer.
The implementation mode can reduce errors of artificial subjective consciousness reading and accelerate the testing speed of peripheral power consumption.
Fifth embodiment
The ATE system of the MCU also comprises an automatic classifier and a jig matched with the automatic classifier. Testers need MCU-based ATE equipment to develop test programs, which typically include electrical connectivity tests, functional tests, parametric tests, and the like. The program will pass or fail according to the test result to carry out physical classification, that is, the passing and failing chips are separated into different containers by an automatic classifier and a jig thereof.
What has been described above are only some embodiments of the invention. For those skilled in the art, without departing from the inventive concept, several modifications and improvements can be made, which are within the scope of the invention.
Claims (10)
1. An ATE equipment of MCU, is used for testing the chip under test, includes: the device comprises a power management module, a test machine, a communication module and a test board; the test board comprises a main control board, and the chip to be tested is arranged on the main control board for testing; the power management module is connected with the test board and used for providing corresponding power, excitation signals and voltage; the method is characterized in that: the communication module is arranged between the test machine platform and the test board, and the test machine platform and the test board carry out data communication through the communication module.
2. The MCU ATE device of claim 1, wherein the communication module comprises a serial communication interface, and the tester is configured with a TX pin and an RX pin, which are connected to a RX pin and a TX pin of a chip under test, respectively.
3. The MCU ATE device of claim 2, wherein the serial communications interface is a UART port.
4. The MCU ATE device of claim 1, wherein the communication module comprises a parallel port communication interface, the main control board is provided with a plurality of chips to be tested, and the main control board independently tests the chips to be tested through the parallel port communication interface.
5. The MCU ATE device of claim 4, wherein the parallel port communication interface is a GPIO port.
6. The MCU ATE device of claim 1, wherein the tester bench comprises a computer.
7. The MCU ATE device of claim 1, wherein a socket is disposed on the main control board, and the to-be-tested chip is placed on the socket and electrically connected to the main control board through the socket.
8. An ATE system for an MCU, comprising: ATE device comprising an MCU as defined in any one of claims 1-7, and a detection unit.
9. The MCU ATE system of claim 8, wherein the detection unit is connected between the main control board and the chip under test for detecting power consumption of the chip under test.
10. The ATE system of MCUs of claim 9, wherein the detection unit is a handheld multimeter.
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CN202220986383.4U CN217385736U (en) | 2022-04-26 | 2022-04-26 | MCU's ATE equipment and system thereof |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN117250483A (en) * | 2023-11-17 | 2023-12-19 | 深圳市航顺芯片技术研发有限公司 | Chip test system and method |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN117250483A (en) * | 2023-11-17 | 2023-12-19 | 深圳市航顺芯片技术研发有限公司 | Chip test system and method |
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