CN214954954U - Hot plug protection circuit and board card - Google Patents
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- CN214954954U CN214954954U CN202120105754.9U CN202120105754U CN214954954U CN 214954954 U CN214954954 U CN 214954954U CN 202120105754 U CN202120105754 U CN 202120105754U CN 214954954 U CN214954954 U CN 214954954U
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Abstract
The utility model relates to the technical field of hot plug, and discloses a hot plug protection circuit and a board card, wherein the hot plug circuit comprises a first MOS (metal oxide semiconductor) tube and a second MOS tube; the source electrode of the first MOS tube is connected with a protected first IO, the grid electrode of the first MOS tube is connected with an enabling signal end, and the drain electrode of the first MOS tube is connected with the drain electrode of the second MOS tube; and the grid electrode of the second MOS tube is connected with the grid electrode of the first MOS tube, and the source electrode of the second MOS tube is connected with the second IO. The embodiment of the utility model provides a pair of hot plug protection circuit and integrated circuit board can prevent that the board from the electricity chronogenesis mistake when the hot plug IO.
Description
Technical Field
The utility model relates to a hot plug technical field especially relates to a hot plug protection circuit and integrated circuit board.
Background
To the frame equipment, each module integrated circuit board all need support the plug to change, requires electrified hot plug even, and at the plug in-process, to the interconnection IO between the module, there are the following influence in several respects mainly: the IO power-on sequence is wrong, and in a short time after the board card is inserted, because the system power supply of a new module cannot start working immediately, the chip system in the board is not supplied with power, but the external interconnection IO has voltage from other modules, so that the problem that the IO is powered on before the chip system is caused. Many chips require that IO cannot have level before the chip is powered on, otherwise the level can flow back to the chip to supply power, so that power-on sequence errors are caused, and even the IO of the chip is damaged.
In order to solve the above problem, the avoidance is basically performed by using a long/short pin + TVS (Transient Voltage Suppressor diode). The long pin and the short pin are used for making a GND pin of the connector longer than other signal pins, so that when the connector is inserted, the ground wire can be firstly connected, and when the connector is pulled out, the ground wire is finally separated, so that the level of systems on two sides is balanced before the signal wire is contacted, the condition that only the signal wire is connected is avoided, and the ESD and surge are prevented from impacting and damaging the IO.
By adopting the mode of the long and short pins and the TVS, although the improvement effect on ESD and surge impact caused by unbalanced system level or static accumulation of the board cards on two sides is remarkable, for some board cards with hot plug function and power supply slow start function, the design of the long and short pins can not effectively prevent the problem of power-on sequence error of IO.
SUMMERY OF THE UTILITY MODEL
The embodiment of the utility model provides a technical problem who solves is: the utility model provides a hot plug protection circuit and integrated circuit board prevents that the integrated circuit board from going up the electrical sequence mistake when hot plug IO.
In order to solve the above technical problem, in a first aspect, an embodiment of the present invention provides a hot plug protection circuit, including a first MOS transistor and a second MOS transistor; wherein,
the source electrode of the first MOS tube is connected with a protected first IO, the grid electrode of the first MOS tube is connected with an enabling signal end, and the drain electrode of the first MOS tube is connected with the drain electrode of the second MOS tube;
and the grid electrode of the second MOS tube is connected with the grid electrode of the first MOS tube, and the source electrode of the second MOS tube is connected with the second IO.
As a preferred scheme, the hot swap protection circuit further comprises a first diode; and the cathode of the first diode is connected with the second IO, and the anode of the first diode is grounded.
As a preferred scheme, the hot plug protection circuit further comprises a double diode clamping circuit; the first end of the double diode clamping circuit is connected with the second IO, the second end of the double diode clamping circuit is grounded, and the third end of the double diode clamping circuit is connected with a voltage source.
As a preferred scheme, the hot plug protection circuit further comprises a first voltage dependent resistor; one end of the first piezoresistor is connected with the second IO, and the other end of the first piezoresistor is grounded.
As a preferred scheme, the hot plug protection circuit further comprises a first resistor; the grid electrode of the first MOS tube is connected with the enabling signal end through the first resistor.
As a preferred scheme, the hot plug protection circuit further comprises a third MOS transistor, a fourth MOS transistor and a fifth MOS transistor; wherein,
the grid electrode of the third MOS tube is connected with the enabling signal end through the first resistor, the source electrode of the third MOS tube is grounded, and the drain electrode of the third MOS tube is connected with the grid electrode of the fifth MOS tube;
the grid electrode of the fourth MOS tube is connected with the drain electrode of the third MOS tube, the source electrode of the fourth MOS tube is connected with the first IO, and the drain electrode of the fourth MOS tube is connected with the drain electrode of the fifth MOS tube;
and the source electrode of the fifth MOS tube is connected with the second IO.
As a preferred scheme, the hot plug protection circuit further comprises a second resistor; and the drain electrode of the third MOS tube is connected with the second IO through the second resistor.
As a preferred scheme, the hot swap protection circuit further includes a third resistor, a second diode, and a third diode; wherein,
one end of the third resistor is connected with the drain electrode of the third MOS tube, and the other end of the third resistor is connected with the cathode of the second diode;
the anode of the second diode is connected with the first IO;
and the anode of the third diode is connected with the second IO, and the cathode of the third diode is connected with the other end of the third resistor.
As a preferred scheme, the first MOS transistor is an NMOS transistor, the second MOS transistor is an NMOS transistor, the third MOS transistor is an NMOS transistor, the fourth MOS transistor is a PMOS transistor, and the fifth MOS transistor is a PMOS transistor.
In order to solve the above technical problem, in a second aspect, an embodiment of the present invention provides a board card, where the board card includes a hot plug protection circuit as in any one of the first aspect.
Compared with the prior art, the utility model provides a pair of hot plug protection circuit and integrated circuit board, its beneficial effect lies in: the isolation of IO (first IO) in the board and IO (second IO) outside the board is realized through the MOS tube, so that the power-on sequence error of IO (input/output) of the board during hot plugging can be prevented; the method is suitable for IO power-on time sequence control of hot plug, can protect IO from being damaged by ESD, and avoids IO from powering on before the chip system; meanwhile, the method is also suitable for controlling the interconnection IO power-on time sequence of different chip systems in a board or between boards, can avoid the problems of IO power-on abnormity, steps, nonmonotony and the like caused by different chip systems due to different power-on time sequences, different power-on and power-off control and the like, and improves the reliability of the chip systems.
Drawings
In order to more clearly illustrate the technical features of the embodiments of the present invention, the drawings needed to be used in the embodiments of the present invention will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic circuit diagram of a first embodiment of a hot plug protection circuit according to the present invention;
fig. 2 is a circuit diagram illustrating a second embodiment of a hot plug protection circuit according to the present invention;
fig. 3 is a circuit diagram illustrating a third embodiment of a hot plug protection circuit according to the present invention;
fig. 4 is a schematic circuit diagram illustrating a fourth embodiment of a hot plug protection circuit according to the present invention;
fig. 5 is a schematic circuit diagram of a fifth embodiment of a hot plug protection circuit according to the present invention;
fig. 6 is a schematic circuit diagram illustrating a sixth embodiment of a hot plug protection circuit according to the present invention;
fig. 7 is a schematic diagram of a power-on timing sequence of a hot plug protection circuit according to the present invention.
Detailed Description
In order to clearly understand the technical features, objects, and effects of the present invention, the following detailed description of the embodiments of the present invention is provided with reference to the accompanying drawings and examples. The following examples are only for illustrating the present invention, but are not intended to limit the scope of the present invention. Based on the embodiment of the present invention, other embodiments obtained by those skilled in the art without creative efforts shall all belong to the protection scope of the present invention.
In the description of the present invention, it should be understood that the numbers themselves, such as "first", "second", etc., are used only for distinguishing the described objects, and do not have a sequential or technical meaning, and cannot be understood as defining or implying the importance of the described objects.
In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Fig. 1 is a schematic circuit diagram of a hot plug protection circuit according to a first embodiment of the present invention.
As shown in fig. 1, the hot swap protection circuit includes a first MOS transistor Q1 and a second MOS transistor Q2; wherein,
the source electrode of the first MOS transistor Q1 is connected with a protected first IO, the gate electrode of the first MOS transistor Q1 is connected with an enable signal end, and the drain electrode of the first MOS transistor Q1 is connected with the drain electrode of the second MOS transistor Q2;
the gate of the second MOS transistor Q2 is connected to the gate of the first MOS transistor Q1, and the source of the second MOS transistor Q2 is connected to the second IO.
Wherein, the utility model discloses a hot plug protection circuit plays the guard action when the integrated circuit board inserts or extracts the system (for example, the mainboard of computer) among being applied to the integrated circuit board. Then, the first IO is an intra-board IO of the board card, and the second IO is an external IO of the board card.
Further, the enabling circuit of the enabling signal terminal may be a GPIO of the CPU or directly connected to a system power supply.
In the hot plug protection circuit provided by this embodiment, an isolation circuit is implemented by a group of back-to-back MOS transistors, gates of the MOS transistors are connected to an enable signal terminal, and when an enable signal is a low level, a first IO and a second IO are in an isolated state, and a voltage of any one of the two is not transmitted to the other one; after the enable signal becomes high level, the first IO and the second IO can realize level synchronization, and therefore the IO power-on sequence error of the board card in hot plug can be prevented. The hot plug protection circuit can realize open-drain IO protection, supports real-time bidirectional communication and is suitable for most IO applications.
Fig. 2 is a schematic circuit diagram illustrating a second embodiment of a hot plug protection circuit according to the present invention.
As shown in fig. 2, based on the first embodiment, the hot swap protection circuit further includes a first diode D1; wherein the cathode of the first diode D1 is connected to the second IO and the anode of the first diode D1 is grounded.
The first diode D1 is a transient voltage suppressor diode, and ESD and surge protection of the hot swap protection circuit is realized.
It is understood that ESD and surge protection implemented by hot swap protection circuit may be replaced by other forms of protection devices, such as a dual diode clamp, a varistor, etc.
Then, in another preferred embodiment, the hot swap protection circuit further comprises a dual diode clamp circuit; the first end of the double diode clamping circuit is connected with the second IO, the second end of the double diode clamping circuit is grounded, and the third end of the double diode clamping circuit is connected with a voltage source.
In another preferred embodiment, the hot swap protection circuit further comprises a first voltage dependent resistor; one end of the first piezoresistor is connected with the second IO, and the other end of the first piezoresistor is grounded.
Fig. 3 is a schematic circuit diagram illustrating a third embodiment of a hot plug protection circuit according to the present invention.
As shown in fig. 3, based on the second embodiment, the hot swap protection circuit further includes a first resistor R1; the gate of the first MOS transistor Q1 is connected to the enable signal terminal through the first resistor R1.
The first resistor R1 can protect the gates of the first MOS transistor Q1 and the second MOS transistor Q2.
Fig. 4 is a schematic circuit diagram illustrating a fourth embodiment of a hot plug protection circuit according to the present invention.
As shown in fig. 4, based on the third embodiment, the hot swap protection circuit further includes a third MOS transistor Q3, a fourth MOS transistor Q4, and a fifth MOS transistor Q5; wherein,
the gate of the third MOS transistor Q3 is connected to the enable signal terminal through the first resistor R1, the source of the third MOS transistor Q3 is grounded, and the drain of the third MOS transistor Q3 is connected to the gate of the fifth MOS transistor Q5;
the gate of the fourth MOS transistor Q4 is connected to the drain of the third MOS transistor Q3, the source of the fourth MOS transistor Q4 is connected to the first IO, and the drain of the fourth MOS transistor Q4 is connected to the drain of the fifth MOS transistor Q5;
and the source electrode of the fifth MOS transistor Q5 is connected with the second IO.
In the hot swap protection circuit provided by this embodiment, the isolation circuit is implemented by two groups of MOS transistors, where the first MOS transistor Q1 and the second MOS transistor Q2 are NMOS transistors, and the fourth MOS transistor Q4 and the fifth MOS transistor Q5 are PMOS transistors; the third MOS transistor Q3 is an NMOS transistor, which is used as an enable signal flip. The hot plug protection circuit is suitable for push-pull driving type IO isolation and supports real-time bidirectional communication.
The specific working principle is as follows:
1. when the enable signal is low: the first MOS transistor Q1, the second MOS transistor Q2 and the third MOS transistor Q3 are in a cut-off state; the gates of the fourth MOS transistor Q4 and the fifth MOS transistor Q5 are in a floating (or pull-up) state, so the fourth MOS transistor Q4 and the fifth MOS transistor Q5 are also in a cut-off state;
2. when the enable signal is high: the gates of the first MOS transistor Q1 and the second MOS transistor Q2 are at a high level, the third MOS transistor Q3 is in a conducting state, the gates of the fourth MOS transistor Q4 and the fifth MOS transistor Q5 are at a low level, and at this time:
a. if the second IO is at a low level, the first MOS transistor Q1 and the second MOS transistor Q2 are turned on; the fourth MOS transistor Q4 and the fifth MOS transistor Q5 are cut off;
b. if the second IO is at a high level, the fourth MOS transistor Q4 and the fifth MOS transistor Q5 are turned on, and the first MOS transistor Q1 and the second MOS transistor Q2 are turned off.
Therefore, when the enable signal is at a high level, no matter whether the second IO is at a high level or a low level, one group of MOS transistors is always in a conducting state.
Fig. 5 is a schematic circuit diagram illustrating a fifth embodiment of a hot plug protection circuit according to the present invention.
As shown in fig. 5, based on the fourth embodiment, the hot swap protection circuit further includes a second resistor R2; the drain of the third MOS transistor Q3 is connected to the second IO through the second resistor R2.
The second resistor R2 is used for providing a pull-up level for the gates of the fourth MOS transistor Q4 and the fifth MOS transistor Q5, so as to improve the anti-interference capability.
Fig. 6 is a schematic circuit diagram illustrating a sixth embodiment of a hot plug protection circuit according to the present invention.
As shown in fig. 6, based on the fourth embodiment, the hot swap protection circuit further includes a third resistor R3, a second diode D2, and a third diode D3; wherein,
one end of the third resistor R3 is connected to the drain of the third MOS transistor Q3, and the other end of the third resistor R3 is connected to the cathode of the second diode D2;
the anode of the second diode D2 is connected to the first IO;
the anode of the third diode D3 is connected to the second IO, and the cathode of the third diode D3 is connected to the other end of the third resistor R3.
The third resistor R3, the second diode D2, and the third diode D3 are used for providing a pull-up level for the gates of the fourth MOS transistor Q4 and the fifth MOS transistor Q5, so as to improve the interference rejection capability.
Fig. 7 is a schematic diagram of a power-on timing sequence of a hot plug protection circuit according to the present invention.
As shown in fig. 7, the initialization process of general hot plug can be divided into three phases, which are an insertion phase, a power-on phase and a working phase. Wherein,
in the insertion phase, the system-on-chip is not powered and the enable signal is low. For the second IO (external IO), an ESD pulse with a very high voltage amplitude and a very short duration exists at the moment of insertion; after the protection circuit is added, the pulse is pressed by the ESD protection diode to be about 20% higher than the normal working voltage, and the MOS tube is prevented from being broken down. Because the enable signal is at a low level, the first IO and the second IO are still in a disconnected state, and the first IO (IO in the board) maintains a zero level, so that the situation that the IO is powered on before the chip system is powered on is avoided, and ESD discharge energy cannot enter the chip system.
In the power-on stage, the power supply of the chipset system starts to power on, and the first IO will be changed to a high level or a low level according to the initialization level configuration of the chipset system. However, since the enable signal is still at a low level, the first IO and the second IO are still in an off state and do not change in level synchronously.
And in a normal working stage, the enabling signal is changed into a high level, the second IO is communicated with the first IO, and level synchronous change and normal communication are realized on two sides.
Therefore, the utility model discloses can keep apart all outside IO interferences before chip system power-on, including ESD, surge and voltage, protection IO is not broken, guarantees the requirement that the power-on sequence of chip system IO satisfies the system simultaneously.
The utility model is suitable for the IO power-on time sequence control of hot plug, can protect IO from being damaged by ESD, avoid IO to power up before the power supply of chip system; meanwhile, the method is also suitable for controlling the interconnection IO power-on time sequence of different chip systems in a board or between boards, can avoid the problems of IO power-on abnormity, steps, nonmonotony and the like caused by different chip systems due to different power-on time sequences, different power-on and power-off control and the like, and improves the reliability of the chip systems.
Correspondingly, the embodiment of the utility model provides a still provide a integrated circuit board, the integrated circuit board includes above-mentioned arbitrary embodiment hot plug protection circuit.
The above description is only a preferred embodiment of the present invention, but the protection scope of the present invention is not limited thereto, and it should be noted that, for those skilled in the art, a plurality of equivalent obvious modifications and/or equivalent substitutions can be made without departing from the technical principle of the present invention, and these obvious modifications and/or equivalent substitutions should also be regarded as the protection scope of the present invention.
Claims (10)
1. A hot plug protection circuit is characterized by comprising a first MOS tube and a second MOS tube; wherein,
the source electrode of the first MOS tube is connected with a protected first IO, the grid electrode of the first MOS tube is connected with an enabling signal end, and the drain electrode of the first MOS tube is connected with the drain electrode of the second MOS tube;
and the grid electrode of the second MOS tube is connected with the grid electrode of the first MOS tube, and the source electrode of the second MOS tube is connected with the second IO.
2. The hot plug protection circuit of claim 1, further comprising a first diode; and the cathode of the first diode is connected with the second IO, and the anode of the first diode is grounded.
3. The hot swap protection circuit of claim 1, further comprising a dual diode clamp circuit; the first end of the double diode clamping circuit is connected with the second IO, the second end of the double diode clamping circuit is grounded, and the third end of the double diode clamping circuit is connected with a voltage source.
4. The hot plug protection circuit of claim 1, further comprising a first voltage dependent resistor; one end of the first piezoresistor is connected with the second IO, and the other end of the first piezoresistor is grounded.
5. A hot plug protection circuit according to any of claims 1 to 4, further comprising a first resistor; the grid electrode of the first MOS tube is connected with the enabling signal end through the first resistor.
6. The hot plug protection circuit according to claim 5, further comprising a third MOS transistor, a fourth MOS transistor and a fifth MOS transistor; wherein,
the grid electrode of the third MOS tube is connected with the enabling signal end through the first resistor, the source electrode of the third MOS tube is grounded, and the drain electrode of the third MOS tube is connected with the grid electrode of the fifth MOS tube;
the grid electrode of the fourth MOS tube is connected with the drain electrode of the third MOS tube, the source electrode of the fourth MOS tube is connected with the first IO, and the drain electrode of the fourth MOS tube is connected with the drain electrode of the fifth MOS tube;
and the source electrode of the fifth MOS tube is connected with the second IO.
7. The hot plug protection circuit of claim 6, further comprising a second resistor; and the drain electrode of the third MOS tube is connected with the second IO through the second resistor.
8. The hot plug protection circuit of claim 6, further comprising a third resistor, a second diode, and a third diode; wherein,
one end of the third resistor is connected with the drain electrode of the third MOS tube, and the other end of the third resistor is connected with the cathode of the second diode;
the anode of the second diode is connected with the first IO;
and the anode of the third diode is connected with the second IO, and the cathode of the third diode is connected with the other end of the third resistor.
9. The hot plug protection circuit of claim 6, wherein the first MOS transistor is an NMOS transistor, the second MOS transistor is an NMOS transistor, the third MOS transistor is an NMOS transistor, the fourth MOS transistor is a PMOS transistor, and the fifth MOS transistor is a PMOS transistor.
10. A board card comprising the hot swap protection circuit of any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120105754.9U CN214954954U (en) | 2021-01-14 | 2021-01-14 | Hot plug protection circuit and board card |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202120105754.9U CN214954954U (en) | 2021-01-14 | 2021-01-14 | Hot plug protection circuit and board card |
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| CN214954954U true CN214954954U (en) | 2021-11-30 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114050714A (en) * | 2022-01-13 | 2022-02-15 | 苏州浪潮智能科技有限公司 | Method, circuit, device and medium for protecting PCIE (peripheral component interface express) card power supply |
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2021
- 2021-01-14 CN CN202120105754.9U patent/CN214954954U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114050714A (en) * | 2022-01-13 | 2022-02-15 | 苏州浪潮智能科技有限公司 | Method, circuit, device and medium for protecting PCIE (peripheral component interface express) card power supply |
| CN114050714B (en) * | 2022-01-13 | 2022-04-22 | 苏州浪潮智能科技有限公司 | Method, circuit, device and medium for protecting PCIE (peripheral component interface express) card power supply |
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