CN210443562U

CN210443562U - Transverse electrostatic induction transistor

Info

Publication number: CN210443562U
Application number: CN201921958966.0U
Authority: CN
Inventors: 范捷; 万立宏; 王绍荣
Original assignee: Jiangsu Lijuan Power Semiconductor Co ltd
Current assignee: Jiangsu Lijuan Power Semiconductor Co ltd
Priority date: 2019-11-13
Filing date: 2019-11-13
Publication date: 2020-05-01
Anticipated expiration: 2029-11-13

Abstract

The utility model discloses a horizontal static induction transistor, relate to the semiconductor technology field, the source electrode and the drain electrode of this static induction transistor all are located the surface of N type silicon layer, the P type bars piece that the interval set up constitutes the grid with the P type outer gate of the P type bars piece of being connected of surface jointly, form the channel region between the P type bars piece, this device is different from traditional fore-and-aft SIT structure, its current direction flows for the horizontal direction, three electrode all is located the front of chip, can conveniently integrate in the middle of the conventional integrated circuit, and the withstand voltage of device is decided by distance and N type silicon layer concentration between grid to the drain electrode, withstand voltage is unrestricted in theory, the device performance is more excellent; and the surface area above the device channel is in a P type and does not participate in conduction any more, so that the influence of the adverse effect on the surface of the device is avoided, and the reliability of the device is improved.

Description

Transverse electrostatic induction transistor

Technical Field

The utility model belongs to the technical field of the semiconductor technology and specifically relates to a horizontal electrostatic induction transistor.

Background

The SIT not only can work in a switch state and be used as a high-power current switch, but also can be used as a power amplifier and used for high-power medium-frequency transmitters, long-wave radio stations, differential converters, high-frequency Induction heating devices, radars and the like, at present, the SIT product reaches 1500V of voltage, 300A of current, 3kW of dissipated power and 30-50 MHz of cut-off frequency, compared with a bipolar transistor, the SIT has the advantages of good linearity and low noise, the power amplifier made of the SIT has better sound quality, tone color and the like than the bipolar transistor, ② has high input impedance and low output impedance, can directly form an OTL circuit, the SIT is a minority of transistors without storage speed, has no storage speed, has high radiation resistance, has high resistance, has no negative resistance, has no resistance, has high resistance, and has the function of storing current, high temperature resistance, high temperature resistance, high voltage resistance, high power resistance, high voltage resistance, high power efficiency, high temperature resistance, high temperature resistance, high temperature resistance, high resistance.

The conventional SIT device is a mesa device, and its cross-sectional structure is shown in fig. 1: the front surface of the chip is provided with a source electrode and a grid electrode of the device, and a drain electrode of the device is positioned on the back surface of the chip. The current from drain to source is a vertical transistor structure. The manufacturing method comprises the following steps: growing an N-epitaxial layer on an N + substrate, forming a P + buried gate with higher concentration on the N-epitaxial layer, then forming an N-epitaxial layer with extremely low concentration on the P + buried gate in an epitaxial manner, forming an N + source electrode above the N-epitaxial layer, then leading out a P + grid electrode through mesa etching, and leading out metal electrodes through front and back metal and etching. In the manufacturing process, when a lightly doped N-epitaxial layer grows above a P + buried gate, the problem that impurities in the P + are reversely expanded into the epitaxial layer inevitably occurs, and the electrical failure caused by the inversion of the epitaxial layer or the abnormal resistivity can be greatly caused. In addition, in the process of gate etching, the situation that some ion damages are usually etched on the gate groove by adopting a wet etching method can be avoided, but the etching depth is difficult to control, the problem of insufficient etching or excessive etching can be caused to cause device failure, and the wet etching can generate transverse underetching, so that a considerable chip area can be occupied, and the integration level of the device can be reduced. Therefore, the conventional structure shown in fig. 1 is difficult to manufacture, and the device may have a failure problem and low reliability. Moreover, the withstand voltage of the device is directly determined by the thickness and concentration of the N-epitaxial layer below the P + buried gate, the thickness of the N-epitaxial layer is generally limited by the total thickness of the substrate, and the withstand voltage of the device is limited accordingly.

SUMMERY OF THE UTILITY MODEL

The inventor of the present invention has proposed a transverse electrostatic induction transistor aiming at the above problems and technical requirements, the technical scheme of the utility model is as follows:

a transverse static induction transistor comprises an N-type substrate, wherein an isolation silicon dioxide layer is arranged on the N-type substrate, and an N-type silicon layer is arranged on the isolation silicon dioxide layer;

two sides of the surface of the N-type silicon layer are respectively provided with an N-type impurity doped region along a first direction to form a drain region and a source region, and the bottoms of the drain region and the source region are both connected with the isolation silicon dioxide layer; the N-type silicon layer is provided with a plurality of P-type gate blocks at intervals along a first direction between the drain region and the source region, and the bottom of each P-type gate block is connected with the isolation silicon dioxide layer; the surface of the N-type silicon layer is provided with a P-type outer grid along a first direction at the position of the P-type grid block, the top of each P-type grid block is connected with the P-type outer grid so as to be connected in series, and an N-channel is formed between every two adjacent P-type grid blocks;

and a dielectric layer is arranged on the N-type silicon layer, contact holes are respectively arranged on the surfaces of the drain region, the source region and the P-type outer grid of the dielectric layer, a metal layer is arranged at each contact hole, the drain region leads out the drain electrode through the metal layer, the source region leads out the source electrode through the metal layer, and the P-type outer grid leads out the grid electrode through the metal layer.

The further technical scheme is that the thickness of the N-type silicon layer is between 1um and 10um, the thickness of the isolation silicon dioxide layer is between 1um and 5um, and the resistivity of the N-type substrate is between 1 ohm and 100ohm cm 2.

The utility model has the beneficial technical effects that:

the application discloses a transverse static induction transistor, which is different from a traditional longitudinal SIT structure in structure, wherein the current direction of the static induction transistor flows in the horizontal direction, and three electrodes are positioned on the front surface of a chip, so that the static induction transistor can be conveniently integrated into a conventional integrated circuit; the withstand voltage of the device is determined by the distance between the grid electrode and the drain electrode and the concentration of the N-type silicon layer 3 above the isolation silicon dioxide layer 2, the withstand voltage is not limited theoretically, and the device performance is better. The surface area above the device channel is in a P type and does not participate in conduction any more, so that the influence of the surface adverse effect of the device is avoided, the reliability of the device is improved, and the structure is similar to the LDD principle in the MOS device due to low impurity concentration, so that the withstand voltage between the grid and the drain can be effectively improved, and the performance of the device is improved.

In addition, the structure of the transverse static induction transistor disclosed by the application does not need to involve a step of low-doping epitaxy above a high-concentration P + buried gate in the manufacturing engineering, and does not have a process of digging a gate groove on the front surface, all process steps are similar to those of a conventional integrated circuit such as a CMOS (complementary metal oxide semiconductor), so that the transverse static induction transistor can be perfectly integrated into the integrated circuit, the manufacturing difficulty of the structure is reduced, and the process control is simpler.

Drawings

Fig. 1 is a structural view of a conventional vertical electrostatic induction transistor.

Fig. 2 is a structural diagram of the lateral static induction transistor of the present application.

Fig. 3 is a cross-sectional structural view of the surface of the N-type silicon layer.

Fig. 4 is a cross-sectional view of the surface of the N-type silicon layer along a first direction.

Fig. 5 is a block diagram of a step in the fabrication process of the lateral electrostatic induction transistor of the present application.

Fig. 6 is a structural diagram of another step in the fabrication process of the lateral electrostatic induction transistor of the present application.

Fig. 7 is a structural diagram of another step in the fabrication process of the lateral electrostatic induction transistor of the present application.

Detailed Description

The following describes the embodiments of the present invention with reference to the accompanying drawings.

Referring to fig. 2, the lateral static induction transistor includes an N-type substrate 1, an isolation silicon dioxide layer 2 is disposed on the N-type substrate 1, and an N-type silicon layer 3 is disposed on the isolation silicon dioxide layer 2. Wherein, the thickness of the N-type silicon layer 3 is between 1um and 10um, the thickness of the isolation silicon dioxide layer 2 is between 1um and 5um, and the resistivity of the N-type substrate 1 is between 1 ohm and 100ohm cm 2.

And N-type impurity doped regions along the first direction are respectively arranged on two sides of the surface of the N-type silicon layer 3 to form a drain region 4 and a source region 5, and the bottoms of the drain region 4 and the source region 5 are both connected with the isolation silicon dioxide layer 2. Referring to the surface structure diagram of the N-type silicon layer 3 shown in fig. 3 and the cross-sectional view of the P-type gate block 6 shown in fig. 4 along the first direction, a plurality of P-type gate blocks 6 are disposed at intervals between the drain region 4 and the source region 5 of the N-type silicon layer 3 along the first direction, and the bottom of each P-type gate block 6 is connected to the isolation silicon dioxide layer 2. The surface of the N-type silicon layer 3 is provided with a P-type outer grid 7 along the first direction at the position of the P-type grid block 6, the top of each P-type grid block 6 is connected with the P-type outer grid 7 so as to be connected in series, and the N-type silicon layer 3 between the adjacent P-type grid blocks 6 forms an N-channel. Fig. 3 is a sectional view at the P-type gate blocks 6, and fig. 2 is a sectional view at the N-channel between the P-type gate blocks 6, and then the N-channel is under the P-type outer gate 7.

The N-type silicon layer 3 is provided with a dielectric layer 8, the dielectric layer 8 is respectively provided with contact holes on the surfaces of the drain region 4, the source region 5 and the P-type outer grid 7, a metal layer 9 is arranged at each contact hole, the drain region 4 leads out a drain electrode through the metal layer, the source region 5 leads out a source electrode through the metal layer, and the P-type outer grid 7 leads out a grid electrode through the metal layer.

As can be seen from fig. 2, the SIT structure of the present application is different from the conventional vertical SIT structure, the current direction of the SIT structure is horizontal, and the three electrodes are all located on the front surface of the chip, so that the static induction transistor can be conveniently integrated into the conventional integrated circuit. The withstand voltage is determined by the distance between the grid and the drain and the concentration of the N-type silicon layer 3 above the isolation silicon dioxide layer 2, the withstand voltage is not limited theoretically, and the device performance is better.

The manufacturing process of the transverse static induction transistor is as follows:

1. a stacked structure of an N-type substrate 1, an isolation silicon dioxide layer 2, and an N-type silicon layer 3 is formed. There are two alternative fabrication schemes:

(1) directly using SOI substrate, the thickness of N type silicon layer 3 above the substrate is between 1um-10um, the thickness of isolation silicon dioxide layer 2 is between 1-5um, and the resistivity of N type substrate 1 is between 1-100ohm cm 2.

(2) Directly performing high-energy high-dose O implantation on the N-type substrate 1, wherein the resistivity of the N-type substrate 1 is between 1 and 100ohm cm2, the implantation energy is between 1M and 10MeV, the implantation depth is between 1um and 10um, and the implantation dose is more than 1E16/cm 2. Then, high-temperature annealing at 1000 ℃ or above is carried out, so that the injected O reacts with the surrounding Si to form an insulating layer with a certain thickness.

2. And photoetching a drain terminal and a source terminal at two sides, and implanting and doping high-concentration N-type impurities to form a source region and a drain region, wherein the doped N-type impurities are P or As, the implantation dose is between 1E15 and 2E16, and the implantation energy is between 50 and 200 kev. Then, high-temperature diffusion propulsion of the source end and the drain end is carried out, the propulsion temperature is between 1000 and 1250 ℃, and the diffusion time is between 1 and 10 hours. The diffusion depth ensures that the lower parts of the source region and the drain region can reach the isolation silicon dioxide layer 2, as shown in fig. 5, so that the current can be ensured to flow uniformly in the N-type silicon layer 3 above the isolation silicon dioxide layer 2, and the reliability of the device is improved.

3. And performing primary gate photoetching, wherein the size of the gate blocks is close to the thickness of the N-type silicon layer 3, and the distance between the gate blocks is slightly smaller than the size of the gate blocks, and is approximately between 2 and 5 um. And then, carrying out one-time gate implantation, wherein the one-time gate implantation is carried out on the surface of the N-type silicon layer 3, the energy is less than 100kev, the implantation impurity is B, and the implantation dosage is 2E14-1E15/cm 2. And then, the photoresist is reserved, and then, the second and third implantation doping of the gate is carried out, the implantation is equal to the dosage of the first implantation, but the energy of the two subsequent implantations needs to be flexibly adjusted, so that the implantation depth is ensured to be uniformly distributed from top to bottom in the N-type silicon layer 3. After the implantation is completed, the impurity profile is shown in fig. 6. When the thickness of the N-type silicon layer 3 is large, the number of times of implantation is not limited to three, and may be increased accordingly.

4. Removing the photoresist, and performing thermal diffusion on the gate, wherein the diffusion temperature is 1000-1150 ℃, and the diffusion time is 1-2 h. The temperature is lower than the diffusion temperature of the source and drain. The lateral diffusion distance is within 1 um. After the diffusion is completed, the implanted impurities are fused together to form the P-type gate blocks 6, and the N-type silicon layer 3 between the P-type gate blocks 6 forms an N-channel, as shown in fig. 7. It should be noted that when the diffusion time is too long, more lateral diffusion of the P-type impurity occurs, so that the N-channel region of the P-type gate block 6 of the SIT is narrowed, thereby reducing the current capability of the device. When the diffusion time is too short, the gates implanted several times are not connected together, and the P-type impurity below cannot play a role in current control.

5. And photoetching and implanting the P-type outer gate 7, wherein the P-type outer gate 7 is in a long strip structure and completely covers the region of the P-type gate block 6, the implantation impurity of the P-type outer gate 7 is B or BF2, the implantation energy is below 100kev, and the implantation dosage is lower than 1E13-1E 14. After the injection, the P-type outer gate 7 connects all the P-type gate blocks 6 in series to ensure the electric potential to be consistent, please refer to the structure shown in fig. 3. And after injection, the topmost surface area above the device channel is in a P type and does not participate in conduction any more, so that the influence of the adverse effect on the surface of the device is avoided, and the reliability of the device is improved. And because the impurity concentration is very low, the structure is similar to the LDD principle in the MOS device, the withstand voltage between the grid and the drain can be effectively improved, and the performance of the device is improved.

6. And then growing an ILD on the front surface to form a dielectric layer, performing photoetching and etching on the contact hole and PVD (physical vapor deposition) growth on the metal layer on the front surface, performing photoetching and etching on the metal layer on the front surface, and finally forming three electrodes of the device on the front surface to form the structure shown in FIG. 2.

What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiments. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and scope of the present invention are to be considered as included within the scope of the present invention.

Claims

1. A transverse static induction transistor is characterized by comprising an N-type substrate, wherein an isolation silicon dioxide layer is arranged on the N-type substrate, and an N-type silicon layer is arranged on the isolation silicon dioxide layer;

two sides of the surface of the N-type silicon layer are respectively provided with an N-type impurity doping region along a first direction to form a drain region and a source region, and the bottoms of the drain region and the source region are both connected with the isolation silicon dioxide layer; a plurality of P-type gate blocks are arranged on the N-type silicon layer at intervals along the first direction between the drain region and the source region, and the bottom of each P-type gate block is connected with the isolation silicon dioxide layer; the surface of the N-type silicon layer is provided with a P-type outer grid along a first direction at the position of a P-type grid block, the top of each P-type grid block is connected with the P-type outer grid so as to be connected in series, and an N-channel is formed between every two adjacent P-type grid blocks;

the N-type silicon layer is provided with a dielectric layer, the dielectric layer is provided with contact holes on the surfaces of the drain region, the source region and the P-type outer grid respectively, a metal layer is arranged at each contact hole, the drain region leads out the drain electrode through the metal layer, the source region leads out the source electrode through the metal layer, and the P-type outer grid leads out the grid electrode through the metal layer.

2. The lateral electrostatic induction transistor of claim 1, wherein said N-type silicon layer is between 1um-10um thick, said isolation silicon dioxide layer is between 1-5um thick, and said N-type substrate has a resistivity of between 1-100ohm cm 2.