CN209045526U - Groove isolation construction - Google Patents
Groove isolation construction Download PDFInfo
- Publication number
- CN209045526U CN209045526U CN201821434102.4U CN201821434102U CN209045526U CN 209045526 U CN209045526 U CN 209045526U CN 201821434102 U CN201821434102 U CN 201821434102U CN 209045526 U CN209045526 U CN 209045526U
- Authority
- CN
- China
- Prior art keywords
- side wall
- nanometers
- groove
- insulation division
- medium layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Element Separation (AREA)
Abstract
The utility model provides a kind of groove isolation construction, and structure includes: substrate, has groove in substrate；Insulating medium layer, including being filled in the first insulation division of groove and protruding from the second insulation division of substrate surface, the second insulation division includes the lug boss on top and the raised interconnecting piece between lug boss and the first insulation division；Side wall protection portion is covered in the side wall for stating the lug boss of the second insulation division；And side wall extension, it is covered in the side wall of the raised interconnecting piece of the second insulation division；Side wall protection portion and insulating medium layer have unlike material.The utility model makes the dielectric of groove isolation construction have the lug boss for protruding from substrate by the way that supporting layer is arranged; and side wall extension and side wall protection portion are formed by the side to the lug boss; side wall protection portion etching selection ratio different and with higher from the material of dielectric; so as to be protected to dielectric, reduce or the side of dielectric is avoided to corrode.
Description
Technical field
The utility model belongs to IC design manufacturing field, more particularly to a kind of groove isolation construction and its production
Method.
Background technique
With the rapid development of semiconductor processing technology, semiconductor devices is in order to reach faster arithmetic speed, bigger
Information storage and more functions, semiconductor chip develop to more high integration direction, i.e. the feature ruler of semiconductor devices
Very little (CD, Critical Dimension) is smaller, and the integrated level of semiconductor chip is higher.Currently, semiconductor integrated circuit is logical
It often include active area and the isolated area between active area, these isolated areas are formed before manufacturing active device.Along with
Semiconductor technology enters deep sub-micron era, and the active area isolation layer of semiconductor devices mostly uses greatly shallow ditch groove separation process
(Shallow Trench Isolation, STI) makes.
Fig. 1 is shown as a kind of overlooking structure diagram of fleet plough groove isolation structure (STI), and Fig. 2 is shown as in Fig. 1 at A-A '
Cross section structure schematic diagram, it can be seen that in the other etching technics for returning carving technology or subsequent manufacturing semiconductor devices, formed
The side wall of fleet plough groove isolation structure (STI) 102 in substrate 101 may occur side corrosion and form side etching tank 103,
The defects of side etching tank 103 will lead to edge current leakage, reduces the reliability of semiconductor devices.
Based on the above, providing one kind can be effectively prevented fleet plough groove isolation structure (STI) generation side etching tank, thus
The groove isolation construction and preparation method thereof for improving device reliability is necessary.
Utility model content
In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of groove isolation construction and
Its production method, the side wall for solving groove isolation construction (STI) in the prior art are easily corroded and lead to edge current leakage etc.
The problem of defect.
In order to achieve the above objects and other related objects, the utility model provides a kind of production side of groove isolation construction
Method, the production method include: that 1) one substrate of offer, Yu Suoshu substrate surface at least sequentially form oxide liner layer and support
Dielectric layer；2) patterning etches the supporting medium layer and the oxide liner layer, in the supporting medium layer and described
Oxide liner layer forms filling window, connects and etches the substrate, to form groove in the substrate；3) deposition insulation is situated between
Matter layer, the insulating medium layer include be filled in the first insulation division of the groove and be filled in it is described filling window second
Insulation division；4) supporting medium layer is removed, so as to protrude from the oxide liner layer convex to be formed for second insulation division
The portion of rising；5) spacer medium layer is deposited, the spacer medium layer includes the first surface portion for covering the oxide liner layer, covering
The second surface portion of the upper surface of the lug boss and the side wall protection portion of the covering lug boss side wall, the spacer medium
Layer has unlike material with the oxide liner layer；And 6) remove the first surface portion, the institute of the spacer medium layer
Second surface portion and the oxide liner layer below the first surface portion are stated, the side for being located at the lug boss is retained
The side wall protection portion of wall, while retaining the oxide liner layer being located at below the side wall protection portion to form side wall
Extension.
Preferably, the method for step 5) deposition medium separation layer includes atomic layer deposition.
Further, the gas source of the atomic layer deposition includes Si3Cl4And NH3。
Preferably, after step 4) removes the supporting medium layer, the lug boss protrudes from the oxide liner layer
Altitude range is between 5 nanometers~25 nanometers.
Preferably, step 6) removes the first surface portion of the spacer medium layer, described second using dry etching
Surface element and the oxide liner layer below the first surface portion.
Preferably, it includes: a) using the first carbon that etching, which is located at the oxide liner layer below the first surface portion,
Fluorine gas performs etching the oxide liner layer as etching gas, so that the etch rate of the oxide liner layer is big
In the etch rate of the spacer medium layer, the oxide liner layer being located at below the first surface portion is etched to one
Residual thickness；B) oxide liner layer is performed etching as etching gas using the second carbon fluorine gas, so that the oxygen
The etch rate of compound laying is greater than the etch rate of the substrate, by the oxide liners with the residual thickness
Layer all removal；Wherein, the carbon content of second fluorocarbon gas is greater than the carbon content of first fluorocarbon gas.
Further, the first carbon fluorine gas includes CHF3, and the second carbon fluorine gas includes C4F6And C4F8In one
Kind.
Preferably, the residual thickness is between the 5%~20% of the original depth of the oxide liner layer.
Preferably, step 6) remaines in the altitude range of the side wall protection portion of the lug boss side wall between 5 nanometers
Between~25 nanometers, width range remaines in the side wall of the side wall of the lug boss between 3 nanometers~20 nanometers
The altitude range of extension is between 3 nanometers~12 nanometers, and width range is between 5 nanometers~20 nanometers.
Preferably, the oxide liner layer and the supporting medium layer have unlike material, the oxide liner layer
Material include silica, the material of the supporting medium layer includes silicon nitride, the initial thickness range of the supporting medium layer
Between 50 nanometers~120 nanometers.
It preferably, further include that thermal oxide is carried out to the side wall and apex angle of the groove after step 2) forms the groove, with
Insulative sidewall and insulation sphering apex angle are formed, to improve the voltage endurance capability of the groove isolation construction.
Preferably, the step 2) groove and it is described filling window total depth range between 250 nanometers~600 nanometers it
Between.
Preferably, the material of the oxide liner layer includes silica, and the material of the spacer medium layer includes nitridation
Silicon.
The utility model also provides a kind of groove isolation construction, comprising:
Substrate has groove in the substrate；
Insulating medium layer, including being filled in the first insulation division of the groove and protruding from first insulation division top surface
The second insulation division, second insulation division include top lug boss and be located at the lug boss and first insulation division
Between raised interconnecting piece；
Side wall protection portion is covered in the side wall for stating the lug boss of the second insulation division；And
Side wall extension is covered in the side wall of the raised interconnecting piece of second insulation division；
Wherein, the side wall protection portion and the insulating medium layer have unlike material.
Preferably, the altitude range of the lug boss of second insulation division is between 5 nanometers~25 nanometers, described second
The altitude range of the interconnecting piece of insulation division is between 5 nanometers~20 nanometers.
Preferably, the altitude range of the side wall protection portion between 5 nanometers~25 nanometers, receive between 3 by width range
Rice~20 nanometers between, the altitude range of the side wall extension between 3 nanometers~12 nanometers, receive between 5 by width range
Rice~20 nanometers between.
Preferably, the side wall extension and the insulating medium layer have same material, the material of the side wall extension
Matter includes silica.
Preferably, the insulative sidewall and insulation sphering apex angle that there is thermal oxide to be formed for the side wall of the groove and apex angle.
Preferably, the altitude range of the insulating medium layer is between 250 nanometers~600 nanometers.
Preferably, the material of the insulating medium layer includes silica, and the material of the spacer medium layer includes silicon nitride.
As described above, the groove isolation construction and preparation method thereof of the utility model, has the advantages that
The utility model by be arranged supporting layer make groove isolation construction dielectric have protrude from the convex of substrate
The portion of rising, and side wall extension and side wall protection portion are formed by side to the lug boss, the side wall protection portion and it is described absolutely
The material of edge medium is different and etching selection ratio with higher, so as to protect to the dielectric, subsequent
Protective effect is persistently generated in multiple tracks processing procedure, reduce or the side of dielectric is avoided to corrode.
Detailed description of the invention
Fig. 1 and Fig. 2 is shown as the structural schematic diagram of fleet plough groove isolation structure in the prior art, the fleet plough groove isolation structure
There are side etching tanks, wherein Fig. 2 is shown as in Fig. 1 the cross section structure schematic diagram at A-A.
The structure that each step of production method that Fig. 3~Figure 13 is shown as the groove isolation construction of the utility model is presented is shown
It is intended to, wherein Figure 12 is shown as in Figure 13 the cross section structure schematic diagram at B-B '.
Component label instructions
101 semiconductor substrates
102 insulating materials
103 side etching tanks
201 substrates
202 oxide liner layers
203 supporting medium layers
204 grooves
205 filling windows
206 insulating medium layers
207 side wall extensions
30 mask patterns
301 hard mask layers
302 anti-reflecting layers
303 litho patterns
40 spacer medium layers
401 first surface portions
402 second surface portions
403 side wall protection portion
501 first insulation divisions
502 second insulation divisions
503 lug bosses
504 raised interconnecting pieces
601 insulative sidewalls
602 insulation sphering apex angles
Specific embodiment
Illustrate the embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition
Different specific embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints and answer
With carrying out various modifications or alterations under the spirit without departing from the utility model.
Please refer to Fig. 3~Figure 13.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model is only shown with related component in the utility model rather than when according to actual implementation in diagram then
Component count, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind
Become, and its assembly layout kenel may also be increasingly complex.
As shown in Fig. 3~Figure 13, the present embodiment provides a kind of production method of 204 isolation structure of groove, the production sides
Method includes:
As shown in figure 3, carrying out step 1) first, a substrate 201 is provided, 201 surface of substrate is formed with oxide liner
Bed course 202.
The substrate 201 can be for silicon substrate 201, germanium silicon substrate 201, silicon carbide substrates 201, germanium substrate 201 etc., can be with
To be doping or undoped, for example, the substrate 201 can be the silicon substrate 201 of p-type doping or the silicon of n-type doping
Substrate 201 etc..
The oxide liner layer 202 can to reduce the substrate 201 and the supporting medium layer 203 that is subsequently formed it
Between stress, and protect 201 surface of substrate, avoid subsequent manufacturing processes on influence caused by the substrate 201, the oxygen
The material of compound laying 202 can be silica, and thickness range can be that can use such as between 5 nanometers~25 nanometers
The formation such as thermal oxidation technology or depositing operation.
As shown in figure 4, then carrying out step 2), supporting medium layer 203 is formed on Yu Suoshu oxide liner layer 202.
The oxide liner layer 202 has unlike material with the supporting medium layer 203, can be using such as low pressure chemical
Vapour deposition process (LPCVD), aumospheric pressure cvd method (APCVD), plasma enhanced chemical vapor deposition method
(PECVD), the techniques such as high density plasma CVD method (HDPCVD) are formed, the material of the supporting medium layer 203
Matter can be silicon nitride, and the initial thickness range of the supporting medium layer 203 is between 50 nanometers~120 nanometers.
As shown in Fig. 5~Fig. 7 a, step 3) is then carried out, forms mask pattern 30, base in Yu Suoshu supporting medium layer 203
The supporting medium layer 203 and the oxide liner layer 202 are etched in the mask pattern 30, in the supporting medium layer
203 and the oxide liner layer 202 form filling window 205, connect and etch the substrate 201, in the substrate 201
Middle formation groove 204, while the mask pattern 30 is removed, retain the supporting medium layer 203 and the oxide liner layer
202。
Specifically, mask pattern 30 is formed in step 3) Yu Suoshu supporting medium layer 203 includes:
Step 3-1 is carried out first), hard mask layer 301 is formed in Yu Suoshu supporting medium layer 203.The hard mask layer 301
Comprising carbon-coating, thickness range is between 100 nanometers~200 nanometers.The hard mask layer 301 can make up litho pattern
303 select with substrate 201 than inadequate defect.
Then step 3-2 is carried out), anti-reflecting layer 302 is formed on Yu Suoshu hard mask layer 301.The anti-reflecting layer 302 wraps
Silicon oxynitride layer is included, thickness range is between 10 nanometers~40 nanometers.302 one side of anti-reflecting layer is as the photoetching figure
On the other hand the etching stop layer of shape 303 can prevent the light in exposure process of litho pattern 303 from reflecting to told photoetching figure
The influence of shape 303.
Then step 3-3 is carried out), litho pattern 303 is formed on Yu Suoshu anti-reflecting layer 302.The litho pattern 303
Thickness range is between 100 nanometers~200 nanometers.
For example, the method for forming the litho pattern 303 can be for prior to forming spin coating photoetching on the anti-reflecting layer 302
Then glue-line forms the litho pattern 303 using exposure technology.
For another example, if the pattern dimension of required litho pattern 303 is less than the characteristic size of exposure, the litho pattern is formed
303 technique can use pitch multiplication process (Pitch Double), to improve the integrated level of device.
Finally carry out step 3-4), it is based on the litho pattern 303, by dry etch process by the litho pattern
303 are transferred in the anti-reflecting layer 302 and the hard mask layer 301, to form the mask pattern 30.
It, can be using the supporting medium layer as described in plasma dry etch technique etching based on the mask pattern 30
203 and the oxide liner layer 202, to form filling window in the supporting medium layer 203 and the oxide liner layer 202
Mouth 205 connects and etches the substrate 201, to form groove 204, in etching process, the exposure mask in the substrate 201
Figure 30 is consumed removal, while may consume the part supporting medium layer 203, for example, the supporting medium layer 203
Initial thickness range between 50 nanometers~120 nanometers, and the groove 204 etching after the completion of, the Supporting Media
The altitude range of layer 203 can be between 5 nanometers~25 nanometers.
The depth of the groove 204 is inconsistent according to different components requirement, in the present embodiment, the groove 204 and institute
The total depth range of filling window 205 is stated between 250 nanometers~600 nanometers.
Preferably, the groove 204 that step 3) is formed includes the first direction groove 204 and that first direction extends
The second direction groove 204 that two directions extend, the first direction groove 204 and 204 cross arrangement of second direction groove,
To be separated out multiple active areas in the substrate 201.
It as shown in Figure 7b, can also include the side wall to the groove 204 and top after step 3) forms the groove 204
Angle carries out thermal oxide, and to form insulative sidewall 601 and insulation sphering apex angle 602,204 isolation structure of groove can be improved
Voltage endurance capability.
As shown in Fig. 8~Fig. 9, step 4) is then carried out, deposits insulating medium layer 206, the insulating medium layer 206 includes
It is filled in the first insulation division 501 of the groove 204 and is filled in the second insulation division 502 of the filling window 205.
The dielectric can be using such as Low Pressure Chemical Vapor Deposition (LPCVD), aumospheric pressure cvd method
(APCVD), plasma enhanced chemical vapor deposition method (PECVD), high density plasma CVD method
(HDPCVD) etc. techniques are formed, as shown in Figure 8.
It is then possible to carving technology or grinding technics, such as CMP process be used back, by the supporting medium layer
Extra dielectric removal on 203, as shown in Figure 9.
The insulating medium layer 206 is including being filled in the first insulation division 501 of the groove 204 and being filled in described fill out
The second insulation division 502 of window 205 is filled, first insulation division 501 is used as primary insulation object, and second insulation division 502 can
The insulation performance that 204 isolation structure of groove is improved with progress one, improves the pressure-resistant performance of device.
As shown in Figure 10, step 5) is then carried out, the supporting medium layer 203 is removed, so that second insulation division 502
The oxide liner layer 202 is protruded to form lug boss 503.
For example, by hot phosphoric acid wet etching or CH can be passed through3F base dry etching is to remove the supporting medium layer
203, so that second insulation division 502 protrudes from the oxide liner layer 202 to form lug boss 503.
After step 5) removes the supporting medium layer 203, second insulation division 502 protrudes from the oxide liner layer
The height h range of 202 lug boss 503 is between 5 nanometers~25 nanometers.
As shown in figure 11, step 6) is then carried out, spacer medium layer 40 is deposited, the spacer medium layer 40 includes covering institute
State the first surface portion 401 of oxide liner layer 202, the upper surface of the covering lug boss 503 second surface portion 402 and
The side wall protection portion 403 of 503 side wall of lug boss is covered, the spacer medium layer 40 has with the insulating medium layer 206
Unlike material.
For example, the spacer medium layer 40, the atom can be deposited in the method for atomic layer deposition by depositing device
The gas source of layer deposition includes Si3Cl4And NH3, can accurately be controlled by the thickness of the spacer medium layer 40 of atomic layer deposition
System, the control precision of the spacer medium layer 40 allow to be applicable in smaller size of technique and smaller up to 0.6~2 angstrom
Side wall deposition.Reduce the occupancy to active region area.The spacer medium layer 40 includes covering the oxide liner layer 202
First surface portion 401, the covering lug boss 503 upper surface second surface portion 402 and the covering lug boss 503
The side wall protection portion 403 of side wall, the spacer medium layer 40 have unlike material with the insulating medium layer 206.
For example, the etching selection ratio of the insulating medium layer 206 and the spacer medium layer 40 is not less than 10:1, to guarantee
The protection of 40 pairs of the spacer medium layer insulating medium layer 206 avoids the side of the insulating medium layer 206 from corroding.At this
In embodiment, the material of the insulating medium layer 206 includes silica, and the material of the spacer medium layer 40 includes silicon nitride.
As shown in FIG. 12 and 13, wherein Figure 12 is shown as in Figure 13 the cross section structure schematic diagram at B-B ', finally carries out
Step 7) removes the first surface portion 401 of the spacer medium layer 40, the second surface portion 402 and is located at described the
The oxide liner layer 202 of one surface element, 401 lower section retains the side wall guarantor for being located at the side wall of the lug boss 503
Shield portion 403, while retaining the oxide liner layer 202 for being located at 403 lower section of side wall protection portion to form side wall extension
Portion 207.
In the present embodiment, using dry etching remove the spacer medium layer the first surface portion, described second
Surface element and the oxide liner layer below the first surface portion.
Specifically, the oxide liner layer of the etching below the first surface portion includes:
Step a) performs etching the oxide liner layer as etching gas using the first carbon fluorine gas, so that institute
The etch rate for stating oxide liner layer is greater than the etch rate of the spacer medium layer, will be located at below the first surface portion
The oxide liner layer be etched to a residual thickness.For example, the first carbon fluorine gas includes CHF3.Preferably, described
Residual thickness is between the 5%~20% of the original depth of the oxide liner layer, to guarantee the oxide liner layer
Removal rate retain the oxide liner of the residual thickness while than more completely retaining the side wall protection portion 403
Bed course, it is ensured that the substrate not will receive damage caused by etching in this step, improve its performance.
Step b) performs etching the oxide liner layer as etching gas using the second carbon fluorine gas, so that institute
The etch rate for stating oxide liner layer is greater than the etch rate of the substrate, by the oxide with the residual thickness
Laying all removes；Wherein, the carbon content of second fluorocarbon gas is greater than the carbon content of first fluorocarbon gas.Example
Such as, the second carbon fluorine gas includes C4F6And C4F8One of.It is carved using biggish second fluorocarbon gas of carbon content
Erosion, can reduce etching damage caused by the substrate.
Step 7) remaines in the altitude range of the side wall protection portion 403 of the side wall of the lug boss 503 between 5 nanometers
Between~25 nanometers, width range remaines in the side of the side wall of the lug boss 503 between 3 nanometers~20 nanometers
The altitude range of wall extension 207 is between 3 nanometers~12 nanometers, and width range is between 5 nanometers~20 nanometers.
204 isolation structure of groove includes 204 isolation structure of first direction groove and second that first direction extends
204 isolation structure of second direction groove that direction extends, 204 isolation structure of first direction groove and the second direction ditch
204 isolation structure cross arrangement of slot, to be separated out multiple active areas in the substrate 201.
The utility model by be arranged supporting layer make 204 isolation structure of groove dielectric have protrude from substrate
201 lug boss 503, and side wall extension 207 and side wall protection portion 403 are formed by the side to the lug boss 503, it is described
The etching selection ratio different and with higher from the material of the dielectric of side wall protection portion 403, so as to described exhausted
Edge medium is protected, and reduces or the side of dielectric is avoided to corrode.
As shown in figure 12, the present embodiment provides a kind of 204 isolation structures of groove, comprising: substrate 201, insulating medium layer
206, side wall protection portion 403 and side wall extension 207.
The substrate 201 can be for silicon substrate 201, germanium silicon substrate 201, silicon carbide substrates 201, germanium substrate 201 etc., can be with
To be doping or undoped, for example, the substrate 201 can be the silicon substrate 201 of p-type doping or the silicon of n-type doping
Substrate 201 etc..
There is groove 204 in the substrate 201.The groove 204 includes the first direction groove 204 that first direction extends
And the second direction groove 204 that second direction extends, the first direction groove 204 are handed over the second direction groove 204
Fork arrangement, to be separated out multiple active areas in the substrate 201, as shown in figure 13, wherein Figure 12 is shown as in Figure 13 at B-B '
Cross section structure schematic diagram.
In another embodiment, the insulative sidewall 601 that there is thermal oxide to be formed for the side wall of the groove 204 and apex angle and absolutely
Edge sphering apex angle 602, to improve the voltage endurance capability of 204 isolation structure of groove.
As shown in figure 12, the insulating medium layer 206 include be filled in the groove 204 the first insulation division 501 and
Protrude from the second insulation division 502 of 201 top surface of substrate, second insulation division 502 include top lug boss 503 and
Raised interconnecting piece 504 between the lug boss 503 and first insulation division 501.First insulation division, 501 conduct
Primary insulation object, second insulation division 502 can improve the insulation performance of 204 isolation structure of a raising groove, improve device
Pressure-resistant performance.
The altitude range of the insulating medium layer 206 is between 250 nanometers~600 nanometers.
The altitude range of the lug boss 503 of second insulation division 502 is between 5 nanometers~25 nanometers, described second
The altitude range of the interconnecting piece of insulation division 502 is between 5 nanometers~20 nanometers.
As shown in figure 12, the side wall protection portion 403 is covered in the side for stating the lug boss 503 of the second insulation division 502
Wall.
The altitude range of the side wall protection portion 403 between 5 nanometers~25 nanometers, width range between 3 nanometers~
Between 20 nanometers.
As shown in figure 12, the side wall extension 207 is covered in the raised interconnecting piece of second insulation division 502
504 side wall；Wherein, the side wall protection portion 403 has unlike material with the insulating medium layer 206.
The altitude range of the side wall extension 207 between 3 nanometers~12 nanometers, width range between 5 nanometers~
Between 20 nanometers.
The side wall extension 207 has same material with the insulating medium layer 206, the insulating medium layer 206
Material includes silica, and the material of the side wall extension 207 includes silica.The side wall extension 207 on the one hand can be with
Reduce the stress between the substrate 201 and the spacer medium layer 40, on the other hand can be used as the insulating medium layer 206
Extension, protect the insulating medium layer 206, prevent it from being corroded by side.
The etching selection ratio of the insulating medium layer 206 and the spacer medium layer 40 is not less than 10:1, described in guaranteeing
The protection of 40 pairs of the spacer medium layer insulating medium layers 206 avoids the side of the insulating medium layer 206 from corroding.In this implementation
In example, the material of the insulating medium layer 206 includes silica, and the material of the spacer medium layer 40 includes silicon nitride.
The utility model by be arranged supporting layer make 204 isolation structure of groove dielectric have protrude from substrate
201 lug boss 503, and side wall extension 207 and side wall protection portion 403, institute are formed by the side to the lug boss 503
The etching selection ratio different and with higher from the material of the dielectric of side wall protection portion 403 is stated, so as to described
Dielectric carries out sustainable protection, reduces or the side of dielectric is avoided to corrode.
The side wall protection portion 403 retained positioned at 503 side wall of lug boss can also form active area periphery shield
Ring, while the side wall extension 207 for retaining the oxide liner layer being located at below the side wall protection portion 403 then can be with shape
At another active area periphery retaining ring, to re-define the multiple active areas surrounded in the upper surface of the substrate 201 by the groove
Exposed area size, and can use the film forming thickness of spacer medium layer 40 to control the width of active area periphery protection ring.Side
The active area periphery retaining ring that the active area periphery retaining ring that wall protection portion 403 is formed is formed with side wall extension 207 can have phase
Deng area coverage.
As described above, 204 isolation structure of groove and preparation method thereof of the utility model, has the advantages that
The utility model by be arranged supporting layer make 204 isolation structure of groove dielectric have protrude from substrate
201 lug boss 503, and side wall extension 207 and side wall protection portion 403 are formed by the side to the lug boss 503, it is described
The etching selection ratio different and with higher from the material of the dielectric of side wall protection portion 403, so as to described exhausted
Edge medium is protected, and persistently generates protective effect in subsequent multiple tracks processing procedure, reduces or the side of dielectric is avoided to corrode.
The utility model effectively overcomes various shortcoming in the prior art and has high industrial utilization value.
The above embodiments are only illustrative of the principle and efficacy of the utility model, and not for limitation, this is practical new
Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model
All equivalent modifications or change completed under mind and technical idea, should be covered by the claim of the utility model.
Claims (7)
1. a kind of groove isolation construction characterized by comprising
Substrate has groove in the substrate；
Insulating medium layer, including being filled in the first insulation division of the groove and protruding from the of first insulation division top surface
Two insulation divisions, second insulation division include the lug boss on top and between the lug boss and first insulation division
Raised interconnecting piece；
Side wall protection portion is covered in the side wall for stating the lug boss of the second insulation division；And
Side wall extension is covered in the side wall of the raised interconnecting piece of second insulation division；
Wherein, the side wall protection portion and the insulating medium layer have unlike material.
2. groove isolation construction according to claim 1, it is characterised in that: the lug boss of second insulation division
Altitude range between 5 nanometers~25 nanometers, receive between 5 nanometers~20 by the altitude range of the interconnecting piece of second insulation division
Between rice.
3. groove isolation construction according to claim 1, it is characterised in that: the altitude range of the side wall protection portion between
Between 5 nanometers~25 nanometers, width range is between 3 nanometers~20 nanometers, and the altitude range of the side wall extension is between 3
Nanometer~12 nanometers between, width range is between 5 nanometers~20 nanometers.
4. groove isolation construction according to claim 1, it is characterised in that: the side wall extension and the dielectric
Layer has same material, and the material of the side wall extension includes silica.
5. groove isolation construction according to claim 1, it is characterised in that: the side wall and apex angle of the groove have hot oxygen
Change the insulative sidewall formed and insulation sphering apex angle.
6. groove isolation construction according to claim 1, it is characterised in that: the altitude range of the insulating medium layer between
Between 250 nanometers~600 nanometers.
7. groove isolation construction according to claim 1, it is characterised in that: the material of the insulating medium layer includes oxidation
The material of silicon, the side wall protection portion includes silicon nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821434102.4U CN209045526U (en) | 2018-09-03 | 2018-09-03 | Groove isolation construction |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821434102.4U CN209045526U (en) | 2018-09-03 | 2018-09-03 | Groove isolation construction |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209045526U true CN209045526U (en) | 2019-06-28 |
Family
ID=67032092
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821434102.4U Active CN209045526U (en) | 2018-09-03 | 2018-09-03 | Groove isolation construction |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209045526U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110875238A (en) * | 2018-09-03 | 2020-03-10 | 长鑫存储技术有限公司 | Trench isolation structure and manufacturing method thereof |
-
2018
- 2018-09-03 CN CN201821434102.4U patent/CN209045526U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110875238A (en) * | 2018-09-03 | 2020-03-10 | 长鑫存储技术有限公司 | Trench isolation structure and manufacturing method thereof |
| CN110875238B (en) * | 2018-09-03 | 2024-09-20 | 长鑫存储技术有限公司 | Trench isolation structure and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104752363B (en) | The forming method of flash memory | |
| CN103151261B (en) | Trench Schottky diode and manufacturing method thereof | |
| CN102779780B (en) | Method for forming non-load-effect large size groove | |
| CN109801931A (en) | Semiconductor structure and semiconductor structure manufacturing method | |
| TW200406041A (en) | Method for producing shallow trench isolation | |
| CN109545790A (en) | The forming method in the channel hole of three-dimensional storage | |
| CN209045526U (en) | Groove isolation construction | |
| CN109037068A (en) | Semiconductor structure and forming method thereof | |
| CN208903993U (en) | Fleet plough groove isolation structure | |
| CN103439862B (en) | Grid LELE double-pattern forming method | |
| CN208923086U (en) | Fleet plough groove isolation structure | |
| CN105742237A (en) | Synchronous etching process of dual-structure contact hole | |
| CN111199911B (en) | Shallow trench isolation structure and manufacturing method thereof | |
| CN103227143B (en) | Shallow ditch groove separation process | |
| CN209029354U (en) | Fleet plough groove isolation structure | |
| CN111933570B (en) | Manufacturing method of shallow trench isolation structure and shallow trench isolation structure formed by same | |
| CN104078330B (en) | The forming method of the triple figures of autoregistration | |
| CN102810471A (en) | Method of forming a trench by a silicon-containing mask | |
| CN102693932B (en) | Manufacturing method of shallow trench isolation structure | |
| CN207781568U (en) | Fleet plough groove isolation structure | |
| CN101777485B (en) | Etching method | |
| CN208706617U (en) | Fleet plough groove isolation structure | |
| CN209045563U (en) | A kind of buried gate structure | |
| CN103578995B (en) | Form the method for FinFET | |
| CN110148584A (en) | The method for forming the air gap |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |