CN1763972A - Three-dimensional multi-gate high-voltage P type transverse double-diffused metal-oxide semiconductor device - Google Patents
Three-dimensional multi-gate high-voltage P type transverse double-diffused metal-oxide semiconductor device Download PDFInfo
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- CN1763972A CN1763972A CN 200510094031 CN200510094031A CN1763972A CN 1763972 A CN1763972 A CN 1763972A CN 200510094031 CN200510094031 CN 200510094031 CN 200510094031 A CN200510094031 A CN 200510094031A CN 1763972 A CN1763972 A CN 1763972A
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Abstract
The invention discloses a three-dimension multigrid P-type lateral dual-diffusion MOS transistor used as high-voltage device, which comprises: a P-type substrate with oxidation layer, a column P-type drift region on oxidation layer; a P-type drain and channel on oxidation layer and two ends of P-type drift region, a P-type source on oxidation layer and near P-type channel; a field oxide to cover the surface of P-type drift region, a grid-oxidation layer on P-type channel surface, a polysilicon layer to cover the field oxidation layer and grid-oxidation layer surface. This invention has compact structure, makes conduction resistance less than one third of traditional tube, and increases current density more than two times.
Description
Technical field
The present invention relates to a kind of P type lateral double-diffused metallic oxide semiconductor tube, relate in particular to a kind of three-dimensional multi-gate high-voltage P type transverse bilateral diffusion metal oxide semiconductor tube that can be used for integrated circuit.
Background technology
The lateral double diffusion metal oxide semiconductor high tension apparatus has advantages such as switching characteristic is good, power consumption is little, what is more important lateral double diffusion metal oxide semiconductor type high tension apparatus is easy to compatibility standard low pressure metal oxide semiconductor technology, reduce production cost of chip, therefore MOS type high pressure integrated device has absolute predominance in the range of application of 10V-600V.The lateral double diffusion metal oxide semiconductor high tension apparatus that employing SOI material (silicon on insulated substrate) is made has better breakdown characteristics, better temperature characterisitic, and the isolation with other circuit simultaneously is more prone to effective.But the shortcoming of lateral double diffusion metal oxide semiconductor high tension apparatus maximum is exactly that conducting resistance is big, and current density is little.But, in the application of many high pressure integrated chips, require the power output of chip very big, this just requires chip to have bigger output current.Just because of improving constantly of application requirements, the new structure of the MOS type high tension apparatus of big electric current constantly occurs, but these structures also all do not have to utilize chip area maximumly, under identical puncture voltage, also do not reach minimum conducting resistance and maximum saturation current.
Summary of the invention
The invention provides a kind of compact conformation and three-dimensional multi-gate high-voltage P type transverse bilateral diffusion metal oxide semiconductor tube that can be compatible mutually with standard SOI metal oxide semiconductor processing, the present invention is under identical puncture voltage, conducting resistance is less than 1/3rd of traditional high pressure lateral double-diffused metallic oxide semiconductor tube, and current density increases more than 2 times.
The present invention adopts following technical scheme:
A kind of three-dimensional multi-gate high-voltage P type transverse bilateral diffusion metal oxide semiconductor tube as high tension apparatus, comprise: P type substrate, on P type substrate, be provided with oxide layer, on oxide layer, be provided with column P type drift region, on oxide layer and be positioned at the adjacent respectively P of the setting type in two ends, P type drift region and leak and the P raceway groove, on oxide layer and be positioned at P raceway groove position adjacent and be provided with P type source, surface in P type drift region is coated with field oxide, surface at the P raceway groove is coated with grid oxide layer, is coated with polysilicon layer on the surface of field oxide and grid oxide layer.
Compared with prior art, the present invention has following advantage:
(1) structure of the silicon-oxide layer-silicon of the present invention's introducing, this has just formed soi structure naturally, the soi structure material is compared with common silicon materials, and the horizontal double diffusion P type high tension apparatus for preparing on the SOI material has better breakdown characteristics, has better temperature characterisitic.
(2) the horizontal double diffusion P of the SOI type high tension apparatus of the present invention's introducing is compared with the horizontal double diffusion P of traditional silicon materials type high tension apparatus, and is at first different on the preparation material, and its preparation technology's difference must adopt new preparation technology then.Can on identical chip area, increase 2-3 polysilicon gate by new preparation technology, this 2-3 polysilicon gate is connected together in the preparation, thereby increased 2-3 raceway groove, though owing to mobility of charge carrier rate difference at each face, conducting resistance can not reduce by 3 times, but it will be traditional about 1/3rd that experimental result shows conducting resistance, and saturation current is about traditional 3 times, these two characteristics will change to some extent according to different preparation methods, but laterally the performance of double diffusion P type high tension apparatus has obtained improving greatly, can reduce the power consumption of horizontal double diffusion P type high tension apparatus greatly.
(3) compare with common silicon materials, the horizontal double diffusion P type high tension apparatus for preparing on the SOI material is more prone to and other device isolation, and isolation effect more.
(4) the horizontal double diffusion P of the SOI type high tension apparatus of the present invention's preparation SOI low pressure process compatibility easy and standard is integrated.
(5) the present invention not only forms raceway groove at silicon face, and has formed 3 raceway grooves in the silicon body, makes full use of chip area like this, makes chip structure compact more, is therefore reaching under the same chip performance situation, and chip area can be saved greatly.
(6) preparation technology of the present invention is simple, can realize based on existing C MOS technology, therefore can compatible existing C MOS technology, thus realize the processing and preparing of power integrated circuit.
Description of drawings
Fig. 1 is a structural representation of the present invention.
Fig. 2 is the structure cutaway view of embodiment of the invention A-A '.
Fig. 3 is an embodiment of the invention B-B ' structure cutaway view.
Fig. 4 is the structure cutaway view of embodiment of the invention C-C '.
Fig. 5 is the partial structurtes cutaway view of the embodiment of the invention.
Embodiment
A kind of three-dimensional multi-gate high-voltage P type transverse bilateral diffusion metal oxide semiconductor tube as high tension apparatus, comprise: P type substrate 1, on P type substrate 1, be provided with oxide layer 2, on oxide layer 2, be provided with column P type drift region 3, on oxide layer 2 and be positioned at the adjacent respectively P of the setting type in 3 two ends, P type drift region and leak 4 and P raceway groove 5, on oxide layer 2 and be positioned at P raceway groove 5 position adjacent and be provided with P type source 6, surface in P type drift region 3 is coated with field oxide 7, be coated with grid oxide layer 8 on the surface of P raceway groove 5, surface at field oxide 7 and grid oxide layer 8 is coated with polysilicon layer 9, in the present embodiment, on the oxide layer 2 and be positioned at P type drift region 3 and P raceway groove 5 below be provided with cavity 21, in cavity 21, be provided with an oxidation bottom 71, grid oxygen bottom 81 and underlying polysilicon layer 91, below and P type drift region 3 that field oxidation bottom 71 is positioned at P type drift region 3 are set at by a field oxide 7 and a space that oxidation bottom 71 surrounds, below and P raceway groove 5 that grid oxygen bottom 81 is positioned at P raceway groove 5 are set at the space that is surrounded by grid oxide layer 8 and grid oxygen bottom 81, underlying polysilicon layer 91 is positioned at an oxidation bottom 71 and grid oxygen bottom 81 belows, and above-mentioned grid oxide layer 8 and grid oxygen bottom 81 and part field oxide 7 and an oxidation bottom 71 are positioned at the space that is surrounded by polysilicon layer 9 and underlying polysilicon layer 91.
A kind of preparation technology who is used to make the described three-dimensional multi-gate high-voltage P type transverse bilateral diffusion metal oxide semiconductor tube of claim 1, it is characterized in that preparation P type substrate earlier, again in P type substrate preparation oxide layer, growing P-type silicon on oxide layer, carrying out the P type on a part of P type silicon mixes, form P type drift region, at the both side surface and the damp and hot oxidation growth of upper surface of P type drift region and form field oxide, carrying out the N type on another part P type silicon mixes, form P type raceway groove, xeothermic oxidation growth and form gate oxide on the both side surface of P type raceway groove and upper surface, deposit polysilicon and form polysilicon layer on the part both side surface of the both side surface of P type raceway groove and upper surface and P type drift region and upper surface, at last, carry out the source, the leakage p type impurity injects, carve the preparation of hole and metal lead wire, in the present embodiment, on the oxide layer and be positioned at regional etching cavity below P type drift region and the P type raceway groove, at the bottom of cavity deposit polysilicon, and etch away unnecessary polysilicon, form underlying polysilicon layer, deposit silicon dioxide in cavity again, form an oxidation bottom and gate oxidation bottom, carry out surface finish then, make oxide layer, field oxidation bottom and gate oxidation bottom are on same plane, at the both side surface and the damp and hot oxidation growth of upper surface of P type drift region and when forming field oxide, field oxide is connected with an oxidation bottom, xeothermic oxidation growth and when forming gate oxide on the both side surface of P type raceway groove and upper surface, gate oxide is connected with the gate oxidation bottom, deposit polysilicon and when forming polysilicon layer on the part both side surface of the both side surface of P type raceway groove and upper surface and P type drift region and upper surface is connected polysilicon layer with underlying polysilicon layer.
The concrete technological process of present embodiment is as follows:
1. prepare P type substrate, concentration is 2 * 10
15Cm
-3
2. in P type substrate preparation oxide layer, oxidated layer thickness is 4 μ m.
3. one 2 dark groove of μ m on oxide layer is used for preparing placement polysilicon, field oxide and gate oxide.
4. the polysilicon of deposit bottom, the thickness of polysilicon is 1 μ m, and etches away unnecessary polysilicon.
5. deposit silicon dioxide forms field oxide and gate oxide, carries out surface finish then, makes oxide layer, field oxide and gate oxide on same plane, and the thickness of field oxide is 1 μ m, and the thickness of gate oxide is 0.025 μ m.
6. the thick P type silicon of epitaxial growth 4 μ m on oxide layer, field oxide and gate oxide, concentration is 1 * 10
15Cm
-3
7. the P type silicon above gate oxide carries out the doping of N type, forms P type channel region, and concentration is 3 * 10
16Cm
-3
8. the P type silicon above field oxide carries out the doping of P type, forms P type drift region, and concentration is 1 * 10
16Cm
-3
9. damp and hot oxidation growth forms field oxide in two sides and surface, is connected with the field oxide of bottom, and thickness is 1 μ m..
10. xeothermic oxidation growth forms gate oxide in two sides and surface, is connected with the gate oxide of bottom, and thickness is 0.025 μ m..
11. at two sides and surface deposition polysilicon, be connected with the polysilicon of bottom, thickness is 1 μ m.
12. source, leakage p type impurity inject, concentration is 1 * 10
21Cm
-3
13. carve the preparation of hole and metal lead wire.
Claims (4)
1, a kind of three-dimensional multi-gate high-voltage P type transverse bilateral diffusion metal oxide semiconductor tube as high tension apparatus, comprise: P type substrate (1), on P type substrate (1), be provided with oxide layer (2), it is characterized in that on oxide layer (2), being provided with column P type drift region (3), go up and be positioned at the adjacent respectively P of the setting type in two ends, P type drift region (3) in oxide layer (2) and leak (4) and P raceway groove (5), go up and be positioned in oxide layer (2) and be provided with P type source (6) with P raceway groove (5) position adjacent, be coated with field oxide (7) on the surface of P type drift region (3), be coated with grid oxide layer (8) on the surface of P raceway groove (5), be coated with polysilicon layer (9) on the surface of field oxide (7) and grid oxide layer (8).
2, three-dimensional multi-gate high-voltage P type transverse bilateral diffusion metal oxide semiconductor tube according to claim 1, it is characterized in that going up and the below that is positioned at P type drift region (3) and P raceway groove (5) is provided with cavity (21) in oxide layer (2), in cavity (21), be provided with an oxidation bottom (71), grid oxygen bottom (81) and underlying polysilicon layer (91), below and P type drift region (3) that field oxidation bottom (71) is positioned at P type drift region (3) are set at by a field oxide (7) and a space that oxidation bottom (71) surrounds, below and P raceway groove (5) that grid oxygen bottom (81) is positioned at P raceway groove (5) are set at the space that is surrounded by grid oxide layer (8) and grid oxygen bottom (81), underlying polysilicon layer (91) is positioned at an oxidation bottom (71) and grid oxygen bottom (81) below, and above-mentioned grid oxide layer (8) and grid oxygen bottom (81) and part field oxide (7) and an oxidation bottom (71) are positioned at the space that is surrounded by polysilicon layer (9) and underlying polysilicon layer (91).
3, a kind of preparation technology who is used to make the described three-dimensional multi-gate high-voltage P type transverse bilateral diffusion metal oxide semiconductor tube of claim 1, it is characterized in that preparation P type substrate earlier, again in P type substrate preparation oxide layer, growing P-type silicon on oxide layer, carrying out the P type on a part of P type silicon mixes, form P type drift region, at the both side surface and the damp and hot oxidation growth of upper surface of P type drift region and form field oxide, carrying out the N type on another part P type silicon mixes, form P type raceway groove, xeothermic oxidation growth and form gate oxide on the both side surface of P type raceway groove and upper surface, deposit polysilicon and form polysilicon layer on the part both side surface of the both side surface of P type raceway groove and upper surface and P type drift region and upper surface, at last, carry out the source, the leakage p type impurity injects, and carves the preparation of hole and metal lead wire.
4, preparation technology according to claim 3, it is characterized in that on the oxide layer and be positioned at regional etching cavity below P type drift region and the P type raceway groove, at the bottom of cavity deposit polysilicon, and etch away unnecessary polysilicon, form underlying polysilicon layer, deposit silicon dioxide in cavity again, form an oxidation bottom and gate oxidation bottom, carry out surface finish then, make oxide layer, field oxidation bottom and gate oxidation bottom are on same plane, at the both side surface and the damp and hot oxidation growth of upper surface of P type drift region and when forming field oxide, field oxide is connected with an oxidation bottom, xeothermic oxidation growth and when forming gate oxide on the both side surface of P type raceway groove and upper surface, gate oxide is connected with the gate oxidation bottom, deposit polysilicon and when forming polysilicon layer on the part both side surface of the both side surface of P type raceway groove and upper surface and P type drift region and upper surface is connected polysilicon layer with underlying polysilicon layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2005100940319A CN100369265C (en) | 2005-08-26 | 2005-08-26 | Three-dimensional multi-gate high-voltage P type transverse double-diffused metal-oxide semiconductor device |
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| CNB2005100940319A CN100369265C (en) | 2005-08-26 | 2005-08-26 | Three-dimensional multi-gate high-voltage P type transverse double-diffused metal-oxide semiconductor device |
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| US6097063A (en) * | 1996-01-22 | 2000-08-01 | Fuji Electric Co., Ltd. | Semiconductor device having a plurality of parallel drift regions |
| SE513284C2 (en) * | 1996-07-26 | 2000-08-14 | Ericsson Telefon Ab L M | Semiconductor component with linear current-to-voltage characteristics |
| DE69942186D1 (en) * | 1998-02-09 | 2010-05-12 | Nxp Bv | METHOD FOR PRODUCING A SEMICONDUCTOR ARRANGEMENT |
| US6028337A (en) * | 1998-11-06 | 2000-02-22 | Philips North America Corporation | Lateral thin-film silicon-on-insulator (SOI) device having lateral depletion means for depleting a portion of drift region |
| US6794719B2 (en) * | 2001-06-28 | 2004-09-21 | Koninklijke Philips Electronics N.V. | HV-SOI LDMOS device with integrated diode to improve reliability and avalanche ruggedness |
| JP3782021B2 (en) * | 2002-02-22 | 2006-06-07 | 株式会社東芝 | Semiconductor device, semiconductor device manufacturing method, and semiconductor substrate manufacturing method |
| US6777746B2 (en) * | 2002-03-27 | 2004-08-17 | Kabushiki Kaisha Toshiba | Field effect transistor and application device thereof |
| JP3944461B2 (en) * | 2002-03-27 | 2007-07-11 | 株式会社東芝 | Field effect transistor and its application device |
| US6800917B2 (en) * | 2002-12-17 | 2004-10-05 | Texas Instruments Incorporated | Bladed silicon-on-insulator semiconductor devices and method of making |
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