CN116759439A

CN116759439A - Super-junction VDMOS device, preparation method thereof and electronic equipment

Info

Publication number: CN116759439A
Application number: CN202310711796.0A
Authority: CN
Inventors: 张玉琦; 戴银; 任文珍
Original assignee: Semiconductor Manufacturing Electronics Shaoxing Corp SMEC
Current assignee: Semiconductor Manufacturing Electronics Shaoxing Corp SMEC
Priority date: 2023-06-15
Filing date: 2023-06-15
Publication date: 2023-09-15

Abstract

The application discloses a super junction VDMOS device, a preparation method thereof and electronic equipment, wherein the super junction VDMOS device comprises: a substrate and a superjunction structure. Wherein the superjunction structure is formed on the substrate; the superjunction structure comprises a first conductive type column and a second conductive type column; each conductive type column penetrates through two opposite surfaces of the super junction structure in the height direction, the doping concentration of each conductive type column in a first set height range of the super junction structure is smaller than that of each conductive type column in a second set height range, and the grid-drain capacitance is optimized, so that the grid-drain capacitance of the super junction structure under the condition of low drain-source voltage is increased, and the phenomenon of grid-drain capacitance pits under the condition of low drain-source voltage is avoided.

Description

Super-junction VDMOS device, preparation method thereof and electronic equipment

Technical Field

The application relates to the field of semiconductors, in particular to a super junction VDMOS device, a preparation method thereof and electronic equipment.

Background

In the prior art, when preparing a superjunction structure in a superjunction VDMOS (vertical double-diffusion metal-oxide semiconductor field effect transistor) device, a mode of forming the superjunction structure by multiple epitaxy is generally adopted. The super junction structure formed in multiple epitaxial growth processes comprises the following steps: growing an epitaxial layer, and respectively carrying out ion implantation of N and P to form an N column and a P column; the steps of growing epitaxial layers with the same thickness and implanting ions are repeated for a plurality of times, and then the junction is pushed through a thermal process to form a super junction structure with P columns and N columns which are distributed approximately uniformly and alternately. However, the super junction VDMOS device prepared by the method has smaller gate-drain capacitance (Cgd) under high drain-source voltage (Vds), and is easy to generate the phenomenon of gate-drain capacitance pit under low drain-source voltage.

Disclosure of Invention

The present application has been made in order to solve at least one of the above problems. According to a first aspect of the present application there is provided a superjunction VDMOS device comprising: a substrate and a superjunction structure. Wherein the superjunction structure is formed on the substrate; the superjunction structure comprises a first conductive type column and a second conductive type column; each conductive type column penetrates through two surfaces of the super junction structure, which are opposite in the height direction, and the doping concentration of each conductive type column in a first set height range of the super junction structure is smaller than that of each conductive type column in a second set height range.

In one embodiment of the present application, the first set height range is 1/2 to 3/4 of the height range of the superjunction structure; the second set height range is other height ranges in the super junction structure except the first set height range.

In one embodiment of the present application, the first conductivity type pillar is a P-type doped pillar and the second conductivity type pillar is an N-type doped pillar.

In one embodiment of the application, the doping concentration of the first conductivity type pillars is greater than the doping concentration of the second conductivity type pillars.

In one embodiment of the application, the substrate is an N-type substrate.

In one embodiment of the present application, the superjunction structure further comprises a plurality of first epitaxial layers; the plurality of first epitaxial layers are sequentially laminated on the substrate; wherein the first conductive type column and the second conductive type column are formed in each layer of the first epitaxial layer; the first conductive type columns in any two adjacent layers of the first epitaxial layers are arranged in a stacked mode, and the second conductive type columns in any two adjacent layers of the first epitaxial layers are arranged in a stacked mode; the multi-layer first epitaxial layer is divided into a first epitaxial layer of a first type and a second epitaxial layer of a second type, the thickness of each first epitaxial layer in the first epitaxial layer of the first type is a first thickness range, and the thickness of each first epitaxial layer in the first epitaxial layer of the second type is a second thickness range; the first epitaxial layer of the first type is positioned in the first set height range of the super junction structure, and the first epitaxial layer of the second type is positioned in the second set height range of the super junction structure; the minimum value of the first thickness range is larger than the maximum value of the second thickness range, the doping amount of each first conductive type column in the first epitaxial layer of the first type and the doping amount of each second conductive type column in the first epitaxial layer of the second type are equal, and the doping amount of each second conductive type column in the first epitaxial layer of the first type and the doping amount of each second conductive type column in the first epitaxial layer of the second type are equal.

In one embodiment of the present application, the first thickness range is a first thickness and the second thickness range is a second thickness; wherein the ratio of the first thickness to the second thickness is not less than 1.2.

In one embodiment of the present application, the superjunction VDMOS device further comprises: the second epitaxial layer, the source electrode structure, the gate electrode structure and the drain electrode structure. The second epitaxial layer is formed on the super junction structure, and a semiconductor source region and a semiconductor body region are formed in the second epitaxial layer; the source structure and the gate structure are formed on the second epitaxial layer; the drain structure is formed on a surface of the substrate facing away from the superjunction structure.

According to a second aspect of the present application, there is provided a method of manufacturing a superjunction VDMOS device, the superjunction VDMOS device comprising: providing a substrate; forming a superjunction structure on the substrate; wherein the superjunction structure comprises a first conductivity type pillar and a second conductivity type pillar; each conductive type column penetrates through two surfaces of the super junction structure, which are opposite in the height direction, and the doping concentration of each conductive type column in a first set height range of the super junction structure is smaller than that of each conductive type column in a second set height range.

In one embodiment of the present application, the forming a superjunction structure on the substrate includes: forming the first conductive type column and the second conductive type column in the uppermost first epitaxial layer after each first epitaxial layer is grown in the process of sequentially growing a plurality of first epitaxial layers on the substrate; the first conductive type columns in any two adjacent layers of the first epitaxial layers are arranged in a stacked mode, and the second conductive type columns in any two adjacent layers of the first epitaxial layers are arranged in a stacked mode; the multi-layer first epitaxial layer is divided into a first epitaxial layer and a second epitaxial layer, the thickness of each first epitaxial layer in the first epitaxial layer is in a first thickness range, and the thickness of each first epitaxial layer in the second epitaxial layer is in a second thickness range; the first epitaxial layer of the first type is positioned in the first set height range of the super junction structure, and the first epitaxial layer of the second type is positioned in the second set height range of the super junction structure; the minimum value of the first thickness range is larger than the maximum value of the second thickness range, the doping amount of each first conductive type column in the first epitaxial layer of the first type and the doping amount of each second conductive type column in the first epitaxial layer of the second type are equal, and the doping amount of each second conductive type column in the first epitaxial layer of the first type and the doping amount of each second conductive type column in the first epitaxial layer of the second type are equal.

According to a third aspect of the present application, there is provided an electronic device comprising: any one of the above-described superjunction VDMOS devices.

According to the super-junction VDMOS device, the preparation method thereof and the electronic equipment, the grid-drain capacitance is optimized by enabling the doping concentration of each conductive type column in the super-junction structure in the first set height range of the super-junction structure to be smaller than the doping concentration of each conductive type column in the second set height range, so that the grid-drain capacitance under the condition of low drain-source voltage is increased, and the phenomenon of grid-drain capacitance pits under the condition of low drain-source voltage is avoided.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort to a person skilled in the art.

FIG. 1 is a schematic cross-sectional view of a superjunction structure of a superjunction VDMOS device according to an embodiment of the application;

FIGS. 2-7 are schematic cross-sectional views illustrating various steps in preparing a superjunction structure according to an embodiment of the present application;

Fig. 8 is a schematic cross-sectional view of a superjunction VDMOS device according to an embodiment of the present invention;

FIG. 9 is a graph showing the gate-drain capacitance versus drain-source voltage for a partial N-type and partial P-type super junction structure according to an embodiment of the present invention;

FIG. 10 is a graph showing the gate-drain capacitance versus drain-source voltage variation curve of a P-bias superjunction structure and a P-bias superjunction structure according to the present invention;

FIG. 11 is a graph showing the variation of drain-source voltage with depletion line of a conventional partial P-type super junction structure;

fig. 12 is a simulation diagram showing a drain-source voltage variation of a depletion line of a partial P-type super junction structure according to an embodiment of the present invention.

Reference numerals:

10-substrate 21-first epitaxial layer 22-second epitaxial layer 31-first conductivity type column

32-second conductivity type pillars 41-semiconductor body 42-semiconductor source 51-gate metal 52-gate oxide 53-gate conductive polysilicon 60-source metal 70-drain metal

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, exemplary embodiments according to the present invention will be described in detail with reference to the accompanying drawings. It should be apparent that the described embodiments are only some embodiments of the present invention and not all embodiments of the present invention, and it should be understood that the present invention is not limited by the example embodiments described herein. Based on the embodiments of the invention described in the present application, all other embodiments that a person skilled in the art would have without inventive effort shall fall within the scope of the invention.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without one or more of these details. In other instances, well-known features have not been described in detail in order to avoid obscuring the invention.

It should be understood that the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to provide a thorough understanding of the present application, detailed structures will be presented in the following description in order to illustrate the technical solutions presented by the present application. Alternative embodiments of the application are described in detail below, however, the application may have other implementations in addition to these detailed descriptions.

Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.

Firstly, an application scene of the super junction VDMOS device is introduced, and the super junction VDMOS device is used as a type of power device and applied to various electronic equipment needing the power device.

The present application also provides a superjunction VDMOS device, referring to fig. 1, comprising: a substrate 21 and a superjunction structure. Wherein a superjunction structure is formed on a substrate 21. The super junction structure includes a first conductivity type pillar 31 and a second conductivity type pillar 32; each conductive type column penetrates through two surfaces of the super junction structure, which are opposite in the height direction, and the doping concentration of each conductive type column in a first set height range of the super junction structure is smaller than that of each conductive type column in a second set height range.

In the above scheme, the grid-drain capacitance is optimized by making the doping concentration of each conductive type column in the super junction structure in the first set height range of the super junction structure smaller than the doping concentration of each conductive type column in the second set height range, so that the grid-drain capacitance under the condition of low drain-source voltage is increased, and the phenomenon of grid-drain capacitance pit under the condition of low drain-source voltage is avoided. The following describes each of the above structures in detail with reference to the accompanying drawings.

As shown in fig. 1 and 2, the substrate 10 may be used as a carrier structure, such as, but not limited to, an N-type substrate, a P-type substrate, etc., particularly in relation to the type of superjunction VDMOS device. For example, in some embodiments, substrate 10 may be an N-type substrate. It should be understood that other layer structures may be provided on the substrate 10, for example, a buffer layer may be provided on the substrate 10, and the type of the buffer layer may be an N-type or P-type buffer layer, etc., which is specifically related to the type of the superjunction VDMOS device.

Referring to fig. 1, a superjunction structure including first and second conductive type pillars 31 and 32 is formed on a substrate 10. Each conductive-type pillar penetrates through two surfaces of the superjunction structure opposite in the height direction. The height direction refers to a direction perpendicular to the substrate 21. The direction away from the substrate 21 in the super junction structure is a positive direction of the height, and the direction close to the substrate 21 in the super junction structure is a negative direction of the height. Of course, the height of the superjunction structure must be a positive number. Each of the first and second conductive type pillars 31 and 32 penetrates through two surfaces equal in the height direction of the superjunction structure, that is, one end of each conductive type pillar is in contact with the substrate 21, and the other end is exposed on a surface of the superjunction structure away from the substrate 21. It can be seen that the extension direction of each conductivity type pillar is substantially parallel to the height direction.

In determining the types of the first conductive type pillars 31 and the second conductive type pillars 32 described above, the first conductive type pillars 31 may be P-type doped pillars, and the second conductive type pillars 32 may be N-type doped pillars. It should be understood that the above only shows one way, but other ways may be adopted, for example, the first conductive type column 31 may be an N-type doped column, and the second conductive type column 32 may be a P-type doped column.

In determining the doping concentrations of the first and second conductive type pillars 31 and 32, the doping concentration of the first conductive type pillar 31 may be made greater than the doping concentration of the second conductive type pillar 32. At this time, when the first conductive type column 31 is a P-type doped column and the second conductive type column 32 is an N-type doped column, the super junction structure is a P-type super junction structure. Of course, the doping concentration of the first conductivity type pillars 31 may be made smaller than or equal to the doping concentration of the second conductivity type pillars 32. For example, when the doping concentration of the first conductive type column 31 is smaller than the doping concentration of the second conductive type column 32, and the first conductive type column 31 is a P-type doped column and the second conductive type column 32 is an N-type doped column, the superjunction structure is an N-type superjunction structure.

As can be seen from fig. 1, the number of the first conductive type pillars 31 and the second conductive type pillars 32 is plural, and the plural first conductive type pillars 31 and the second conductive type pillars 32 are alternately arranged. It should be understood that fig. 1 shows only one arrangement of conductive type pillars, and that other arrangements may be used.

And the doping concentration of each conductive type column in the first set height range of the super junction structure is smaller than the doping concentration of the conductive type column in the second set height range. Specifically, for each first conductivity type pillar 31, the doping concentration of the first conductivity type pillar 31 in the first set height range of the superjunction structure is smaller than the doping concentration of the first conductivity type pillar 31 in the second set height range. For each second conductivity type pillar 32, the doping concentration of the second conductivity type pillar 32 in the first set height range of the superjunction structure is less than the doping concentration of the second conductivity type pillar 32 in the second set height range. The doping concentration of each conductive type column in the height direction is not uniform, but is smaller than that in the second set height range, so that the resistivity of each conductive type column in the first set height range is larger than that in the second set height range, the grid-drain capacitance is optimized, the grid-drain capacitance is increased under the condition of low drain-source voltage, and the phenomenon of grid-drain capacitance pit under the condition of low drain-source voltage is avoided.

The first set height range and the second set height range are determined, and are specifically related to the total height of the superjunction structure, and are also related to factors such as the type of doping ions, doping concentration, and the like.

For example, in some embodiments, the first set height range may be a 1/2 to 3/4 height range of the superjunction structure, and the second set height range may be other height ranges within the superjunction structure than the first set height range. The doping concentration of each conductive type column in the 1/2-3/4 height range of the super junction structure is smaller than that in other height ranges of the super junction structure, so that the resistivity of each conductive type column in the 1/2-3/4 height range of the super junction structure is larger than that in other height ranges, the grid-drain capacitance is optimized, the grid-drain capacitance under the condition of low drain-source voltage is increased, and the phenomenon of grid-drain capacitance pit under the condition of low drain-source voltage is avoided. It should be understood that the above only shows one way of determining the first set height range and the second set height range, but that other ways may be used.

In some embodiments, referring to fig. 2-6, the superjunction structure may further include a plurality of first epitaxial layers 21, the plurality of first epitaxial layers 21 being sequentially stacked on the substrate 10. First conductivity type pillars 31 and second conductivity type pillars 32 are formed in each of the first epitaxial layers 21; the first conductivity type pillars 31 in any adjacent two layers of the first epitaxial layer 21 are stacked, and the second conductivity type pillars 32 in any adjacent two layers of the first epitaxial layer 21 are stacked. I.e. each of the conductive type pillars is formed by stacking a plurality of conductive type pillars provided in a plurality of first epitaxial layers 21. Specifically, each first conductivity type pillar 31 is formed by stacking a plurality of sections of first conductivity type pillars 31 provided in the plurality of first epitaxial layers 21. Each second conductivity type pillar 32 is formed by stacking a plurality of sections of second conductivity type pillars 32 provided in the plurality of second epitaxial layers 22. It should be noted that, since only a partial region of the superjunction VDMOS device is illustrated in the cross-sectional view of fig. 1, the partial region is illustrated as a region where the superjunction structure is provided.

In the process of preparing the super junction structure, after each first epitaxial layer 21 is grown, a P-type ion and an N-type ion are required to be implanted into the newly grown first epitaxial layer 21 located at the uppermost layer, respectively, to form different first conductivity type pillars 31 and second conductivity type pillars 32, so fig. 3 does not show the first epitaxial layer 21, but only shows the first conductivity type pillars 31 and the second conductivity type pillars 32 formed after the P-type ion and the N-type ion are implanted.

Referring to fig. 1, the plurality of first epitaxial layers 21 may be divided into first epitaxial layers 21 of a first type and first epitaxial layers 21 of a second type, the thickness of each first epitaxial layer 21 in the first epitaxial layers 21 of the first type being a first thickness range, and the thickness of each first epitaxial layer 21 in the first epitaxial layers 21 of the second type being a second thickness range. The thickness of the first epitaxial layer 21 of the first type is significantly thicker than the thickness of the first epitaxial layer 21 of the second type in the plurality of first epitaxial layers 21. I.e. the first epitaxial layer 21 of the first type has a thickness in a first thickness range and the first epitaxial layer 21 of the second type has a thickness in a second thickness range, the minimum value of the first thickness range being greater than the maximum value of the second thickness range. By modifying the thickness of the specific first epitaxial layer 21, the thickness of the single-layer first epitaxial layer 21 in the specific region is thickened to a first thickness range, and the doping amount in each layer of first epitaxial layer 21 can be controlled to be the same subsequently, so that the doping concentrations of the conductive type columns in different first epitaxial layers 21 are adjusted, the adjustment of the doping concentrations of the different conductive type columns in the height direction is realized, the grid-drain capacitance is optimized, the grid-drain capacitance of the grid-drain capacitor under the low drain-source voltage condition is increased, and the phenomenon of grid-drain capacitance pit under the low drain-source voltage is avoided.

In some embodiments, the first type first epitaxial layer 21 may be located within a first set height range of the superjunction structure, and the second type first epitaxial layer 21 may be located within a second set height range of the superjunction structure. The doping amount of each conductive type column in the first-type first epitaxial layer 21 and the second-type first epitaxial layer 21 is also made equal. Specifically, the doping amounts of each first conductive type pillar 31 in the first epitaxial layer 21 and the second epitaxial layer 21 are equal, and the doping amounts of each second conductive type pillar 32 in the first epitaxial layer 21 and the second epitaxial layer 21 are equal. So that the doping concentration of each of the conductive type pillars formed in the first-type first epitaxial layer 21 is smaller than the doping concentration of the conductive type pillars formed in the second-type first epitaxial layer 21. The preparation process is simplified by controlling the equal doping amount of each time, and the concentration distribution of each conductive type column in the height direction is reduced and adjusted. It should be understood that the manner of adjusting the concentration distribution of each conductive type column in the height direction is not limited to the manner shown above, but other manners may be adopted. For example, the thickness of the first epitaxial layer 21 may be adjusted to be equal, but the doping amount is different each time to adjust the doping concentration profile of each conductive type column in the height direction.

In determining the first thickness range and the second thickness range, the first thickness range may be made to be a first thickness and the second thickness range may be made to be a second thickness, for example. Namely, the first thickness range and the second thickness range take separate values respectively, so that the multiple layers of the first epitaxial layers 21 are divided into two types according to the thickness, wherein the thickness of the first epitaxial layers 21 of the first type is a thicker first thickness, the thickness of the first epitaxial layers 21 of the second type is a thinner second thickness, the thicknesses of the first epitaxial layers 21 of the same type are uniform, and the stability of the process and the electric field stability of the first epitaxial layers 21 of the same type are easy to ensure under the same injection condition.

In determining the size of the first thickness and the second thickness, the ratio of the first thickness to the second thickness may be not less than 1.2, i.e. the first thickness is at least 20% greater than the second thickness. Specifically, the ratio of the first thickness to the second thickness may be any value of 1.20, 1.25, 1.30, 1.35, 1.40, 1.45, 1.50, etc. not less than 1.2. It should be understood that the first thickness range and the second thickness range are not limited to the first thickness and the second thickness range alone, and that other thickness range arrangements may be employed. For example, the first thickness range may include at least two thickness values, and the thickness of the first epitaxial layer 21 in the first thickness range may take any value in the first thickness range; the second thickness range may include at least two thickness values, and the thickness of the first epitaxial layer 21 in the second thickness range may take any value in the second thickness range.

It should be further explained here that, since the first conductive type pillars 31 and the second conductive type pillars 32 are formed in the first epitaxial layer 21 newly grown and located at the uppermost layer after each first epitaxial layer 21 is grown, the thicknesses of the first conductive type pillars 31 and the second conductive type pillars 32 of different sections formed sequentially are substantially equal to the thickness of the first epitaxial layer 21 where they are located. When the thickness of the first-type first epitaxial layer 21 is increased, the thicknesses of the first-conductivity-type pillars 31 and the second-conductivity-type pillars 32 formed in the first-type first epitaxial layer 21 are also increased. The doping amount of each conductive type column in the first epitaxial layer 21 of the first type and the second epitaxial layer 21 is equal, and the doping concentration of each conductive type column formed in the first epitaxial layer 21 of the first type is smaller than the doping concentration of the conductive type column formed in the first epitaxial layer 21 of the second type.

In determining which first epitaxial layers 21 are the first type first epitaxial layers 21 for the plurality of first epitaxial layers 21, the first type first epitaxial layers 21 may be located within a first set height range of the plurality of first epitaxial layers 21. Only the first epitaxial layer 21 located in the preset area of the plurality of first epitaxial layers 21 is thickened, and the first epitaxial layers 21 at other positions are not thickened. In a more preferred embodiment, the first set height range may be in the range of 1/2 to 3/4 of the total height of the multi-layered first epitaxial layer 21. The first type first epitaxial layer 21 is located within 1/2 to 3/4 of the total height of all the first epitaxial layers 21.

It should be noted that when the set height range is 1/2 to 3/4 of the total height of the multi-layered first epitaxial layer 21, it means that the distance from the upper surface of the substrate 10 is in the range of 1/2 to 3/4 of the total thickness of the multi-layered first epitaxial layer 21. As shown in fig. 1, the total thickness of the first epitaxial layers 21 is D, and the first epitaxial layer 21 of the first type having a thickness D1 is located between 1/2*D and 3/4*D from the upper surface of the substrate 10 with reference to the upper surface of the substrate 10. It should be noted that the above-mentioned set height range is not limited to the range of 1/2 to 3/4 of the total height of all the first epitaxial layers 21, and the size of the set height range may be specifically adjusted according to the thickness of the first epitaxial layers 21, the size of the conductive type pillars, the material, and other related factors.

In addition, referring to fig. 1 and 8, the superjunction VDMOS device may further include: a second epitaxial layer 22, a source structure, a gate structure, and a drain structure. A second epitaxial layer 22 is formed on the superjunction structure, and a semiconductor source region 42 and a semiconductor body region 41 are formed in the second epitaxial layer 22; a source structure and a gate structure are formed on the second epitaxial layer 22; a drain structure is formed on the surface of the substrate 10 facing away from the superjunction structure.

The thickness of the second epitaxial layer 22 may be equal to or not equal to the thickness of the first epitaxial layer 21. After the second epitaxial layer 22 is grown, the semiconductor source region 42 and the semiconductor body region 41 are formed by ion implantation, respectively. Semiconductor source region 42 may be an N-type source or a P-type source. The semiconductor body 41 may be an N-type body or a P-type body.

In forming the source structure on the second epitaxial layer 22, a source metal 60 may be formed on the first epitaxial layer 21, the source metal 60 electrically connecting two semiconductor source regions 42 located within the same semiconductor body region 41.

In forming the gate structure on the second epitaxial layer 22, a gate oxide layer 52 may be formed on the first epitaxial layer 21, after which a gate conductive polysilicon 53 is formed on the gate oxide layer 52, and a gate metal 51 is formed on the gate conductive polysilicon 53.

When a drain structure is formed on the surface of the substrate 10 facing away from the superjunction structure, referring to fig. 8, a drain metal 70 may be formed on the lower surface of the substrate 10 as the drain structure, to complete the preparation of the superjunction VDMOS device.

It should be noted that the above is only exemplary of the manner in which the source, gate and drain structures are fabricated, and that other manners may be employed.

In the various embodiments shown above, the gate-drain capacitance is optimized by making the doping concentration of each conductive type column in the superjunction structure in the first set height range of the superjunction structure smaller than that of the conductive type column in the second set height range, so that the gate-drain capacitance under the condition of low drain-source voltage is increased, and the phenomenon of gate-drain capacitance pit under the condition of low drain-source voltage is avoided. And in the process of preparing the super junction structure, under the condition that impurity ions are injected after a single-layer epitaxial layer is grown, the gate-drain capacitance is optimized by modifying the thickness of a specific first epitaxial layer 21 and thickening the single-layer first epitaxial layer 21 in a specific area to a first thickness range, so that the gate-drain capacitance is increased under the condition of low drain-source voltage, and the phenomenon of gate-drain capacitance pits under the condition of low drain-source voltage is avoided. The mode disclosed by the application is easy to implement without changing the overall process conditions of the super-junction VDMOS device. And compared with the traditional structure, the application has basically consistent other static and dynamic parameters and does not cause the deterioration of other performances.

In addition, referring to fig. 1 to 6, the embodiment of the application further provides a preparation method of the super junction VDMOS device, where the super junction VDMOS device includes:

providing a substrate 21;

forming a superjunction structure on the substrate 21; wherein the superjunction structure includes a first conductivity type pillar 31 and a second conductivity type pillar 32; each conductive type column penetrates through two surfaces of the super junction structure, which are opposite in the height direction, and the doping concentration of each conductive type column in a first set height range of the super junction structure is smaller than that of each conductive type column in a second set height range.

In the above scheme, the grid-drain capacitance is optimized by making the doping concentration of each conductive type column in the super junction structure in the first set height range of the super junction structure smaller than the doping concentration of each conductive type column in the second set height range, so that the grid-drain capacitance under the condition of low drain-source voltage is increased, and the phenomenon of grid-drain capacitance pit under the condition of low drain-source voltage is avoided. The steps are described in detail below with reference to the accompanying drawings.

First, referring to fig. 2, a substrate 21 is provided, and the substrate 10 is used as a structure for carrying the growth of a plurality of first epitaxial layers 21, such as, but not limited to, an N-type substrate, a P-type substrate, etc., and is particularly relevant to the type of superjunction VDMOS device. For example, in some embodiments, substrate 10 may be an N-type substrate. It should be understood that other layer structures may be provided on the substrate 10, for example, a buffer layer may be provided on the substrate 10, and the type of the buffer layer may be an N-type or P-type buffer layer, etc., which is specifically related to the type of the superjunction VDMOS device.

Next, referring to fig. 1, 2 to 6, a superjunction structure is formed on the substrate 21. Wherein the superjunction structure comprises a first conductivity type pillar 31 and a second conductivity type pillar 32. Each conductive type column penetrates through two surfaces of the super junction structure, which are opposite in the height direction, and the doping concentration of each conductive type column in a first set height range of the super junction structure is smaller than that of each conductive type column in a second set height range.

The manner in which the superjunction structure is formed on the substrate 21 may take a variety of forms, one implementation of which is described below by way of example in connection with the accompanying drawings.

Referring to fig. 2 to 6, a plurality of first epitaxial layers 21 are sequentially grown on the substrate 10, and first and second conductive type pillars 31 and 32 are formed in the uppermost first epitaxial layer 21 after each first epitaxial layer 21 is grown in the process of sequentially growing the plurality of first epitaxial layers 21 on the substrate 10. Wherein, the first conductive type pillars 31 in any two adjacent layers of the first epitaxial layers 21 are stacked, and the second conductive type pillars 32 in any two adjacent layers of the first epitaxial layers 21 are stacked. The first epitaxial layers 21 are divided into first epitaxial layers 21 of a first type and second epitaxial layers 21, wherein the thickness of each first epitaxial layer 21 in the first epitaxial layers 21 of the first type is a first thickness range, and the thickness of each first epitaxial layer 21 in the first epitaxial layers of the second type is a second thickness range, and the minimum value of the first thickness range is larger than the maximum value of the second thickness range. The first type first epitaxial layer 21 is located in a first set height range of the superjunction structure, the second type first epitaxial layer 21 is located in a second set height range of the superjunction structure, and doping amounts of each conductive type column in the first type first epitaxial layer 21 and the second type first epitaxial layer 21 are equal.

The manner in which the first epitaxial layer 21 is grown each time, and the different conductivity type pillars are formed after the first epitaxial layer 21 is grown, will be described in detail.

Referring to fig. 2, a first epitaxial layer 21 is grown on a substrate 10, and first and second conductive type pillars 31 and 32 are formed in the first epitaxial layer 21, which is just grown, at the uppermost layer. Specifically, when two different conductivity type pillars are formed in the first epitaxial layer 21, P-type ions and N-type ions are implanted into the first epitaxial layer 21, respectively, to form the first conductivity type pillars 31 and the second conductivity type pillars 32. As can be seen from fig. 3, the number of the first conductive type pillars 31 and the second conductive type pillars 32 is plural, and the plural first conductive type pillars 31 and the second conductive type pillars 32 are alternately arranged. It should be understood that fig. 3 shows only one arrangement of conductive type pillars, and that other arrangements may be used.

It should be explained that, since only a partial region of the superjunction VDMOS device is shown in cross-section in fig. 2 and 3, the partial region is shown as a region where the superjunction structure is provided. In the process of preparing the super junction structure, after each first epitaxial layer 21 is grown, a P-type ion and an N-type ion are required to be implanted into the newly grown first epitaxial layer 21 located at the uppermost layer, respectively, to form different first conductivity type pillars 31 and second conductivity type pillars 32, so fig. 3 does not show the first epitaxial layer 21, but only shows the first conductivity type pillars 31 and the second conductivity type pillars 32 formed after the P-type ion and the N-type ion are implanted.

Referring to fig. 4 and 5, a layer of the first epitaxial layer 21 is epitaxially grown again on the first epitaxial layer 21 formed with the first and second conductive type pillars 31 and 32, and the first and second conductive type pillars 31 and 32 are formed in the newly grown and uppermost layer of the first epitaxial layer 21. Referring to fig. 5, the first conductive type pillars 31 in the adjacent two first epitaxial layers 21 are stacked, and the second conductive type pillars 32 in the adjacent two first epitaxial layers 21 are stacked. When the first conductive type columns 31 and the second conductive type columns 32 in the adjacent two layers of the first epitaxial layers 21 are stacked, one P-type ion and one N-type ion can be implanted into the adjacent two layers of the first epitaxial layers 21 to form different first conductive type columns 31 and second conductive type columns 32, and the same mask patterns are used, and alignment marks at the same positions are used in different processes to align, so that the first conductive type columns 31 and the second conductive type columns 32 can be formed at the same positions basically, the first conductive type columns 31 in the adjacent two layers of the first epitaxial layers 21 are stacked, and the second conductive type columns 32 in the adjacent two layers of the second epitaxial layers 22 are stacked.

Referring to fig. 6 and 1, the above steps are repeated, and in the process of sequentially growing the plurality of first epitaxial layers 21 in the above manner, after each first epitaxial layer 21 is grown, the first conductive type pillars 31 and the second conductive type pillars 32 are formed in the newly grown first epitaxial layer 21 located at the uppermost layer until the superjunction structure as shown in fig. 1 is formed.

Referring to fig. 1, in the process of sequentially growing a plurality of first epitaxial layers 21 in the present application, the plurality of first epitaxial layers 21 are divided into a first type of first epitaxial layers 21 and a second type of first epitaxial layers 21, wherein the thickness of each first epitaxial layer 21 in the first type of first epitaxial layers 21 is in a first thickness range, and the thickness of each first epitaxial layer 21 in the second type of first epitaxial layers is in a second thickness range, wherein the minimum value of the first thickness range is greater than the maximum value of the second thickness range. That is, the thickness of some of the first epitaxial layers 21 in the plurality of first epitaxial layers 21 is within a first thickness range, and the thickness of other first epitaxial layers 21 is within a second thickness range. The first epitaxial layer 21 of the first type having a thickness D1 in fig. 1 is significantly thicker than the second epitaxial layer 21 of the second type having a thickness D2, i.e. D1 is larger than D2. The number of layers of the first epitaxial layer 21 of the first type having a thickness within the first thickness range may be one layer or two or more layers in fig. 1. Compared with the prior art, the method and the device have the advantages that the thickness of the specific first epitaxial layer 21 is modified, the thickness of the single-layer first epitaxial layer 21 in the specific area is thickened to a first thickness range, the doping amount in each layer of first epitaxial layer 21 can be controlled to be the same, so that the doping concentrations of the conductive type columns in different first epitaxial layers 21 are adjusted, the adjustment of the doping concentrations of the different conductive type columns in the height direction is realized, the grid-drain capacitance is optimized, the grid-drain capacitance of the grid-drain capacitor under the low drain-source voltage condition is increased, and the phenomenon of grid-drain capacitance pit under the low drain-source voltage is avoided.

In determining the size of the first thickness and the second thickness, the ratio of the first thickness to the second thickness may be not less than 1.2, i.e. the first thickness is at least 20% greater than the second thickness. Specifically, the ratio of the first thickness to the second thickness may be any value of 1.20, 1.25, 1.30, 1.35, 1.40, 1.45, 1.50, etc. not less than 1.2. It should be understood that the first thickness range and the second thickness range are not limited to the first thickness and the second thickness range alone, and that other thickness range arrangements may be employed. For example, the first thickness range may include at least two thickness values, and the thickness of the first epitaxial layer 21 of the first type may take any value within the first thickness range; the second thickness range may include at least two thickness values, and the thickness of the second type first epitaxial layer 21 may take any value within the second thickness range.

It should be noted that, since the first conductive type pillars 31 and the second conductive type pillars 32 are formed in the first epitaxial layer 21 newly grown and located at the uppermost layer after each first epitaxial layer 21 is grown, the thicknesses of the first conductive type pillars 31 and the second conductive type pillars 32 formed in succession are substantially equal to the thickness of the first epitaxial layer 21 where they are located. When the thickness of the first-type first epitaxial layer 21 is increased, the thicknesses of the first-conductivity-type pillars 31 and the second-conductivity-type pillars 32 formed in the first-type first epitaxial layer 21 are also increased. In the preparation process, the implantation doses of the P-type ions and the N-type ions are kept consistent on the first epitaxial layer 21 with different thicknesses, and the final thermal process push junction can be kept consistent or reduced appropriately with the previous process, so that the doping concentration of the conductive type column formed in the first epitaxial layer 21 is smaller than that of the conductive type column formed in the second epitaxial layer 21.

In determining which first epitaxial layers 21 for the plurality of first epitaxial layers 21 are the first type first epitaxial layers 21, the first type first epitaxial layers 21 may be located within a first set height range of the plurality of first epitaxial layers 21. Only the first epitaxial layer 21 located in the preset area of the plurality of first epitaxial layers 21 is thickened, and the first epitaxial layers 21 at other positions are not thickened. In a more preferred embodiment, the first set height range may be in the range of 1/2 to 3/4 of the total height of the multi-layered first epitaxial layer 21. The first type first epitaxial layer 21 is located within 1/2 to 3/4 of the total height of all the first epitaxial layers 21. The purpose of this is to make the impurity concentration of the set height region lower than that of the other regions, so that the first conductivity type pillars 31 easily form non-depleted closed regions at a lower drain-source voltage (Vds), improving the gate-drain capacitance of the superjunction VDMOS device.

After all the first epitaxial layers 21 are grown in sequence and after each first epitaxial layer 21 is grown, the first conductive type pillars 31 and the second conductive type pillars 32 are formed in the newly grown first epitaxial layer 21 located at the uppermost layer, and after the structure shown in fig. 1 is obtained, a superjunction structure in which the first conductive type pillars 31 and the second conductive type pillars 32 having a concentration approximately uniformly distributed are alternately arranged is formed by a thermal process junction pushing.

It should be noted that, since the first conductive type pillars 31 and the second conductive type pillars 32 are formed in one segment after each first epitaxial layer 21 is grown, the first conductive type pillars 31 and the second conductive type pillars 32 are formed between the first epitaxial layers 21 of different layers, and the conductive type pillars mask patterns are aligned in the manufacturing process although the alignment process is used between different processes, so that the two segments of conductive type pillars formed in the adjacent two first epitaxial layers 21 are stacked. But because the alignment process is subject to errors, there is less misalignment between adjacent conductivity type pillars.

Meanwhile, after one P-type ion and N-type ion are implanted into the first epitaxial layer 21 to form different first conductive type columns 31 and second conductive type columns 32, a junction is pushed through a thermal process, and in the junction pushing process from top to bottom, each conductive type column is located in the lower half part corresponding to the first epitaxial layer 21 and slightly narrower than the column width located in the upper half part corresponding to the first epitaxial layer 21, so that after a plurality of sections of each first conductive type column 31 which is finally formed are stacked, a first conductive type column 31 with a gourd shape like a type sugar can be generated. Similarly, after stacking the sections of each of the second conductivity-type pillars 32, the second conductivity-type pillars 32 of the type of sugar-gourd shape are also produced. In the prior art, since the thicknesses of the multi-layer epitaxial layers are uniform, the problem can be improved by controlling the time of junction pushing in the thermal process.

However, in the preparation process, the first epitaxial layer 21 is thickened, the implantation doses of P-type ions and N-type ions are kept consistent on the first epitaxial layer 21 with different thicknesses, and the final thermal process push junction can be kept consistent or reduced appropriately with the previous process, so that the widths of the lower half parts of the first conductive type columns 31 and the second conductive type columns 32 in the first epitaxial layer 21 are obviously narrower, the junction of the conductive type columns and the first conductive type columns 31 and the second conductive type columns 32 in the second epitaxial layer 21 below the junction is provided with obvious concave formed by wide-narrow connection, and the concave is under a certain low drain-source voltage, so that the gate-drain capacitance can be optimized, the gate-drain capacitance is increased, and the phenomenon of gate-drain capacitance concave under the low drain-source voltage is avoided. That is, the present application improves the gate-drain capacitance of the superjunction VDMOS device by making the impurity concentration of the set height region lower than that of the other regions, so that the first conductivity type pillars 31 easily form the non-depleted closed region at a lower drain-source voltage (Vds).

In addition, referring to fig. 7 and 8, the preparation method may further include: growing a second epitaxial layer 22 on the superjunction structure, and forming a semiconductor source region 42 and a semiconductor body region 41 in the second epitaxial layer 22; forming a source structure and a gate structure on the second epitaxial layer 22; a drain structure is formed on the surface of the substrate 10 facing away from the superjunction structure.

When the second epitaxial layer 22 is grown on the superjunction structure, the thickness of the second epitaxial layer 22 may be equal to or not equal to the thickness of the first epitaxial layer 21 of any one of the above layers. After the second epitaxial layer 22 is grown, the semiconductor source region 42 and the semiconductor body region 41 are formed by ion implantation, respectively. Semiconductor source region 42 may be an N-type source region or a P-type source region. The semiconductor body 41 may be an N-type body or a P-type body. In forming the source structure on the second epitaxial layer 22, a source metal 60 may be formed on the first epitaxial layer 21, the source metal 60 electrically connecting two semiconductor source regions 42 located within the same semiconductor body region 41.

The super-junction VDMOS device disclosed by the application is described in detail below with reference to figures 9-12, and can optimize the gate-drain capacitance, so that the gate-drain capacitance is increased under the condition of low drain-source voltage, and the principle of the phenomenon of gate-drain capacitance pit under the condition of low drain-source voltage is avoided.

In general, in the super-junction structure formed by multiple epitaxy, in order to ensure Breakdown Voltage (BV) and anti-surge capability (EAS capability), a region with P-type breakdown point, i.e., a region with P-type impurity concentration lower than that of N-type impurity concentration, is often selected in a window, but the gate-drain capacitance of the region under high drain-source voltage is smaller than that under N-type breakdown point, and the problem that the gate-drain capacitance is suddenly reduced and pit is formed easily under low drain-source voltage is solved. As shown in fig. 9, comparing the curves of the gate-drain capacitance of the partial N-type and partial P-type super junction structures with the drain-source voltage, it can be seen that the gate-drain capacitance of the partial P-type super junction structure obviously drops suddenly and forms a pit under the low drain-source voltage in the area defined by the dotted line. The gate-drain capacitor pit and the low gate-drain capacitor are easy to cause high voltage change rate (dV/dt) in a switch test, so that the drain-source voltage and the driving voltage (Vgs) of the MOS tube vibrate, the high current change rate (dI/dt) and the source-drain current (Ids) vibrate, and the source-drain current voltage peak and the like occur.

In the process of preparing the super junction structure, under the condition of not changing the process of implanting impurity ions after growing a single-layer epitaxial layer, the thickness of a specific first epitaxial layer 21 is modified, the single-layer first epitaxial layer 21 in a specific area is thickened to a first thickness range, and as part of the first epitaxial layer 21 is thickened, the column widths of the lower half parts of the first conductive type column 31 and the second conductive type column 32 in the first epitaxial layer 21 are obviously narrower, so that the connection part of the conductive type column and the first conductive type column 31 and the second conductive type column 32 in the second epitaxial layer 21 below the connection part is provided with obvious concave formed by connecting the width, and the concave part is under a certain low drain-source voltage, so that the gate-drain capacitance can be increased. In addition, the doping concentration of each conductive type column in the height direction is not uniform, but the doping concentration in the first set height range is smaller than that in the second set height range, so that the resistivity of each conductive type column in the first set height range is larger than that in the second set height range. Through the mode, the grid-drain capacitance is optimized, so that the grid-drain capacitance is increased under the condition of low drain-source voltage, and the phenomenon of grid-drain capacitance pits under the condition of low drain-source voltage is avoided. Namely, under the condition of not changing the single-layer injection condition, the application optimizes the grid leakage capacitance by modifying the thickness of the specific first epitaxial layer 21, and improves the phenomenon of grid leakage tolerance when the P is biased.

Taking a super junction structure with a drain-source voltage of 600V as an example, in the traditional preparation method, the thicknesses of the multiple epitaxial layers are opposite, the ion implantation conditions are consistent each time, and the super junction structure similar to a sugarcoated haw structure is formed by pushing the junction through a final thermal process. The following exemplary description describes a fabricated superjunction VDMOS device, where the first conductive type pillar 31 is a P-type doped pillar, the second conductive type pillar 32 is an N-type doped pillar, the substrate 10 is an N-type substrate, and the doping concentration of the first conductive type pillar 31 is greater than the doping concentration of the second conductive type pillar 32, i.e., the superjunction VDMOS device is a P-type superjunction VDMOS device. By adopting the preparation method, the single-layer first epitaxial layer 21 of the preset area of the super junction structure formed by multiple epitaxy is thickened. The doping concentration of each conductive type column in the height direction is not uniform, but the doping concentration in the first set height range is smaller than that in the second set height range, so that the resistivity of each conductive type column in the first set height range is larger than that in the second set height range. By the mode, the depletion speed and the depletion shape of the PN junction under the low drain-source voltage can be changed, so that the problem that the gate-drain capacitance drops too fast under the low drain-source voltage is solved; meanwhile, the problem of small gate-drain capacitance under high drain-source voltage can be solved. Illustratively, referring to fig. 1, six first epitaxial layers 21 in the present application are formed, and four first epitaxial layers 21 from bottom to top are formed to have a thickness d2=5um, and the four first epitaxial layers 21 are the second type first epitaxial layers 21. Thereafter, the first epitaxial layer 21 having the thickness D1 is regrown to a thickness of 6um, and this layer of first epitaxial layer 21 is the second type of first epitaxial layer 21. Then, a first epitaxial layer 21 with a thickness of D2 is grown, and the first epitaxial layer 21 is a second type first epitaxial layer 21. After the superjunction structure shown in fig. 1 is prepared, the amplitude of single-layer thickening is 20% through simulation verification of sentaurus_tcad (a simulation software), and the position of the single-layer thickening is more preferable in a 1/2-3/4 height area from bottom to top in the superjunction area.

Aiming at the existing partial P type super junction structure and the partial P type super junction structure shown in the application, TCAD simulation is carried out under the same N/P condition, and under the condition that the same partial P and the breakdown voltage are basically consistent, the obtained curve of the gate-drain capacitance along with the drain-source voltage is shown in figure 10. As can be seen from fig. 10, the partial P-type super junction structure prepared by the preparation method of the application obviously improves the pit phenomenon at the position of drain-source voltage vds=50v, and obviously improves the gate-drain capacitance of the drain-source voltage at 50-300V, the capacitance in the interval improves the variation rate (dV/dt) of high voltage, drain-source voltage, gate-source voltage (Vgs) and drain-source current (Ids) in the switching process of the super junction VDMOS device, and the stability of the super junction VDMOS device is improved to a certain extent.

In addition, in order to more clearly describe the principle of avoiding the phenomenon of gate drain capacitance pit under low drain-source voltage, the application also carries out cloud pattern simulation on the depletion condition of the driving voltage vgs=0v of the MOS tube under 30V, 40V, 50V and 60V of the drain-source voltage Vds aiming at the existing P-type super junction structure and the P-type super junction structure shown by the application, and respectively obtains fig. 11 and 12. FIG. 11 is a simulation graph of the drain-source voltage variation of the depletion line of the existing partial P-type super junction structure; fig. 12 is a simulation diagram showing a drain-source voltage variation of a depletion line of a partial P-type super junction structure according to an embodiment of the present application.

As can be seen from fig. 11 and 12, the N pillars (second conductivity type pillars 32) of both (the existing P-type superjunction structure and the P-type superjunction structure of the present application) are depleted at 60V to the bottom, which corresponds to the gate-drain capacitance being reduced to the lowest point at around 60V. But between 30-50V, a large difference was found between the depletion of the P-pillars (first conductivity type pillars 31), the existing P-type superjunction structure, and the P-type superjunction structure of the present application. In the P-type super junction structure of the present application, when the depletion line of the P column (the first conductive type column 31) is 40-50V, the depletion pinch-off occurs in the region of the first epitaxial layer 21 of the first type, so that a Floating region (Floating region) appears in the region below the P column (the first conductive type column 31), the potential of the Floating region will be the same as the surrounding potential, and the potential of the region above fig. 12, which is communicated with the semiconductor Source region 42, is 0V, which causes the electric field at the bottom of the N column (the second conductive type column 32) to be more directed to the non-depleted region below the semiconductor Source region 42 (Source region) and to the Junction Field Effect Transistor (JFET) region in the process of continuing depletion, and less directed to the Floating region, which is why the gate-drain capacitance of the structure of the present patent drops more slowly and the lowest peak point is higher with the rise of the drain-Source voltage than the existing P-type super junction structure. The principle of how the application avoids the phenomenon of gate drain capacitance pit under low drain-source voltage can be better understood through the above description.

It should be noted that, when the present application is applied to an N-type super junction structure, the first conductive type pillars 31 are P-type doped pillars, the second conductive type pillars 32 are N-type doped pillars, and the doping concentration of the second conductive type pillars 32 is greater than that of the first conductive type pillars 31. According to the application, by modifying the thickness of the specific first epitaxial layer 21, the single-layer first epitaxial layer 21 in the specific area is thickened to a first thickness range, and as part of the first epitaxial layer 21 is thickened, the column widths of the lower half parts of the first conductive type columns 31 and the second conductive type columns 32 in the first epitaxial layer 21 are obviously narrower, so that the connection part of the conductive type columns and the first conductive type columns 31 and the second conductive type columns 32 in the second epitaxial layer 21 below the connection part is provided with obvious concave formed by wide-narrow connection, and the concave is specific to an N-type super junction structure. In addition, the doping concentration of each conductive type column in the height direction is not uniform, but the doping concentration in the first set height range is smaller than that in the second set height range, so that the resistivity of each conductive type column in the first set height range is larger than that in the second set height range. By the mode, the gate-drain capacitance can be still increased under certain low drain-source voltage, so that the gate-drain capacitance is optimized, the gate-drain capacitance under the low drain-source voltage condition is increased, and the phenomenon of gate-drain capacitance pit under the low drain-source voltage is avoided.

In addition, the application also provides electronic equipment which comprises the super junction VDMOS device. The electronic device may specifically be a mobile terminal such as, but not limited to, a smart phone, a tablet computer, a notebook computer, an intelligent wearable device, a bluetooth headset, etc., and may also be a terminal device such as, but not limited to, a vehicle-mounted terminal, an industrial personal computer, etc. In the process of preparing the superjunction structure of the superjunction VDMOS device, under the condition that impurity ions are injected after a single-layer epitaxial layer is grown, the gate-drain capacitance is optimized by modifying the thickness of a specific first epitaxial layer 21 and thickening the single-layer first epitaxial layer 21 in a specific area to a first thickness range, so that the gate-drain capacitance is increased under the condition of low drain-source voltage, and the phenomenon of gate-drain capacitance pits under the condition of low drain-source voltage is avoided. The mode disclosed by the application is easy to implement without changing the overall process conditions of the super-junction VDMOS device. And compared with the traditional structure, the application has basically consistent other static and dynamic parameters and does not cause the deterioration of other performances.

The present application has been illustrated by the above-described embodiments, but it should be understood that the above-described embodiments are for purposes of illustration and description only and are not intended to limit the application to the embodiments described. In addition, it will be understood by those skilled in the art that the present application is not limited to the embodiments described above, and that many variations and modifications are possible in light of the teachings of the application, which variations and modifications are within the scope of the application as claimed. The scope of the application is defined by the appended claims and equivalents thereof.

Claims

1. A superjunction VDMOS device, comprising:

a substrate;

a superjunction structure formed on the substrate; wherein the superjunction structure comprises a first conductivity type pillar and a second conductivity type pillar; each conductive type column penetrates through two surfaces of the super junction structure, which are opposite in the height direction, and the doping concentration of each conductive type column in a first set height range of the super junction structure is smaller than that of each conductive type column in a second set height range.

2. The superjunction VDMOS device of claim 1, wherein the first set height range is 1/2-3/4 of the height range of the superjunction structure;

the second set height range is other height ranges in the super junction structure except the first set height range.

3. The superjunction VDMOS device of claim 1, wherein the first conductivity-type pillars are P-type doped pillars and the second conductivity-type pillars are N-type doped pillars.

4. The superjunction VDMOS device of claim 3, wherein the doping concentration of the first conductivity type pillars is greater than the doping concentration of the second conductivity type pillars.

5. The superjunction VDMOS device of claim 1, wherein the substrate is an N-type substrate.

6. The superjunction VDMOS device of any of claims 1-5, further comprising a plurality of first epitaxial layers; the plurality of first epitaxial layers are sequentially laminated on the substrate; wherein the first conductive type column and the second conductive type column are formed in each layer of the first epitaxial layer; the first conductive type columns in any two adjacent layers of the first epitaxial layers are arranged in a stacked mode, and the second conductive type columns in any two adjacent layers of the first epitaxial layers are arranged in a stacked mode;

the multi-layer first epitaxial layer is divided into a first epitaxial layer of a first type and a second epitaxial layer of a second type, the thickness of each first epitaxial layer in the first epitaxial layer of the first type is a first thickness range, and the thickness of each first epitaxial layer in the first epitaxial layer of the second type is a second thickness range; the first epitaxial layer of the first type is positioned in the first set height range of the super junction structure, and the first epitaxial layer of the second type is positioned in the second set height range of the super junction structure;

The minimum value of the first thickness range is larger than the maximum value of the second thickness range, the doping amount of each first-type conductive column in the first-type first epitaxial layer and the doping amount of each second-type conductive column in the second-type first epitaxial layer are equal.

7. The superjunction VDMOS device of claim 6, wherein the first thickness range is a first thickness and the second thickness range is a second thickness;

wherein the ratio of the first thickness to the second thickness is not less than 1.2.

8. The superjunction VDMOS device of claim 1, further comprising:

the second epitaxial layer is formed on the super junction structure, and a semiconductor source region and a semiconductor body region are formed in the second epitaxial layer;

a source electrode structure and a grid electrode structure which are both formed on the second epitaxial layer;

and the drain electrode structure is formed on the surface of the substrate, which faces away from the super junction structure.

9. The preparation method of the super junction VDMOS device is characterized by comprising the following steps of:

providing a substrate;

forming a superjunction structure on the substrate; wherein the superjunction structure comprises a first conductivity type pillar and a second conductivity type pillar; each conductive type column penetrates through two surfaces of the super junction structure, which are opposite in the height direction, and the doping concentration of each conductive type column in a first set height range of the super junction structure is smaller than that of each conductive type column in a second set height range.

10. The method of manufacturing of claim 9, wherein forming a superjunction structure on the substrate comprises:

forming the first conductive type column and the second conductive type column in the uppermost first epitaxial layer after each first epitaxial layer is grown in the process of sequentially growing a plurality of first epitaxial layers on the substrate; the first conductive type columns in any two adjacent layers of the first epitaxial layers are arranged in a stacked mode, and the second conductive type columns in any two adjacent layers of the first epitaxial layers are arranged in a stacked mode;

the multi-layer first epitaxial layer is divided into a first epitaxial layer and a second epitaxial layer, the thickness of each first epitaxial layer in the first epitaxial layer is in a first thickness range, and the thickness of each first epitaxial layer in the second epitaxial layer is in a second thickness range; the first epitaxial layer of the first type is positioned in the first set height range of the super junction structure, and the first epitaxial layer of the second type is positioned in the second set height range of the super junction structure;

11. An electronic device, comprising: a superjunction VDMOS device as claimed in any of claims 1 to 8.