CN1411607A - 把msq粘附到衬里氧化物的方法和结构 - Google Patents

把msq粘附到衬里氧化物的方法和结构 Download PDF

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CN1411607A
CN1411607A CN01802450A CN01802450A CN1411607A CN 1411607 A CN1411607 A CN 1411607A CN 01802450 A CN01802450 A CN 01802450A CN 01802450 A CN01802450 A CN 01802450A CN 1411607 A CN1411607 A CN 1411607A
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CN1241249C (zh
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R·V·安纳普拉加达
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Abstract

在半导体基板上沉积衬里电介质的方法保证了用亚微米工艺在金属层之中低介电常数旋压材料的足够的粘附。在实施例中，该方法保证把MSQ粘附在衬里氧化物在半导体基板上的铝合金层上。首先，将基板放入PECVD环境中。把三甲基硅烷和N2O的气体混合物导入PECVD环境中，三甲基硅烷与N2O的比例大约为1∶20－1∶30。气体混合物起反应，沉积一预定厚度的氧化物衬里。把三甲基硅烷与N2O气体混合物的比例调到大约1∶3－1∶7，经过5－20秒钟，持续反应，由此沉积甲基掺杂氧化物。

Description

把MSQ粘附到衬里氧化物的方法和结构
发明领域
一般而言，本发明针对半导体器件的制造。具体而言涉及提供把甲基硅倍半氧烷(MSQ)膜粘附到衬里氧化物的改进的工艺。
发明背景
当器件尺寸降到亚微米水平时，电气特性变得非常显著，如在尺寸为数微米器件中可忽略的电容。例如，在亚0.2μm工艺里，低介电常数(例如“low K”)材料已有了更新的意义。
加工亚微型器件的目的是在栅-源和栅-漏电容最小化的同时保持栅电容的水平。当氧化物被做得很薄时。电容就增加，如下面关系式： C ox = ϵ 0 ϵ SiO 2 t os · A ,
其中：A＝栅极面积
      εsio2＝介电常数(或sio2相对介电常数取3.9)
      tox＝氧化物厚度
由于米勒效应，在切换过程中，栅—漏电容被放大，栅—漏电容对晶体管性能尤其关键。例如在一系列的逻辑阶段中，对前逻辑阶段的等效电容负载为栅—源电容乘以1加上晶体管增益。如果晶体管具有增益为100，观察到的输入电容为101乘以栅—漏电容。当然，最好是不改变增加电容的参数。因此，使用具有更低的介电常数的电介质降低了电容。在整个集成电路设计中使用更低K材料是有利的，该设计可能使寄生电容最小化。
对亚0.25微米和更小的器件的低K材料的需求已经更新了旋压电介质如甲基硅倍半氧烷(MSQ)和氢硅倍半氧烷(HSQ)的意义。MSQ的介电常数为～2.9。MSQ的经验公式是CH3SiO1.5。在碱性的O-Si-O主架上附加有机侧基，其结果改善了该膜的抗裂性。该结构比SiO2具有较低的密度，因此有较低的介电常数。
在一个工艺例子中，要使MSQ一体化变成一种低K的电介质是困难的。由于表面甲基基团的存在，MSQ和PECVD(增强的等离子体化学汽相沉积)氧化物不能很好地相互粘附。该材料中有效的甲基含量高达约25％。甲基基团的存在使该膜具有疏水性，因为通过破坏Si-CH3键而形成SiOH键是困难的。
图1描绘了有110条金属丝的基板100。MSQ130从衬里氧化物120的剥离可能降低器件的性能。
这就需要保证MSQ与PECVD氧化物的粘附，能用这种低K材料防止剥离，以改进器件合格率和产品性能。
发明概述
本发明要用很多实施例来说明，下面简述其中之一。当把MSQ用作间隙填充材料时要获得MSQ与铝合金的足够粘附是困难的。用衬里电介质可以改善粘附，该电介质一方面呈现与铝有良好的粘附，还与MSQ也有良好的粘附。无论如何，如果衬里电介质与MSQ之间有突变的界面，MSQ层可能会剥离。在二氧化硅与甲基掺杂氧化物之间的衬里电介质上制成过渡层，每个膜分别与铝合金和MSQ提供足够的粘附。
在半导体基板上沉积衬里电介质的方法保证了低K旋压材料的足够粘附。在实施例中，在半导体基板上有一种往金属层上粘附旋压电介质的方法。第一预定厚度的衬里电介质被沉积在金属层上。衬里电介质与金属层有化学亲和力。第二预定厚度的过渡层形成于衬里电介质上；过渡层与金属层有较小的化学亲和力，随着过渡层厚度的增加，它与旋压电介质的化学亲合力也增加。第三预定厚度的衬里电介质被沉积在过渡层上；衬里电介质与旋压电介质有化学亲和力。
在另一个实施例中，粘附硅倍半环氧乙烷化合物的方法提供了在半导体基板上铝合金金属层上的衬里电介质，该方法包括把半导体基板放在CVD环境中。含有前体气体和N2O的气体混合物导入CVD环境中。预先确定前体气体和N2O的比例。气体混合物发生反应，以沉积预定厚度的衬里电介质。该实施方案的另一个特点是：在气体混合物反应期间，前体气体与N2O的比例可以调节，以便把二氧化硅沉积在第一预定厚度的铝合金金属层上。通过再调节前体气体与N2O的比例，第二预定厚度的甲基掺杂氧化物沉积在第一预定厚度的二氧化硅上。因此，该实施方案另一个特点就是：再调节前体气体与N2O的比例，在从二氧化硅区到甲基掺杂氧化物区的衬里电介质里产生一个过渡层。
本发明以上概述并不打算叙述本发明的每个公开的实施方案或各方面。本发明的其它方面和实施例由下面的附图和详细描述给出。
附图简要描述
通过对本发明相关附图的不同实施方案的详细描述，可以更完整地了解本发明。其中：
图1是描述MSQ从衬里氧化物剥离的器件结构的剖面图；
图2A是在衬里氧化物沉积处器件结构的剖面图；
图2B是根据本发明的实施方案在衬里氧化物上形成甲基掺杂氧化物过渡层之后的图2A；
图2C描述MSQ沉积之后的图2B；以及
图2D描述覆盖氧化物之后的图2C。
然而，本发明对各种变更和可变的形式很敏感，所以通过附图中的例子，已经显示了具体的实施方案，并在这里进行详细说明。
详细说明
本发明已经找到在衬里氧化物和MSQ旋压材料之间提供更可靠的粘附方面有关的有用的、便利的方法。在下面讨论中，用MOS结构来描述本发明的实施例。然而，本发明并不局限于此。
在依据本发明的实例工艺中，在半导体基板上沉积衬里氧化物之后，在其上形成过渡层。过渡层为MSQ和衬里氧化物之间提供了桥梁。在过渡层与衬里氧化物接触的一面，其物理性质和化学性质与衬里氧化物类似。在过渡层与MSQ接触的另一面，过渡层的化学性质和物理性质与MSQ类似。因为过渡层里的这些性质与MSQ/过渡层和衬里氧化物/过渡层界面处的性质相匹配，所以在随后的处理界面之间性质失配时不存在界面突变问题。图2A-2D描述了一系列改进MSQ与衬里氧化物粘附的步骤。
参见图2A，半导体基板200处于制作金属沉积阶段，在组件下面，如晶体管、电阻(未示出)用金属丝210相互连接。每个设计规则都要求给定的工艺，各金属丝210相互间至少要隔开最小的距离。金属丝之间的间隔230一般用电介质填充。当器件尺寸减小时，需要把电容减到最小，且使用低K电介质如MSQ或HSQ。
根据本发明的一个实施例，在使用旋压电介质之前，把半导体基板放在增强型等离子体化学汽相沉积(PECVD)室里。过渡衬里氧化物可使用三甲基硅烷或四甲基硅烷作为形成甲基掺杂氧化膜的前体而制成。基板上无论是沉积氧化物还是甲基掺杂氧化物，均由三甲基硅烷与N2O的比例决定。在高的N2O流量下，形成二氧化硅层220a，并以约250的厚度镀到铝金属上。二氧化硅对铝金属丝粘附良好。
依靠沉积工艺化学，硅—氧比例可以改变。例如，本工艺可以形成“富硅”氧化物，SiO。为了计入化学计量学的变化，把公式描述成SixOy是合适的。
参见图2B，在沉积的后期，N2O逐渐减少，在衬里形成250的甲基掺杂氧化物220b。二氧化硅220a和甲基掺杂氧化物220b之间的过渡是渐进的。沉积后，基板从室内移出。
在另一个工艺例子里，二氧化硅层220a在分离室里形成，甲基掺杂氧化物220b可在另一个分离室内形成。
完成氧化物220a和甲基掺杂氧化物220b的过渡衬里氧化物沉积，可使用旋压MSQ或HSQ。参考图2C。MSQ层240填充金属丝210之间的间隙230。参考图2D。在MSQ层240上，用氧化层250覆盖。遵照具体工艺要求，氧化物罩层240被平整，以使器件可被进一步处理。若在器件的设计中使用另一个金属层，可重复前面提到的工艺，以使低K电介质在金属丝之间应用。
根据本发明的一个工艺例子，PECVD室可以是许多生产厂商诸如Applied Materials或Novellus的产品。在温度约为150℃-400℃，压力约2-10托，RF功率范围约在50-250瓦的情况下，SiO2被沉积在金属上。SiO2是由一种前体气体，三甲基硅烷SiH(CH3)3或四甲基硅烷SiH(CH3)4与N2O以约1∶20-1∶30的比例结合而制备成的。前体气体流量率约为10-60sccm，和约200-1800sccm。在衬里氧化物沉积了约100-1000后，气体混合物过渡需经过3-25秒钟。
完成过渡后，沉积甲基掺杂氧化物。前体气体三甲基硅烷，SiH(CH3)3或四甲基硅烷，SiH(CH3)4与N2O的比例约为大约1∶3至大约1∶7。前体气体流量率范围约为10-60sccm，N2O流量率范围约为30-360sccm。
虽然用几个具体实施例对本发明进行了描述，本领域的技术人员将认识到在不违背本发明的精神和范围的情况下会做出很多变化，在权利要求条款中作出规定。

Claims (10)

1.一种半导体器件，该器件包括形成图案的金属层、第一衬里电介质层、第二衬里电介质层和旋压电介质层，第二衬里电介质层比第一衬里电介质层具有对金属更小的化学亲和力和对旋压电介质层更强的化学亲和力。
2.依据权利要求1的半导体器件，其特征在于第一衬里电介质从一组二氧化硅、富硅氧化物和SixOy中选取，其中x＝1，0.48≤y≤2，且第二衬里电介质是甲基掺杂氧化物。
3.依据权利要求1或2的半导体器件，其特征在于在第一和第二衬里电介质层之间存在过渡层，该过渡层成份从第一衬里电介质到第二衬里电介质进行变化，成份变化方向为从金属层到旋压电介质层。
4.依据权利要求1-3的半导体器件，其中第一和第二衬里电介质层的每一个厚度范围在5-100nm。
5.依据权利要求3或4的半导体器件，其中过渡层厚度范围在10-200nm。
6.依据权利要求1或2的半导体器件，其特征在于旋压电介质包括至少下列之一：甲基硅倍半氧烷，氢硅倍半氧烷。
7.一种制造半导体器件的方法，其中将旋压电介质粘附于金属层的方法，该方法的特征在于包括如下步骤：
在金属层上沉积第一衬里电介质层；
在第一衬里电介质层上形成过渡层；
在过渡层上沉积第二衬里电介质层；
提供旋压电介质，第二衬里电介质比第一衬里电介质具有对金属较弱的化学亲和力和对旋压电介质较强的化学亲和力。
8.如权利要求7所要求的方法，其特征在于第一和第二衬里电介质层是使用前体气体，由增强型等离子体化学汽相沉积(PECVD)或化学汽相沉积(CVD)来沉积，前体气体与氧化氮(N2O)按预先确定的比例混合而成。
9.如权利要求8所要求的方法，其特征在于将产生第一衬里电介质的预定比例逐渐变化到产生第二衬里电介质，由此形成过渡层。
10.根据权利要求9的方法，其中为了形成第一衬里电介质，前体气体与N2O的预定比例范围在1∶20-1∶30，为了形成第二衬里电介质，其预定比例范围在1∶3-1∶7。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103199080B (zh) * 2012-01-05 2016-04-27 国际商业机器公司 用于互连结构的层间电介质堆叠及其形成方法
CN105593157A (zh) * 2013-10-02 2016-05-18 卡文迪什动力有限公司 用于实现电介质与有机材料之间的良好粘附的方法

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100292409B1 (ko) * 1999-05-24 2001-06-01 윤종용 실리콘-메틸 결합을 함유하는 절연층을 포함하는 다층 구조의 절연막 및 그 형성방법
US6753258B1 (en) * 2000-11-03 2004-06-22 Applied Materials Inc. Integration scheme for dual damascene structure
US7208426B2 (en) * 2001-11-13 2007-04-24 Chartered Semiconductors Manufacturing Limited Preventing plasma induced damage resulting from high density plasma deposition
US6992003B2 (en) * 2003-09-11 2006-01-31 Freescale Semiconductor, Inc. Integration of ultra low K dielectric in a semiconductor fabrication process
US6903004B1 (en) 2003-12-16 2005-06-07 Freescale Semiconductor, Inc. Method of making a semiconductor device having a low K dielectric
US7547643B2 (en) * 2004-03-31 2009-06-16 Applied Materials, Inc. Techniques promoting adhesion of porous low K film to underlying barrier layer
US20060038293A1 (en) * 2004-08-23 2006-02-23 Rueger Neal R Inter-metal dielectric fill
US7375027B2 (en) 2004-10-12 2008-05-20 Promos Technologies Inc. Method of providing contact via to a surface
WO2006086661A2 (en) * 2005-02-10 2006-08-17 Above Sea Level, Llc Lead generation method and system
JP5112668B2 (ja) * 2006-09-22 2013-01-09 財団法人高知県産業振興センター 半導体装置の製法
JP2008294123A (ja) * 2007-05-23 2008-12-04 Nec Electronics Corp 半導体装置及び半導体装置の製造方法
US7927990B2 (en) * 2007-06-29 2011-04-19 Sandisk Corporation Forming complimentary metal features using conformal insulator layer

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5114757A (en) * 1990-10-26 1992-05-19 Linde Harold G Enhancement of polyimide adhesion on reactive metals
US5616202A (en) * 1995-06-26 1997-04-01 Dow Corning Corporation Enhanced adhesion of H-resin derived silica to gold
EP0881678A3 (en) * 1997-05-28 2000-12-13 Texas Instruments Incorporated Improvements in or relating to porous dielectric structures
JP3277990B2 (ja) * 1997-10-23 2002-04-22 日本電気株式会社 半導体装置の製造方法
JP3193335B2 (ja) * 1997-12-12 2001-07-30 松下電器産業株式会社 半導体装置の製造方法
US6034420A (en) * 1997-12-18 2000-03-07 Advanced Micro Devices, Inc. Electromigration resistant patterned metal layer gap filled with HSQ
US6054379A (en) * 1998-02-11 2000-04-25 Applied Materials, Inc. Method of depositing a low k dielectric with organo silane
US6153512A (en) * 1999-10-12 2000-11-28 Taiwan Semiconductor Manufacturing Company Process to improve adhesion of HSQ to underlying materials

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103199080B (zh) * 2012-01-05 2016-04-27 国际商业机器公司 用于互连结构的层间电介质堆叠及其形成方法
CN105593157A (zh) * 2013-10-02 2016-05-18 卡文迪什动力有限公司 用于实现电介质与有机材料之间的良好粘附的方法
US9908774B2 (en) 2013-10-02 2018-03-06 Cavendish Kinetics, Inc. Method for achieving good adhesion between dielectric and organic material
CN105593157B (zh) * 2013-10-02 2018-03-20 卡文迪什动力有限公司 用于实现电介质与有机材料之间的良好粘附的方法

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