CN1319163C - Semiconductor package with radiating fins - Google Patents
Semiconductor package with radiating fins Download PDFInfo
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- CN1319163C CN1319163C CNB031561357A CN03156135A CN1319163C CN 1319163 C CN1319163 C CN 1319163C CN B031561357 A CNB031561357 A CN B031561357A CN 03156135 A CN03156135 A CN 03156135A CN 1319163 C CN1319163 C CN 1319163C
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- Prior art keywords
- fin
- semiconductor package
- package part
- substrate
- protrusion unit
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/163—Connection portion, e.g. seal
- H01L2924/16315—Shape
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The present invention relates to a semiconductor package member with a heat sink, which comprises a base board with a first surface and a relative second surface, at least one chip, a plurality of welding balls, a heat sink and an adhesive material, wherein the chip is connected to the first surface of the base board and is electrically connected to the base board; the welding balls are connected to the second surface of the base board; the heat sink has a flat part and a supporting part extending from the edges of the flat part. The heat sink is connected to the first surface of the base board by the supporting surface of the supporting part; a concave part is arranged on the supporting surface; at least one protuberant unit is arranged on the surface of the concave part. The adhesive material is laid between the supporting part and the base board. Consequently, the adhesive force between the heat sink and the base board is greatly enhanced unit under the condition without increasing manufacturing cost by the adhesive material filled in the concave part and coated around the protuberant; thus, the heat sink can not be easily desquamated when vibrated, and the structural design can also not influence the layout of lines on the base board and result in chip rupture.
Description
Technical field
The invention relates to a kind of semiconductor package part with fin, particularly about a kind of can the semiconductor package part with fin of firm bonding fin to avoid it to come off.
Background technology
Flip chip ball grid array (Flip-Chip Ball Grid Array, FCBGA) semiconductor package part is a kind of encapsulating structure that has flip-chip and ball grid array simultaneously, the active surface (Active Surface) of at least one chip is electrically connected on the surface of substrate (Substrate) by a plurality of solder joints (Solder Bumps), and on another surface of substrate, plants a plurality of soldered balls (Solder Ball) as I/O (I/O) end; This encapsulating structure can significantly reduce volume, has also removed the design of existing bonding wire (Wire) simultaneously, can reduce impedance, improve electrically, fails in transmission course to avoid signal, has therefore become the main flow encapsulation technology of chip and electronic building brick.
Because the advantageous characteristic of flip chip ball grid array encapsulation, it is used in the multicore chip package of high integration (Integration) more, with volume and the computing demand that satisfies this electronic building brick, but because the high-frequency computation performance of this electron-like assembly, make its heat that in running, produces than general packaging part height, therefore, whether radiating effect well becomes the important key that influences this class encapsulation technology rate best in quality; Existing flip chip ball grid array packaging part is on the passive surface (Non-active Surface) that directly fin (Heat Sink) is covered at chip, and do not transmit heat by the relatively poor packing colloid (Encapsulant) of thermal conductivity, thereby form the direct heat dissipation path in chip-adhesive-fin-external world, reach than the better radiating effect of other packaging part.
For this class encapsulating structure, in the prior art, be directly fin to be bonded on the substrate with adhesive (Adhesive) or scolder adhesive materials such as (Solder), and the area that makes fin is greater than area of chip, and to reach preferable radiating effect, for example United States Patent (USP) the 5th, 311, No. 402 cases, the 5th, 396, No. 403 cases, the 5th, 931, No. 222 cases, the 5th, 637, No. 920 cases, the 5th, 650, No. 918 cases or the 6th, 011, No. 304 case disclosed; But, at this sticking actual bond area between fin and substrate and little in the method for putting, limited its bonding steadiness, especially when also connecing on the substrate when being equipped with other passive component that improves its electrical property efficiency (Passive Component), reduced the bond area of substrate and fin more, make fin very easily when subsequent impacts test (Shock Test) or the vibrations of other external force, bear a shearing force and come off.
For addressing this is that, United States Patent (USP) the 6th, 093, No. 961 case also discloses a kind of package structure, strengthen the joint steadiness of fin mechanically, as shown in figure 11, edge designs rubber-like at fin 50 colludes shape leg 51, mode with clamping is fastened on fin 50 on the chip 52, with the joint steadiness of raising fin 50, yet this design is only considered the firm of fin 50, but cause the bigger destruction of packaging part, this be because the thermal coefficient of expansion of fin 50 and chip 52 (Coefficient ofThermal Expansion CTE) differs greatly, thus the contact surface 53 of fin 50 with collude shape leg 51 very easily in follow-up high-temperature process or reliability test, because of the thermal deformation measures of dispersion of itself and chip 52 chip 52 of extruding, and then cause break (Crack) of chip 52.
In sum, how under the situation of the contact area that reduces fin and chip, to strengthen the adhesion strength of this fin, it is an important R﹠D direction, therefore, the somebody proposes several and locatees the method for attachment of fin with adding fixture, United States Patent (USP) the 5th as shown in figure 12,396, No. 403 cases promptly are to offer location hole 62,63 respectively on the correspondence position of fin 60 and substrate 61, are embedded wherein with bolt 64, to avoid coming off of fin 60, United States Patent (USP) the 5th, 926, No. 371 case has also disclosed approximate method of attachment; Except the above-mentioned mode that is spirally connected, the structure of also useful fastener location fin, for example United States Patent (USP) the 6th, 441, No. 485 cases, as shown in figure 13, promptly be that the hook arrangement 71 that will be arranged on fin 70 edges is embedded in the hole 73 on substrate 72, with location fin 70.
Yet, above-mentioned various usefulness are added the existing structure of fixture location fin, its common ground is to offer hole on the reservation area on the substrate, this design can reduce available configuration area on the substrate, also increased simultaneously substrate manufacturing costs, if and this hole invaded by extraneous moisture or pollutant, can't predict the acceptance rate of packaging part in operation.
Therefore, relevant improvement develops with the direction of strengthening its adhesion to changing heat sink design gradually, to avoid in fixing cooling fins, undermining the original function of chip and substrate, Figure 14 promptly is the packaging part cutaway view of wherein a kind of design, be characterized on the surface of substrate 81 contacts, offering groove 82 at fin 80, by the filling of adhesive material 83 in groove 82, increase the contact area of fin 80 and adhesive material 83, and then improve the anchorage of fin 80; Yet, the fin adherence that this class design provides is only a little more than the mode that directly fin is covered on substrate, be difficult to deal with the subsequent impacts test and transport the vibration environment of process, still can't solve the problem that fin comes off, also do not meet user's needs.
Recent development then is to do an improvement at the design of Figure 14, as shown in figure 15, change the groove on the fin into a dovetail slot type groove structure 91, make the bore of its openend be slightly less than the inwall bore, to strengthen adhering to of fin 90, this design has improved the adhesion effect of fin 90 really, but still can not satisfy the needs of volume production, this be because, in the jig that existing machinery is made, forming bore, to have continually varying convergent or cumulative groove be a difficult problem on making, still more as the microsize technical field as the semiconductor packages, therefore, though dovetail groove structure 91 shown in Figure 15 has theoretic effect, but its operation implements but very difficulty, and precision also is difficult to control, and difficulty satisfies volume production scale and its cost demand.
Course of reforms by above-mentioned prior art can be found, if the problem at the adhesion of enhance heat sheet improves, other operation of having derived again when solving existing issue limits, though perhaps can overcome all difficult problems, but expend high process cost, be difficult to carry out commerce and implement, so there is not a kind of settling mode that can fully meet industry demand all the time.
In sum, how to develop a kind of semiconductor package part with fin, fin is unlikely to come off to make, and also can take into account the simple and demand with low cost of operation simultaneously, the acceptance rate of also unlikely reduction chip and substrate is the problem that relevant research and development field need urgently be faced.
Summary of the invention
For overcoming the shortcoming of above-mentioned prior art, the object of the present invention is to provide a kind of can the semiconductor package part with fin of firm bonding fin to avoid it to come off.
An also purpose of the present invention is to provide a kind of operation simple and have a semiconductor package part with fin of fin locking function.
Another object of the present invention is to provide a kind of semiconductor package part that has fin cheaply.
A further object of the present invention is to provide a kind of unlikelyly influences configuration on the substrate and the semiconductor package part with fin that can firm bonding fin.
Another purpose of the present invention is to provide a kind of unlikely semiconductor package part with fin that causes chip rupture.
For reaching above-mentioned and other purpose, the semiconductor package part with fin provided by the invention comprises: the substrate with a first surface and an opposing second surface; At least one chip connects and puts on the first surface of substrate and be electrically connected to substrate; Fin, have a par with from this extended support portion, edge, par, connect by this support portion and to put on the first surface of substrate, and chip is coated on par, support portion and substrate encloses in the space that is set to, wherein, have recess on the surface of support portion and substrate contacts, and have at least one protrusion unit on the surface of recess; Adhesive material, between the support portion of the fin that is laid in and the first surface of substrate, be packed in the recess and coat this protrusion unit around; And a plurality of soldered balls, plant on the second surface that is connected on substrate.Wherein, above-mentioned recess can be groove or a plurality of opening.
Semiconductor package part with fin of the present invention also can comprise: the substrate with a first surface and an opposing second surface; At least one chip connects and puts on the first surface of substrate and be electrically connected to substrate; One fin, have a par with from this extended support portion, edge, par, connect by this support portion and to put on the first surface of substrate, and chip is coated on par, support portion and substrate encloses in the space that is set to, wherein, the support portion with on the surface of this substrate contacts does not have at least one protrusion unit; One adhesive material, between the support portion of the fin that is laid in and the first surface of substrate, and the surface of this support portion, be coated on protrusion unit around; And a plurality of soldered balls, plant on the second surface that is connected on substrate.
Above-mentioned protrusion unit can be single burr (Burr), two burr or whole row's formula burr of colluding, and it is formed on the two relative inner wall surface of groove or opening, or be formed on the inner wall surface of support portion, and make the first surface of its projection towards substrate, and this protrusion unit can be shaped with wedge angle staking punch (Punch) punching out (Stamp), and also the striking of available horizontal staking punch is shaped.
In addition, this groove or opening also are to form with the staking punch punching out, and its cross sectional shape is decided according to the kind of staking punch, can be square, V-shape, semicircle or other shape.
Therefore, by above-mentioned protrusion unit design, can utilize this adhesive material and put on the first surface of substrate fin is sticking, and exert pressure adhesive material is packed in groove or the opening, to be coated on around the protrusion unit, or directly be coated on around the protrusion unit of abutment surfaces, and then, provide the strength of locking fin by the contacting of protrusion unit and adhesive material, make that fin is unlikely to come off easily when being shaken, and operation is simple and easy, and is with low cost.Simultaneously, its structural design can not influence the configuration on the substrate yet and cause chip rupture.
Description of drawings
Figure 1A is the preferred embodiment cutaway view of tool fin semiconductor package part of the present invention;
Figure 1B is the upward view of fin shown in Figure 1;
Fig. 2 A is the shaping schematic diagram of groove shown in Figure 1;
Fig. 2 B is the shaping schematic diagram of protrusion unit shown in Figure 1;
Fig. 3 is the fin support portion shown in Figure 1 and the adhesion schematic diagram of substrate;
Fig. 4 is embodiment 2 schematic diagrames of protrusion unit of the present invention, is the upward view of this fin;
Fig. 5 A and Fig. 5 B are embodiment 3 schematic diagrames of protrusion unit of the present invention;
Fig. 6 A to Fig. 6 C is embodiment 4 schematic diagrames of protrusion unit of the present invention;
Fig. 7 A and Fig. 7 B are other embodiment schematic diagrames of groove of the present invention;
Fig. 8 A and Fig. 8 B are other embodiment schematic diagrames of groove of the present invention;
Fig. 9 A is another embodiment cutaway view of tool fin semiconductor package part of the present invention;
Fig. 9 B is the upward view of the fin shown in Fig. 9 A;
Figure 10 is an embodiment cutaway view again of tool fin semiconductor package part of the present invention;
Figure 11 is a United States Patent (USP) the 6th, 093, the packaging part cutaway view of No. 961 case announcements;
Figure 12 is a United States Patent (USP) the 5th, 396, the packaging part cutaway view of No. 403 case announcements;
Figure 13 is a United States Patent (USP) the 6th, 441, the packaging part cutaway view of No. 485 case announcements;
Figure 14 is the existing packaging part cutaway view of offering groove on fin; And
Figure 15 is the existing packaging part cutaway view of offering dovetail slot type groove structure on fin.
Embodiment
Embodiment 1
Figure 1A is the preferred embodiment cutaway view with fin semiconductor package part of the present invention, it is a flip chip ball grid array packaging part 1 (FCBGA), comprise substrate 10 as chip bearing member (Chip Carrier), be electrically connected to substrate 10 and connect the chip of putting on the first surface 10a of substrate 10 12 with projection 11, be filled in projection 11 bottom filling (Underfill) insulating material 13 on every side, connect the square radiating plate of putting on the first surface 10a of substrate 10 14, be laid in the adhesive material 15 between fin 14 and substrate first surface 10a, and plant second surface 10b that is connected to substrate 10 and a plurality of soldered balls 16 that electrically connect with a plurality of projections 11; Wherein, this square radiating plate 14 has a square par 14a and the support portion 14b that extends to substrate 10 directions around the 14a of this par, be bonded in by support portion 14b on the first surface 10a of substrate 10, simultaneously, offer a closed groove 17 on the annular support part 14b, and on two opposed inner walls surfaces in the groove 17, have a plurality of spaced protrusion unit 18 respectively, and make the direction of the projection of protrusion unit 18 towards substrate 10.
Be the upward view of above-mentioned fin shown in Figure 1B, the fin of present embodiment is a square radiating plate 14, as shown in the figure, the closed groove of offering on this annular support part 14b 17 encompasses square, and have a plurality of spaced protrusion unit 18 respectively on two opposed inner walls surfaces in this groove 17, strengthen the adhesion strength of 15 pairs of fin 14 of adhesive material by this protrusion unit 18; Wherein, this groove 17 is shown in Fig. 2 A, form with existing square staking punch 21 (Punch) punching out (Stamp), so that its cross sectional shape is square, and have two parallel opposite first 17a and second surface 17b respectively, 18 of a plurality of protrusion unit are shown in Fig. 2 B, wedge angle staking punch 22 punching out with triangular shape form, so that groove 17 first, second surface 17a, on the 17b respectively according to the predetermined relative single projection burr (Burr) in a plurality of intervals that forms, and make the direction of the projection of this burr 18 towards substrate 10, therefore, by this quick pressing, can be simple and easy and make required fin groove 17 and protrusion unit 18 at low cost.
Fig. 3 is the support portion enlarged diagram after fin adheres to substrate, adhesive material 15 zone that the first surface 10a of substrate 10 contacts with the support portion 14b of fin 14 that is laid in advance wherein, and inserted in the groove 17 of support portion 14b by extruding, fill be coated on after a certain amount of protrusion unit 18 around, solidify through baking (Baking) step again, to utilize protrusion unit 18 to reach the effect of locking (Locking), simultaneously, utilize first of groove 17, second surface 17a, the mode that is spaced of the protrusion unit 18 (shown in Figure 1B) on the 17b, can make more even that the locking force of 15 pairs of fin 14 of adhesive material distributes, increasing its adhesion strength, thereby come off after avoiding fin 14 to be shaken; In general, the loading of adhesive material 15 is many more, also will be good more to the adherence of fin 14.At least need make the packed height of adhesive material 15 in groove 17 be higher than h-h line shown in Figure 3 in the design of the present invention, make its fully be coated on a plurality of protrusion unit 18 around, just can reach the locking fin 14 effect.
Therefore, by the design of the groove on the fin 14 of the present invention 17 with protrusion unit 18, can be under the situation that does not change substrate 10 layout designs, improve the adhesion strength of fin 14, to avoid it come off by shake, simultaneously, because fin 14 of the present invention is not to utilize with the contact relation of 12 of chips to locate, so can in follow-up high-temperature process, not oppress chip 12, cause chip 12 to break; In addition, because the design of groove 17 and protrusion unit 18 such as above-mentioned be with easy stamping procedure shaping, so only need arrange in pairs or groups suitable staking punch can be at low cost volume production significantly, can not offer mode as existing dovetail groove or other groove, expend a large amount of process costs, can solve the difficult problem of all prior aries simultaneously.
Embodiment 2
Embodiment 3
Forming mode according to protrusion unit, also non-only limiting to above-mentionedly carried out punching out with triangle staking punch 22, and the projection direction of protrusion unit is also non-to only limit to towards substrate 10, groove 17 surfaces shown in Fig. 5 A, Fig. 5 B, promptly be to utilize horizontal staking punch 21, eliminate the layer of material on the first surface 17a of groove 17 in the striking mode, make the flange burr 38 shown in Fig. 5 B, equally can be after adhesive material 15 be coated on around it, the function of performance locking fin 14.
Embodiment 4
The form of protrusion unit is also non-to only limit to single burr, the mode of also available multistage punching press, make burr with multistage projection, as Fig. 6 A, Fig. 6 B, groove 17 surfaces shown in Fig. 6 C, earlier go out one first burr 48a with 22 punching out of triangle wedge angle staking punch, repeat above-mentioned action again and make one second burr 48b, thereby become the two shape burrs 48 that collude that have the first burr 48a and the second burr 48b shown in Fig. 6 C, though this embodiment has higher process cost, but its locking effect is better than the foregoing description, and make adhesive material 15 and groove 17 surfaces have more contact area, can decide according to user's cost and adherence demand.
The various embodiments described above all are that the groove 17 with the square-section is an example, in fact, the cross sectional shape of groove is also non-to be limited to above-mentioned shape, as Fig. 7 A, Fig. 7 B, promptly be to replace above-mentioned horizontal staking punch 21 with wedge angle staking punch 23, punching out goes out a V-shape groove 27, can form protrusion unit 18 respectively on two surface as Fig. 7 B too; Fig. 8 A, Fig. 8 B then are the semi-circular recesses 37 that forms with circular staking punch 24 punching out, can bring into play effect of the present invention equally.
Remove this, for reaching the firm adhesion of fin 14, key is protrusion unit 18,28,38,48 with the coating of adhesive material 15 design, rather than groove 17,27,37 form, therefore, also can consider groove of the present invention is replaced to other design, as Fig. 9 A, embodiment shown in Fig. 9 B, promptly be that groove 17 is replaced to illustrated square aperture 40, these eight square aperture 40 are as fin 14 upward views of Fig. 9 B, be opened in respectively on the angle edge or edge of fin support portion 14b, also be formed with protrusion unit 18 respectively on its opening 40 inner wall surface, so that after adhesive material 15 is packed into each square aperture 40 respectively, evenly be coated on a plurality of protrusion unit 18 around, and behind baking-curing the function of performance locking fin 14.
The quantity of above-mentioned opening 40 with offer the position and there is no certain limitation, relatively good but its position has certain symmetry so that the locking force of 15 pairs of fin 14 of adhesive material is evenly distributed, thereby have the effect of adhering preferably; Simultaneously, be formed at opening 40 lip-deep protrusion unit 18 also as the various embodiments described above, have all places Rankine-Hugoniot relations, forming mode and projection form, can decide according to designer's demand, the cross section of this opening 40 is also non-to only limit to squarely, also can utilize different staking punch and makes V-shape or circle waits other shape.
As previously mentioned, the key that reaches the firm adhesion of fin 14 is to be protrusion unit 18,28,38,48 with the coating of adhesive material 15 design, therefore, also can consider the above-mentioned groove 17 of complete economization, 27,37 or the design of opening 40, as shown in figure 10, directly on the inner wall surface 140b of fin 14 support portion 14b, form a plurality of protrusion unit 18, just make protrusion unit 18 rank being installed with in the space 141 in fin 14 coating chips 12, can reach identical reinforcement adhesion effect equally, also can reduce simultaneously and offer groove 17,27,37 or the manufacturing cost of opening 40, more can satisfy the needs of volume production, but in such an embodiment, at least need make the packed height of adhesive material 15 in being installed with space 141 be higher than the h-h line of icon, make its fully be coated on a plurality of protrusion unit 18 around, to bring into play its locking function; Figure 10 only is to be the explanation of protrusion unit with the single burr in the foregoing description 1 18, but this protrusion unit also can be whole row's formula burr 28, flange burr 38 or two various execution modes such as shape burr 48 that collude.
In sum, the semiconductor package part with fin of the present invention really has the effect of firm adhesion fin, simultaneously, the also unlikely destruction of causing of its structural design to chip and substrate, and then can bring into play the simple and advantage with low cost of its operation, reach the volume production demand.
Claims (30)
1. the semiconductor package part with fin is characterized in that, this semiconductor package part comprises:
Substrate has a first surface and an opposing second surface;
At least one chip connects and puts on the first surface of substrate and be electrically connected to substrate;
Fin, have a par with from this extended support portion, edge, par, connect by this support portion and to put on the first surface of substrate, and chip is coated on par, support portion and substrate encloses in the space that is set to, wherein, have at least one recess on the surface of support portion and substrate contacts, and have at least one protrusion unit on the surface of this recess;
Adhesive material, between the support portion of the fin that is laid in and the first surface of substrate, be packed in the recess and coat this protrusion unit around; And
A plurality of soldered balls are planted on the second surface that is connected to substrate.
2. the semiconductor package part with fin as claimed in claim 1 is characterized in that, this recess is a groove.
3. the semiconductor package part with fin as claimed in claim 1 is characterized in that, this recess is an opening.
4. the semiconductor package part with fin as claimed in claim 1 is characterized in that, this protrusion unit is a single burr.
5. the semiconductor package part with fin as claimed in claim 1 is characterized in that, this protrusion unit is that a pair of colludes burr.
6. the semiconductor package part with fin as claimed in claim 1 is characterized in that, this protrusion unit is whole row's formula burr.
7. the semiconductor package part with fin as claimed in claim 1 is characterized in that, this protrusion unit is formed at respectively on two opposed inner walls surfaces on the recess.
8. the semiconductor package part with fin as claimed in claim 1 is characterized in that the projection of this protrusion unit is towards the first surface of substrate.
9. the semiconductor package part with fin as claimed in claim 1 is characterized in that, this protrusion unit is to form with the punching out of wedge angle staking punch.
10. the semiconductor package part with fin as claimed in claim 1 is characterized in that, this protrusion unit is to form with horizontal staking punch striking.
11. the semiconductor package part with fin as claimed in claim 1 is characterized in that the cross section of this recess is square.
12. the semiconductor package part with fin as claimed in claim 1 is characterized in that the cross section of this recess is a V-shape.
13. the semiconductor package part with fin as claimed in claim 1 is characterized in that, the cross section of this recess is semicircle.
14. the semiconductor package part with fin as claimed in claim 1 is characterized in that, this recess is to form with the staking punch punching out.
15. the semiconductor package part with fin as claimed in claim 1 is characterized in that, this chip utilizes the first surface of conductive projection and substrate to electrically connect.
16. the semiconductor package part with fin as claimed in claim 15 is characterized in that, this semiconductor package part also comprises the insulating material that is filled in around the conductive projection.
17. the semiconductor package part with fin as claimed in claim 1 is characterized in that this semiconductor package part also comprises the heat-conducting glue of adhering chip and fin par.
18. the semiconductor package part with fin as claimed in claim 1 is characterized in that, this semiconductor package part is the flip chip ball grid array semiconductor package part.
19. the semiconductor package part with fin is characterized in that, this semiconductor package part comprises:
Substrate has a first surface and an opposing second surface;
At least one chip connects and puts on the first surface of substrate and be electrically connected to substrate;
Fin, have a par with from this extended support portion, edge, par, connect by this support portion and to put on the first surface of substrate, and chip is coated on par, support portion and substrate encloses in the space that is set to, wherein, the support portion with on the surface of substrate contacts does not have at least one protrusion unit;
Adhesive material is laid between the first surface of the support portion of fin and substrate, and the surface of this support portion, with coat protrusion unit around; And
A plurality of soldered balls are planted on the second surface that is connected to substrate.
20. the semiconductor package part with fin as claimed in claim 19 is characterized in that, this protrusion unit is a single burr.
21. the semiconductor package part with fin as claimed in claim 19 is characterized in that, this protrusion unit is that a pair of colludes burr.
22. the semiconductor package part with fin as claimed in claim 19 is characterized in that, this protrusion unit is whole row's formula burr.
23. the semiconductor package part with fin as claimed in claim 19 is characterized in that, this protrusion unit is formed at respectively on the inner wall surface of support portion, to be installed with in the space of coating chip.
24. the semiconductor package part with fin as claimed in claim 19 is characterized in that the projection of this protrusion unit is towards the first surface of substrate.
25. the semiconductor package part with fin as claimed in claim 19 is characterized in that, this protrusion unit is to form with the punching out of wedge angle staking punch.
26. the semiconductor package part with fin as claimed in claim 19 is characterized in that, this protrusion unit is to form with horizontal staking punch striking.
27. the semiconductor package part with fin as claimed in claim 19 is characterized in that, this chip utilizes the first surface of conductive projection and substrate to electrically connect.
28. the semiconductor package part with fin as claimed in claim 27 is characterized in that, this semiconductor package part also comprises the insulating material that is filled in around the conductive projection.
29. the semiconductor package part with fin as claimed in claim 19 is characterized in that this semiconductor package part also comprises the heat-conducting glue of adhering chip and fin par.
30. the semiconductor package part with fin as claimed in claim 19 is characterized in that, this semiconductor package part is the flip chip ball grid array semiconductor package part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031561357A CN1319163C (en) | 2003-08-29 | 2003-08-29 | Semiconductor package with radiating fins |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031561357A CN1319163C (en) | 2003-08-29 | 2003-08-29 | Semiconductor package with radiating fins |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1591850A CN1591850A (en) | 2005-03-09 |
| CN1319163C true CN1319163C (en) | 2007-05-30 |
Family
ID=34598320
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031561357A Expired - Fee Related CN1319163C (en) | 2003-08-29 | 2003-08-29 | Semiconductor package with radiating fins |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1319163C (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8848375B2 (en) * | 2009-09-24 | 2014-09-30 | Lear Corporation | System and method for reduced thermal resistance between a power electronics printed circuit board and a base plate |
| US20110115067A1 (en) * | 2009-11-18 | 2011-05-19 | Jen-Chung Chen | Semiconductor chip package with mold locks |
| US20120188721A1 (en) * | 2011-01-21 | 2012-07-26 | Nxp B.V. | Non-metal stiffener ring for fcbga |
| CN102683221B (en) * | 2011-03-17 | 2017-03-01 | 飞思卡尔半导体公司 | Semiconductor device and its assemble method |
| CN104810328B (en) * | 2014-01-28 | 2018-07-06 | 台达电子企业管理（上海）有限公司 | Package casing and the power module with the package casing |
| CN104934399A (en) * | 2015-06-23 | 2015-09-23 | 日月光封装测试(上海)有限公司 | Semiconductor substrate and method for fabricating same |
| TWI618911B (en) * | 2017-05-24 | 2018-03-21 | Excel Cell Electronic Co Ltd | Wafer packaging device and heat sink and heat sink manufacturing method thereof |
| CN109037172B (en) * | 2017-06-12 | 2021-03-19 | 百容电子股份有限公司 | Packaging device of chip, heat dissipation member thereof and manufacturing method of heat dissipation member |
| TWI706523B (en) * | 2019-09-02 | 2020-10-01 | 矽品精密工業股份有限公司 | Electronic package |
| CN114823550B (en) * | 2022-06-27 | 2022-11-11 | 北京升宇科技有限公司 | Chip packaging structure and packaging method suitable for batch production |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5311402A (en) * | 1992-02-14 | 1994-05-10 | Nec Corporation | Semiconductor device package having locating mechanism for properly positioning semiconductor device within package |
| US5926371A (en) * | 1997-04-25 | 1999-07-20 | Advanced Micro Devices, Inc. | Heat transfer apparatus which accommodates elevational disparity across an upper surface of a surface-mounted semiconductor device |
| CN1387252A (en) * | 2001-05-21 | 2002-12-25 | 矽品精密工业股份有限公司 | Semiconductor package with heat sink structure |
| CN2567778Y (en) * | 2002-06-18 | 2003-08-20 | 矽品精密工业股份有限公司 | Semiconductor package device with radiation structure |
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- 2003-08-29 CN CNB031561357A patent/CN1319163C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5311402A (en) * | 1992-02-14 | 1994-05-10 | Nec Corporation | Semiconductor device package having locating mechanism for properly positioning semiconductor device within package |
| US5926371A (en) * | 1997-04-25 | 1999-07-20 | Advanced Micro Devices, Inc. | Heat transfer apparatus which accommodates elevational disparity across an upper surface of a surface-mounted semiconductor device |
| CN1387252A (en) * | 2001-05-21 | 2002-12-25 | 矽品精密工业股份有限公司 | Semiconductor package with heat sink structure |
| CN2567778Y (en) * | 2002-06-18 | 2003-08-20 | 矽品精密工业股份有限公司 | Semiconductor package device with radiation structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1591850A (en) | 2005-03-09 |
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