CN1279603C - Method of forming double insertion structure - Google Patents
Method of forming double insertion structure Download PDFInfo
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- CN1279603C CN1279603C CN 02128694 CN02128694A CN1279603C CN 1279603 C CN1279603 C CN 1279603C CN 02128694 CN02128694 CN 02128694 CN 02128694 A CN02128694 A CN 02128694A CN 1279603 C CN1279603 C CN 1279603C
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- dielectric layer
- cap rock
- damascene structure
- interlayer hole
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Abstract
The present invention relates to a method of forming double insertion structures, wherein firstly, a substrate with a dielectric layer is provided; a top cover layer and a mask layer with at least one groove pattern are then formed on the dielectric layer; subsequently, a light resistor layer with an interlayer cave pattern is formed on the mash layer and the top cover layer, and the interlayer cave pattern is positioned corresponding to the groove pattern; the interlayer cave pattern is transferred to the upper parts of the top cover layer and the dielectric layer, and then the light resistor layer is removed; the groove pattern is then transferred to the upper parts of the top cover layer and the dielectric layer, and the interlayer cave pattern is transferred to the lower part of the dielectric layer; finally, a conducting layer is filled into the groove of the dielectric layer and an interlayer cave. The present invention has the efficiency of preventing the poison of a light resistor and improving the outline of a double insertion structure.
Description
Invention field
The invention relates to a kind of manufacture method of semiconductor integrated circuit,, poison to prevent photoresist particularly relevant for a kind of method that forms dual-damascene structure.
Background technology
As everyone knows, in semi-conductor industry, expend the semiconductor device of considerable time in the high service speed of making great efforts to develop.Yet, along with integrated circuit (IC) process technique develops rapidly, under the situation with the integration that increases integrated circuit, the size of semiconductor device is dwindled and will be made the resistance value of plain conductor rise, it is more serious that the problem of parasitic capacitance effect becomes, thereby reduce the rate of current in the plain conductor.
In order to reduce resistance value and parasitic capacitance effect, plain conductor is the material that adopts low-resistance value, and for example copper, and the insulating barrier between the plain conductor is to adopt low-k (low k) material.
In recent years, develop the double-insert process of the metal material of the dielectric layer that the use low-k and low-resistance value, in integrated circuit (IC) apparatus, to make high-reliability and intraconnections cheaply.In order to further specify background technology of the present invention, below cooperate Fig. 1-Fig. 4 to illustrate that conventional art forms the method for dual-damascene structure.
At first, consult shown in Figure 1ly, a substrate 100 is provided, for example semiconductor substrate then, forms a capping layer 102 and a low dielectric constant material layer 104 in regular turn in substrate 100, then, on low dielectric constant material layer 104, form a mask layer 106 with most groove opening 106a.
Next, consult shown in Figure 2ly, on mask layer 106, apply one deck photoresist layer 108, and fill up groove opening 106a.Then, photoresist layer 108 is implemented a lithography step, on mask layer 106 and dielectric layer 104, to form photoresist pattern layer 108 with most interlayer holes (via) opening 108a.Wherein, the position of interlayer hole opening 108a is the groove opening 106a corresponding to below mask layer 106.Yet,, make that the side wall profile (Profile) of photoresist pattern layer 108 is not good herein owing to the ammonia in the dielectric layer 104 (amino) causes photoresist to poison.
Next, consult shown in Figure 3ly, utilize photoresist pattern layer 108, dielectric layer 104 is implemented an anisotropic etching as mask, and with the first half of interlayer hole design transfer to dielectric layer 104.
At last, consult shown in Figure 4ly, divest photoresist pattern layer 108.Then, utilize mask layer 106 to come etching dielectric layer 104, and utilize capping layer 102, and channel patterns is transferred to the first half of dielectric layer 104 as etch stop layer with groove opening 106a.Simultaneously, also with the Lower Half of dielectric layer 104 first half interlayer hole design transfer to dielectric layer 104.The groove 104b and the interlayer hole 104a that are formed in the dielectric layer 104 constitute dual-damascene structure.Afterwards, the capping layer 102 that will be positioned at interlayer hole 104a below is removed, to expose substrate 100 surfaces.Its major defect is:
Owing to be subjected to the influence that above-mentioned photoresist poisons, the interlayer hole profile in the dual-damascene structure is not good, and reduces the reliability of integrated circuit (IC) apparatus.
Summary of the invention
The purpose of this invention is to provide a kind of method that forms dual-damascene structure,, directly touch dielectric layer, reach the purpose that prevents that photoresist from poisoning to avoid photoresist by cap rock in extra formation one on the dielectric layer.
Another object of the present invention provides a kind of method that forms dual-damascene structure, by form one as anti-reflecting layer (anti-reflective layer, last cap rock ARL) reach the purpose of the profile that improves dual-damascene structure.
The object of the present invention is achieved like this: a kind of method that forms dual-damascene structure is characterized in that: which comprises at least the following step:
(1) provides substrate, have dielectric layer in this substrate;
(2) forming cap rock on this dielectric layer:
(3) on this, form mask layer above the cap rock, wherein on this mask layer, also be formed with an anti-reflecting layer with at least one channel patterns;
(4) form photoresist layer on the cap rock at this anti-reflecting layer and on this, and the position of this interlayer hole pattern is corresponding to this channel patterns with at least one interlayer hole pattern;
(5) this interlayer hole design transfer extremely is somebody's turn to do the first half of going up cap rock and this dielectric layer;
(6) remove this photoresist layer;
(7) this channel patterns is transferred to the first half of cap rock and this dielectric layer on this, and simultaneously with the Lower Half of this interlayer hole design transfer to this dielectric layer;
(8) in the groove of this dielectric layer and interlayer hole, insert conductive layer.
This substrate includes plain conductor, and this plain conductor is positioned at the below of this interlayer hole of this dielectric layer.Be coated with capping layer on the plain conductor of this substrate.This mask layer includes anti-reflecting layer.
Method of the present invention also comprises the steps:
Remove this anti-reflecting layer, this mask layer and should go up cap rock, to expose the dielectric layer surface that this has groove and interlayer hole; Reach on this dielectric layer and groove and interlayer hole surface compliance formation metal barrier layer.
This metal barrier layer is to be selected from any of titanium, tantalum, titanium nitride or tantalum nitride.This dielectric layer is a low dielectric constant material layer.Should go up cap rock and be any that is selected from undoped silicon glass, carborundum or silicon fluoride.Should go up cap rock is to form by chemical vapour deposition technique, and uses silane or tetraethyl-metasilicate as reacting gas.
Describe in detail below in conjunction with the preferred embodiment conjunction with figs..
Description of drawings
Fig. 1-in 4 is generalized sections that tradition forms the dual-damascene structure method;
Fig. 5-Figure 10 is the generalized section that the present invention forms the dual-damascene structure method.
Embodiment
Consult Fig. 5-shown in Figure 10, be the method for formation dual-damascene structure of the present invention.
At first, consult shown in Figure 5ly, a substrate 200 is provided, for example semiconductor substrate has most plain conductors 201, for example copper conductor in the substrate 200.Then, in substrate 200, form a capping layer 202.Afterwards, on capping layer 202, deposit one as dielectric layer between metal layers (intermetal dielectric, dielectric layer 204 IMD).Herein, capping layer 202 is to cause oxidation in order to prevent plain conductor 201 ingresss of air, and prevents that the atom/ions diffusion in the plain conductor 201 from entering dielectric layer 204, and causes leakage current or bad electrical contact.In the present embodiment, preferably silicon nitride (SiN) or carborundum (SiC) of capping layer 202 employed materials.In addition, preferably advanced low-k materials, for example BD, Coral, Aurora or GreenDot of dielectric layer 204 employed materials.Afterwards, on dielectric layer 204, form cap rock 206, a mask layer 208 and a photoresist layer 212 on one in regular turn.In the present embodiment, last cap rock 206 employed materials can be that (undoped silicate glass, USG), carborundum or gasification silicon (SiF), and its thickness is in the scope of 300f1J00 dust for unadulterated silex glass.Cap rock 204 can (chemical vapor deposition, CVD) method forms, and wherein is to utilize silane (SiH by chemical vapour deposition (CVD) on this
4) or tetraethyl-metasilicate (tetraethyl orthosillcate is TEOS) as reacting gas.Moreover, mask layer 208 be in double-insert process in order to the definition channel patterns, its preferable material is a silicon nitride, and thickness is in the scope of 800-1200 dust.In addition, optionally on mask layer 208, form a thickness the anti-reflecting layer of the scope of 200-400 dust (anti-reflective layer, ARL) 210, its preferable material is silicon oxynitride (SiON).
Next, consult shown in Figure 6ly, photoresist layer 212 is implemented a lithography step, in photoresist layer 212, to form most groove opening 212a.Subsequently, as mask, the mask layer 208 of anisotropic etching anti-reflecting layer 210 and below thereof is to the last cap rock 206 that exposes as etch stop layer with the photoresist layer 212 of patterning.Thus, just with the groove opening design transfer to mask layer 208.
Next, consult shown in Figure 7ly, utilize traditional photoresist to divest method and remove photoresist layer 212, for example oxygen electricity slurry ashing method.Afterwards, on anti-reflecting layer 210, apply another photoresist layer 214 and fill up groove opening 212a.Next, equally photoresist layer 214 is implemented a lithography step, form photoresist pattern layer 214 with most interlayer holes (via) opening 214a to reach on the cap rock 206 at anti-reflecting layer 210.Wherein, the position of interlayer hole opening 214a is the groove opening 212a corresponding to below anti-reflecting layer 210 and mask layer 208.
Next, consult shown in Figure 8ly, as the mask mask, the last cap rock 206 and the dielectric layer 204 of anisotropic etching interlayer hole opening 124a below are with the first half with supreme cap rock 206 of interlayer hole design transfer and dielectric layer 204 with the photoresist layer 214 of patterning.In the present embodiment, because last cap rock 206 is to be formed between mask layer 208 and the dielectric layer 204, photoresist layer 214 can't directly contact with dielectric layer 204, therefore can prevent that photoresist from poisoning phenomenon.Moreover, because the cap rock 206 of going up of the present invention also can be used as an anti-reflecting layer, therefore can further avoid problems such as standing wave effect and reflection indentation to produce.
Next, consult shown in Figure 9ly, utilize the photoresist of traditional oxygen electricity slurry ashing method to divest method equally, remove photoresist layer 214.Herein, last cap rock 206 can protect dielectric layer 204 to exempt to be subjected to oxygen electricity slurry to attack and damage.Afterwards, utilize the top to be coated with the mask layer with channel patterns 208 of an anti-reflecting layer 210 and as the capping layer 202 of etch stop layer, dielectric layer 204 to last cap rock 206 and below thereof carries out etching, with the first half of the dielectric layer 204 that channel patterns is transferred to cap rock 206 and below thereof.Simultaneously, the interlayer hole pattern of original dielectric layer 204 first halves also is transferred to the Lower Half of dielectric layer 204.These groove 204b and interlayer hole 204a that are formed in the dielectric layer 204 constitute dual-damascene structure.Then, remove the capping layer 202 that is positioned at interlayer hole 204a below, to expose the plain conductor 201 of interlayer hole 204a below.
At last, consult shown in Figure 10ly, remove anti-reflecting layer 210, mask layer 208 in regular turn and go up cap rock 206, to expose dielectric layer 204 surfaces with groove 204b and interlayer hole 204a.Then, on dielectric layer 204 and groove 204b and interlayer hole 204a sidewall compliance form a metal barrier layer 215.Herein, the material of metal barrier layer 215 preferably is selected from any of titanium (Ti), tantalum (Ta), titanium nitride (TiN) and tantalum nitride (TaN).Similarly, metal barrier layer 215 is in order to prevent that atom/ion in the metal (not illustrating) from after the subsequent implementation metallization process, diffusing to dielectric layer 204, and causing bad electrical contact or leakage current.Afterwards, deposition one conductive layer 216 on dielectric layer 204, copper metal layer for example, and fill up its groove 204b and interlayer hole 204a, electrically contact with plain conductor 201.Then, (chemicamechanical polishing CMP) grinds unnecessary conductive layer 216 in dielectric layer 204 tops and metal barrier layer 215, to form intraconnections in the groove 204b of dielectric layer 204 and interlayer hole 204a by chemical mechanical milling method.
Major advantage of the present invention is:
Compared to the method for tradition formation dual-damascene structure, the present invention avoids dielectric layer 204 and photoresist layer 214 to be in contact with one another by forming an extra last cap rock 206.Therefore, can prevent that the problem that photoresist poisons from producing, and then improve the profile of dual-damascene structure.That is, can effectively promote the reliability of integrated circuit (IC) apparatus.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limiting the present invention, anyly has the knack of this skill person, and without departing from the spirit and scope of the present invention, institute does to change and retouch, and all belongs within protection scope of the present invention.
Claims (9)
1, a kind of method that forms dual-damascene structure is characterized in that: which comprises at least the following step:
(1) provides substrate, have dielectric layer in this substrate;
(2) forming cap rock on this dielectric layer;
(3) on this, form mask layer above the cap rock, wherein on this mask layer, also be formed with an anti-reflecting layer with at least one channel patterns;
(4) form photoresist layer on the cap rock at this anti-reflecting layer and on this, and the position of this interlayer hole pattern is corresponding to this channel patterns with at least one interlayer hole pattern;
(5) this interlayer hole design transfer extremely is somebody's turn to do the first half of going up cap rock and this dielectric layer;
(6) remove this photoresist layer;
(7) this channel patterns is transferred to the first half of cap rock and this dielectric layer on this, and simultaneously with the Lower Half of this interlayer hole design transfer to this dielectric layer;
(8) in the groove of this dielectric layer and interlayer hole, insert conductive layer.
2, the method for formation dual-damascene structure according to claim 1 is characterized in that: this substrate includes plain conductor, and this plain conductor is positioned at the below of this interlayer hole of this dielectric layer.
3, the method for formation dual-damascene structure according to claim 2 is characterized in that: be coated with capping layer on the plain conductor of this substrate.
4, the method for formation dual-damascene structure according to claim 1 is characterized in that: this method also comprises the steps:
Remove this anti-reflecting layer, this mask layer and should go up cap rock, to expose the dielectric layer surface that this has groove and interlayer hole;
On this dielectric layer and groove and interlayer hole surface compliance form metal barrier layer.
5, the method for formation dual-damascene structure according to claim 4 is characterized in that: this metal barrier layer is to be selected from any of titanium, tantalum, titanium nitride or tantalum nitride.
6, the method for formation dual-damascene structure according to claim 1 is characterized in that: this dielectric layer is a low dielectric constant material layer.
7, the method for formation dual-damascene structure according to claim 1 is characterized in that: cap rock is to be selected from any of undoped silicon glass, carborundum or silicon fluoride on this.
8, the method for formation dual-damascene structure according to claim 1 is characterized in that: cap rock is to form by chemical vapour deposition technique on this, and uses silane as reacting gas.
9, the method for formation dual-damascene structure according to claim 1 is characterized in that: cap rock is to form by chemical vapour deposition technique on this, and uses tetraethyl-metasilicate as reacting gas.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02128694 CN1279603C (en) | 2002-08-12 | 2002-08-12 | Method of forming double insertion structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02128694 CN1279603C (en) | 2002-08-12 | 2002-08-12 | Method of forming double insertion structure |
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| CN1476074A CN1476074A (en) | 2004-02-18 |
| CN1279603C true CN1279603C (en) | 2006-10-11 |
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| CN 02128694 Expired - Lifetime CN1279603C (en) | 2002-08-12 | 2002-08-12 | Method of forming double insertion structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7811929B2 (en) | 2006-12-21 | 2010-10-12 | Hynix Semiconductor, Inc. | Method for forming dual damascene pattern |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102543849A (en) * | 2011-10-21 | 2012-07-04 | 上海华力微电子有限公司 | Method for etching first metal layer |
| CN103531528B (en) * | 2012-07-03 | 2018-03-13 | 联华电子股份有限公司 | The preparation method of dual-damascene structure |
| CN104425357B (en) * | 2013-08-27 | 2017-12-01 | 中芯国际集成电路制造(上海)有限公司 | The forming method of dual-damascene structure |
-
2002
- 2002-08-12 CN CN 02128694 patent/CN1279603C/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7811929B2 (en) | 2006-12-21 | 2010-10-12 | Hynix Semiconductor, Inc. | Method for forming dual damascene pattern |
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| CN1476074A (en) | 2004-02-18 |
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Owner name: LIANHUA ELECTRONICS CO., LTD. Free format text: FORMER OWNER: XITONG SCIENCE AND TECHNOLOGY CO LTD Effective date: 20050408 |
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Effective date of registration: 20050408 Address after: Hsinchu Science Park, Taiwan Applicant after: UNITED MICROELECTRONICS Corp. Address before: Hsinchu Science Park, Taiwan Applicant before: SILICON INTEGRATED SYSTEMS Corp. |
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