CN1251445A - Computer system of controlling clock signals of storage and control method thereof - Google Patents
Computer system of controlling clock signals of storage and control method thereof Download PDFInfo
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- CN1251445A CN1251445A CN99111095A CN99111095A CN1251445A CN 1251445 A CN1251445 A CN 1251445A CN 99111095 A CN99111095 A CN 99111095A CN 99111095 A CN99111095 A CN 99111095A CN 1251445 A CN1251445 A CN 1251445A
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
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- G06F1/06—Clock generators producing several clock signals
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Abstract
A computer system controlling a memory clock signal of a DIMM (dual in-line memory module) socket is described and which includes a processor controlling a 66 MHz or a 100 MHz system bus clock signal to be generated, a DIMM memory module supporting the 66 MHz or the 100 MH system bus clock signal, a clock generator generating the 66 MHz or the 100 MHz system bus clock signal, a clock buffer, a first and a second system controllers. As a result, a clock signal is cut off to an unused memory model module socket or an unused clock signal of a using memory module socket is cut off in response to kind of an inserted insertion of a memory module.
Description
The present invention relates to computer system, be specifically related to the computer system and the control method thereof of control store clock signal.
The system bus of computer system is CPU (CPU (central processing unit)), and storer and peripherals transmit the passage of data each other.For example, 100MHz system bus transmission speed means the speed transmission of data with 100MHz.
The chipset manufacturer of intention elevator system bus speed points out that present 66MHz system bus transmission speed (hereinafter referred to as " PC66 ") does not catch up with the speed of development of CPU.Therefore, the system bus transmission speed (hereinafter referred to as " PC100 ") of 100MHz has been developed in Intel Company's fast development of being adapted to CPU.
That is, PC100 means that the system bus transmission speed is promoted to 100MHz.For example, PC100 can be used to be equipped with on the mainboard of Intel 440BX chipset and the high-speed CPU that uses Pentium 350MHz and more speed.
PC100 has two advantages, and one is the lifting of system performance.For example, the running time of 66MHz system bus is 66 * 10
6/ second.Owing to once can operate 64 bits and 8 bits are equivalent to a byte, so transmission speed was 528 MB/ seconds.On the other hand, the running time of 100MHz system bus is 10
8/ second, so transmission speed is 800MB/ second.In fact, data rate has improved 51%.
Another advantage is the stability of peripherals.Because the processing speed of 66MHz system bus is too fast, PCI (peripheral parts interconnected) bus is operated in 33MHz.Therefore, peripherals such as graphics card and hard disk drive are operated in 33MHz.
If to 100MHz, then pci bus will be operated in 37.5MHz (promptly exceed and limit 13%) to the clock frequency of system bus by the 66MHz overclocking.Therefore, because overclocking may cause faults such as system closing.
Pci bus makes 33.3MHz satisfy the PCI standard with 1/3 clock frequency work in the 100MHz system bus.Although adopted high system bus clock frequency, can stablize the use high-speed peripheral.And the 100MHz system bus can use high-speed CPU of future generation.
Fig. 1 has showed the computer system motherboard that is equipped with as Intel Pentium II processor or compatible with it processor (CPU).66MHz that mainboard control will be exported or the bus clock of 100MHz.
Referring to Fig. 1, mainboard comprises groove 10 that CPU is installed and a plurality of slots 20 (22,24 and 26) that can insert main memory module.
Groove 10 is slot 1 type, is used for installing as Intel Pentium II processor, and comprises a mechanism that cooling fan can be installed.
The slot 20 that comprises 3 or 4 slots is the connectors that are used to expand primary memory.Can insert DIMM (dual inline memory modules) in each slot 22,24 and 26.The memory bus clock signal that is fit to 66MHz or 100MHz system bus speed is transfused among the DIMM, carries out the write/read operation of signal then.
Computer system also comprises BIOS (basic input/output) 50, is used for determining whether to have inserted primary memory by POST (startup self-detection) a HOST TO PCI bridge controller 30 and a PCI TO ISA bridge controller 40.
Fig. 2 has showed the structure of computer system shown in Figure 1.
Referring to Fig. 2, the computer system that comprises mainboard determines whether to have installed memory module by the handling procedure of BIOS ROM (basic input/output ROM (read-only memory)) 50, cuts off the memory bus clock signal of the slot that memory module is not installed in the dimm socket 20 then.
For example, CPU12 is Intel Pentium II processor and comprises internal cache memory 14.
CPU12 also comprises the HOST TO PCI bridge controller 30 between HOST bus and pci bus, and the PCI TO ISA bridge controller 40 between pci bus and ISA bridge controller.For example, HOST TO PCI bridge controller 30 is for having HOST TOPCI interface, Memory Controller, and the Intel 440BX chipset of function such as AGP (Accelerated Graphics Port) controller.For example, PCI TO ISA bridge controller 40 is for having the PCI-ISA interface, the Intel PIIX4E chipset of functions such as IDE controller and USB controller or compatible with it chipset.
CPU12 is used to select 66MHz or 100MHz system bus clock signal according to the bus speed output control signal 100_66# of the memory module of inserting.Then, clock generator 18 responsive control signal 100_66# are to the HOST clock signal BXCLK of HOST TO PCI bridge controller 30 output 66MHz or 100MHz.Then, HOST TO PCI bridge controller 30 is exported first to fourth memory clock signal CLK0-CLK3 respectively to each memory module slot 20 (22,24 and 26).
After the computer system energized, CPU determines whether memory module is inserted in the memory module slot 20 and the insertion time during the POST of BIOS50.
At this moment, enable whole first to fourth memory clock signal CLK0-CLK3 of memory module slot 20, forbid being confirmed as not inserting the memory clock signal CLK0-CLK3 of the memory module slot of memory module.First to fourth memory clock signal CLK0-CLK3 is output to each memory module slot according to the system bus transmission speed.
In conventional computer system, clock signal constantly offered in the storer dimm socket empty slot or, as mentioned above, although cut off the memory clock signal of untapped dimm socket, but still continue to provide the not use memory clock signal of the slot that is using.Its result is that described conventional computer system is subjected to EMI (electromagnetic interference (EMI)).
Therefore one of purpose of the present invention provides a kind of computer system, this computer system can cut off the clock signal of untapped memory module slot in the computer system and the clock signal of the memory module slot that using in untapped clock signal.
Another object of the present invention provides a kind of method that is used for control computer system storage clock signal.
According to the present invention, be used to export control signal to generate the processor of first or second bus clock signal a kind of comprising, comprise with the computer system of at least one memory module: first system controller, read master data and export the be provided with data corresponding with memory data then from memory module; Clock generator is according to control signal the output first or two HOST clock signal corresponding with data are set; Second system controller, according to the first or the 2nd HOST clock signal, output is as first or second reference clock signal of the memory clock signal reference of memory module; With a clock buffer, be used to receive first or second reference clock signal and export first to fourth memory clock signal corresponding to memory module then with data are set.If memory module is the single side memory module, clock buffer cuts off the untapped memory clock signal of single face memory module in first to fourth memory clock signal by the described data that are provided with so.
In a preferred embodiment, first system controller is by SM (system management) bus transfer memory data with data are set.
In a preferred embodiment, clock generator and clock buffer comprise and are used to store the register that data are set.
In a preferred embodiment, if memory module is the single side memory module, then when input first reference clock signal, clock buffer is forbidden second memory clock signal and the 4th memory clock signal, and when input second reference clock signal, clock buffer is forbidden the 3rd memory clock signal and the 4th memory clock signal.
According to the present invention, the method that is used for the memory clock signal of at least one DIMM of control computer system (dual inline memory modules) may further comprise the steps:
Enable first to fourth memory clock signal of all memory banks, determine whether memory module is inserted in certain slot of the memory bank that enables;
If memory module is inserted into wherein, then determine the type of the memory module of insertion;
If memory module is the double-side type memory module, then keep first to fourth memory clock signal that enables;
If memory module is the single side memory module, determine that then the bus speed of memory module is first speed or second speed;
If bus speed is first speed, then forbid memory clock signal corresponding in first to fourth memory clock signal with the memory module second speed;
If bus speed is a second speed, then forbid in first to fourth memory clock signal and the corresponding memory clock signal of memory module first speed.
In a preferred embodiment, if memory module is not inserted into wherein, then forbid first to fourth memory clock signal of respective memory module slot.
Thereby microprocessor determines by the program of carrying out BIOS (basic input/output) whether memory module is inserted into memory module slot, reads memory data in the memory module by a system controller then.Then, microprocessor with the data storage that reads in clock generator and clock buffer.Its result will control the not use clock signal of the memory module of inserting according to the type of the first or second system bus clock signal and memory module.
Specify its preferred embodiment by the reference accompanying drawing, it is more obvious that above-mentioned purpose of the present invention and advantage will become, wherein:
Fig. 1 is for showing the stereographic map of conventional computer system mainboard;
Fig. 2 is for showing the block scheme of Computer Systems Organization shown in Figure 1;
Fig. 3 is for showing the block scheme according to Computer Systems Organization of the present invention;
Fig. 4 is for showing the block scheme according to computer system clock signal access structure shown in Figure 3;
Fig. 5 is for showing the stereographic map of DIMM (dual inline memory modules);
Fig. 6 A is the cut-open view that is applicable to the single side memory module of 66MHz system bus clock;
Fig. 6 B is the cut-open view that is applicable to the single side memory module of 100MHz system bus clock;
Fig. 6 C is the cut-open view that is applicable to the double-side type memory module of 66/100MHz system bus clock;
Fig. 7 is the detailed circuit diagram of clock generator shown in Figure 3;
Fig. 8 is the detailed circuit diagram of clock buffer shown in Figure 3;
Fig. 9 is the detailed circuit diagram of memory module slot shown in Figure 3;
Figure 10 is the process flow diagram that does not use the memory clock signal control procedure of the memory clock signal of showing untapped memory module slot and the memory module slot that using; With
Figure 11 is the process flow diagram of the memory clock signal control procedure of a displaying memory module slot shown in Figure 10.
Specify this method referring now to accompanying drawing 3-11 and in conjunction with the preferred embodiments of the present invention.
Referring to Fig. 3, computer system 100 comprises CPU (CPU (central processing unit)) 102, primary memory 110, and BIOS (basic input/output) 116.
The CPU102 that comprises kernel 104 and L2 cache 106 exports control signal 100_66#, is used to select to export the system bus clock signal of 66MHz or 100MHz.
HOST TOPCI bridge controller 108 between the HOST of computer system 100 bus and pci bus has HOST TO pci interface, Memory Controller, AGP (Accelerated Graphics Port) controller, the function of a plurality of clock signals and detection control.And HOST TO PCI bridge controller 108 is from the clock generator 126 receptions HOST clock signal BXCLK corresponding with PC66 or PC100, then to clock buffer 130 output reference clock signal DCLK0.
PCI TO ISA bridge controller 114 between pci bus and isa bus comprises PCI TO ISA interface, IDE controller, USB controller and SM bus controller.Correspondingly, PCI TO ISA bridge controller 114 reads memory data in the memory module by the SM bus, then to clock buffer 130 and clock generator 126 outputs corresponding with memory data data are set.
The memory data that stores among the ROM of memory module 200 shown in Figure 5 (EEPROM) 204, comprise the capacity of RAM 202 and regularly (as, CAS regularly and the RAS timing).
The memory module 200 that is inserted in memory module slot 120,122 and 124 shown in Figure 5 comprises the RAM 202 that is used for the write and read data and is used to store the ROM (EEPROM) 204 that waits memory data as memory span and timing.Memory data is supported SPD (detecting of serial presence bit) (the serial presence detect) standard by Intel Company's formulation, and transmits shared SM data and clock signals by the SM bus of computer system 100 to PCI TO ISA controller 114.
Referring to Fig. 3, clock generator 126 comprises register 128 again, is used for storing from the PCITO ISA bridge controller data that are provided with that are corresponding with memory data memory module 114.Then, clock generator 126 responses come from the control signal 100_66# of CPU 102, export HOST clock signal BXCLK (BXHCLK and BXPCLK) to HOST TO PCI bridge controller 108 then, and output is for every all very necessary cpu clock signal CPU CLK and pci clock signal PCI CLK of system's operation.
Referring to Fig. 4, computer system 100 is supported the system bus transmission speed of 66/100MHz.Correspondingly, CPU 102 and primary memory 110 are supported the system bus speed of 66/100MHz.
If connect the power supply of computer system 100, then CPU 102 is by BIOS 116 controls, then to control signal 100_66# who is used to select PC 66 clock signal of system or PC100 clock signal of system of clock generator 126 outputs.Then, CPU 102 determines by the handling procedure of BIOS 116 whether memory module is inserted in memory module slot 120,122 and 124 and the type of inserting memory module wherein.
At this moment, PCI TO ISA bridge controller 114 reads the memory data among the ROM of the memory module that is stored in insertion by the SM bus, then corresponding with memory data is provided with data storage in the register 128 and 132 of clock generator 126 and clock buffer 130.Then, clock generator 126 responsive control signals 100 66# are then to the HOST TO PCI bridge controller 108 outputs HOST clock signal BXCLK corresponding with clock signal of system.HOST TO PCI bridge controller 108 response HOST clock signal BXCLK are then to clock buffer 130 output reference clock signal DCLK0.Correspondingly, clock buffer 130 is exported first to fourth memory clock signal CLK0-CLK3 by the data that are provided with that are stored in the internal register 132 to each memory module slot 120,122 and 124.And clock buffer 130 cuts off the clock signal of empty store module slot.
Shown in Fig. 6 A-6C, memory module 200 is divided into single side memory module 200a and 200b and the double-side type memory module 200c that supports 66MHz or 100MHz memory bus speeds.66MHz single face memory module 200a is by first clock signal clk 0 and the second clock signal CLK1 of input front, and the 3rd clock signal clk 2 of cut-out back and 3 work of the 4th clock signal clk.100MHz single face memory module 200b is by first clock signal clk 0 and the 3rd clock signal clk 2 of input front, and the second clock signal CLK1 of cut-out back and the 4th clock signal clk 3 execution write/read operation.Double-side type memory module 200c is by irrespectively importing first to fourth clock signal clk 0-CLK3 work with the 66/100MHz memory bus speeds.
Referring to Fig. 7, clock generator 126 receives the control signal 100_6# that is used for the selective system bus clock signal that comes from CPU 102.And clock generator 126 receives memory data SMBDATA and the SMBCLK that comes from PCI TO ISA bridge controller 114 by the SM bus, deposits data SMBDATA and SMBCLK in register 128 then.Correspondingly, the HOST clock signal BXCLK that is suitable for 66MHz or 100MHz system bus clock signal is output in the HOST TO PCI bridge controller 108, and output cpu clock signal CPU CLK (CPU0 and CPU1) and pci clock signal PCIF-PCI6.
Referring to Fig. 8, clock buffer 130 receives memory data SMBDATA and the SMBCLK that comes from PCI TO ISA bridge controller 114 by the SM bus, deposits data SMBDATA and SMBCLK in register 132 then.And, clock buffer 130 receive come from HOST TO PCI bridge controller 108 with 66MHz or 100MHz system bus clock signal corresponding reference clock signal DCLK0.Thereby the memory module of insertion is corresponding to single side or the double-side type memory module of 66/100MHz, then to memory module slot 120,122 and 124 outputs, first to fourth clock signal clk 0-CLK3 (DCLK[11:0]).
Fig. 9 has showed the circuit of memory module slot 120 or 122 or 124, and illustrate from clock buffer 130 and PCI TO ISA bridge controller 114 receptions first to fourth clock signal clk 0-CLK3, shared SM data SMBDATA and clock signal SMBCLK are by the SM bus transfer.
Referring to Figure 10, if the system 100 in step S300 connects with the mains, then BIOS 116 enables the clock signal clk 0-CLK3 of first to the 3rd DIMM memory module slot 120,122 and 124.In step S310, whether be inserted into a DIMM memory module slot 120 according to memory module, control corresponding clock signals CLK0-CLK3.Then, the clock signal clk 0-CLK3 of control second memory slot 122 and the 3rd memory bank 124.That is to say, according to the memory module of determine inserting whether back-up system bus and memory module be single face or two-sided memory module, control first to fourth clock signal clk 0-CLK3 of each memory module slot.
Referring to Figure 11, in step S340, the present invention determines whether memory module is inserted in the memory module slot 120 or 122 or 124 that enables first to fourth memory clock signal CLK0-CLK3.If be not inserted into, then step S340 goes to step S352.In step 352, forbid all first to fourth clock signal clk 0-CLK3.If be inserted into, then step S340 goes to step S342.In step S342, the present invention determines whether the memory module of inserting is the single side memory module.
If memory module is the double-side type memory module,, keep the first to fourth clock signal clk 0-CLK3 that is enabled then no matter how many memory bus clock speeds is.If memory module is the single side memory module, then step S342 goes to step S346.In step S346, the present invention determines whether the memory module of inserting supports the memory bus speeds of 100MHz.If support, then in step S348, forbid being not used in the clock signal of 100MHz memory bus clock speed.That is, forbid second clock signal CLK1 and the 4th clock signal clk 3.If do not support (that is, supporting 66MHz memory bus clock speed), then step S346 goes to step S350.In step S350, forbid being not used in the clock signal of 66MHz memory bus clock speed.That is, forbid the 3rd clock signal clk 2 and the 4th clock signal clk 3.
Computer system of the present invention has not only been cut off the clock signal of untapped memory module slot, has also cut off the clock signal of the memory module of inserting, and gets rid of EMI (electromagnetic interference (EMI)) with this.
Under the situation that does not break away from its spirit and essential feature, the present invention can implement by other particular form.It is illustrative and not restrictive that the foregoing description all only should be taken as from every side.Therefore, the appointment of the scope of the invention is depended on accessory claim rather than depend on the explanation of front.
Claims (6)
1. one kind comprises and is used to export control signal with the processor that generates first or second bus clock signal and the computer system of at least one memory module, comprising:
First system controller reads master data and exports the be provided with data corresponding with described memory data then from described memory module;
Clock generator is according to control signal output and described the first or the 2nd corresponding HOST clock signal of data that is provided with;
Second system controller, according to the described first or the 2nd HOST clock signal, output is as first or second reference clock signal of the memory clock signal reference of described memory module; With
Clock buffer is used to receive described first or second reference clock signal and will exports described memory module to the described first to fourth corresponding memory clock signal of data that is provided with then,
Wherein, if described memory module is the single side memory module, so described clock buffer cuts off the untapped memory clock signal of single face memory module described in described first to fourth memory clock signal by the described data that are provided with.
2. computer system as claimed in claim 1 is characterized in that described first system controller is by described memory data of SM (system management) bus transfer and the described data that are provided with.
3. computer system as claimed in claim 1 is characterized in that described clock generator and described clock buffer comprise and is used to store the described register that data are set.
4. as claim 1 or 3 described computer systems, it is characterized in that if described memory module is the single side memory module, then described clock buffer,
When described first reference clock signal of input, forbid described second memory clock signal and described the 4th memory clock signal and
When described second reference clock signal of input, forbid described the 3rd memory clock signal and described the 4th memory clock signal.
5. be used for the method for the memory clock signal of at least one DIMM of control computer system (dual inline memory modules), may further comprise the steps:
Enable first to fourth memory clock signal of all memory banks;
Determine whether memory module is inserted in certain slot in the described memory bank that enables;
If described memory module is inserted into wherein, then determine the type of the memory module of described insertion;
If described memory module is the double-side type memory module, then keep described first to fourth memory clock signal that enables;
If described memory module is the single side memory module, determine that then the bus speed of described memory module is first speed or second speed;
If described bus speed is described first speed, then forbid memory clock signal corresponding in described first to fourth memory clock signal with the described second speed of described memory module;
If described bus speed is described second speed, then forbid in described first to fourth memory clock signal the corresponding memory clock signal of described first speed with described memory module.
6. method as claimed in claim 5 is characterized in that if described memory module is not inserted into wherein, then forbids described first to fourth memory clock signal of respective memory module slot.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980043756A KR100578112B1 (en) | 1998-10-16 | 1998-10-16 | Computer system and method controlled memory clock signal |
| KR43756/1998 | 1998-10-16 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1251445A true CN1251445A (en) | 2000-04-26 |
| CN1118735C CN1118735C (en) | 2003-08-20 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN99111095A Expired - Fee Related CN1118735C (en) | 1998-10-16 | 1999-07-29 | Computer system of controlling clock signals of storage and control method thereof |
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| Country | Link |
|---|---|
| US (1) | US6530001B1 (en) |
| EP (1) | EP0994405A3 (en) |
| JP (1) | JP2000187525A (en) |
| KR (1) | KR100578112B1 (en) |
| CN (1) | CN1118735C (en) |
| TW (1) | TW452697B (en) |
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-
1998
- 1998-10-16 KR KR1019980043756A patent/KR100578112B1/en not_active IP Right Cessation
-
1999
- 1999-07-09 TW TW088111660A patent/TW452697B/en not_active IP Right Cessation
- 1999-07-29 CN CN99111095A patent/CN1118735C/en not_active Expired - Fee Related
- 1999-09-29 EP EP99307691A patent/EP0994405A3/en not_active Ceased
- 1999-10-18 US US09/419,774 patent/US6530001B1/en not_active Expired - Lifetime
- 1999-10-18 JP JP11295155A patent/JP2000187525A/en not_active Ceased
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110568905A (en) * | 2019-08-09 | 2019-12-13 | 苏州浪潮智能科技有限公司 | Hard disk backboard, signal processing method and medium |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0994405A2 (en) | 2000-04-19 |
| JP2000187525A (en) | 2000-07-04 |
| KR100578112B1 (en) | 2006-07-25 |
| KR20000026281A (en) | 2000-05-15 |
| US6530001B1 (en) | 2003-03-04 |
| EP0994405A3 (en) | 2005-11-09 |
| TW452697B (en) | 2001-09-01 |
| CN1118735C (en) | 2003-08-20 |
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