CN1228827C - Semiconductor chip package and process of operation - Google Patents
Semiconductor chip package and process of operation Download PDFInfo
- Publication number
- CN1228827C CN1228827C CNB03101951XA CN03101951A CN1228827C CN 1228827 C CN1228827 C CN 1228827C CN B03101951X A CNB03101951X A CN B03101951XA CN 03101951 A CN03101951 A CN 03101951A CN 1228827 C CN1228827 C CN 1228827C
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- carrier
- chip
- rerouting
- circuit
- insulating protective
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention relates to a semiconductor chip encapsulating structure and process steps thereof. A plurality of semiconductor chip encapsulating pieces with high density and small size are made on the same carrier in a batch method. The semiconductor chip encapsulating structure and the process steps are characterized in that insulating and isolating layers are formed on chips; weld spot arrays are formed on the insulating and isolating layers by using line rearrangement techniques; rearrangement lines are electrically connected to weld pads on the chips; weld spot arrays after rearrangement are arranged in areas exceeding the surface rang of the chips and are rather than the prior art that weld spot arrays are only limited on circuit surfaces of chips, and therefore, the present invention can be applied to the encapsulating structures of new microminiaturization (such as chip smaller than 90 nanometers) chips.
Description
Technical field
The invention relates to a kind of semiconductor die package technology, particularly about a kind of semiconductor chip package and operation, it can produce a plurality of high density and undersized semiconductor chip package in bulk mode on a slice carrier.
Background technology
Chip scale encapsulation technology (Chip Scale Package, CSP) as a kind of advanced person's encapsulation technology, packaging part can be sized to the size that is slightly larger than packaged chip, therefore can make packaging part reach minimized degree, meet compact requirement.
The CSP encapsulation technology of wafer scale (Wafer Level CSP) then is a kind of more advanced encapsulation technology, and all chips that each wafer can be cut out carry out the packaging process of chip scale in bulk mode, once can finish a plurality of packaging parts.
The relevant patent of the CSP encapsulation technology of wafer scale includes: United States Patent (USP) the 5th, 886, No. 409 " ELECTRODE STRUCTURE OF WIRING SUBSTRATE OFSEMICONDUCTOR DEVICE HAVING EXPANDED PITCH "; United States Patent (USP) the 5th, 892, No. 179 " SOLDER BUMPS AND STRUCTURES FORINTEGRATED REDISTRIBUTION ROUTING CONDUCTORS "; United States Patent (USP) the 6th, 103, No. 552 " WAFER SCALE PACKAGING SCHEME "; United States Patent (USP) the 6th, 350, No. 668 " LOW COST CHIP SIZE PACKAGE AND METHODOF FABRICATING THE SAME "; United States Patent (USP) the 6th, 433, No. 427 " WAFERLEVEL PACKAGE INCORPORATING DUAL STRESS BUFFERLAYERS FOR I/O REDISTRIBUTION AND, METHOD FORFABRICATION ".
The CSP encapsulation technology of wafer scale normally adopts rewiring technology (RedistributionLayer, RDL), solder joint is exported, gone into to non-power supply that is equally spaced and signal on the chip, be incorporated into a predefined equidistant weld pad array zone of arranging on the chip by the rewiring technology, use welding block (solder bumps) to be welded on this solder joint array again, thereby form ball grid array (Ball Grid Array, BGA), packaging part is welded and is electrically connected to outside printed circuit board (PCB) by this ball grid array.
Yet above-mentioned rewiring technology is that the solder joint array is configured on the chip surface, along with the semiconductor process development of technology, chip area dwindles gradually, the chip of minification does not have unnecessary space surface to hold the solder joint array of rewiring, therefore adapt to the trend of packaging part chip microminiaturization of new generation (less than 90 nanometers), the semiconductor industry need be developed a kind of new semiconductor chip package and operation.
Summary of the invention
For overcoming the shortcoming of above-mentioned prior art, main purpose of the present invention is to provide a kind of and is applicable to as semiconductor chip package and operation less than the microminiaturized Chip Packaging of new generation of 90 nanometers.
Semiconductor die package operation of the present invention comprises at least: (1) prefabricated carrier, this carrier have a positive and back side; (2) carry out putting brilliant program, with at least one chip placing on the front of this carrier; Wherein this chip has a circuit face and an inverter circuit face, and is formed with many weld pads on this circuit face; (3) carry out an insulation isolation layer operation, on the front of this carrier, form an insulation isolation layer whereby, and make this insulation isolation layer cover this chip fully, and expose the weld pad on this chip circuit face; (4) carry out a rewiring operation, on this insulation isolation layer, form many rerouting circuits whereby; Wherein an end points of each bar rerouting circuit is a corresponding weld pad that is electrically connected on this chip circuit face, and another end points then is predefined for pad; (5) carry out an insulating protective layer operation, form an insulating protective layer whereby and cover each bar rerouting circuit, but expose the predetermined pad of each bar rerouting circuit; (6) carry out planting the ball program, whereby a plurality of soldered balls are welded on each bar rerouting circuit not on the pad that is covered by this insulating protective layer, to form a ball grid array structure; And (7) carry out all single operations, cuts this carrier whereby, is partitioned into a plurality of semiconductor package parts.
Semiconductor chip package of the present invention comprises at least: (a) carrier, and it has a positive and back side; (b) chip, it has a circuit face and an inverter circuit face, and is formed with many weld pads on this circuit face; (c) an insulation isolation layer, this insulation isolation layer is to cover each chip fully, and exposes many weld pads on each chip circuit face; (d) many rerouting circuits, it is formed on this insulation isolation layer, and wherein an end points of each bar rerouting circuit is a corresponding weld pad that is electrically connected on this chip circuit face, and another end points is predefined for pad; (e) insulating protective layer in order to covering each bar rerouting circuit, but exposes the predetermined pad of each bar rerouting circuit; And (f) ball grid array, comprise a plurality of soldered balls, and each soldered ball is to be welded on each bar rerouting circuit not by on the pad that this insulating protective layer covered.
The characteristics of semiconductor chip package of the present invention and operation are that formation one insulation isolation layer forms the solder joint array with the rerouting circuit again on this insulation isolation layer on chip, and these rerouting circuits are electrically connected on the chip pad.Make the zone that needs the solder joint of circuit rerouting array to be placed in to exceed beyond the chip surface scope, and not only be confined on the chip surface, make the microminiaturized chip of a new generation's (below 90 nanometers) increase the shortcoming that layer technology remedies chip circuit layout area deficiency by resin.
Description of drawings
Fig. 1 is a cross-sectional view, shows the carrier of semiconductor chip package of the present invention and operation employing and the cross-section structure form of chip;
Fig. 2 is a cross-sectional view, shows the brilliant program of putting in the semiconductor die package operation of the present invention;
Fig. 3 is a cross-sectional view, shows the insulation isolation layer operation in the semiconductor die package operation of the present invention;
Fig. 4 is a cross-sectional view, shows the rerouting circuit operation in the semiconductor die package operation of the present invention;
Fig. 5 is a cross-sectional view, shows the insulating protective layer operation in the semiconductor die package operation of the present invention;
Fig. 6 is a cross-sectional view, shows to plant the ball program in the semiconductor die package operation of the present invention;
Fig. 7 is a cross-sectional view, wherein shows the segmentation procedure in the semiconductor die package operation of the present invention;
Fig. 8 is a cross-sectional view, shows another embodiment of semiconductor chip package of the present invention.
Embodiment
Embodiment
Below be conjunction with figs., describe the implementation process of semiconductor chip package of the present invention and operation in detail.It is noted that herein, Fig. 1 to Fig. 7 is the schematic diagram of simplification, therefore mode with signal illustrates basic conception of the present invention, only shows the assembly relevant with the present invention, and shown assembly is not, and number, shape and dimension scale when implementing with reality drawn; Number, shape and dimension scale during its actual enforcement can be a kind of design alternatives of randomness, and its assembly layout form may be more complicated.
At first, see also Fig. 1, the initial step of semiconductor die package operation of the present invention is the prefabricated carrier 10 of elder generation, this carrier 10 has positive 10a and back side 10b, and it can be selected from BT (Bismaleimide Triazine) substrate, metal substrate (for example copper substrate), ceramic substrate, silicon system substrate etc.In addition, cook up many lines of cut 11 in advance on this carrier front, in order to distinguish the entity scope of each packaging part.
Above-mentioned carrier 10 carries a collection of chip 20 simultaneously (to be annotated: because the canned program of these chips 20 is all identical, therefore in order to simplify accompanying drawing and explanation, in Fig. 1 and follow-up accompanying drawing, only show a chip), these chips 20 are that the thickness of elder generation's wafer that it is original (showing in the accompanying drawing) is ground to below the 3mil, cut into many single chips 20 again.Each chip 20 all has a circuit face 20a and an inverter circuit face 20b, and be formed with on its circuit face 20a a plurality of provide power supply and signal export into weld pad 21.
Secondly, see also Fig. 2, next procedure is the brilliant program of putting, and just with the inverter circuit face 20b of each chip 20, sticks with glue agent (as elargol) and pastes on the positive 10a of carrier 10, and the circuit face 20a that makes chip 20 up.
Afterwards, see also Fig. 3, next procedure is the isolation layer operation that insulate, on the positive 10a of this carrier 10, form insulation isolation layer 30 whereby, make this insulation isolation layer 30 cover each chip 20 fully, but insulation isolation layer 30 is formed with a plurality of openings 31, is used for exposing outside all weld pads 21 on the circuit face 20a of chip 20.Insulation isolation layer operation is to adopt existing rotary coating technology (spin coating), insulating material (dielectric) is coated on the positive 10a of carrier 10, thereby forms this insulation isolation layer 30.
Have, see also Fig. 4, next procedure is to carry out the rewiring operation (RedistributionLayer RDL), implements metallization (metallization) whereby to form many rerouting circuits 40 on this insulation isolation layer 30; Wherein an end points of each bar rerouting circuit 40 is the last corresponding pad 21 of circuit face 20a that are electrically connected to this chip 20, and another end points of rerouting circuit 40 is defined as pad 41.This rerouting circuit operation can adopt sputter technology (sputtering) or electroless plating coating technique (Electroless-plating) to form above-mentioned rerouting circuit 40.
Afterwards; see also Fig. 5; next procedure is to carry out the insulating protective layer operation; form an insulating protective layer (passivation layer) 50 whereby and cover above-mentioned all rerouting circuits 40; be formed with a plurality of openings 51 on this insulating protective layer 50, expose outside pad 41 predetermined on each bar rerouting circuit 40.These insulating protective layer 50 materials can be selected polyimides (polyimide), epoxy polymer (epoxy) for use or refuse welding flux layer (Solder Mask).
Then, see also Fig. 6, next procedure is to plant the ball program, whereby a plurality of soldered balls 60 is welded on each bar rerouting circuit 40 not on the pad 41 that is covered by this insulating protective layer 50, thereby forms ball grid array.
See also Fig. 7, next procedure is to cut single operation; This carrier 10 is cut list along its line of cut 11, be partitioned into a plurality of packaging parts whereby, promptly finish semiconductor die package operation of the present invention.
Generally speaking, the invention provides a kind of semiconductor chip package and operation of novelty, be characterized on chip, forming the insulation isolation layer, on this dielectric isolation layer, form the solder joint array with the rewiring technology again, these rerouting circuits are electrically connected to respectively on the weld pad of chip.Can make the solder joint array of finishing the circuit rerouting can be placed in the zone that exceeds outside the chip surface scope, rather than only be confined on the chip surface, therefore the microminiaturized chip of a new generation's (as less than 90 nanometers) can remedy the disappearance of chip circuit layout area deficiency by packaging process technology of the present invention.
Fig. 8 is another embodiment of semiconductor chip package of the present invention, operation that this embodiment adopts and structure and the foregoing description are roughly the same, on the pairing crystal area of packaging part scope that its difference is to plan in advance on this carrier 10, offer the opening 100 of place's area greater than semiconductor chip 20, putting brilliant program when carrying out, with chip 20 sticking being set in this opening 100, the chip 20 that makes tradition be placed in carrier 10 tops can further reduce the whole height of semiconductor package part by the taking in of this opening 100.
Claims (20)
1. a semiconductor die package operation is characterized in that, this packaging process may further comprise the steps:
(1) a prefabricated carrier, it has a positive and back side;
(2) carry out putting brilliant program, in order to settle at least the semiconductor chip to this carrier front, this chip has an action face and a relative non-action face, the non-action face of this semiconductor chip is contacted with carrier, and be formed with many weld pads on this action face;
(3) carry out an insulation isolation layer operation, on this chip and carrier, to form an insulation isolation layer, be formed with many openings on this insulation isolation layer so that on the chip respectively this weld pad expose;
(4) carry out a rerouting circuit operation, to form many rerouting circuits on this insulation isolation layer, wherein, each bar rerouting circuit is electrically connected to a corresponding pad on this chip, and forms a pad at line scan pickup coil side;
(5) carry out an insulating protective layer operation, cover the insulating protective layer of each bar rerouting circuit in order to form one, and expose the pad of each bar rerouting circuit;
(6) carry out planting the ball program, thereby form a ball grid array on the rerouting circuit pad that respectively exposes, to plant soldered ball respectively; And
(7) carry out all single operations, form a plurality of semiconductor package parts to cut this carrier.
2. semiconductor die package operation as claimed in claim 1 is characterized in that, the described carrier of step (1) is a silicon system substrate.
3. semiconductor die package operation as claimed in claim 1 is characterized in that, the described carrier of step (1) is a copper substrate.
4. semiconductor die package operation as claimed in claim 1 is characterized in that, the described carrier of step (1) is a BT substrate.
5. semiconductor die package operation as claimed in claim 1 is characterized in that, the described carrier of step (1) is a ceramic substrate.
6. semiconductor die package operation as claimed in claim 1 is characterized in that, the described insulation isolation layer of step (3) operation is to adopt the rotary coating technology, an insulating material is coated on the front of this carrier, forms this insulation isolation layer.
7. semiconductor die package operation as claimed in claim 1 is characterized in that, the described rerouting circuit of step (4) operation is to adopt the sputter technology to form these rerouting circuits on this insulation isolation layer.
8. semiconductor die package operation as claimed in claim 1 is characterized in that, the described rerouting circuit of step (4) operation is to adopt the electroless plating technology to form these rerouting circuits on this insulation isolation layer.
9. semiconductor die package operation as claimed in claim 1 is characterized in that, the described insulating protective layer operation of step (5) is to adopt polyimides to form this insulating protective layer.
10. semiconductor die package operation as claimed in claim 1 is characterized in that, the described insulating protective layer operation of step (5) is to adopt epoxy polymer to form this insulating protective layer.
11. semiconductor die package operation as claimed in claim 1 is characterized in that, the described insulating protective layer operation of step (5) is to adopt to refuse welding flux layer and form this insulating protective layer.
12. a semiconductor chip package is characterized in that, this structure comprises at least:
One carrier, it has a positive and back side;
One chip, it has a circuit face and an inverter circuit face, and this circuit face is provided with an assembly welding pad, and this chip placing is on the carrier front, and the inverter circuit face of this chip contacts with carrier;
One insulation isolation layer, and make this insulation isolation layer cover this chip fully, but expose the weld pad on this chip circuit face;
Many rerouting circuits are formed on this insulation isolation layer, and wherein, each rerouting circuit is electrically connected to a corresponding pad on this chip, and forms a pad at line scan pickup coil side;
One insulating protective layer covers each bar rerouting circuit, and exposes the pad of each bar rerouting circuit; And
One ball grid array, it comprises that further a plurality of planting is connected on this rerouting circuit and exposes soldered ball on the pad.
13. semiconductor chip package as claimed in claim 12 is characterized in that, this carrier is a silicon system substrate.
14. semiconductor chip package as claimed in claim 12 is characterized in that, this carrier is a copper substrate.
15. semiconductor chip package as claimed in claim 12 is characterized in that, this carrier is a BT substrate.
16. semiconductor chip package as claimed in claim 12 is characterized in that, this carrier is a ceramic substrate.
17. semiconductor chip package as claimed in claim 12 is characterized in that, on this carrier front corresponding to offering the opening of taking in chip on this semiconductor chip crystal area.
18. semiconductor chip package as claimed in claim 12 is characterized in that, the material of this insulating protective layer is a polyimides.
19. semiconductor chip package as claimed in claim 12 is characterized in that, the material of this insulating protective layer is an epoxy resin.
20. semiconductor chip package as claimed in claim 12 is characterized in that, the material of this insulating protective layer is to refuse welding flux layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB03101951XA CN1228827C (en) | 2003-01-30 | 2003-01-30 | Semiconductor chip package and process of operation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB03101951XA CN1228827C (en) | 2003-01-30 | 2003-01-30 | Semiconductor chip package and process of operation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1521818A CN1521818A (en) | 2004-08-18 |
| CN1228827C true CN1228827C (en) | 2005-11-23 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB03101951XA Expired - Lifetime CN1228827C (en) | 2003-01-30 | 2003-01-30 | Semiconductor chip package and process of operation |
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| CN (1) | CN1228827C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106971988A (en) * | 2015-12-11 | 2017-07-21 | 爱思开海力士有限公司 | Wafer-level packaging part and its manufacture method |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8264085B2 (en) * | 2008-05-05 | 2012-09-11 | Infineon Technologies Ag | Semiconductor device package interconnections |
| CN102376590B (en) * | 2010-08-05 | 2013-11-27 | 矽品精密工业股份有限公司 | Chip scale package and production method thereof |
| CN102427058B (en) * | 2011-11-09 | 2015-07-22 | 深南电路有限公司 | Method of manufacturing circuit pattern through sputtering technology and rewiring method of chip |
| CN105895605A (en) * | 2016-06-12 | 2016-08-24 | 华天科技（昆山）电子有限公司 | Thin chip mounted substrate fan-out type packaging structure and manufacturing method therefor |
-
2003
- 2003-01-30 CN CNB03101951XA patent/CN1228827C/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106971988A (en) * | 2015-12-11 | 2017-07-21 | 爱思开海力士有限公司 | Wafer-level packaging part and its manufacture method |
| CN106971988B (en) * | 2015-12-11 | 2019-11-08 | 爱思开海力士有限公司 | Wafer-level packaging part and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1521818A (en) | 2004-08-18 |
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