CN1214531C - Single-terminal input voltage level converter controlled by grid voltage - Google Patents
Single-terminal input voltage level converter controlled by grid voltage Download PDFInfo
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- CN1214531C CN1214531C CN 99121537 CN99121537A CN1214531C CN 1214531 C CN1214531 C CN 1214531C CN 99121537 CN99121537 CN 99121537 CN 99121537 A CN99121537 A CN 99121537A CN 1214531 C CN1214531 C CN 1214531C
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Abstract
The present invention relates to a single-ended input voltage level converter controlled by a grid voltage, which comprises a plurality of transistors and a phase inverter and is used for converting an input signal into an output signal of another voltage level, wherein grids of the transistors, which are used for controlling the input signal, can be converted at different voltage levels, so the input signal can be controlled to be switched on or switched off. Thus, the consumption of direct current can be decreased. Moreover, the structure can shorten converting time, improve the reaction speed and decrease electric consumption.
Description
The present invention relates to the signal voltage level transducer between a kind of integrated circuit (Integrated Circuit, be called for short IC), particularly a kind of voltage level shifter that uses the single-ended input that grid voltage controls.
Because semiconductor fabrication process demand benefit for low power consumption IC on deep-sub-micrometer (deep sub-micron) technological progress and the market increases, make that the operating voltage of IC inside is more and more lower, reduce to 3.3V or 2.5V from 5V in the past, and even reduced to 1.8V recently.But the signal transmission between the different IC must meet the bus-bar specification of industrial standard, can not follow the operating voltage of IC inside to diminish so export/go into buffer (input/output buffer) with the outside voltage level that connects of IC.
With reference to Fig. 1, it is two schematic diagrames that the signal between IC transmits.
As shown in the figure, the bus bar voltage specification of supposing the data passes between IC 110 and the IC 120 is Vpp (for example 3.3V), and the operating voltage of the core circuit among the IC 110 (core) 115 is Vdd
1(for example 3.3V, 2.5V or lower and 1.8V), the operating voltage of the core circuit 125 among the IC 120 then is Vdd
2Because it is different that the operating voltage of IC inside and external data are transmitted used voltage level, therefore have voltage level shifter 116 responsible voltage of signals level conversion between the core circuit 115 in IC 110 and the holding wire 130, the low voltage operating conversion of signals of IC inside is become the high voltage operation signal.Same, also have voltage level shifter 126 between core circuit 125 in IC120 and the holding wire 130 and be responsible for the voltage of signals level conversion.
With reference to Fig. 2 A, it is a kind of known voltage level shifter.
As shown in the figure, known voltage level shifter 200 comprise transistor 211,212,221, with 222, and inverter 230.Input signal Vi and be coupled to the grid of transistor 221 and 222 respectively through the complementary input signal Vi of inverter 230 output, therefore at one time in, have only a meeting conducting among the transistor 221 and 222. Transistor 211 and 212 is connected into regenerative structure in addition, can make the high-tension output signal Vo of output and complementary output signal Vo keep complementary state.
With reference to Fig. 2 B, it is the input signal Vi of known voltage level shifter 200 and the waveform of complementary output signal Vo.
At first, at time t
1, input signal Vi is Vdd (complementary input signal Vi is 0V), will make transistor 221 conductings and transistor 222 close this moment.This circuit is in when design, and the driving force that is about to transistor 221 and 222 is set at greater than transistor 211 and 212, so when the stable state of transistor 221 in conducting, will make complementary output signal Vo maintain 0V, and make transistor 212 conductings.Because transistor 222 closes and transistor 212 conductings, institute is so that output signal Vo maintains Vpp, and transistor 211 is closed.
When input signal Vi becomes 0V by Vdd, complementary input signal Vi will become Vdd, when just beginning to switch, and transistor 211 not conductings, transistor 221 is become by conducting closes, so complementary output signal Vo maintains 0V.At this moment, transistor 222 beginning conductings, because the grid of complementary output signal Vo oxide-semiconductor control transistors 212 makes transistor 212 keep conducting, therefore in this moment, the transistor 212 and 222 of series connection becomes conducting simultaneously.But because the driving force of transistor 222 is greater than transistor 212, and this moment, the drain electrode and the voltage difference between the source electrode of transistor 222 were bigger than the drain electrode and the voltage difference between the source electrode of transistor 212, so can being stayed by Vpp, the current potential of output signal Vo falls, at the same time, also can make transistor 211 conducting gradually, the related current potential of complementary output signal Vo that makes is toward rising.The current potential of complementary output signal Vo rises and also will impel transistor 212 to close, and makes the easier decline of output signal Vo.Forward circulation like this makes output signal Vo be stabilized in 0V at last and complementary output signal Vo is stabilized in Vpp, as the time t among the figure
2Shown in.
Though known voltage level shifter can reach the function of voltage of signals level conversion, but know by above discussion, in the process of switching, the transistor 211 and the transistor 221 of series connection, or transistor 212 and transistor 222 conducting simultaneously, and relying on the driving force of transistor 221 greater than transistor 211 again after the conducting fully, or the driving force of transistor 222 is greater than transistor 212, output signal Vo, or complementary output signal Vo is pulled to last stable potential, reaches the purpose of switching.Because in the process of switching, be connected on two transistors conducting simultaneously between power supply and the ground wire, make switching time elongated, reaction speed slows down, and because of the effect of direct-current short circuit power consumption is increased.
Therefore by above discussion, the handoff procedure of known voltage level shifter is because the conducting simultaneously of the transistor of series connection as can be known, and makes switching time elongated, and speed slows down, and than power consumption.
Therefore main purpose of the present invention is exactly a kind of voltage level shifter that uses the single-ended input that grid voltage controls to be provided, can to shorten switching time, improving reaction speed, and reduce power consumption.
For reaching above-mentioned and other purposes of the present invention, the present invention proposes a kind of single ended input voltage level translator that uses grid voltage control, in order to be a secondary signal with one first conversion of signals, this single ended input voltage level translator comprises a first transistor, a transistor seconds, one the 3rd transistor, one
Four transistors, one first inverter, and one second inverter.
Wherein the source electrode of this first transistor is coupled to this first signal.
The input of this first inverter is coupled to the drain electrode of this first transistor, second complementary signal of its output output and this secondary signal complementation, this second complementary signal is also delivered to the input of this second inverter, and the output of this second inverter is exported this secondary signal.
The source electrode of this transistor seconds is coupled to one first power supply, and its drain electrode is coupled to the grid of this first transistor, and its grid is accepted this second complementary signal control.Relative, the 3rd transistorized source electrode is coupled to a second source, and its drain electrode is coupled to the grid of this first transistor, and its grid is accepted this secondary signal control.Transistor seconds and the 3rd transistorized base stage all are coupled to this second source.
The 4th transistor drain and source electrode are coupled to input and this second source of this first inverter respectively, and its grid then is coupled to the output of this first inverter.And the 4th transistor is the faint transistor of driving force.
According to a preferred embodiment of the present invention, wherein the amplitude of this first signal be 0V between this first power supply, and the amplitude of this secondary signal is that 0V is between this second source.Therefore the power supply of this first inverter and this second inverter is this second source.
Wherein this first transistor is a NMOS FET, other transistor seconds, the 3rd transistor, and the 4th transistor all be a PMOS FET.
In order to improve driving force, also can comprise one the 3rd inverter and one the 4th inverter, the input of the 3rd inverter is coupled to the input of this first inverter, the output of the 3rd inverter is coupled to the output of the 4th inverter, an output output signal identical of the 3rd inverter with this second complementary signal, the output output signal identical with this secondary signal of the 4th inverter is in order to drive more load.
Also the two poles of the earth voltage level shifter can be connected in series, so that the conversion of the bigger signal of voltage differences to be provided.
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Fig. 1 is two schematic diagrames that the signal between IC transmits.
Fig. 2 A is known voltage level shifter.
Fig. 2 B is the input signal of known voltage level shifter and the waveform of output signal.
Fig. 3 is the circuit diagram of the single ended input voltage level translator of use grid voltage control of the present invention.
Fig. 4 A～Fig. 4 D and Fig. 5 A～Fig. 5 D are input signal, output signal, and the voltage waveforms of node of the voltage level shifter of Fig. 3.
Fig. 6 is that the voltage level shifter at Fig. 3 adds that extra inverter provides bigger driving force.
Fig. 7 is the bipolar voltage level translator that the voltage level shifter with two-stage Fig. 3 is concatenated into.
With reference to Fig. 3, it is a kind of circuit diagram that uses the single ended input voltage level translator of grid voltage control according to a preferred embodiment of the present invention, this voltage level shifter can be used to input signal Vi is converted to output signal Vo, wherein the amplitude of input signal Vi is between the 0V to Vdd, and the amplitude of output signal Vo is between the 0V to Vpp.
As shown in the figure, voltage level shifter 300 comprise transistor 310,312,314, with 316 and inverter 330 and 332.Wherein transistor 310 is N type metal oxide semiconductor (N typeMetal Oxide Semiconductor, be called for short NMOS) field-effect transistor (Field Effect Transistor, be called for short FET), and transistor 312,314, and 316 all be P-type mos (P typeMetal Oxide Semiconductor, be called for short PMOS) FET.Inverter 330 and 332 power supply are all power supply Vpp in addition.
Below explain the operation principles of voltage level shifter 300.
Making the input of inverter 330 is node N1, and the grid of transistor 310 is node N2.Output signal Vo changes can oxide- semiconductor control transistors 312 and 314 and change the current potential of node N2, when output signal Vo is 0V, when complementary output signal Vo is Vpp, transistor 312 will be closed, transistor 314 conductings, this moment, the current potential of node N2 was Vpp, and is relative, when output signal Vo is Vpp, when complementary output signal Vo is 0V, to make transistor 312 conductings, transistor 314 is closed, and this moment, the current potential of node N2 was Vdd.
When input signal Vi is 0V, the current potential of pipe node N2 is not Vpp or Vdd, all will make transistor 310 conductings, makes the current potential of node N1 become 0V, the complementary output signal Vo of inverter 330 outputs then becomes Vpp, and the output signal Vo of inverter 332 outputs becomes 0V.Because complementary output signal Vo is Vpp, transistor 316 will be closed, therefore the current potential of node N1 can maintain 0V, the change of output signal Vo and complementary output signal Vo in addition, transistor 312 will be closed, and making transistor 314 conductings, the current potential that makes node N2 is Vpp.
When input signal Vi rises to Vdd by 0V, because the current potential of node N2 is Vpp, and Vpp is greater than Vdd, so the current potential of node N1 can rise to the current potential near Vdd, make the complementary output signal Vo of inverter 330 outputs can switch to 0V, the output signal Vo of inverter 332 outputs then switches to Vpp.Because the variation of output signal Vo and complementary output signal Vo makes transistor 312 conductings, and transistor 314 closes, and the potential drop that makes node N2 is to Vdd.The grid of transistor 310 and the current potential of source electrode are all Vdd at this moment, and promptly the potential difference between grid and source electrode becomes 0V, and transistor 310 is closed.And the complementary output signal Vo of 0V can make transistor 316 conductings, and the current potential of node N1 is promoted to Vpp, and the consumption of no direct current between the source electrode of transistor 310 and drain electrode.
Inverter is the most basic element in the CMOS digit circuit, and its time delay is minimum, fastest, and voltage level shifter of the present invention is realized voltage level converting at a high speed by the advantage of inverter.And this circuit can be eliminated direct current via suitably arranging inverter.Therefore the voltage level shifter of designing can reach the high-speed purpose of low power consumption, and the ratio that does not need voltage level shifter as is well known will carefully adjust the driving force between the transistor just can reach best function.
In addition, also do not need to provide complementary input signal Vi, and can directly use when exporting at the complementary output signal Vo that the inverter of voltage level shifter of the present invention is exported via extra inverter at voltage level shifter of the present invention.
Moreover the transistorized grid voltage of known voltage level shifter all is with fixed voltage control, and the transistorized grid voltage of the control input signals in the voltage level shifter of the present invention is to adopt transformable mode, can promote switch speed.
Wave form varies when below being the running of voltage level shifter of the present invention.With reference to Fig. 4 A～Fig. 4 D and Fig. 5 A～Fig. 5 D, it is input signal Vi, output signal Vo, and the voltage waveform of node of voltage level shifter 300.
Wherein the Vdd of Fig. 4 A～Fig. 4 D is that 3.0V and Vpp are 5.0V.Waveform when being depicted as input signal Vi and becoming high potential by electronegative potential as Fig. 4 A, after input signal Vi rises to 3.0V by 0V, complementary output signal Vo drops to 0V by 5V earlier, and output signal Vo is delaying a blink slightly, also rises to 5V by 0V.Waveform when being depicted as input signal Vi and becoming electronegative potential by high potential as Fig. 4 B, after input signal Vi drops to 0V by 3.0V, complementary output signal Vo rises to 5V by 0V earlier, and output signal Vo is delaying a blink slightly, also drops to 0V by 5V.No matter know that by the waveform among the figure output signal is that rise time or fall time are all at 0.5NS (10
-9Second) within, and the rise time of known voltage level shifter, or then surpass 1NS fall time.Fig. 4 C is input signal Vi when rising to 3.0V by 0V, and the current potential that the current potential of node N1 rises to 5.0V and node N2 by 0V is dropped to the waveform of 3.0V by 5.0V.Relative, Fig. 4 D is input signal Vi when dropping to 0V by 3.0V, and the current potential that the current potential of node N1 drops to 0V and node N2 by 5.0V is risen to the waveform of 5.0V by 3.0V.
Wherein the Vdd of Fig. 5 A～Fig. 5 D is that 2.5V and Vpp are 3.3V.Shown in Fig. 5 A, after input signal Vi rose to 2.5V by 0V, complementary output signal Vo dropped to 0V by 3.3V earlier, and output signal Vo is delaying a blink slightly, also rises to 3.3V by 0V.Shown in Fig. 5 B, after input signal Vi dropped to 0V by 2.5V, complementary input signal Vo rose to 3.3V by 0V earlier, and output signal Vo is delaying a blink slightly, also drops to 0V by 3.3V.No matter know that by the waveform among the figure output signal is that rise time or fall time are all at 0.3NS (1NS=10
-9Second) within.Fig. 5 C is input signal Vi when rising to 2.5V by 0V, and the current potential that the current potential of node N1 rises to 3.3V and node N2 by 0V is dropped to the waveform of 2.5V by 3.3V.Relative, Fig. 5 D is input signal Vi when dropping to 0V by 2.5V, and the current potential that the current potential of node N1 drops to 0V and node N2 by 3.3V is risen to the waveform of 3.3V by 2.5V.
The reaction time of the output signal of voltage level shifter of the present invention all can be lower than 0.5NS as can be known by above waveform, the reaction time of known voltage level shifter then can surpass 1NS, and therefore voltage level shifter of the present invention has reaction speed faster than known voltage level shifter.
With reference to Fig. 6, it is for adding that extra inverter is to provide bigger driving force.
As shown in the figure,, in the circuit of original voltage level shifter 300, add extra inverter 630 and 632, wherein the signal Vo that exports of inverter 630 outputs in order to provide bigger driving force to drive more or bigger load
1With complementary output signal Vo is identical, can be used to drive load 640, and the signal Vo that inverter 632 outputs are exported
1Then identical with output signal Vo, can be used to drive load 642.Through the inverter 630 and 632 of the extra adding of circuit thus, make it have bigger driving force, but can not influence the speed of feedback circuit, can keep the reaction speed of voltage level shifter 300.
When the amplitude of input signal Vi and output signal Vo differs too big, promptly Vdd＜＜Vpp, can use the twin-stage voltage level shifter 700 of two-stage structure as shown in Figure 7 to carry out conversion of signals, so that can reach optimization time of delay.
As shown in the figure, twin-stage voltage level shifter 700 is to be formed by first order voltage level shifter 710 and second level voltage level shifter 720 serial connections.Wherein input signal Vi delivers to first order voltage level shifter 710, the complementary output signal Vo of first order voltage level shifter 710 outputs
1The input signal Vi that then treats as second level voltage level shifter 720
2, last output signal Vo by second level voltage level shifter 720 output required voltage level
2And Vo
2Wherein the amplitude of input signal Vi is 0 to Vdd, output signal Vo
1(Vo
1) amplitude be 0 to Vdd
2, Shu Chu output signal Vo at last
2(Vo
2) amplitude be 0 to Vpp.
From above discussion, the single ended input voltage level translator of use grid voltage control of the present invention as can be known and the known practice relatively have following advantage, can shorten switching time, promote reaction speed, and reduce power consumption.And can add extra inverter at an easy rate to drive more load, also can provide the conversion of the signal of big voltage differences, make to reach optimization time of delay with the two poles of the earth voltage level shifter of serial connection.
Though the present invention discloses as above with a preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when the change that can do a little and retouching, so protection scope of the present invention should be as the criterion with claims institute confining spectrum.
Claims (15)
1. single ended input voltage level translator that uses grid voltage control, in order to be a secondary signal with one first conversion of signals, this single ended input voltage level translator comprises:
One the first transistor, its source electrode are coupled to this first signal;
One first inverter, its input is coupled to the drain electrode of this first transistor, one second complementary signal of its output output and this secondary signal complementation;
One second inverter, its input is coupled to the output of this first inverter, and its output is exported this secondary signal;
One transistor seconds, its source electrode are coupled to one first power supply, and its drain electrode is coupled to the grid of this first transistor, and its grid is accepted this second complementary signal control.
One the 3rd transistor, its source electrode is coupled to a second source, and its drain electrode is coupled to the grid of this first transistor, and its grid is accepted this secondary signal control; And
One the 4th transistor, its source electrode is coupled to the input of this first inverter, and its drain electrode is coupled to this second source, and its grid is coupled to the output of this first inverter.
2. the single ended input voltage level translator of use grid voltage control as claimed in claim 1, wherein the amplitude of this first signal is that 0V is between this first power supply.
3. the single ended input voltage level translator of use grid voltage control as claimed in claim 2, wherein the amplitude of this secondary signal is that 0V is between this second source.
4. the single ended input voltage level translator of use grid voltage control as claimed in claim 3, wherein the power supply of this first inverter and this second inverter is this second source.
5. the single ended input voltage level translator of use grid voltage control as claimed in claim 1, wherein this first transistor is a NMOS FET.
6. the single ended input voltage level translator of use grid voltage as claimed in claim 5 control, wherein this transistor seconds, the 3rd transistor, and the 4th transistor be a PMOS FET.
7. the single ended input voltage level translator of use grid voltage control as claimed in claim 1, wherein the 4th transistorized driving force is fainter than other transistorized driving forces in the circuit.
8. the single ended input voltage level translator of use grid voltage control as claimed in claim 1, wherein also comprise one the 3rd inverter and one the 4th inverter, the input of the 3rd inverter is coupled to the input of this first inverter, the output of the 3rd inverter is coupled to the input of the 4th inverter, an output output signal identical of the 3rd inverter with this second complementary signal, the output output signal identical with this secondary signal of the 4th inverter is in order to drive more loads.
9. single ended input voltage level translator that uses grid voltage control, in order to being a secondary signal with one first conversion of signals, this single ended input voltage level translator comprises one first voltage level shifter and one second voltage level shifter, and each this voltage level shifter all comprises:
One the first transistor;
One first inverter, its input is coupled to the drain electrode of this first transistor;
One second inverter, its input is coupled to the output of this first inverter;
One transistor seconds, its drain electrode is coupled to the grid of this first transistor, and its grid is coupled to the output of this first inverter;
One the 3rd transistor, its drain electrode is coupled to the grid of this first transistor, and its grid is coupled to the output of this second inverter; And
One the 4th transistor, its drain electrode is coupled to the input of this first inverter, and its grid is coupled to the output of this inverter,
Wherein, the source electrode of this first transistor of this first voltage level shifter is coupled to this first signal, the output of this first inverter of this first voltage level shifter is coupled to the source electrode of this first transistor of this second voltage level shifter, the output of this first inverter of this second voltage level shifter is exported this secondary signal, the source electrode of this transistor seconds of this first voltage level shifter is coupled to one first power supply, the 3rd transistor of this first voltage level shifter and the 4th transistorized source electrode are coupled to a second source, the 3rd transistor of this second voltage level shifter and the 4th transistorized source electrode are coupled to one the 3rd power supply, and the source electrode of this transistor seconds of this second voltage level shifter is coupled to this second source.
10. the single ended input voltage level translator of use grid voltage control as claimed in claim 9, wherein the amplitude of this first signal is that 0V is between this first power supply.
11. the single ended input voltage level translator of use grid voltage control as claimed in claim 10, wherein the amplitude of this secondary signal is that 0V is between this second source.
12. the single ended input voltage level translator of use grid voltage control as claimed in claim 11, wherein the power supply of this first inverter of this first voltage level shifter and this second inverter is this second source.
13. the single ended input voltage level translator of use grid voltage control as claimed in claim 12, wherein the power supply of this first inverter of this second voltage level shifter and this second inverter is the 3rd power supply.
14. the single ended input voltage level translator of use grid voltage as claimed in claim 9 control, wherein the two this first transistor of this first voltage level shifter and this second voltage level shifter is a NMOS FET.
15. the single ended input voltage level translator of use grid voltage as claimed in claim 14 control, wherein this second voltage level shifter of this first voltage level shifter the two this transistor seconds, the 3rd transistor, and the 4th transistor be a PMOS FET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 99121537 CN1214531C (en) | 1999-10-15 | 1999-10-15 | Single-terminal input voltage level converter controlled by grid voltage |
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|---|---|---|---|
| CN 99121537 CN1214531C (en) | 1999-10-15 | 1999-10-15 | Single-terminal input voltage level converter controlled by grid voltage |
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| CN1214531C true CN1214531C (en) | 2005-08-10 |
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1999
- 1999-10-15 CN CN 99121537 patent/CN1214531C/en not_active Expired - Lifetime
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