CN118763119A

CN118763119A - Super junction power device and manufacturing method thereof

Info

Publication number: CN118763119A
Application number: CN202411247783.3A
Authority: CN
Inventors: 王宝柱; 徐弘毅; 吴九鹏; 王加坤
Original assignee: Hangzhou Xinmai Semiconductor Technology Co ltd
Current assignee: Hangzhou Xinmai Semiconductor Technology Co ltd
Priority date: 2024-09-06
Filing date: 2024-09-06
Publication date: 2024-10-11

Abstract

The application discloses a super junction power device which comprises a substrate layer, an epitaxial layer, a gate structure, a dielectric region, well regions, a source region and a well contact region, wherein the dielectric region is positioned below the gate structure, the well regions are positioned on two sides of the gate structure and the dielectric region, and the source region and the well contact region are positioned in the well region. A semiconductor layer having a second conductivity type is coated on a portion of the sidewall of the dielectric region. The portion of the dielectric region not covering the semiconductor layer is located at least under the gate structure between the source regions. The super junction power device provided by the application has the advantages that the cell size is obviously reduced, and the conduction performance of the device is good. Meanwhile, the manufacturing method provided by the application is simple and feasible, and can obviously reduce the process time and the manufacturing cost.

Description

Super junction power device and manufacturing method thereof

Technical Field

The application relates to the technical field of semiconductors, in particular to a super junction power device and a manufacturing method thereof.

Background

In a power device having a superjunction structure, the drift layer generally includes an n-type pillar and a p-type pillar. The n-type pillars constitute the current path of the power device. The p-type pillars are used to obtain a high reverse breakdown voltage between the drain and source of the power device. When the power device is turned on, the high impurity concentration in the n-type column makes the on-resistance of the power device small. When the power device is turned off and a reverse voltage is applied, a depletion region between the n-type pillar and the p-type pillar extends laterally so as to form a high reverse breakdown voltage even in the case of a high impurity concentration within the n-type pillar.

The existing super junction power device manufacturing method mainly comprises two types. One such method is a multi-layer epitaxy technique, i.e., forming epitaxial layers multiple times, and forming p-type regions in each epitaxial layer using a masking process. And p-type areas in the epitaxial layers are overlapped up and down to form p-type columns, so that a super junction structure is realized. The p-type pillars of the multilayer epitaxial technique are formed by multiple p-type ion implants and push junctions. The device size is larger. And the concentration of the interface of the pn junction formed by injecting the push junction is not uniform, and the sugar-gourd-shaped distribution is presented. Such a curved interface is detrimental to charge balance across the pn junction and may lead to a drop in the breakdown voltage of the power device. Another method is deep trench epitaxial backfill technique, i.e., etching multiple deep trenches in the epitaxial layer, followed by filling the deep trenches with p-type material to form p-type pillars, thereby realizing a superjunction structure. The p-type column of the deep trench epitaxy backfill technology is realized by the deep trench backfill p-type material, the process flow is relatively simple compared with the multilayer epitaxy technology, the device size is usually smaller than that of the multilayer epitaxy, and the concentration distribution of the pn junction interface is relatively straight and uniform. However, the process difficulty of filling epitaxy in the deep groove is high, the p-type column formed by backfilling is easy to generate holes, so that the leakage between the source and the drain of the power device is increased, and the power device is possibly invalid when serious.

Disclosure of Invention

The application provides a super junction power device and a manufacturing method thereof. The super junction power device provided by the application has the advantages that the cell size is obviously reduced, and the conduction performance of the device is excellent. And the gate-drain capacitance of the device is greatly reduced due to the structure of filling the dielectric medium in the deep groove, so that the switching speed of the device is improved, and the switching loss of the device is further reduced. The manufacturing method provided by the application forms the super junction structure in the epitaxial layer by forming the semiconductor layer with the specific doping type on the side wall of the deep groove of the epitaxial layer and then filling the dielectric medium into the deep groove covered with the semiconductor layer. The manufacturing method provided by the application is simple and feasible, and can obviously reduce the process time and the manufacturing cost.

According to an embodiment of the present application, there is provided a superjunction power device including a substrate layer, an epitaxial layer, a gate structure, a dielectric region, a well region, a source region, and a well contact region. The substrate layer has a first conductivity type. The epitaxial layer is located over the substrate layer and has a first conductivity type. A dielectric region is located under the gate structure. The well region is positioned in the epitaxial layer and at two sides of the grid structure and has a second conductivity type. The source region is positioned in the well region and at two sides of the gate structure and has a first conductivity type. The well contact region is positioned in the well region and at two sides of the gate structure and has a second conductivity type. A portion of the sidewall of the dielectric region is covered with a semiconductor layer having a second conductivity type. The portion of the dielectric region not covering the semiconductor layer is located at least under the gate structure between the source regions.

According to an embodiment of the present application, in the super junction power device, the source regions and the well contact regions are alternately distributed in a first direction parallel to a length direction of the gate structure on each side of the gate structure.

According to an embodiment of the present application, the super junction power device further includes a well contact region including a hanging portion. The underhung portion is connected with the side wall of the gate structure and connected with the top of the semiconductor layer.

According to an embodiment of the application, a method for manufacturing a super junction power device is provided. The superjunction power device includes parallel and opposing first and second surfaces. The manufacturing method comprises the following steps: forming a substrate layer; forming an epitaxial layer over the substrate layer; forming a well region in the epitaxial layer at a part close to the first surface of the super junction power device; forming source regions distributed in a strip shape in the well region; forming grooves in the epitaxial layer along the direction perpendicular to the source regions distributed in the strip shape; covering ion implantation protective layers on the groove areas between the source areas and the upper parts of the source areas; performing first inclined ion implantation, and forming a semiconductor layer on the side wall of the groove and the surface area of the well region which are not covered by the ion implantation protective layer; forming a well contact region in a region of the semiconductor layer near the top of the trench by a second inclined ion implantation, wherein the angle of the second inclined ion implantation is larger than that of the first inclined ion implantation, and the well contact region comprises a flat portion and a lower hanging portion, and the lower hanging portion is connected with the semiconductor layer; filling dielectric in the groove after removing the ion implantation protective layer to form a dielectric region, wherein the distance from the top of the dielectric region to the first surface of the super junction power device is larger than the distance from the bottom of the well region to the first surface of the super junction power device; and forming a gate structure in the dielectric filled trench.

According to an embodiment of the application, a method for manufacturing a super junction power device is provided. The superjunction power device includes parallel and opposing first and second surfaces. The manufacturing method comprises the following steps: forming a substrate layer; forming an epitaxial layer over the substrate layer; forming a well region in the epitaxial layer at a part close to the first surface of the super junction power device; forming source regions distributed in a strip shape in the well region; forming grooves in the epitaxial layer along the direction perpendicular to the source regions distributed in the strip shape; covering ion implantation protective layers on the channel regions between the source regions corresponding to the two sides of the channel and the upper parts of the source regions; performing first inclined ion implantation, and forming a semiconductor layer on the side wall of the groove and the surface area of the well region which are not covered by the ion implantation protective layer; a second angled ion implantation to reduce the impurity concentration of the region of the semiconductor layer near the top of the trench, wherein the impurity type of the second angled ion implantation is related to the impurity type of the first angled ion implantation, and the angle of the second angled ion implantation is greater than the angle of the first angled ion implantation; vertical ion implantation, forming a well contact region in the region of the semiconductor layer in the well region, wherein the bottom of the well contact region is higher than the bottom of the well region; filling dielectric in the groove after removing the ion implantation protective layer to form a dielectric region, wherein the distance from the top of the dielectric region to the first surface of the super junction power device is larger than the distance from the bottom of the well region to the first surface of the super junction power device; and forming a gate structure in the dielectric filled trench.

According to an embodiment of the application, a method for manufacturing a super junction power device is provided. The superjunction power device includes parallel and opposing first and second surfaces. The manufacturing method comprises the following steps: forming a substrate layer; forming an epitaxial layer over the substrate layer; forming a well region in the epitaxial layer at a part close to the first surface of the super junction power device; forming source regions distributed in a strip shape in the well region; forming a first trench in the epitaxial layer along a direction perpendicular to the source regions of the stripe-shaped distribution; removing the epitaxial layer below the first trenches between the well regions to form second trenches while retaining the epitaxial layer below the first trenches between the source regions; covering an ion implantation protection layer on the source region and the region in the first groove between the source regions; performing first inclined ion implantation, and forming a semiconductor layer on the side wall of the second groove and the surface area of the well region which are not covered by the ion implantation protective layer; forming a well contact region in a region of the semiconductor layer near the top of the second trench by a second inclined ion implantation, wherein the angle of the second inclined ion implantation is larger than that of the first inclined ion implantation, and the well contact region comprises a flat portion and a lower hanging portion, and the lower hanging portion is connected with the semiconductor layer; filling dielectric in the second groove after removing the ion implantation protective layer to form a dielectric region, wherein the top of the dielectric region in the second groove is flush with the bottom of the first groove, and the distance from the top of the dielectric region in the second groove to the first surface of the super junction power device is larger than the distance from the bottom of the well region to the first surface of the super junction power device; and forming a gate structure in the first trench and over the dielectric region.

According to an embodiment of the present application, in the super junction power device, a junction between the underhung portion of the well contact region and the semiconductor layer is lower than a bottom of the gate structure.

Drawings

The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application with reference to the accompanying drawings in which:

fig. 1 is a schematic structural diagram of a partial cell region of a superjunction power device 100 according to an embodiment of the present application;

FIG. 2 is a schematic cross-sectional view of a portion of the cell region of the superjunction power device 100 shown in FIG. 1 along line A-A in accordance with one embodiment of the present application;

FIG. 3 is a schematic cross-sectional view of a portion of the cell region of the superjunction power device 100 shown in FIG. 1 along line B-B according to an embodiment of the present application;

fig. 4 illustrates a top view of a superjunction power device 400 according to an embodiment of the present application;

fig. 5 illustrates a process of steps of a method 500 of fabricating a superjunction power device 100 according to an embodiment of the present application;

Fig. 6A-6J illustrate schematic device structure diagrams during the fabrication of superjunction power device 100 according to a fabrication method 500 according to an embodiment of the present application;

Fig. 7 is a schematic structural diagram of a partial cell region of a superjunction power device 700 according to an embodiment of the present application;

fig. 8 illustrates a process of steps of a method 800 of fabricating a superjunction power device 700 according to an embodiment of the present application;

fig. 9 is a schematic structural diagram of a partial cell region of a superjunction power device 900 according to an embodiment of the present application;

FIG. 10 is a schematic cross-sectional view of a portion of a cell region of the super junction power device 900 shown in FIG. 9 along the line C-C according to an embodiment of the present application;

FIG. 11 is a schematic cross-sectional view of a portion of the cell region of the superjunction power device 900 shown in FIG. 9 along the D-D line, according to an embodiment of the present application;

FIG. 12 is a schematic cross-sectional view of a portion of a cell region of the superjunction power device 900 shown in FIG. 9 along the D-D line, according to another embodiment of the present application;

fig. 13 illustrates a process of steps of a method 1300 of fabricating a superjunction power device 900 according to an embodiment of the present application;

Fig. 14A-14E illustrate device schematic diagrams during the fabrication of a superjunction power device 900 according to a fabrication method 1300 according to an embodiment of the present application;

fig. 15 is a schematic structural diagram of a partial cell area of a superjunction power device 1500 according to an embodiment of the present application.

Detailed Description

Specific embodiments of the application will be described in detail below, it being noted that the embodiments described herein are for illustration only and are not intended to limit the application. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one of ordinary skill in the art that: no such specific details are necessary to practice the application. In other instances, well-known circuits, materials, or methods have not been described in detail in order not to obscure the application.

Throughout the specification, references to "one embodiment," "an embodiment," "one example," or "an example" mean: a particular feature, structure, or characteristic described in connection with the embodiment or example is included within at least one embodiment of the application. Thus, the appearances of the phrases "in one embodiment," "in an embodiment," "one example," or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments or examples. Moreover, those of ordinary skill in the art will appreciate that the drawings are provided herein for illustrative purposes and that the drawings are not necessarily drawn to scale. Like reference numerals designate like elements. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items. The figures are not drawn to scale and are for illustrative purposes only. For purposes of clarity, the same elements have been designated by corresponding reference numerals in the different drawings unless otherwise specified.

The terms "having," "including," "comprising," and the like are open-ended, and these terms mean that there are additional elements or features, but not exclude additional elements or features.

When describing the structure of a device, when a layer, an area, is referred to as being "on" or "over" another layer, another area, it can be directly on the other layer, another area, or other layers or areas can be included between the layer, another area, and the other layer, another area. And if the device is flipped, the one layer, one region, will be "under" or "under" the other layer, another region.

If, for the purposes of describing a situation directly overlying another layer, another region, the expression "directly overlying … …" or "overlying and adjoining … …" will be used herein.

The relative doping concentrations are illustrated herein by indicating "-" or "+" alongside the doping types "n" or "p". For example, "n-" means that the doping concentration is lower than that of the "n" doped region, and the "n" doped region has a higher doping concentration than the "n-" doped region. Doped regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" type doped regions may have the same or different absolute doping concentrations.

In an embodiment of the present application, each semiconductor layer or region has either a first conductivity type or a second conductivity type. The first conductivity type refers to one of n-type or p-type, and the second conductivity type is the other. That is, the semiconductor layer having the first conductivity type may be an n-type semiconductor layer or a p-type semiconductor layer. When the semiconductor layer having the first conductivity type is an n-type semiconductor layer, the semiconductor layer having the second conductivity type is a p-type semiconductor layer. The n-type semiconductor layer is formed by doping an n-type impurity in the semiconductor layer. The n-type impurity may be a pentavalent element such as phosphorus, arsenic, etc. The p-type semiconductor layer is formed by doping a p-type impurity in the semiconductor layer. The p-type impurity may be trivalent elements such as boron, indium, gallium, etc.

Fig. 1 is a schematic structural diagram of a partial cell region of a superjunction power device 100 according to an embodiment of the present application. It should be appreciated that superjunction power device 100 includes multiple functional regions, such as a cell region and a termination region, where the cell region also includes multiple repeating cell units. For clarity of illustration, FIG. 1 shows a portion of the cell area therein to facilitate an understanding of embodiments of the present application.

Superjunction power device 100 may be or include a insulated gate field effect Transistor, such as a MOSFET (Metal Oxide Semiconductor FIELD EFFECT Transistor) or the like.

As shown in fig. 1, superjunction power device 100 has a first surface 101 and a second surface 102. The first surface 101 and the second surface 102 are parallel to each other and are opposite, i.e. facing in opposite directions in the y-direction as shown in fig. 1. Superjunction power device 100 includes a substrate layer 110, an epitaxial layer 111, a gate structure 103, a well region 112, a well contact region 114, and a source region 115.

In the fig. 1 embodiment, substrate layer 110 has parallel and opposite first and second surfaces. The first surface of the substrate layer 110 is in contact with the epitaxial layer 111, i.e. the epitaxial layer 111 is located above the first surface of the substrate layer 110. The second surface of the substrate layer 110 is the second surface 102 of the superjunction power device 100. The epitaxial layer 111 has a first surface and a second surface. The first surface of epitaxial layer 111 is first surface 101 of superjunction power device 100. The second surface of epitaxial layer 111 interfaces with the first surface of substrate layer 110. In the fig. 1 embodiment, both substrate layer 110 and epitaxial layer 111 have a first conductivity type. The doping concentration of the substrate layer 110 is higher than the doping concentration of the epitaxial layer 111.

In the embodiment of fig. 1, superjunction power device 100 is an n-type MOSFET, the first conductivity type is n-type, and the second conductivity type is p-type. It should be appreciated that the first conductivity type and the second conductivity type may be switched with different applications. For example, in a p-type MOSFET, the first conductivity type is p-type and the second conductivity type is n-type.

The embodiment of fig. 1 shows a structure in which the epitaxial layer is a semiconductor layer of a single doping concentration. It should be appreciated that in other embodiments, the epitaxial layer may comprise a plurality of semiconductor layers of different doping concentrations.

In the embodiment of fig. 1, the gate structure 103 is a trench gate structure, and is in a stripe shape in the epitaxial layer 111, and its length direction is along the z direction as shown in fig. 1. The gate structure 103 includes a gate trench 131, a gate insulating layer 117, and a gate electrode 116. The gate trench 131 extends vertically from the first surface 101 into the epitaxial layer 111. The gate insulating layer 117 covers the inner wall of the gate trench 131. The gate electrode 116 is located in the gate trench 131 and is isolated from the gate trench 131 by the gate insulating layer 117. In some embodiments, the material of the gate insulating layer 117 may be silicon oxide, silicon nitride, a combination of both, or the like, formed by thermal oxygen growth or deposition. In some embodiments, the gate electrode 116 is made of a conductive material such as metal or polysilicon.

As shown in fig. 1, well region 112 is located in a portion of epitaxial layer 111 that is adjacent to first surface 101. Well region 112 is distributed on both sides of gate structure 103. Well region 112 has a second conductivity type. Source region 115 is located in well region 112 and is exposed at first surface 101. At the first surface 101, the source regions 115 are distributed in a stripe shape in the x-direction as shown in fig. 1. The stripe-shaped source region 115 is perpendicular to the length direction of the gate structure 103 and is cut by the gate structure 103, so as to form a structure distributed on both sides of the gate structure 103. Source region 115 has a first conductivity type. Well contact region 114 is located in well region 112 and is exposed at first surface 101. On the first surface 101, the well contact regions 114 are distributed in a stripe shape in the x direction as shown in fig. 1. The stripe-shaped well contact region 114 is perpendicular to the length direction of the gate structure 103 and is cut off by the gate structure 103, forming a structure distributed on both sides of the gate structure 103. In the z-direction as shown in fig. 1, well contact region 114 meets source region 115. The source region 115 and the well contact region 114 are each distributed along the length direction of the gate structure 103 on both sides of the gate structure 103.

In the embodiment of fig. 1, dielectric regions 118 are distributed in the lower region of the gate structure 103. The dielectric region 118 extends from the bottom of the gate structure 103 to the second surface of the epitaxial layer 111, i.e., to the first surface of the substrate layer 110.

In the fig. 1 embodiment, dielectric region 118 includes a first dielectric region 118a and a second dielectric region 118b. The first dielectric regions 118a and the second dielectric regions 118b are alternately arranged along the z-direction. The first dielectric region 118a is located below the gate structure 103 and at a position between the well contact regions 114 on both sides of the gate structure 103. A second dielectric region 118b (shown in fig. 2) is located below the gate structure 103 and between the source regions 115 on either side of the gate structure 103. The first dielectric regions 118a and the second dielectric regions 118b are alternately arranged along the z-direction. A semiconductor layer 113 is coated on a sidewall of the first dielectric region 118a along the z-direction. The semiconductor layer 113 has a second conductivity type.

The well contact region 114 includes a flat portion 114a and an underhung portion 114b, which are schematically distinguished by a broken line in fig. 1. The lower hanging portion 114b meets the flat portion 114a and extends downward along the sidewall of the gate structure 103, i.e., in a direction away from the first surface 101. The bottom of the under-hanging portion 114b of the well contact region 114 is connected to the semiconductor layer 113. In the embodiment of fig. 1, the interface position of the underhung portion 114b of the well contact region 114 and the semiconductor layer 113 is lower than the bottom of the gate structure 103. For a SiC MOSFET device, when the gate structure 103 is a trench gate structure, the interface position of the well contact region 114 connected to the semiconductor layer 113 is lower than the bottom of the gate structure 103, so that the maximum electric field of the gate oxide of the trench gate can be effectively reduced, and the long-term reliability of the device can be improved.

In the embodiment of fig. 1, the doping concentration of the well contact region 114 is higher than the doping concentration of the semiconductor layer 113. In contrast, the well contact region 114 and the source region 115 are regions of high doping concentration. When superjunction power device 100 is used in a circuit, well contact region 114 is connected to the well potential and source region 115 is connected to the source potential. In some embodiments, the well potential and the source potential are the same.

Fig. 2 is a schematic cross-sectional view of a portion of a cell region of the superjunction power device 100 shown in fig. 1 along A-A line according to an embodiment of the present application. As shown in fig. 2, well region 112 is located in epitaxial layer 111 near first surface 101, source region 115 is located within well region 112, and its bottom does not exceed the bottom of well region 112, i.e., the entire source region 115 is located within well region 112. One of the sidewalls of the source region 115 and the well region 112 is connected to a sidewall of the gate structure 103. Below the gate structure 103 is a second dielectric region 118b that meets the bottom of the gate structure 103. In this cross section, the semiconductor layer 113 is not present on the sidewalls of the second dielectric region 118b along the z direction, and the second dielectric region 118b directly adjoins the epitaxial layer 111 on both sides. Epitaxial layer 111 on both sides of second dielectric region 118b provides a current path from source region 115 to substrate layer 110. It should be appreciated that when the current capability requirements of the device are not high, the semiconductor layer 113 may suitably extend to the region between the source regions 115, and not necessarily under the gate structure 103 between the well contact regions 114. Similarly, when there is another region of the power device other than the well contact region 114 and the source region 115, the dielectric region sidewall under the gate structure between the other regions may also be covered with the semiconductor layer 113. That is, as long as a certain region not covered by the semiconductor layer 113 remains on the side wall of the dielectric region under the gate structure between the sources to ensure a current path from the source region to the substrate layer, it is not necessary that all the side walls of the dielectric region under the gate structure between the sources do not cover the semiconductor layer 113. Likewise, the semiconductor layer 113 does not have to cover all sidewalls of the dielectric region under the gate structure 103 between the well contact regions 114.

In the superjunction power device 100, the n-type epitaxial layer 111 and the p-type semiconductor layer 113 constitute a superjunction structure. The dielectric region 118 under the gate structure 103 also reduces the gate-drain capacitance of the superjunction power device 100, which can increase the switching speed of the superjunction power device 100 and reduce the switching loss.

Fig. 3 is a schematic cross-sectional view of a portion of a cell region of the superjunction power device 100 shown in fig. 1 along line B-B according to an embodiment of the present application. The cross section along line B-B is parallel to the first surface 101 and the second surface 102. As shown in fig. 3, on this cross section, alternating first dielectric regions 118a and second dielectric regions 118b at the bottom of the gate structure 103 can be seen. The first dielectric region 118a is covered with the semiconductor layer 113 along the sidewalls in the length direction of the gate structure 103 (i.e., along the z-direction as shown in fig. 1).

Fig. 4 illustrates a top view of a superjunction power device 400 according to an embodiment of the present application. The top view shows a first surface of a portion of the cell region of superjunction power device 400. As shown in fig. 4, on the first surface, the source regions 415 and the well contact regions 414 are alternately arranged along the length direction of the gate structure 103. In prior art power devices, the source and well contact regions are typically aligned in a direction perpendicular to the length of the gate structure, e.g., one side of the source region interfaces with a sidewall of the gate structure, and the well contact region is aligned on the other side of the source region interfaces with the other side of the source region. In this case, the length of the single unit cell in the length direction perpendicular to the gate structure is large. According to the embodiment of the application, the source regions and the well contact regions are alternately arranged in the direction parallel to the gate structure, so that the cell size of the super junction power device is effectively reduced, and the conduction performance of the super junction power device is improved.

Fig. 5 illustrates a process of steps of a method 500 of fabricating a superjunction power device 100 according to an embodiment of the present application. It should be understood that the steps of the manufacturing method 500 shown in fig. 5 are not necessarily sequential. The manufacturing method 500 includes: step 501, forming a substrate layer 110; step 502, forming an epitaxial layer 111 over a substrate layer 110; step 503, forming a well region 112 in a portion of the epitaxial layer 111 near the first surface 101 of the superjunction power device 100; step 504, forming source regions 115 in a stripe distribution in the well region 112; step 505 of forming a trench in the epitaxial layer 111 along a direction perpendicular to the source regions 115 of the stripe-shaped distribution; step 506, covering the trench regions between the source regions 115 and the upper side of the source regions 115 with an ion implantation protection layer; step 507, performing first inclined ion implantation to form a semiconductor layer on the side wall of the trench and the area of the surface of the well region 112, which is not covered by the ion implantation protection layer; step 508, performing second inclined ion implantation to form a well contact region 114 in a region of the semiconductor layer near the top of the trench, wherein the angle of the second inclined ion implantation is larger than that of the first inclined ion implantation, and the well contact region 114 comprises a flat portion 114a and a hanging portion 114b, and the hanging portion 114b is connected with the semiconductor layer 113 and is lower than the bottom of the well region 114; step 509, filling a dielectric in the trench after removing the ion implantation protection layer to form a dielectric region 118, wherein the distance from the top of the dielectric region 118 to the first surface 101 of the superjunction power device 100 is greater than the distance from the bottom of the well region 112 to the first surface 101 of the superjunction power device 100; and step 510, forming the gate structure 103 in the dielectric filled trench.

Fig. 6A-6J illustrate schematic device structure diagrams during the fabrication of superjunction power device 100 according to a fabrication method 500 according to an embodiment of the present application. The method 500 of fabricating the superjunction power device 100 is described below in conjunction with fig. 5 and fig. 6A-6J.

Fig. 6A is a schematic diagram of a device after completion of steps 501 and 502 according to an embodiment of the present application. The superjunction power device 100 now has a substrate layer 110 and an epitaxial layer 111 over the substrate layer 110. The substrate layer 110 and the epitaxial layer 111 have a first conductivity type, and the doping concentration of the substrate layer 110 is higher than the doping concentration of the epitaxial layer 111. In some embodiments, the first conductivity type is n-type, and the substrate layer 110 and the epitaxial layer 111 are both n-type semiconductor layers, but have different doping concentrations.

Fig. 6B is a schematic diagram of the device after completion of step 503 according to an embodiment of the present application. At this time, a portion of the epitaxial layer 111 of the superjunction power device 100 near the first surface 101 forms a well region 112. The well region 112 may be fabricated by any suitable method, such as ion implantation. It should be appreciated that when there are other regions of the power device surface that require ion implantation of certain specific regions to form well region 112, the method of fabricating well region 112 further includes a masking process to effect ion implantation of the specific regions.

Fig. 6C is a schematic diagram of the device after completion of step 504 according to an embodiment of the present application. A source region 115 of high doping concentration is formed in the well region 112 of the superjunction power device 100 at this time. In some embodiments, well region 112 is a p-type semiconductor region having a relatively low doping concentration and source region 115 is an n-type semiconductor region having a relatively high doping concentration. Source region 115 may be formed by a suitable process such as a masking process, i.e., a masking process that covers first surface 101 of the device with a mask (e.g., photoresist), then forming a window in a particular location on the mask, and then implanting impurities into the device through the window of the mask to form source region 115.

Fig. 6D is a schematic diagram of the device after completion of step 505 according to an embodiment of the present application. At this time, the superjunction power device 100 forms the trench 104 in a direction perpendicular to the stripe-shaped source region 115, dividing the source region 115 into portions located at both sides of the trench. The bottom of the trench 104 reaches the substrate layer 110. The trench 104 may be formed by any suitable method. For example, a window is formed in the trench by a masking process, and the epitaxial layer 111 is etched toward the window.

Fig. 6E is a schematic diagram of the device after completion of step 506 according to an embodiment of the present application. The source regions 115 and the trenches 104 between the source regions 115 are now covered with the ion implantation protection layer 105. The ion implantation protection layer 105 may be a photoresist, a silicon oxide layer, a silicon nitride layer, polysilicon, or a combination of different materials. After the ion implantation protection layer 105 is covered, the well region 112 on the first surface 101 of the device and the portion of the trench 104 not covered by the ion implantation protection layer 105 are both exposed.

Fig. 6F is a schematic diagram of the device after the implementation of step 507 according to an embodiment of the present application. In step 507, a first angled ion implantation is used to implant impurities into the sidewalls within the trench 104 and the surface of the well region 112 of the device to form a semiconductor layer having a particular conductivity type. In one embodiment, the implanted impurity is a p-type impurity, and the p-type layer is formed without covering the trench sidewall and the well region of the ion implantation protection layer 105, as shown in fig. 6F. By controlling the angle A1 of the angled ion implantation and the intensity of the implantation, the thickness and doping concentration of the p-type layer can be controlled. In fig. 6F, the semiconductor layer 113 covers to the bottom of the trench, i.e., the bottom of the semiconductor layer 113 reaches the substrate layer 110. In some embodiments, the bottom of semiconductor layer 113 may not extend to substrate layer 110.

Fig. 6G is a schematic diagram of the device after completion of step 508 according to an embodiment of the present application. In step 508, a second angled ion implantation is performed to form a well contact region 114 in a region of the semiconductor layer 113 near the top of the trench, where the region is formed after the first angled ion implantation. In one embodiment, the implanted impurity is a p-type impurity, and the angle A2 of the second angled ion implantation is greater than the angle A1 of the first angled ion implantation, thereby forming a region having a higher doping concentration than the original semiconductor layer 113 in the region near the top of the trench. By controlling the angle A2 of the second inclined ion implantation, the length of the extension of the under-hanging portion 114b of the well contact region 114 toward the semiconductor layer 113 can be controlled.

Fig. 6H is a schematic view of the device structure after removing the ion implantation protection layer 105 according to an embodiment of the present application. As shown in fig. 6H, well region 112 on each side of trench 104 has source region 115 and well contact region 114 spaced apart and contiguous. Well contact region 114 in turn includes contiguous planar portion 114a and underhung portion 114b. The hanging portion 114b is connected to the semiconductor layer 113. Below source region 115 is well region 112 and epitaxial layer 111 and underlying substrate layer 110. So that a current path from the source region 115 to the substrate layer 110 is ensured.

Fig. 6I is a schematic diagram of the device structure after step 509 is performed according to an embodiment of the present application. The trenches of superjunction device 100 are now filled with dielectric region 118. The material of the dielectric region 118 may be an insulating material with a high dielectric constant such as silicon oxide, silicon nitride, or aluminum oxide, or may be a combination of different insulating materials. It should be appreciated that after filling the trenches with dielectric, there may be instances where the top of the dielectric region portions is not flat or the heights of the dielectric regions within each trench are not uniform for process reasons. Thus, there may also be programs for further processing of the dielectric region 118, such as etching polishing and the like.

Fig. 6J is a schematic diagram of a device structure after step 510 according to an embodiment of the present application. After forming the dielectric region 118, the gate structure 103 is formed in the trench remaining on top of the dielectric region 118, as shown in fig. 6J. Any suitable method for forming a trench gate structure may be used in embodiments of the present application. For example, a silicon oxide layer may be formed in the trench as the gate insulating layer 117 by deposition, and then the trench may be filled with a conductive material such as metal or polysilicon to form the gate electrode 116.

Fig. 7 is a schematic structural diagram of a partial cell region of a superjunction power device 700 according to an embodiment of the present application. In contrast to superjunction power device 100, well contact region 714 of superjunction power device 700 does not include an underhung portion. The well contact region 714 of the superjunction power device 700 includes only flat portions, respectively adjoining the sidewalls of the gate structure 103 and the source region 115 in different directions, and being spaced apart from the source region 115 along the length direction of the gate structure 103 and distributed within the well region 712. In superjunction power device 700, when a specific voltage is applied to the gate electrode of the device to turn on the conduction current of the device channel, the side wall of well region 712 under well contact region 714 also forms a channel, increasing the channel area, reducing the channel resistance, and improving the conduction capability of the device.

Fig. 8 illustrates a process of steps of a method 800 of fabricating a superjunction power device 700 according to an embodiment of the present application. It should be understood that the steps of the manufacturing method 800 shown in fig. 8 are not necessarily sequential. The manufacturing method 800 includes: step 801, forming a substrate layer 110; step 802, forming an epitaxial layer 111 over a substrate layer 110; step 803, forming a well region 712 in the epitaxial layer 111 near the first surface 101 of the superjunction power device 700; step 804, forming source regions 115 in a stripe distribution in the well region 712; step 805, forming trenches 104 in the epitaxial layer along a direction perpendicular to the source regions 115 of the stripe-shaped distribution; step 806, covering the trench regions between the source regions 115 and the upper side of the source regions 115 with an ion implantation protection layer; step 807, performing first tilt ion implantation to form a semiconductor layer 113 on the trench sidewall and the well surface region not covered by the ion implantation protection layer; in step 808, the second tilt ion implantation reduces the impurity concentration of the region of the semiconductor layer near the top of the trench (i.e., the region of the well region 712 where the doping concentration is increased by the first tilt ion implantation to form the semiconductor layer) to recover the well region 712 as shown in fig. 7. In some embodiments, the first angled ion implanted impurity is a p-type impurity and the semiconductor layer 113 is p-type doped. At the time of the first oblique ion implantation, the concentration of the region of the well region 712 near the trench portion is higher than that of the remaining portion. The second angled ion implantation implants an n-type impurity to neutralize the concentration of the portion of well region 712 near the trench, returning it to the original doping concentration. In order to implant the impurity of the second inclined ion implantation into the portion of the well region 712 near the trench, the angle of the second inclined ion implantation is greater than that of the first inclined ion implantation; step 809, vertical ion implantation, forming a well contact region 714 in the well region 712; step 810, filling a dielectric in the trench after removing the ion implantation protection layer to form a dielectric region 118, wherein the distance from the top of the dielectric region 118 to the first surface 101 of the superjunction power device 700 is greater than the distance from the bottom of the well region 712 to the first surface 101 of the superjunction power device 700; and a step 811 of forming a gate structure 103 in the dielectric filled trench.

The method 800 for fabricating the superjunction power device 700 is substantially the same as the method 500 for fabricating the superjunction power device 100, except that the angle of the second angled ion implantation, the impurity type, and the subsequent step of forming the well contact region are different, and will not be described in detail herein.

Fig. 9 is a schematic structural diagram of a partial cell region of a superjunction power device 900 according to an embodiment of the present application. The structure of the dielectric region 918 of the superjunction power device 900 is different compared to the superjunction power device 100 shown in fig. 1. Fig. 10 is a schematic cross-sectional view of a portion of a cell region of the superjunction power device 900 shown in fig. 9 along a C-C line according to an embodiment of the present application.

As shown in fig. 10, well region 112 is located in epitaxial layer 111 near first surface 101, source region 115 is located within well region 112, and the bottom thereof does not exceed the bottom of well region 112, i.e., the entire source region 115 is located within well region 112. The sidewalls of source region 115 and well region 112 meet the sidewalls of gate structure 103. Below the gate structure 103 is an epitaxial layer 111 that meets the bottom of the gate structure 103. That is, the superjunction power device 900 does not have a second dielectric region, as compared to the superjunction power device 100. The respective dielectric regions 918 are separated by epitaxial layer 111. A dielectric region 918 is located at the bottom of gate structure 103 and between well contact regions 114. At the bottom of gate structure 103 and between source regions 115 is epitaxial layer 111.

Fig. 11 is a schematic cross-sectional view of a portion of a cell region of the superjunction power device 900 shown in fig. 9 along the D-D line according to an embodiment of the present application. The cross section along the D-D line is parallel to the first surface 101 and the second surface 102. As shown in fig. 11, on this cross-section, a dielectric region 918 at the bottom of the gate structure 103 can be seen. The two dielectric regions 918 are separated by the epitaxial layer 111. A semiconductor layer 113 is overlying sidewalls of the dielectric region 918 along the length of the gate structure 103 (i.e., along the z-direction as shown in fig. 1).

Fig. 12 is a schematic cross-sectional view of a portion of a cell region of the superjunction power device 900 shown in fig. 9 along the D-D line according to another embodiment of the present application. The cross section along the D-D line is parallel to the first surface 101 and the second surface 102. As shown in fig. 12, on this cross-section, a dielectric region 918 at the bottom of the gate structure 103 can be seen. The two dielectric regions 918 are separated by the epitaxial layer 111. The semiconductor layer 113 is covered on the sidewalls of the dielectric region 918 along the length direction of the gate structure 103 (i.e., along the z-direction as shown in fig. 1) and perpendicular to the length direction of the gate structure 103 (i.e., along the x-direction as shown in fig. 1).

Fig. 13 illustrates a process of steps of a method 1300 of fabricating a superjunction power device 900 according to an embodiment of the present application. It should be appreciated that the steps of the manufacturing method 1300 shown in fig. 13 are not necessarily sequential. The manufacturing method 1300 includes: step 1301, forming a substrate layer 110; step 1302, forming an epitaxial layer 111 over a substrate layer 110; step 1303, forming a well region 112 in the epitaxial layer 111 near the first surface 101 of the superjunction power device 900; step 1304, forming source regions 115 in a stripe distribution in the well region 112; step 1305, forming a first trench 904 in the epitaxial layer 111 along a direction perpendicular to the source regions 115 of the stripe-shaped distribution; step 1306, removing the epitaxial layer 111 between the well regions under the first trench 904 on the basis of the first trench 904 to form a second trench 905 while retaining the epitaxial layer 111 between the source regions 115 under the first trench 904; step 1307, covering the regions between the source regions 115 and above the source regions 115 in the first trench 904 with an ion implantation protection layer; step 1308, performing first tilt ion implantation to form a semiconductor layer 113 on the sidewall of the second trench 905 and the area of the surface of the well region 112 not covered by the ion implantation protection layer; step 1309, performing a second tilt ion implantation to form a well contact region 114 in a region of the semiconductor layer 113 near the top of the second trench 905, wherein the angle A2 of the second tilt ion implantation is greater than the angle A1 of the first tilt ion implantation, the well contact region 114 comprises a flat portion 114a and a lower hanging portion 114b, and the lower hanging portion 114b is connected with the semiconductor layer 113 and is lower than the bottom of the well region 112; step 1310, filling a dielectric in the second trench 905 after removing the ion implantation protection layer to form a dielectric region 918, wherein the top of the dielectric region 918 in the second trench 905 is flush with the bottom of the first trench 904, and the distance from the top of the dielectric region 918 in the second trench 905 to the first surface 101 of the superjunction power device 900 is greater than the distance from the bottom of the well region 112 to the first surface 101 of the superjunction power device 900; and step 1311, forming gate structure 103 in first trench 904 and over dielectric region 918.

Fig. 14A-14E illustrate device diagrams during the fabrication of superjunction power device 900 according to a fabrication method 1300 according to an embodiment of the present application. The method 1300 of fabricating the superjunction power device 900 is described below in conjunction with fig. 13 and 14A-14E.

Fig. 14A is a schematic view of the device after completion of steps 1301-1305 according to one embodiment of the present application. At this time, the superjunction power device 900 forms the first trench 904 in a direction perpendicular to the stripe-shaped source region 115, dividing the source region 115 into portions located at both sides of the first trench 904. The bottom of the first trench 904 is located in the epitaxial layer 111 and is lower than the bottom of the well region 112. The first trench 904 may be formed using any suitable method. A window is formed in the trench, for example, by a masking process, and the epitaxial layer 111 is etched at the location of the window.

Fig. 14B is a schematic diagram of the device structure after completion of step 1306 in accordance with an embodiment of the present application. The epitaxial layer 111 between the well regions under the first trenches 904 is removed at this time to form second trenches 905. While the epitaxial layer 111 under the first trenches 904 between the source regions 115 remains. The second trench 905 may be formed using any suitable method. A window is formed in the location of the second trench, for example, by a masking process, and the epitaxial layer 111 is etched at the location of the window. Thereafter, the mask 106 shown in fig. 14B is removed, or the mask 106 is further subjected to photolithography to form the ion implantation protection layer 105 required in the next step.

Fig. 14C is a schematic view of the device structure after completion of step 1307 according to an embodiment of the present application. At this time, the first trenches 904 between the source regions 115 and the surface positions of the source regions 115 are covered with the ion implantation protection layer 105. The ion implantation protection layer may be a photoresist, a silicon oxide layer, a silicon nitride layer, polysilicon, or a combination of materials, etc. After the ion implantation protection layer 105 is covered, the well region position not covered by the ion implantation protection layer 105 and the second trench 905 are both in an exposed state.

Fig. 14D is a schematic view of the device structure after completion of steps 1308 and 1309 according to an embodiment of the present application. In step 1308, impurities are implanted into the sidewalls and the well region surfaces inside the second trench 905 of the device by means of the first angled ion implantation to form the semiconductor layer 113 having a specific conductivity type. In one embodiment, the implanted impurity is a p-type impurity, and the p-type layer is formed on both sides of the trench and the well region not covered by the ion implantation protection layer 105. Thereafter, in step 1309, a second angled ion implantation is performed to form a well contact region 114 in a region of the semiconductor layer 113 formed after the first angled ion implantation near the top of the second trench 905. In one embodiment, the implanted impurity is a p-type impurity, and the angle A2 of the second angled ion implantation is greater than the angle A1 of the first angled ion implantation, thereby forming a region having a higher doping concentration than the original semiconductor layer 113 in the region near the top of the trench. By controlling the angle A2 of the second angled ion implantation, the length of the under-hanging portion 114b of the well contact region 114 can be controlled.

It should be appreciated that the underhung portion 114b of the well contact region 114 is not required. In the manufacturing method 1300, the step 1309 of performing a second angled ion implantation may be replaced with the steps 808 and 809 of the manufacturing method 800, i.e., performing a second angled ion implantation and a vertical ion implantation, thereby forming the well contact region 114 without the hanging portion.

Fig. 14E is a schematic diagram of a device after completion of step 1310 according to an embodiment of the present application. In step 1310, the ion implantation protection layer 105 is removed and then the second trench 905 is filled with a dielectric, forming a dielectric region 918. The top of the dielectric regions 918 and the top of the epitaxial layer 111 between adjacent dielectric regions 918 together form the bottom of the gate structure 103. The super junction power device 900 shown in fig. 9 is obtained after forming the gate structure 103 in the device trench as shown in fig. 14E.

Fig. 15 is a schematic structural diagram of a partial cell area of a superjunction power device 1500 according to an embodiment of the present application. In contrast to superjunction power device 100 shown in fig. 1, the sidewalls of dielectric region 1518 of superjunction power device 1500 are not perpendicular to the first and second surfaces of superjunction power device 1500. Dielectric region 1518 forms a lower narrow upper wide structure that facilitates improving the quality of semiconductor layer 113 during device fabrication. It should be appreciated that in superjunction power device 1500, the distribution of dielectric regions 1518 may be divided into alternating first dielectric regions between well contact regions 114 and second dielectric regions between source regions 115 as in superjunction power device 100, or dielectric regions 1518 may be located between well contact regions 114 and epitaxial layer 111 may be located between source regions 115 as in superjunction power device 900.

The application takes a MOSFET device with a trench gate structure as an example to illustrate the principle of the application. It should be appreciated that the present application is equally applicable to power devices of planar gate structures. After reading the application, one of ordinary skill in the art can combine the power device of the same plane gate structure together as required to realize the superjunction structure in the power device of the plane gate structure.

The present application illustrates the principles of the application with respect to strip-like cells. It should be understood that the application is equally applicable to cell structures of other shapes, such as circular, hexagonal, etc. In particular, it is also within the spirit of the present application that, in other shapes of cell structures, the sidewalls of the embodiments of the present application cover the dielectric regions of the p-type semiconductor layer with, for example, p-pillars in the superjunction, or the sidewalls of the embodiments of the present application cover the dielectric regions of the n-type semiconductor layer with, for example, n-pillars in the superjunction.

Embodiments in accordance with the present application, as described above, are not intended to be exhaustive or to limit the application to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, to thereby enable others skilled in the art to best utilize the application and various modifications as are suited to the particular use contemplated. The application is limited only by the claims and the full scope and equivalents thereof.

Claims

1. A superjunction power device, comprising:

a substrate layer having a first conductivity type;

an epitaxial layer, located above the substrate layer, having a first conductivity type;

A gate structure;

A dielectric region located under the gate structure;

the well region is positioned in the epitaxial layer and on two sides of the grid structure and is provided with a second conductive type;

The source region is positioned in the well region and at two sides of the grid structure and is provided with a first conductive type; and

The well contact area is positioned in the well area and positioned at two sides of the grid structure and is provided with a second conductive type;

a portion of the sidewall of the dielectric region is covered with a semiconductor layer having the second conductivity type, and a portion of the dielectric region not covered with the semiconductor layer is located at least under the gate structure between the source regions.

2. The superjunction power device of claim 1, wherein the source and well contact regions are alternately distributed in a first direction parallel to a length direction of the gate structure on each side of the gate structure.

3. The superjunction power device of claim 1, wherein the well contact region comprises an underhung portion, the underhung portion being contiguous with a sidewall of the gate structure and with a top portion of the semiconductor layer.

4. The superjunction power device of claim 3, wherein the underhung portion of the well contact region meets the semiconductor layer at a position lower than a bottom of the gate structure.

5. The superjunction power device of claim 1, wherein the dielectric regions comprise first and second dielectric regions alternately distributed and contiguous in a first direction parallel to a length direction of the gate structure, the first dielectric region underlying the gate structure between well contact regions, and the first dielectric region being overlaid with a semiconductor layer of a second conductivity type on sidewalls along the first direction, the second dielectric region underlying the gate structure between source regions.

6. The superjunction power device of claim 1, wherein the dielectric region is under the gate structure between well contact regions and under the gate structure between source regions is an epitaxial layer, the plurality of dielectric regions are separated by the epitaxial layer in a first direction parallel to a length direction of the gate structure, and sidewalls of the dielectric region along the first direction are covered with a semiconductor layer having a second conductivity type.

7. The superjunction power device of claim 1, wherein the dielectric region is located under the gate structure between the well contact regions and under the gate structure between the source regions is an epitaxial layer, the plurality of dielectric regions are separated by the epitaxial layer in a first direction parallel to a length direction of the gate structure, and sidewalls of the dielectric regions are covered with a semiconductor layer having the second conductivity type.

8. The superjunction power device of claim 1, having parallel first and second surfaces, wherein the top of the dielectric region meets the bottom of the gate structure, and the bottom of the gate structure is farther from the first surface of the superjunction power device than the bottom of the well region is from the first surface of the superjunction power device.

9. The superjunction power device of claim 1, wherein the gate structure comprises a trench gate structure.

10. A method of manufacturing a superjunction power device comprising parallel and opposing first and second surfaces, the method comprising:

forming a substrate layer;

Forming an epitaxial layer over the substrate layer;

forming a well region in the epitaxial layer at a part close to the first surface of the super junction power device;

Forming source regions distributed in a strip shape in the well region;

forming grooves in the epitaxial layer along the direction perpendicular to the source regions distributed in the strip shape;

covering ion implantation protective layers on the groove areas between the source areas and the upper parts of the source areas;

Performing first inclined ion implantation, and forming a semiconductor layer on the side wall of the groove and the surface area of the well region which are not covered by the ion implantation protective layer;

Forming a well contact region in a region of the semiconductor layer close to the top of the trench by a second inclined ion implantation, wherein the angle of the second inclined ion implantation is larger than that of the first inclined ion implantation, and the well contact region comprises a flat part and a hanging part which is connected with the semiconductor layer;

Filling dielectric in the groove after removing the ion implantation protective layer to form a dielectric region, wherein the distance from the top of the dielectric region to the first surface of the super junction power device is larger than the distance from the bottom of the well region to the first surface of the super junction power device; and

A gate structure is formed in the dielectric filled trench.

11. The method of manufacturing a superjunction power device as claimed in claim 10, wherein the underhung portion of the well contact region meets the semiconductor layer at a position lower than a bottom of the well region.

12. A method of manufacturing a superjunction power device comprising parallel and opposing first and second surfaces, the method comprising:

forming a substrate layer;

Forming an epitaxial layer over the substrate layer;

Forming source regions distributed in a strip shape in the well region;

Covering ion implantation protective layers on the channel regions between the source regions corresponding to the two sides of the channel and the upper parts of the source regions;

A second angled ion implantation to reduce the impurity concentration of the region of the semiconductor layer near the top of the trench, wherein the impurity type of the second angled ion implantation is related to the impurity type of the first angled ion implantation, and the angle of the second angled ion implantation is greater than the angle of the first angled ion implantation;

Vertical ion implantation, forming a well contact region in the region of the semiconductor layer in the well region, wherein the bottom of the well contact region is higher than the bottom of the well region;

A gate structure is formed in the dielectric filled trench.

13. A method of manufacturing a superjunction power device comprising parallel and opposing first and second surfaces, the method comprising:

forming a substrate layer;

Forming an epitaxial layer over the substrate layer;

Forming source regions distributed in a strip shape in the well region;

forming a first trench in the epitaxial layer along a direction perpendicular to the source regions of the stripe-shaped distribution;

Removing the epitaxial layer below the first trenches between the well regions to form second trenches while retaining the epitaxial layer below the first trenches between the source regions;

Covering an ion implantation protection layer on the source region and the region in the first groove between the source regions;

performing first inclined ion implantation, and forming a semiconductor layer on the side wall of the second groove and the surface area of the well region which are not covered by the ion implantation protective layer;

Forming a well contact region in a region of the semiconductor layer close to the top of the second trench by second inclined ion implantation, wherein the angle of the second inclined ion implantation is larger than that of the first inclined ion implantation, and the well contact region comprises a flat part and a hanging part which is connected with the semiconductor layer;

Filling dielectric in the second groove after removing the ion implantation protective layer to form a dielectric region, wherein the top of the dielectric region in the second groove is flush with the bottom of the first groove, and the distance from the top of the dielectric region in the second groove to the first surface of the super junction power device is larger than the distance from the bottom of the well region to the first surface of the super junction power device; and

A gate structure is formed in the first trench and over the dielectric region.

14. The method of manufacturing a superjunction power device as claimed in claim 13, wherein the underhung portion of the well contact region meets the semiconductor layer at a position lower than a bottom of the well region.