CN118473390A - Power-on reset circuit and method - Google Patents
Power-on reset circuit and method Download PDFInfo
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Abstract
The invention relates to the technical field of reset circuits, and particularly discloses a power-on reset circuit and a method thereof, wherein the circuit comprises the following components: the voltage divider comprises a voltage division MOS tube and a voltage division resistor, and is provided with a voltage division output point for generating trigger voltage division and adjusting the power consumption of the power-on reset circuit; the hysteresis device comprises a hysteresis MOS tube which is electrically connected with the voltage division output point and is used for avoiding reset voltage jitter caused by power voltage jitter; the input end of the comparator is electrically connected with the voltage division output point, and the output end of the comparator is electrically connected with the input end of the hysteresis device and is used for converting the triggering voltage division into logic signals; and the input end of the buffer is electrically connected with the output end of the comparator, and the output end is used as the output end of the power-on reset circuit and used for increasing the driving capability of the power-on reset circuit. The trigger point is accurate, insensitive to process angle and temperature change, the range of the trigger point along with the process angle, temperature and power supply voltage is +/-100mV, and the trigger point does not rise along with the rise of the power supply voltage, so that the trigger point has small area and low cost.
Description
Technical Field
The invention relates to the technical field of reset circuits, in particular to a power-on reset circuit and a method.
Background
The power-on reset provides an indication to start working after the chip is powered on. The power-on reset circuit generally generates a reset signal by utilizing different node changes in the power-on process. When the memory cell IP is integrated in a high-precision product or on a chip, a relatively accurate power-on reset point is required. Therefore, the minimum power supply voltage requirement of the storage unit IP can be ensured, and the influence on the normal operation of other analog circuits due to the fact that the power supply voltage is too low can be avoided. In addition, portable device applications often have stringent requirements for the overall power consumption of the chip, and designing a power-on reset circuit with very low power consumption will be unavoidable. While very low power circuits tend to mean a larger area, this will greatly increase the cost of the chip, thereby reducing the competitiveness of the chip.
A circuit structure of the existing power-on reset circuit is shown in fig. 1, and the power-on reset circuit has the following disadvantages: 1. the voltage divider is connected in series by the PMOS tube and the NMOS tube to realize the communication between the power supply and the ground, and the PMOS tube and the NMOS tube L/W of the voltage divider are required to be made large for realizing low power consumption; 2. the trigger point is highly dependent on the threshold voltages of PMOS and NMOS, and is sensitive to temperature and process corner; 3. the power consumption is highly dependent on the supply voltage. And the power consumption is high under high power supply voltage.
Another circuit structure of the existing power-on reset circuit is shown in fig. 2, and the power-on reset circuit has the advantages of simpler structure and the following disadvantages: 1. large area: the voltage divider is connected with the ground through the PMOS tube, the NMOS tube and the resistor in series, and the PMOS tube and the NMOS tube L/W of the voltage divider are required to be quite large for realizing low power consumption; 2. the trigger point is highly dependent on the threshold voltages of PMOS and NMOS, and the resistance, and is sensitive to temperature and process angle; 3. the power consumption is highly dependent on the supply voltage, and the power consumption is large at high supply voltages, with an error of about +/-200mV.
Therefore, there is a particular need for a reset circuit that can achieve low power consumption, small area, and temperature compensation, thereby improving the accuracy of the reset point.
Based on the technical background, the invention researches a power-on reset circuit and a method.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a power-on reset circuit and a method, wherein the circuit has accurate trigger point, is insensitive to process angle and temperature change, has the trigger point within +/-100mV along with the process angle, temperature and power supply voltage, does not rise along with the rise of the power supply voltage, and has small area and low cost.
To achieve the above object, a first aspect of the present invention provides a power-on reset circuit, including:
the voltage divider comprises a voltage division MOS tube and a voltage division resistor, and is provided with a voltage division output point for generating trigger voltage division and adjusting the power consumption of the power-on reset circuit;
The hysteresis device comprises a hysteresis MOS tube which is electrically connected with the voltage division output point and is used for avoiding reset voltage jitter caused by power voltage jitter;
The input end of the comparator is electrically connected with the voltage division output point, and the output end of the comparator is electrically connected with the input end of the hysteresis device and is used for converting the trigger voltage division into logic signals;
And the input end of the buffer is electrically connected with the output end of the comparator, and the output end of the buffer is used as the output end of the power-on reset circuit to output reset voltage for increasing the driving capability of the power-on reset circuit.
The first aspect of the present invention provides a power-on reset method performed in the power-on reset circuit, including:
generating the trigger voltage division through the voltage division MOS tube and the voltage division resistor and adjusting the power consumption of the power-on reset circuit;
the trigger voltage division is transmitted to the input ends of the hysteresis and the comparator at the same time;
The hysteresis device performs signal hysteresis through the trigger voltage division and the output signal of the comparator, so that reset voltage jitter caused by power voltage jitter is avoided;
The comparator converts the trigger voltage division into a logic signal and outputs the logic signal to the buffer;
the buffer converts the logic signal output by the comparator into a driving signal to drive an external circuit.
The beneficial effects of the invention include:
(1) The power-on reset circuit provided by the invention has the advantages that the trigger point is accurate, insensitive to process angle and temperature change, the trigger point is within +/-100mV along with the process angle, temperature and power supply voltage, and does not rise along with the rise of the power supply voltage, and the power-on reset circuit is small in area and low in cost.
(2) The power-on reset circuit provided by the invention has the advantages that the power consumption is controlled by the electric leakage of the intrinsic NMOS tube, the power consumption does not rise along with the rising of the power supply voltage, and the current of a voltage divider channel can be flexibly changed through the resistance value of the voltage dividing resistor, so that the extremely low power consumption target of the whole design is realized.
(3) According to the power-on reset circuit, the current is controlled by controlling the gate-source voltage of the intrinsic NMOS tube, so that the design of extremely low power consumption is realized, and meanwhile, the use of a large-size MOS tube is avoided, so that the cost is saved.
(4) The power-on reset circuit provided by the invention has the advantages that the trigger voltage division is controlled by the intrinsic NMOS tube, the first voltage division NMOS tube and the second voltage division NMOS tube, and the three are NMOS transistors, so that better process and temperature following can be realized, and the trigger voltage division is smaller in different processes and temperatures.
Additional features and advantages of the invention will be set forth in the detailed description which follows.
Drawings
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular descriptions of exemplary embodiments of the invention as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout the exemplary embodiments of the invention.
Fig. 1 is a schematic circuit structure diagram of a conventional power-on reset circuit.
Fig. 2 is a schematic diagram of another circuit structure of a conventional power-on reset circuit.
Fig. 3 is a schematic structural diagram of a power-on reset circuit according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of voltage waveforms of each node in an embodiment of the power-on reset circuit according to the present invention.
Reference numerals illustrate:
M0-second voltage-dividing NMOS tube, M1-first voltage-dividing NMOS tube, M2-intrinsic NMOS tube, M3-second hysteresis NMOS tube, M4-first hysteresis NMOS tube, M5-comparison NMOS tube, M6-comparison PMOS tube, M7-first buffer NMOS tube, M8-first buffer PMOS tube, M9-second buffer NMOS tube, M10-second buffer PMOS tube, R0-voltage-dividing resistor;
VDD-power, GND-ground, A-divided output point, B-comparator output, PORB-power-on reset circuit output.
Detailed Description
Preferred embodiments of the present invention will be described in more detail below. While the preferred embodiments of the present invention are described below, it should be understood that the present invention may be embodied in various forms and should not be limited to the embodiments set forth herein.
In the present invention, unless otherwise indicated, terms of orientation such as "upper and lower" are used to generally refer to the upper and lower portions of the device in normal use, and "inner and outer" are used with respect to the profile of the device. Furthermore, the terms "first, second, third and the like" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first, second, third" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
The present invention provides a power-on reset circuit, as shown in fig. 3, comprising:
The voltage divider comprises a voltage division MOS tube and a voltage division resistor R0, and is provided with a voltage division output point A for generating trigger voltage division and adjusting the power consumption of the power-on reset circuit;
the hysteresis device comprises a hysteresis MOS tube which is electrically connected with the voltage division output point A and is used for avoiding reset voltage jitter caused by power supply VDD voltage jitter;
the input end of the comparator is electrically connected with the voltage division output point A, and the output end of the comparator is electrically connected with the input end of the hysteresis device and is used for converting the triggering voltage division into logic signals;
And the input end of the buffer is electrically connected with the output end B of the comparator, and the output end is used as the output end PORB of the power-on reset circuit to output reset voltage for increasing the driving capability of the power-on reset circuit.
In the invention, the trigger point is accurate, insensitive to process angle and temperature change, the trigger point is within +/-100mV along with the process angle, temperature and power supply VDD voltage change range, and does not rise along with the power supply VDD voltage rise, and the invention has small area and low cost.
According to the invention, the voltage division MOS tube comprises an intrinsic NMOS tube M2, a first voltage division NMOS tube M1 and a second voltage division NMOS tube M0;
the drain electrode of the intrinsic NMOS tube M2 is electrically connected with a power supply VDD, and the source electrode is electrically connected with one end of a divider resistor R0;
the other end of the divider resistor R0 is electrically connected with the grid electrode of the intrinsic NMOS tube M2 and the drain electrode of the first divider NMOS tube M1 at the same time and is used as a divider output point A;
The source electrode of the first voltage division NMOS tube M1 is electrically connected with the drain electrode of the second voltage division NMOS tube M0, and the grid electrode is electrically connected with the power supply VDD;
the source electrode of the second voltage division NMOS tube M0 is electrically connected with the ground GND, and the grid electrode is electrically connected with the drain electrode of the second voltage division NMOS tube M0.
In the invention, the power consumption is controlled by the electric leakage of the intrinsic NMOS tube M2, does not rise along with the rising of the voltage of the power supply VDD, and can flexibly change the current of a voltage divider passage through the resistance value of the voltage dividing resistor R0, thereby realizing the aim of extremely low power consumption of the whole design.
In the invention, the gate-source voltage of the intrinsic NMOS tube M2 is controlled to control the current, so that the design of extremely low power consumption is realized, and meanwhile, the use of a large-size MOS tube is avoided, thereby saving the cost.
In the invention, the trigger voltage division is controlled by the intrinsic NMOS tube M2, the first voltage division NMOS tube M1 and the second voltage division NMOS tube M0, and the three are NMOS transistors, so that better process and temperature following can be realized, and the voltage of the trigger point is less changed under different processes and temperatures.
In the invention, the trigger point voltage refers to the voltage of the corresponding power supply at the moment when the reset voltage suddenly changes from the logic low level to the logic high level or from the logic high level to the logic low level along with the rising or falling of the power supply; the trigger voltage division is the voltage generated by the trigger point voltage at the divided output point a of the voltage divider, as shown in fig. 3.
According to the invention, the hysteresis NMOS tube comprises a first hysteresis NMOS tube M4 and a second hysteresis NMOS tube M3;
the drain electrode of the first hysteresis NMOS tube M4 is electrically connected with the voltage division output point A, and the source electrode is electrically connected with the drain electrode of the second hysteresis NMOS tube M3;
The source electrode of the second hysteresis NMOS tube M3 is electrically connected with the ground GND, and the grid electrode is electrically connected with the drain electrode of the second hysteresis NMOS tube M.
According to the invention, the comparator comprises a comparison PMOS tube M6 and a comparison NMOS tube M5;
the source electrode of the comparison PMOS tube M6 is electrically connected with the power supply VDD, and the drain electrode of the comparison NMOS tube M5 is electrically connected with the drain electrode;
The source electrode of the comparison NMOS tube M5 is electrically connected with the ground GND, and the drain electrode of the comparison NMOS tube M5 is electrically connected with the grid electrode of the first hysteresis NMOS tube M4;
The gates of the comparison PMOS tube M6 and the comparison NMOS tube M5 are electrically connected with the voltage division output point A at the same time.
Preferably, the buffer comprises at least two stages of buffer units connected in series;
the input end of the first-stage buffer unit is electrically connected with the drain electrode of the comparison NMOS tube M5;
The output end of the final buffer unit is used as the output end PORB of the power-on reset circuit;
the input end of each stage of buffer unit is electrically connected with the output end of the previous stage of buffer unit except the final stage;
the number of the buffer units connected in series in at least two stages is even.
Preferably, each stage of buffer unit comprises a buffer PMOS tube and a buffer NMOS tube;
the source electrode of the buffer PMOS tube is electrically connected with the power supply VDD, and the drain electrode of the buffer PMOS tube is electrically connected with the drain electrode of the buffer NMOS tube;
the source electrode of the buffer NMOS tube is electrically connected with the ground GND;
The grid electrodes of the buffer PMOS tube and the buffer NMOS tube are electrically connected with each other and serve as the input end of the buffer unit;
the drain electrode of the buffer NMOS tube is used as the output end of the buffer unit.
The invention also provides a power-on reset method performed in the power-on reset circuit, which comprises the following steps:
Triggering voltage division is generated through a voltage division MOS tube and a voltage division resistor R0, and the power consumption of a power-on reset circuit is adjusted;
The trigger voltage division is transmitted to the input ends of the hysteresis and the comparator at the same time;
The hysteresis device performs signal hysteresis by triggering the voltage division and the output signal of the comparator, so that reset voltage jitter caused by power supply VDD voltage jitter is avoided;
the comparator converts the trigger voltage division into a logic signal and outputs the logic signal to the buffer;
the buffer converts the logic signal output by the comparator into a driving signal to drive an external circuit.
According to the invention, the generation of the trigger voltage division and the adjustment of the power consumption of the power-on reset circuit through the voltage division MOS tube and the voltage division resistor R0 comprises the following steps:
when the voltage of the power supply VDD is lower than the sum of threshold voltages of the first voltage dividing NMOS tube M1 and the second voltage dividing NMOS tube M0, the first voltage dividing NMOS tube M1 and the second voltage dividing NMOS tube M0 are not conducted, the intrinsic NMOS tube M2 is conducted without current, and the voltage division is triggered to be high level;
When the voltage of the power supply VDD is not less than the sum of the threshold voltages of the first voltage dividing NMOS transistor M1 and the second voltage dividing NMOS transistor M0 and gradually increases, the voltage between the source and the drain of the intrinsic NMOS transistor M2 gradually increases, the current flowing through the voltage gradually increases, the voltage between the gate and the source gradually decreases, and the value of the voltage is equal to the negative value of the product of the current flowing through the intrinsic NMOS transistor M2 and the voltage dividing resistor R0, in this process, the intrinsic NMOS transistor M2 works in a linear region and triggers the voltage dividing to gradually decrease;
when the power supply VDD voltage increases to the trigger point voltage, the trigger voltage division is low enough to cause the reset voltage to jump from a logic low level to a logic high level;
When the voltage of the power supply VDD continues to increase, so that the decrease of the voltage between the gate and the source of the intrinsic NMOS transistor M2 causes the decrease of the current flowing through the intrinsic NMOS transistor M2 to exceed the increase of the voltage between the source and the drain, so that the current flowing through the intrinsic NMOS transistor M2 works in a saturation region, the current flowing through the intrinsic NMOS transistor M2 remains unchanged, and the value of the trigger voltage division is close to the voltage of the gate and the source of the second voltage division NMOS transistor M0 and remains unchanged;
The current flowing through the voltage divider channel is regulated by regulating the size of the voltage regulating resistor, so that the power consumption of the power-on reset circuit is regulated.
Preferably, the hysteresis device performs signal hysteresis by triggering the voltage division and the output signal of the comparator, and avoiding reset voltage jitter caused by power supply VDD voltage jitter includes:
when the trigger voltage division is at a high level, the output voltage of the comparator is at a low level, and the hysteresis is turned off;
When the trigger voltage is gradually reduced to the threshold voltage of the comparator, the output voltage of the comparator is high level, the first hysteresis NMOS tube M4 is turned on due to the rising of the grid voltage, the second hysteresis NMOS tube M3 is turned on accordingly to continuously pull down the trigger voltage, and if the power supply VDD voltage in the power-down process is reduced to the trigger point voltage in the rising of the power supply VDD, the trigger voltage prevents the reset voltage from changing from the logic high level to the logic low level unless the power supply VDD voltage is continuously reduced, so that reset voltage jitter caused by the shaking of the power supply VDD voltage is avoided.
According to the present invention, a buffer for converting a logic signal output from a comparator into a driving signal to drive an external circuit includes:
The logic signals output by the comparator are converted into driving signals in a grading way through at least two stages of buffer units connected in series to drive an external circuit.
The present invention will be described in more detail with reference to the following examples.
Example 1
As shown in fig. 3, the present embodiment provides a power-on reset circuit, including:
The voltage divider comprises a voltage division MOS tube and a voltage division resistor R0, and is provided with a voltage division output point A for generating trigger voltage division and adjusting the power consumption of the power-on reset circuit;
the hysteresis device comprises a hysteresis MOS tube which is electrically connected with the voltage division output point A and is used for avoiding reset voltage jitter caused by power supply VDD voltage jitter;
the input end of the comparator is electrically connected with the voltage division output point A, and the output end of the comparator is electrically connected with the input end of the hysteresis device and is used for converting the triggering voltage division into logic signals;
The input end of the buffer is electrically connected with the output end B of the comparator, and the output end is used as the output end PORB of the power-on reset circuit to output reset voltage for increasing the driving capability of the power-on reset circuit;
The voltage division MOS tube comprises an intrinsic NMOS tube M2, a first voltage division NMOS tube M1 and a second voltage division NMOS tube M0;
the drain electrode of the intrinsic NMOS tube M2 is electrically connected with a power supply VDD, and the source electrode is electrically connected with one end of a divider resistor R0;
the other end of the divider resistor R0 is electrically connected with the grid electrode of the intrinsic NMOS tube M2 and the drain electrode of the first divider NMOS tube M1 at the same time and is used as a divider output point A;
The source electrode of the first voltage division NMOS tube M1 is electrically connected with the drain electrode of the second voltage division NMOS tube M0, and the grid electrode is electrically connected with the power supply VDD;
the source electrode of the second voltage division NMOS tube M0 is electrically connected with the ground GND, and the grid electrode is electrically connected with the drain electrode of the second voltage division NMOS tube M0;
The hysteresis NMOS tube comprises a first hysteresis NMOS tube M4 and a second hysteresis NMOS tube M3;
the drain electrode of the first hysteresis NMOS tube M4 is electrically connected with the voltage division output point A, and the source electrode is electrically connected with the drain electrode of the second hysteresis NMOS tube M3;
The source electrode of the second hysteresis NMOS tube M3 is electrically connected with the ground GND, and the grid electrode is electrically connected with the drain electrode of the second hysteresis NMOS tube M3;
The comparator comprises a comparison PMOS tube M6 and a comparison NMOS tube M5;
the source electrode of the comparison PMOS tube M6 is electrically connected with the power supply VDD, and the drain electrode of the comparison NMOS tube M5 is electrically connected with the drain electrode;
The source electrode of the comparison NMOS tube M5 is electrically connected with the ground GND, and the drain electrode of the comparison NMOS tube M5 is electrically connected with the grid electrode of the first hysteresis NMOS tube M4;
the grid electrodes of the comparison PMOS tube M6 and the comparison NMOS tube M5 are electrically connected with the voltage division output point A at the same time;
in this embodiment, the buffer includes two stages of buffer units connected in series;
The input end of the first-stage buffer unit is electrically connected with the drain electrode of the comparison NMOS tube M5;
The output end of the second-stage buffer unit is used as the output end PORB of the power-on reset circuit;
the input end of the second-stage buffer unit is electrically connected with the output end of the first-stage buffer unit;
In this embodiment, the first stage buffer unit includes a first buffer PMOS tube M8 and a second buffer NMOS tube M7; the second-stage buffer unit comprises a second buffer PMOS tube M10 and a second buffer NMOS tube M9;
The source electrode of each stage of buffer PMOS tube is electrically connected with the power supply VDD, and the drain electrode is electrically connected with the drain electrode of the buffer NMOS tube;
The source electrode of each stage of buffer NMOS tube is electrically connected with the ground GND;
The grid electrodes of each stage of buffer PMOS tube and buffer NMOS tube are mutually and electrically connected and serve as the input end of the buffer unit;
the drain electrode of each stage of buffer NMOS tube is used as the output end of the buffer unit.
The embodiment provides a power-on reset method, which includes:
When the power supply VDD voltage is lower, the second voltage dividing NMOS tube M0 or the first voltage dividing NMOS tube M1 is not conducted, and the voltage divider channel is closed; the intrinsic NMOS transistor M2 is conductive but no current flows, vgs=0, vds=0; the voltage division output point A rises along with the voltage of the power supply VDD; the output end of the comparator is at low level at this time, and the output end PORB of the power-on reset circuit is at low level; at the moment, the gate voltage of the first hysteresis NMOS tube M4 is low level, and the hysteresis channel is in an off state;
when the voltage of the power supply VDD gradually exceeds the sum of the threshold voltages of the second voltage dividing NMOS tube M0 and the first voltage dividing NMOS tube M1, the second voltage dividing NMOS tube M0 and the first voltage dividing NMOS tube M1 are gradually conducted, and the voltage dividing output point A is rapidly pulled down; at this time, the intrinsic NMOS tube M2 is in a linear region, and Vds thereof gradually becomes larger, so that the current gradually rises, but Vgs of the intrinsic NMOS tube M2 also gradually decreases; vgs_m2= -R0; when the voltage of the voltage division output point A drops to the threshold voltage of the comparator, the voltage of the output end B of the comparator is quickly raised, and the PORB signal of the output end of the power-on reset circuit jumps from 0 to 1;
When the voltage of the power supply VDD reaches a certain value, vgs of the intrinsic NMOS tube M2 is reduced to cause the current of the intrinsic NMOS tube M2 to be reduced, the current of the intrinsic NMOS tube M2 is increased by exceeding that of Vds, and the current of the intrinsic NMOS tube M2 is kept to be certain; the enough Vds enables the intrinsic NMOS tube M2 to enter a saturation region, the voltage of the power supply VDD continuously rises, and the current of the intrinsic NMOS tube M2 is kept unchanged; at this time, the voltage at the voltage division output point A approaches to the Vgs of the second voltage division NMOS tube M0 and keeps unchanged;
The gate voltage of the first hysteresis NMOS tube M4 is changed to be high to conduct the hysteresis passage, and the voltage division output point A is pulled down to be lower by the currents generated by the second hysteresis NMOS tube M3 and the first hysteresis NMOS tube M4, so that when the power supply VDD is powered down, the trigger point is lower than the trigger point when the power supply VDD is raised, and the jitter of the output end PORB of the power-on reset circuit caused by the jitter of the power supply VDD can be avoided;
The current of the voltage divider channel can be flexibly changed by adjusting the resistance value of the voltage dividing resistor R0, so that the aim of extremely low power consumption of the whole design is fulfilled;
the circuit controls the current by controlling the Vgs of the intrinsic NMOS tube M2 of the intrinsic NMOS tube, so that the design with extremely low power consumption is realized, and meanwhile, the use of a large-size MOS tube is avoided, thereby saving the cost;
The triggering voltage division of the voltage division output point A is limited by an intrinsic NMOS tube M2, a first voltage division NMOS tube M1 and a second voltage division NMOS tube M0; because the three are NMOS transistors, better process and temperature follow-up can be realized, and the trigger point has smaller change under different processes and temperatures.
Fig. 4 shows a schematic diagram of voltage waveforms of each node in the power-on reset circuit, from which it can be seen that the power-on reset method provided by the invention realizes accurate triggering of the trigger point.
The power-on reset circuit provided by the embodiment of the invention has the advantages of accurate trigger point, insensitivity to process angle and temperature change, small area and low cost, and the trigger point is within +/-100mV along with the process angle, temperature and power supply voltage, and does not rise along with the rising of the power supply voltage.
The foregoing description of embodiments of the invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described.
Claims (10)
1. A power-on reset circuit, comprising:
the voltage divider comprises a voltage division MOS tube and a voltage division resistor, and is provided with a voltage division output point for generating trigger voltage division and adjusting the power consumption of the power-on reset circuit;
The hysteresis device comprises a hysteresis MOS tube which is electrically connected with the voltage division output point and is used for avoiding reset voltage jitter caused by power voltage jitter;
The input end of the comparator is electrically connected with the voltage division output point, and the output end of the comparator is electrically connected with the input end of the hysteresis device and is used for converting the trigger voltage division into logic signals;
And the input end of the buffer is electrically connected with the output end of the comparator, and the output end of the buffer is used as the output end of the power-on reset circuit to output the reset voltage for increasing the driving capability of the power-on reset circuit.
2. The power-on reset circuit of claim 1, wherein the voltage division MOS transistor comprises an intrinsic NMOS transistor, a first voltage division NMOS transistor, and a second voltage division NMOS transistor;
the drain electrode of the intrinsic NMOS tube is electrically connected with a power supply, and the source electrode is electrically connected with one end of the divider resistor;
The other end of the voltage dividing resistor is electrically connected with the grid electrode of the intrinsic NMOS tube and the drain electrode of the first voltage dividing NMOS tube at the same time and is used as the voltage dividing output point;
The source electrode of the first voltage division NMOS tube is electrically connected with the drain electrode of the second voltage division NMOS tube, and the grid electrode of the first voltage division NMOS tube is electrically connected with a power supply;
The source electrode of the second voltage division NMOS tube is electrically connected with the ground, the gate is electrically connected to its own drain.
3. The power-on reset circuit of claim 1, wherein the hysteresis NMOS transistor comprises a first hysteresis NMOS transistor and a second hysteresis NMOS transistor;
The drain electrode of the first hysteresis NMOS tube is electrically connected with the voltage division output point, and the source electrode of the first hysteresis NMOS tube is electrically connected with the drain electrode of the second hysteresis NMOS tube;
And the source electrode of the second hysteresis NMOS tube is electrically connected with the ground, and the grid electrode of the second hysteresis NMOS tube is electrically connected with the drain electrode of the second hysteresis NMOS tube.
4. A power-on reset circuit as recited in claim 3, wherein the comparator comprises a compare PMOS transistor and a compare NMOS transistor;
the source electrode of the comparison PMOS tube is electrically connected with a power supply, and the drain electrode of the comparison NMOS tube is electrically connected with the drain electrode of the comparison NMOS tube;
the source electrode of the comparison NMOS tube is electrically connected with the ground, and the drain electrode of the comparison NMOS tube is electrically connected with the grid electrode of the first hysteresis NMOS tube;
and the grid electrodes of the comparison PMOS tube and the comparison NMOS tube are electrically connected with the voltage division output point at the same time.
5. The power-on reset circuit of claim 1, wherein the buffer comprises at least two stages of buffer cells connected in series;
The input end of the first-stage buffer unit is electrically connected with the drain electrode of the comparison NMOS tube;
the output end of the final-stage buffer unit is used as the output end of the power-on reset circuit;
the input end of each stage of buffer unit is electrically connected with the output end of the previous stage of buffer unit except the final stage;
The number of the buffer units connected in series in at least two stages is an even number.
6. The power-on reset circuit of claim 5, wherein each stage of buffer unit comprises a buffer PMOS transistor and a buffer NMOS transistor;
the source electrode of the buffer PMOS tube is electrically connected with a power supply, and the drain electrode of the buffer PMOS tube is electrically connected with the drain electrode of the buffer NMOS tube;
the source electrode of the buffer NMOS tube is electrically connected with the ground;
the grid electrodes of the buffer PMOS tube and the buffer NMOS tube are mutually and electrically connected and serve as the input end of the buffer unit;
and the drain electrode of the buffer NMOS tube is used as the output end of the buffer unit.
7. A power-on reset method performed in a power-on reset circuit as claimed in any one of claims 1-6, comprising:
generating the trigger voltage division through the voltage division MOS tube and the voltage division resistor and adjusting the power consumption of the power-on reset circuit;
the trigger voltage division is transmitted to the input ends of the hysteresis and the comparator at the same time;
The hysteresis device performs signal hysteresis through the trigger voltage division and the output signal of the comparator, so that reset voltage jitter caused by power voltage jitter is avoided;
The comparator converts the trigger voltage division into a logic signal and outputs the logic signal to the buffer;
the buffer converts the logic signal output by the comparator into a driving signal to drive an external circuit.
8. The power-on reset circuit of claim 7, wherein generating the trigger voltage division and adjusting the power consumption of the power-on reset circuit through the voltage division MOS transistor and the voltage division resistor comprises:
When the power supply voltage is lower than the sum of threshold voltages of the first voltage dividing NMOS tube and the second voltage dividing NMOS tube, the first voltage dividing NMOS tube and the second voltage dividing NMOS tube are not conducted, the intrinsic NMOS tube is conducted without current, and the trigger voltage division is in a high level;
When the power supply voltage is not less than the sum of the threshold voltages of the first voltage dividing NMOS tube and the second voltage dividing NMOS tube and gradually rises, the voltage between the source and the drain of the intrinsic NMOS tube gradually becomes larger, the current flowing through the intrinsic NMOS tube gradually increases, the voltage between the gate and the source gradually decreases, and the value of the voltage is equal to the negative value of the product of the current flowing through the intrinsic NMOS tube and the voltage dividing resistor, and in the process, the intrinsic NMOS tube works in a linear region and triggers the voltage dividing to gradually decrease;
when the power supply voltage is increased to the trigger point voltage, the trigger voltage division is low enough to cause the reset voltage to jump from the logic low level to the logic high level;
when the power supply voltage continues to increase, and the voltage between the gate and the source of the intrinsic NMOS tube is reduced to cause the current flowing through the intrinsic NMOS tube to be reduced more than the voltage between the source and the drain to be increased to cause the current flowing through the intrinsic NMOS tube to be increased, the intrinsic NMOS tube works in a saturation region, the current flowing through the intrinsic NMOS tube is kept unchanged, and the value of the trigger voltage division is close to the voltage of the gate and the source of the second voltage division NMOS tube and is kept unchanged;
And the current flowing through the voltage divider passage is regulated by regulating the size of the voltage regulating resistor, so that the power consumption of the power-on reset circuit is regulated.
9. The power-on reset circuit of claim 8, wherein the hysteresis device performs signal hysteresis by the trigger voltage division and the output signal of the comparator, and avoiding reset voltage jitter caused by power supply voltage jitter comprises:
When the trigger voltage division is at a high level, the output voltage of the comparator is at a low level, and the hysteresis is turned off;
When the trigger voltage division gradually decreases to the threshold voltage of the comparator, the output voltage of the comparator is high level, the first hysteresis NMOS tube is conducted due to the increase of the grid voltage, the second hysteresis NMOS tube is conducted along with the increase of the grid voltage to continuously pull down the trigger voltage division, and if the power supply voltage in the power-down process decreases to the trigger point voltage in the power-up process, the trigger voltage division prevents the reset voltage from changing from the logic high level to the logic low level unless the power supply voltage is continuously decreased, and reset voltage jitter caused by power supply voltage jitter is avoided.
10. The power-on reset circuit of claim 9, wherein the buffer converting the logic signal output by the comparator into a drive signal to drive an external circuit comprises:
and the logic signals output by the comparator are converted into driving signals in a grading way through at least two stages of buffer units connected in series to drive an external circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410633048.XA CN118473390A (en) | 2024-05-21 | 2024-05-21 | Power-on reset circuit and method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410633048.XA CN118473390A (en) | 2024-05-21 | 2024-05-21 | Power-on reset circuit and method |
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