CN118197998B - Half-bridge rectifying chip for improving power density of device - Google Patents
Half-bridge rectifying chip for improving power density of device Download PDFInfo
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- CN118197998B CN118197998B CN202410623600.7A CN202410623600A CN118197998B CN 118197998 B CN118197998 B CN 118197998B CN 202410623600 A CN202410623600 A CN 202410623600A CN 118197998 B CN118197998 B CN 118197998B
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- 239000000758 substrate Substances 0.000 claims description 33
- 238000002955 isolation Methods 0.000 claims description 20
- 238000000034 method Methods 0.000 abstract description 34
- 238000005538 encapsulation Methods 0.000 abstract description 6
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 description 12
- 238000001259 photo etching Methods 0.000 description 10
- 238000005468 ion implantation Methods 0.000 description 8
- 238000005530 etching Methods 0.000 description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0814—Diodes only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
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- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
A half-bridge rectifying chip for improving the power density of a device relates to the technical field of semiconductors. The traditional half-bridge device needs to encapsulate two diode chips in an anti-parallel way, the encapsulation process flow is complex, the encapsulation body is large, the reduction of the power density of the device and the increase of the cost are caused, in the scheme, the two anti-parallel diodes are integrated on one chip by the half-bridge rectification chip, the diodes in the area from the first anode to the first cathode are vertically conductive, the diodes in the area from the second anode to the second cathode are horizontally conductive, the area of the chip is effectively utilized, only one chip needs to be encapsulated by the half-bridge rectification chip in the scheme, the encapsulation process step and the cost are reduced, the use amount of the half-bridge rectification chip can be reduced by half, and the power density of the device is 2 times that of the traditional half-bridge device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a half-bridge rectifying chip for improving the power density of a device.
Background
In the technical field of power electronic devices, the conversion of alternating current to direct current is always an important application field, and current rectifying modes comprise diode rectification, half-bridge rectification and full-bridge rectification.
The half-bridge rectification is used as a common rectification mode, and needs to be realized by using a rectification half-bridge, wherein the traditional rectification half-bridge is formed by packaging two diode chips into a device in an anti-parallel mode, the packaging process flow is complex, the packaging body is large, the power density of the device is reduced, the cost is increased, and along with the higher and higher requirements of a power semiconductor on the power density and the cost performance, the power density of the rectification half-bridge is increased to pay more attention to people.
Disclosure of Invention
The invention aims at the problems and provides the half-bridge rectifier chip for effectively improving the power density of the rectifier half-bridge.
The technical scheme of the invention is as follows:
the half-bridge rectifier chip for improving the power density of the device and the preparation method thereof comprise the following steps:
step S100, preparing a first heavily doped P region on a substrate;
step S200, preparing a plurality of second lightly doped N regions in the first heavily doped P region;
Step S300, preparing a second heavily doped P region in the second lightly doped N region;
Step S400, preparing a second heavily doped N region connected with the first heavily doped P region in the second lightly doped N region;
step S500, depositing an isolation layer on the substrate, and respectively windowing in the first heavily doped P region, the second heavily doped P region and the second heavily doped N region;
step S600, preparing a corresponding first anode, a corresponding second anode and a corresponding second cathode at the window; preparing a first cathode at the bottom of the substrate;
And step S700, the whole device is prepared.
Specifically, step S100 includes:
Step S110, protecting the outer area of the first heavily doped P region by using a mask through a photoetching process;
in step S120, a first heavily doped P region is formed by a diffusion or ion implantation process.
Specifically, step S200 includes:
step S210, protecting the outer areas of the plurality of second lightly doped N areas by using a mask through a photoetching process;
In step S220, a plurality of second lightly doped N regions are formed by diffusion or ion implantation.
Specifically, step S300 includes:
step S310, protecting the outer area of the second heavily doped P region by using a mask through a photoetching process;
In step S320, a second heavily doped P region is formed by a diffusion or ion implantation process.
Specifically, step S400 includes:
step S410, protecting the outer area of the second heavily doped N region by using a mask through a photoetching process;
in step S420, a second heavily doped N region is formed by a diffusion or ion implantation process.
Specifically, step S500 includes:
step S510, preparing an isolation layer through chemical vapor deposition;
And step S520, protecting the external areas of the first heavily doped P region, the second heavily doped P region and the second heavily doped N region by using a mask through a photoetching process, and windowing the first heavily doped P region, the second heavily doped P region and the second heavily doped N region by using an etching process.
Specifically, step S600 includes:
Step S610, preparing a first anode, a second anode and a second cathode at the windows of the first heavily doped P region, the second heavily doped P region and the second heavily doped N region by a stripping process or an etching process;
In step S620, a first cathode is prepared at the bottom of the substrate by a thinning process and a back gold process.
The half-bridge rectification chip for improving the power density of the device comprises a first cathode, a substrate and an isolation layer which are sequentially connected from bottom to top;
the first lightly doped N region in the substrate is provided with:
The first heavily doped P region extends downwards from the top surface of the first lightly doped N region of the substrate, and the bottom surface of the first heavily doped P region is higher than the bottom surface of the first lightly doped N region;
the second lightly doped N region is provided with a plurality of second lightly doped N regions which extend downwards from the top surface of the first heavily doped P region respectively, and the bottom surface of the second lightly doped N region is higher than the bottom surface of the first heavily doped P region;
The second heavily doped P region is provided with a plurality of second lightly doped N regions which extend downwards from the top surface of the second lightly doped N region respectively, and the bottom surface of the second heavily doped P region is higher than the bottom surface of the second lightly doped N region;
The second heavily doped N region is provided with a plurality of second lightly doped N regions which extend downwards from the top surface of the second lightly doped N region respectively and are connected with the first heavily doped P region, and the bottom surface of the second heavily doped N region is higher than the bottom surface of the second lightly doped N region;
The isolating layer is internally provided with:
a first anode extending downwards from the top surface of the isolation layer and connected with the first heavily doped P region to form ohmic contact;
a second anode extending downwards from the top surface of the isolation layer and connected with the second heavily doped P region to form ohmic contact;
And the second cathode extends downwards from the top surface of the isolation layer and is connected with the second heavily doped N region to form ohmic contact, and the first anode and the second cathode are connected.
Specifically, the substrate is an N-type substrate and comprises a first heavily doped N region and a first lightly doped N region from bottom to top, and the first cathode is connected with the first heavily doped N region to form ohmic contact.
Specifically, the doping concentration of the first lightly doped N region is 1e 13.cm-3 to 1e 17.cm-3, and the doping concentration of the first heavily doped N region is 1e 19.cm-3 to 1e 21.cm-3.
The invention has the beneficial effects that:
The traditional half-bridge device needs to encapsulate two diode chips in an anti-parallel way, the encapsulation process flow is complex, the encapsulation body is large, the reduction of the power density of the device and the increase of the cost are caused, in the scheme, the two anti-parallel diodes are integrated on one chip by the half-bridge rectification chip, the diodes in the area from the first anode to the first cathode are vertically conductive, the diodes in the area from the second anode to the second cathode are horizontally conductive, the area of the chip is effectively utilized, only one chip needs to be encapsulated by the half-bridge rectification chip in the scheme, the encapsulation process step and the cost are reduced, the use amount of the half-bridge rectification chip can be reduced by half, and the power density of the device is 2 times that of the traditional half-bridge device.
Drawings
FIG. 1 is a process flow diagram of the present invention;
fig. 2 is a schematic cross-sectional structure of the device in step S100;
Fig. 3 is a schematic cross-sectional structure of the device in step S200;
fig. 4 is a schematic cross-sectional structure of the device in step S300;
fig. 5 is a schematic cross-sectional structure of the device in step S400;
Fig. 6 is a schematic cross-sectional structure of the device in step S500;
fig. 7 is a schematic cross-sectional structure of the device in step S600;
In the figure, 1 is a substrate, 2 is a first heavily doped P region, 3 is a second lightly doped N region, 4 is a second heavily doped P region, 5 is a second heavily doped N region, 6 is an isolation layer, 7 is a first anode, 8 is a second anode, 9 is a second cathode, 10 is a first cathode, 11 is a first heavily doped N region, and 12 is a first lightly doped N region.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.
In the description of the present invention, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention. In the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
The invention is described below with reference to fig. 1-7;
the half-bridge rectifier chip for improving the power density of the device and the preparation method thereof comprise the following steps:
Step S100, preparing a first heavily doped P region 2 on a substrate 1; as shown in fig. 2;
Step S110, protecting the outer area of the first heavily doped P region 2 by using a mask through a photoetching process;
in step S120, the first heavily doped P region 2 is formed by a diffusion or ion implantation process.
Correspondingly, the substrate 1 is an N-type substrate, which consists of a first heavily doped N region 11 and a first lightly doped N region 12 from bottom to top, wherein the thickness of the substrate is 110-2500um, the thickness of the first heavily doped N region 11 is 100-2000um, the thickness of the first lightly doped N region 12 is 10-500um, the first heavily doped P region 2 is positioned in the first lightly doped N region 12, the upper surface and the upper surface of the substrate 1 are horizontal, the lower surface is higher than the lower surface of the first lightly doped N region 12, the junction depth is set to 1-100um, the width is set to 100-10000um, the doping concentration of all lightly doped regions is 1e 13.cm-3 -1 e 17.cm-3, the doping concentration of the heavily doped regions is 1e 19.cm-3 -1 e 21.cm-3, the N-type doped element is phosphorus or arsenic, the P-type doped element is boron, and the related parameters are set and the electrical design of the device is relevant;
In this embodiment, the thickness of the substrate 1 is 600um, the doping element of the first heavily doped N region 11 is phosphorus, the doping concentration is 2e 19.cm-3, the thickness is 500um, the doping element of the first lightly doped N region 12 is phosphorus, the doping concentration is 1e 14.cm-3, the thickness is 100um, the doping element of the first heavily doped P region 2 is boron, the doping concentration is 2e 19.cm-3, the junction depth is 30um, the width is 550um, and the first heavily doped P region 2 is formed by using a diffusion process.
Step S200, preparing a plurality of second lightly doped N regions 3 in the first heavily doped P region 2; as shown in fig. 3;
step S210, protecting the outer areas of the plurality of second lightly doped N regions 3 by using a mask through a photoetching process;
In step S220, a plurality of second lightly doped N regions 3 are formed by diffusion or ion implantation.
Correspondingly, the second lightly doped N regions 3 are positioned in the first heavily doped P regions 2, the upper surface of the second lightly doped N regions is horizontal to the upper surface of the substrate 1, the lower surface of the second lightly doped N regions is higher than the lower surface of the first heavily doped P regions 2, the junction depth is set to be 1-90um, the width is set to be 5-500um, a plurality of the second lightly doped N regions 3 are not connected, the distance is set to be 1-100um, and related parameter settings are related to the electrical design of devices;
in this embodiment, the doping element of the second lightly doped N region 3 is phosphorus, the doping concentration is 1e 14.cm-3, the junction depth is 25um, the width is 230um, the distance between the first heavily doped P regions 2 is 30um, and 2 second lightly doped N regions 3 are prepared by using a diffusion process.
Step S300, preparing a second heavily doped P region 4 in the second lightly doped N region 3; as shown in fig. 4;
Step S310, protecting the outer area of the second heavily doped P region 4 by using a mask through a photoetching process;
In step S320, the second heavily doped P region 4 is formed by a diffusion or ion implantation process.
Correspondingly, the second heavily doped P region 4 is positioned in the second lightly doped N region 3, the upper surface is horizontal to the upper surface of the substrate 1, the lower surface is higher than the lower surface of the second lightly doped N region 3, the junction depth is set to be 1-80um, the width is set to be 5-50um, and the related parameter setting is related to the electrical design of the device;
In this embodiment, the doping element of the second heavily doped P region 4 is boron, the doping concentration is 2e 19.cm-3, the junction depth is 5um, and the width is 30um, so that the second heavily doped P region 4 is prepared by a diffusion process.
Step S400, preparing a second heavily doped N region 5 connected with the first heavily doped P region 2 in the second lightly doped N region 3; as shown in fig. 5;
step S410, protecting the outer area of the second heavily doped N region 5 by using a mask through a photoetching process;
in step S420, the second heavily doped N region 5 is formed by a diffusion or ion implantation process.
Correspondingly, the second heavily doped N region 5 is positioned in the second lightly doped N region 3, the upper surface is horizontal to the upper surface of the substrate 1, the lower surface is higher than the lower surface of the second lightly doped N region 3, the junction depth is set to be 1-80um, the width is set to be 5-50um, the second heavily doped P region 4 and the second heavily doped N region 5 are not connected, the distance between the two is set to be 10-500um, the first heavily doped P region 2 and the second heavily doped N region 5 are connected, and related parameter setting is related to the electrical design of a device;
In this embodiment, the doping element of the second heavily doped N region 5 is phosphorus, the doping concentration is 2e 19.cm-3, the junction depth is 5um, the width is 30um, the second heavily doped N region 5 is prepared by using a diffusion process, the distance between the second heavily doped P region 4 and the second heavily doped N region 5 is set to 70um, and the first heavily doped P region 2 and the second heavily doped N region 5 are connected.
Step S500, depositing an isolation layer 6 on the substrate 1, and respectively windowing the first heavily doped P region 2, the second heavily doped P region 4 and the second heavily doped N region 5; as shown in fig. 6;
step S510, preparing the isolation layer 6 by chemical vapor deposition;
Step S520, the outer areas of the first heavily doped P region 2, the second heavily doped P region 4 and the second heavily doped N region 5 are protected by using a mask through a photoetching process, and windows are opened at the positions of the first heavily doped P region 2, the second heavily doped P region 4 and the second heavily doped N region 5 by using an etching process.
Correspondingly, the isolation layer 6 plays a role in protection, the material is SiO 2 or Si 3N4, the thickness is set to be 10-5000nm, the ICP dry etching is used for windowing, and related parameter setting and device electrical design are related;
In this embodiment, si 3N4 is used as the isolation layer 6, the thickness is set to 200nm, and CF 4 is used for ICP dry etching, the etching rate is 10nm/min to ensure the accuracy of etching, and the etching time is set to 21min to ensure the success of windowing.
Step S600, preparing a first anode 7, a second anode 8 and a second cathode 9 at the window; and preparing a first cathode 10 at the bottom of the substrate 1; as shown in fig. 7;
Step S610, preparing a first anode 7, a second anode 8 and a second cathode 9 at the windows of the first heavily doped P region 2, the second heavily doped P region 4 and the second heavily doped N region 5 through a stripping process or an etching process;
in step S620, the first cathode 10 is prepared at the bottom of the substrate 1 through a thinning process and a back gold process.
Correspondingly, the first anode 7, the second anode 8, the second cathode 9 are in contact with the first heavily doped P region 2, the second heavily doped P region 4 and the second heavily doped N region 5 below and form ohmic contact, the first anode 7 and the second cathode 9 are connected, and the first cathode 10 is connected with the first heavily doped N region 11 above and forms ohmic contact;
The first anode 7, the second anode 8 and the second cathode 9 are prepared by using a metal stripping process, four layers of metals of Al/Ti/Ni/Ag are used as ohmic contact metals, the first anode 7 and the second cathode 9 form metal interconnection, a thinning process is used for thinning a 600um substrate to 180um, and a back gold process is used for depositing four layers of metals of Al/Ti/Ni/Ag as ohmic contact metals of the first cathode 10.
And step S700, the whole device is prepared.
The half-bridge rectification chip for improving the power density of the device comprises a first cathode 10, a substrate 1 and an isolation layer 6 which are sequentially connected from bottom to top;
the first lightly doped N region 12 in the substrate 1 is provided with:
a first heavily doped P region 2 extending downward from the top surface of the first lightly doped N region 12 of the substrate 1; the bottom surface is higher than the bottom surface of the first lightly doped N region 12;
The second lightly doped N region 3 is provided with a plurality of second lightly doped N regions, and each second lightly doped N region extends downwards from the top surface of the first heavily doped P region 2; the bottom surface is higher than the bottom surface of the first heavily doped P region 2; a plurality of second lightly doped N regions 3 are not interconnected;
the second heavily doped P region 4 is provided with a plurality of second lightly doped N regions 3, which extend downwards from the top surface of the second lightly doped N region, and the bottom surface is higher than the bottom surface of the second lightly doped N region 3;
The second heavily doped N region 5 is provided with a plurality of second lightly doped N regions which extend downwards from the top surface of the second lightly doped N region 3 respectively and are connected with the first heavily doped P region 2, and the bottom surface of the second heavily doped N region is higher than the bottom surface of the second lightly doped N region 3; the second heavily doped P region 4 is separated from the second heavily doped N region 5;
the isolation layer 6 is provided with:
A first anode 7 extending downward from the top surface of the isolation layer 6 and connected to the first heavily doped P region 2 to form an ohmic contact;
A second anode 8 extending downward from the top surface of the isolation layer 6 and connected to the second heavily doped P region 4 to form an ohmic contact;
a second cathode 9 extending downward from the top surface of the isolation layer 6 and connected to the second heavily doped N region 5 to form an ohmic contact, the first anode 7 and the second cathode 9 being interconnected;
Further defined, the substrate is an N-type substrate comprising a first heavily doped N region 11 and a first lightly doped N region 12 from bottom to top, the first cathode 10 being in contact with the first heavily doped N region 11 forming an ohmic contact.
Further defined, the doping concentration of the first lightly doped N region 12 is 1e 13.cm-3 to 1e 17.cm-3, the doping concentration of the first heavily doped N region 11 is 1e 19.cm-3 to 1e 21.cm-3, the N-type doped element is phosphorus or arsenic, and the P-type doped element is boron.
The invention has the following advantages:
In the scheme, the half-bridge rectifying chip integrates two diodes which are connected in parallel in an opposite direction on one chip, a first anode 7 and a second cathode 9 are connected with each other, one end of an external alternating current power supply is connected, a second anode 8 and a first cathode 10 are connected with each other through a packaging frame and a jumper wire, the other end of the power supply is connected, when the first anode 7 and the second cathode 9 are connected with positive voltage during power on, current flows into the first cathode 10 from the first anode 7 through a first heavily doped P region 2, a first lightly doped N region 12 and a first heavily doped N region 11, and the second anode 9 and the second anode 8 are reversely cut off through an NP junction formed by a second lightly doped N region 3 and a second heavily doped P region 4; when the power is on, the second anode 8 and the first cathode 10 are connected with positive voltage, and current flows from the second anode 8 into the second cathode 9 through the second heavily doped P region 4, the second lightly doped N region 3 and the second heavily doped N region 5, and the NP junction formed by the first lightly doped N region 12 and the first heavily doped P region 2 of the first cathode 10 and the first anode 7 is reversely cut off.
When the half-bridge rectifying chip is used, only one chip is required to be packaged, the packaging process steps and the cost are reduced, the half-bridge rectifying chip can be used for reducing the use amount of half chips, and the power density of the device is 2 times that of a traditional half-bridge device.
For the purposes of this disclosure, the following points are also described:
1. the drawings of the embodiments disclosed in the present application relate only to the structures related to the embodiments disclosed in the present application, and other structures can refer to common designs;
2. Under the condition of no conflict, the embodiments disclosed in the present application and the features in the embodiments can be combined with each other to obtain new embodiments;
The above is only a specific embodiment disclosed in the present application, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (3)
1. The half-bridge rectifier chip for improving the power density of the device is characterized by comprising a first cathode (10), a substrate (1) and an isolation layer (6) which are sequentially connected from bottom to top;
the first lightly doped N region (12) in the substrate (1) is internally provided with:
a first heavily doped P region (2) extending downwards from the top surface of a first lightly doped N region (12) of the substrate (1);
the second lightly doped N region (3) is provided with a plurality of second lightly doped N regions which extend downwards from the top surface of the first heavily doped P region (2);
the second heavily doped P region (4) is provided with a plurality of second lightly doped N regions (3) which extend downwards from the top surface of the second lightly doped N region;
The second heavily doped N region (5) is provided with a plurality of second lightly doped N regions (3) which extend downwards from the top surface of the second lightly doped N region and are connected with the first heavily doped P region (2);
the isolating layer (6) is provided with:
A first anode (7) extending downwards from the top surface of the isolation layer (6) and connected with the first heavily doped P region (2) to form ohmic contact;
A second anode (8) extending downwards from the top surface of the isolation layer (6) and connected with the second heavily doped P region (4) to form ohmic contact;
And a second cathode (9) extending downwards from the top surface of the isolation layer (6) and connected with the second heavily doped N region (5) to form ohmic contact, wherein the first anode (7) and the second cathode (9) are interconnected.
2. The half-bridge rectifier chip for increasing the power density of a device according to claim 1, wherein the substrate (1) is an N-type substrate comprising a first heavily doped N-region (11) and a first lightly doped N-region (12) from bottom to top, and the first cathode (10) and the first heavily doped N-region (11) are connected to form an ohmic contact.
3. The half-bridge rectifier chip of claim 2 wherein said first lightly doped N region (12) has a doping concentration of 1e 13.cm-3 to 1e 17.cm-3 and said first heavily doped N region (11) has a doping concentration of 1e 19.cm-3 to 1e 21.cm-3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410623600.7A CN118197998B (en) | 2024-05-20 | 2024-05-20 | Half-bridge rectifying chip for improving power density of device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410623600.7A CN118197998B (en) | 2024-05-20 | 2024-05-20 | Half-bridge rectifying chip for improving power density of device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118197998A CN118197998A (en) | 2024-06-14 |
| CN118197998B true CN118197998B (en) | 2024-08-02 |
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| CN106449640B (en) * | 2016-11-30 | 2023-07-18 | 上海芯石微电子有限公司 | Novel schottky device for full-bridge rectification and manufacturing method |
| CN111524885B (en) * | 2020-05-27 | 2024-05-14 | 捷捷半导体有限公司 | Power integrated circuit chip and manufacturing method thereof |
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