CN118118010A - Clock detection circuit, clock detection method, chip and communication system - Google Patents

Clock detection circuit, clock detection method, chip and communication system Download PDF

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Publication number
CN118118010A
CN118118010A CN202410236899.0A CN202410236899A CN118118010A CN 118118010 A CN118118010 A CN 118118010A CN 202410236899 A CN202410236899 A CN 202410236899A CN 118118010 A CN118118010 A CN 118118010A
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China
Prior art keywords
clock
trigger
signal
detection signal
unit
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CN202410236899.0A
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CN118118010B (en
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阮召崧
吴磊
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Nanjing Jinzhen Microelectronics Technology Co ltd
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Nanjing Jinzhen Microelectronics Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/40—Monitoring; Error detection; Preventing or correcting improper counter operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

The application provides a clock detection circuit, a detection method, a chip and a communication system, wherein the circuit comprises: a trigger unit including a first trigger and a second trigger; the detected clock is input to the first trigger; a synchronization unit outputting a synchronization signal of the first trigger; an inverting unit outputting an inverted signal corresponding to the synchronization signal, the inverted signal being received by the second flip-flop and outputting an intermediate detection signal; the reset synchronization unit resets the intermediate detection signal output by the second trigger and then transmits the intermediate detection signal to the reset input end of the first trigger; and the clock detection unit is used for outputting a clock detection signal after detecting the intermediate detection signal output by the second trigger. The application provides a clock detection circuit through the construction of a pure digital circuit, and circuit resources are saved.

Description

Clock detection circuit, clock detection method, chip and communication system
Technical Field
The present application relates to a detection circuit, and more particularly, to a clock detection circuit, a detection method, a chip, and a communication system.
Background
Clock signals are critical in various application areas, such as communication systems, and the reliability requirements for the clock signals are very stringent. For stable signal transmission, the phenomenon of continuous loss of clock signal pulses is not allowed. When the clock signal is lost or abnormal, the chip cannot work normally, so that it is necessary to design a special clock detection circuit.
The traditional method for detecting the loss of the clock signal is that the clock signal is sent to the outside of a chip, such as an oscilloscope, for observation; or testing the average frequency of the clock in a preset period, and the method may not immediately detect the input clock loss error; the other is to control the discharge of the capacitor of the basic timing unit after the reference clock edge is extracted by the reference clock edge extraction circuit, output the voltage information of the capacitor by the Schmitt trigger, and obtain the final state information by the counter processing. This does not rely on an additional reference clock, but the circuit is relatively complex and not easy to integrate.
Disclosure of Invention
The application provides a clock detection circuit, a detection method, a chip and a communication system, which are used for solving the problems that the detection is not timely and the detection circuit is complex in the traditional clock detection mode.
In a first aspect, the present application provides a clock detection circuit, the circuit comprising: a trigger unit including a first trigger and a second trigger; the detected clock is input to the first trigger; the synchronous unit is connected with the output end of the first trigger and outputs a synchronous signal of the first trigger; the inverting unit is respectively connected with the output end of the synchronizing unit and the input end of the second trigger and outputs an inverting signal corresponding to the synchronizing signal, and the inverting signal is received by the second trigger and then outputs an intermediate detection signal; the reset synchronization unit is respectively connected with the reset input end of the first trigger and the output end of the second trigger, and transmits an intermediate detection signal output by the second trigger to the reset input end of the first trigger after being reset; and the clock detection unit is connected with the output end of the second trigger, and outputs a clock detection signal after detecting the intermediate detection signal output by the second trigger.
In one implementation manner of the first aspect, the first flip-flop is a D flip-flop; the detected clock is input to the clock end of the D trigger, and the input end of the D trigger is connected with a high level.
In one implementation of the first aspect, the clock detection signal includes a clock loss signal; the clock detection unit comprises a lost period counter and a lost threshold comparator, and the lost period counter is connected with the lost threshold comparator; and responding to the intermediate detection signal to be at a high level, inputting the high level by the loss period counter, outputting a loss counting result to the loss threshold comparator, and outputting the clock loss signal by the loss threshold comparator.
In an implementation manner of the first aspect, the clock detection signal includes a clock recovery signal; the clock detection unit comprises a recovery period counter and a recovery threshold comparator, and the recovery period counter is connected with the recovery threshold comparator; and responding to the intermediate detection signal as a recovery clock rising edge, inputting the recovery clock rising edge by the recovery period counter, outputting a recovery counting result to the recovery threshold comparator, and outputting the clock loss signal by the recovery threshold comparator.
In an implementation manner of the first aspect, the circuit further includes a first parameter design unit; the first parameter design unit is used for determining that one of a plurality of detected clocks is input to the first trigger.
In an implementation manner of the first aspect, the second flip-flop includes at least one flip-flop, and each flip-flop outputs the intermediate detection signal after cascading.
In an implementation manner of the first aspect, the circuit further includes a second parameter design unit; the second parameter design unit is used for determining at least one of the plurality of second triggers to cascade and then outputting the intermediate detection signal.
In a second aspect, the present application provides a clock detection method, the method comprising: inputting the detected clock to a first trigger; outputting a synchronizing signal of the first trigger; outputting an inverted signal corresponding to the synchronous signal, wherein the inverted signal is received by a second trigger and then an intermediate detection signal is output; the intermediate detection signal output by the second trigger is reset and then transmitted to the input of the first trigger; and outputting a clock detection signal after detecting the intermediate detection signal output by the second trigger.
In a third aspect, the present application provides a chip comprising: the circuit.
In a fourth aspect, the present application provides a communication system comprising: the circuit; the communication system communicates using a detected clock that is clock detected by the circuit.
As described above, the clock detection circuit, the clock detection method, the chip and the communication system of the present application have the following advantages:
The application provides a clock detection method which is built by a pure digital circuit, has low cost, quick response and easy integration, and can also realize the detection of a plurality of clocks through parameter design, thereby saving circuit resources. The application has simple integration, can be integrated in one PLD (Programmable Logic Device programmable logic device) to be realized, and improves the reliability of clock detection.
Drawings
Fig. 1 is a schematic circuit diagram of a clock detection circuit according to an embodiment of the application.
Fig. 2 is a schematic circuit diagram of a clock detection circuit according to an embodiment of the application.
Fig. 3 is a schematic diagram of clock detection of the clock detection circuit according to an embodiment of the application.
Fig. 4 shows a clock detection timing chart of the clock detection circuit according to an embodiment of the application.
Fig. 5 is a schematic flow chart of a clock detection method according to an embodiment of the application.
Fig. 6 is a schematic structural diagram of a chip according to an embodiment of the application.
Fig. 7 is a schematic structural diagram of a communication system according to an embodiment of the present application.
Description of element reference numerals
1. Clock detection circuit
11. Trigger unit
111. First trigger
112. Second trigger
12. Synchronization unit
13. Inverting unit
14. Reset synchronization unit
15. Clock detection unit
151. Lost period counter
152. Loss threshold comparator
153. Recovery period counter
154. Recovery threshold comparator
S51 to S55 steps
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the illustrations, not according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
The following describes the technical solution in the embodiment of the present application in detail with reference to the drawings in the embodiment of the present application.
Referring to fig. 1, a circuit diagram of a clock detection circuit according to an embodiment of the application is shown. As shown in fig. 1, the present embodiment provides a clock detection circuit 1, specifically including: a flip-flop unit 11, a synchronization unit 12, an inversion unit 13, a reset synchronization unit 14, and a clock detection unit 15.
The trigger unit 11 includes a first trigger 111 and a second trigger 112; the detected clock is input to the first flip-flop 111.
The synchronization unit 12 is connected to the output terminal of the first flip-flop 111, and outputs a synchronization signal of the first flip-flop 111.
The inverting unit 13 is respectively connected with the output end of the synchronizing unit 12 and the input end of the second trigger 112, and outputs an inverted signal corresponding to the synchronizing signal, and the inverted signal is received by the second trigger 112 and then outputs an intermediate detection signal.
The reset synchronization unit 14 is respectively connected to the reset input terminal of the first trigger 111 and the output terminal of the second trigger 112, and transmits the intermediate detection signal output by the second trigger 112 to the reset input terminal of the first trigger 111 after resetting.
The clock detection unit 15 is connected to the output end of the second flip-flop 112, and outputs a clock detection signal after detecting the intermediate detection signal output from the second flip-flop 112.
Referring to fig. 2, a schematic circuit diagram of a clock detection circuit according to an embodiment of the application is shown. As shown in fig. 2, the first flip-flop 111 and the second flip-flop 112 are D flip-flops with a reset input terminal, the D flip-flop used for the first flip-flop 111 is used as a first D flip-flop, and the D flip-flop used for the second flip-flop 112 is used as a second D flip-flop.
Referring to fig. 2, the detected clock is input to the clock terminal of the first D flip-flop, and the input terminal D terminal of the D flip-flop is connected to the high level 1' b 1.
The synchronization unit 12 is connected to the output Q terminal of the first D flip-flop 111, and the synchronization unit 12 outputs a synchronization signal of the first D flip-flop 111.
The inverting unit 13 is respectively connected with the output end of the synchronizing unit 12 and the input end D end of the second D flip-flop 112, and outputs an inverted signal corresponding to the synchronizing signal, where the inverted signal is received by the D end of the second flip-flop 112 and then output an intermediate detection signal by the Q end.
The reset synchronization unit 14 is respectively connected to the reset input terminal CLR of the first D flip-flop 111 and the output terminal Q of the second D flip-flop 112, and transmits the intermediate detection signal output by the second D flip-flop 112 to the reset input terminal CLR of the first D flip-flop 111 after being reset.
The clock detection unit 15 is connected to the output Q of the second D flip-flop 112, and outputs a clock detection signal, such as a clock loss signal clk_loss, after detecting the intermediate detection signal output from the second D flip-flop 112 under the effect of the enable signal enable.
Specifically, the synchronization unit includes a synchronizer, the inversion unit includes an inverter, and the reset synchronization unit includes a reset synchronizer.
It should be noted that the D flip-flop is only one embodiment of the present application, and other electronic components having a data input terminal, a clock input terminal, a reset input terminal, and a data output terminal and capable of implementing the clock detection principle of the present application are all within the scope of the present application.
Referring to fig. 3, a schematic diagram of clock detection of the clock detection circuit according to an embodiment of the application is shown. As shown in fig. 3, the clock detection signals output by the clock detection unit 15 in different states of the clock are different, and the clock detection signal output when the clock is lost is a clock lost signal; and after the clock is lost, recovering the clock detection signal output by the clock recovery circuit to obtain a clock recovery signal.
In one embodiment, the clock detection signal comprises a clock loss signal.
As shown in fig. 3, the clock detection unit 15 includes a lost period counter 151 and a lost threshold comparator 152, and the lost period counter 151 is connected to the lost threshold comparator 152.
In response to the intermediate detection signal being at a high level, the loss period counter 151 inputs the high level, outputs a loss count result to the loss threshold comparator 152, and the loss threshold comparator 152 outputs the clock loss signal.
In another embodiment, the clock detection signal comprises a clock recovery signal.
As shown in fig. 3, the clock detection unit includes a recovery period counter 153 and a recovery threshold comparator 154, and the recovery period counter 153 is connected to the recovery threshold comparator 154.
In response to the intermediate detection signal being a recovered clock rising edge, the recovery period counter 153 inputs the recovered clock rising edge, outputs a recovery count result to the recovery threshold comparator 154, and the recovery threshold comparator 154 outputs the clock loss signal.
In one embodiment, the circuit further comprises a first parameter design unit;
The first parameter design unit is used for determining that one of a plurality of detected clocks is input to the first trigger.
Specifically, the detected clock is selected by instantiating multiple times or using mux, thus the application selects the detected clock by mux, multiplexes the same set of clock detection logic to save circuit resources. In practical applications, the detected clocks may be determined according to a multiple relationship different from the reference clock.
In an embodiment, the second flip-flop includes at least one flip-flop, and each flip-flop outputs the intermediate detection signal after cascade connection. As shown in fig. 2, the second D flip-flops are cascaded, the input terminal D of the foremost second D flip-flop is connected to the inverting unit 13, the output terminal Q of the rearmost second D flip-flop is connected to the clock detecting unit 15, and the output terminals Q of the intermediate second D flip-flops are all connected to the input terminal D of the latter. All the clock terminals of the second D flip-flops are connected with an internal reliable clock, and the CLR reset terminal is connected with reliable reset. The reliable clock refers to a crystal oscillator clock, or a clock which is not lost is determined, and the reliable reset refers to reset generated under the reliable clock.
In an embodiment, the circuit further comprises a second parameter design unit.
The second parameter design unit is used for determining at least one of the plurality of second triggers to cascade and then outputting the intermediate detection signal.
Specifically, the second parameter unit may be implemented by a selection circuit including a switching on/off device, and one or more second flip-flops are shorted or connected by opening and closing the switch, so as to determine which second flip-flop or second flip-flops are connected to the clock detection circuit.
The application can realize the detection of different clocks due to the parameterized design of the first parameter design unit; through the parameterization design of the second parameter design unit, the number of the D trigger groups is controllable in parameters, so that the reliability and stability detection of clock loss can be ensured.
Referring to fig. 2 and 3, the clock detection circuit in this embodiment operates as follows:
As shown in fig. 2, the high level is connected to the D terminal of the first D flip-flop, and when the detected clock is lost, the Q terminal of the first D flip-flop outputs 0 due to the lost clock. The synchronized signal is changed into 1 through the first-stage synchronizer, connected to the D end of the second D trigger, 1 is output from the Q end of the second D trigger at the last stage through a plurality of D triggers, one end of the signal is connected to the reset end CLR of the first D trigger through the reset synchronizer, and the other end of the signal is connected to the clock detection unit. Because the first D trigger has no clock, the Q end output is always 0, so the Q end of the last stage D trigger is always high level; in the clock detection unit, the present time of the high level is recorded by the lost period counter, and when the set lost threshold is reached, for example, the preset lost threshold is 5 periods, a clock lost signal is output. In practical application, the setting of the loss threshold mainly considers the frequency relation between the detected clock and the reference clock and the criterion that the clock is considered to be lost; for the criterion, in order to avoid that the clock is only flashed off, the detected clock is generally pulled down for at least 5-6 periods and is considered to be lost; and the final threshold value is set according to the multiple relation of the two.
When the detected clock is recovered, the Q end of the first D trigger outputs 1, after passing through the synchronizer and the inverter, the output 0 is connected to the second D trigger group, the second D trigger of the last stage outputs 0, one end of the second D trigger passes through the reset synchronizer and then is connected to the reset end CLR of the first D trigger, and as the reset low level is effective, the first D trigger outputs 0, and after passing through the synchronizer and the inverter, the second D trigger outputs 1; thus, at the clock detection unit, the signal seen is a 0,1 transition; the clock detection unit records the jump times from 0 to 1 through the recovery period counter, and when the recovery threshold is reached, the clock loss signal is withdrawn, namely the clock loss signal is changed into a clock recovery signal. In practical applications, the recovery threshold is set as well as the loss threshold, and whether the detected clock is actually recovered or jumps for a moment needs to be considered, so that the detected clock is maintained for at least 4-5 periods and is considered to be recovered.
Referring to fig. 4, a clock detection timing diagram of a clock detection circuit according to an embodiment of the application is shown. As shown in fig. 4, the det_clk represents the detected clock, ref_clk represents the reference clock, clk_loss represents the clock loss signal, if_en represents the clock detection unit enable signal, dout represents the output signal of the last second D flip-flop. It can be seen that the clk_loss high period is the output period of the clock loss signal.
Referring to fig. 5, a schematic flow chart of a clock detection method according to an embodiment of the application is shown. As shown in fig. 5, the present embodiment provides a clock detection method applied to a clock detection circuit, where the clock detection circuit includes: a trigger unit including a first trigger and a second trigger; the detected clock is input to the first trigger; the synchronous unit is connected with the output end of the first trigger and outputs a synchronous signal of the first trigger; the inverting unit is respectively connected with the output end of the synchronizing unit and the input end of the second trigger and outputs an inverting signal corresponding to the synchronizing signal, and the inverting signal is received by the second trigger and then outputs an intermediate detection signal; the reset synchronization unit is respectively connected with the reset input end of the first trigger and the output end of the second trigger, and transmits an intermediate detection signal output by the second trigger to the reset input end of the first trigger after being reset; and the clock detection unit is connected with the output end of the second trigger, and outputs a clock detection signal after detecting the intermediate detection signal output by the second trigger. The clock detection method specifically includes steps S51 to S55:
S51, inputting the detected clock to the first trigger.
In an embodiment, the first flip-flop is a D flip-flop; the detected clock is input to the clock end of the D trigger, and the input end of the D trigger is connected with a high level.
In one embodiment, the circuit further comprises a first parameter design unit; the first parameter design unit is used for determining that one of a plurality of detected clocks is input to the first trigger.
S52, outputting the synchronous signal of the first trigger.
And S53, outputting an inverted signal corresponding to the synchronous signal, wherein the inverted signal is received by the second trigger and then an intermediate detection signal is output.
In an embodiment, the second flip-flop includes at least one flip-flop, and each flip-flop outputs the intermediate detection signal after cascade connection.
In an embodiment, the circuit further comprises a second parameter design unit; the second parameter design unit is used for determining at least one of the plurality of second triggers to cascade and then outputting the intermediate detection signal.
S54, the intermediate detection signal output by the second trigger is reset and then transmitted to the input of the first trigger.
And S55, detecting the intermediate detection signal output by the second trigger and then outputting a clock detection signal.
In one embodiment, the clock detection signal comprises a clock loss signal; the clock detection unit comprises a lost period counter and a lost threshold comparator, and the lost period counter is connected with the lost threshold comparator; and responding to the intermediate detection signal to be at a high level, inputting the high level by the loss period counter, outputting a loss counting result to the loss threshold comparator, and outputting the clock loss signal by the loss threshold comparator.
In one embodiment, the clock detection signal comprises a clock recovery signal; the clock detection unit comprises a recovery period counter and a recovery threshold comparator, and the recovery period counter is connected with the recovery threshold comparator; and responding to the intermediate detection signal as a recovery clock rising edge, inputting the recovery clock rising edge by the recovery period counter, outputting a recovery counting result to the recovery threshold comparator, and outputting the clock loss signal by the recovery threshold comparator.
The protection scope of the clock detection method according to the embodiment of the present application is not limited to the execution sequence of the steps listed in the embodiment, and all the schemes implemented by adding or removing steps and replacing steps according to the prior art according to the principles of the present application are included in the protection scope of the present application.
The clock detection circuit provided by the embodiment of the application can realize the clock detection method of the application, but the realizing device of the clock detection method of the application comprises but is not limited to the structure of the clock detection circuit listed in the embodiment, and all structural modifications and substitutions of the prior art according to the principles of the application are included in the protection scope of the application.
In the several embodiments provided in the present application, it should be understood that the disclosed circuit device or method may be implemented in other manners. For example, the above-described circuit embodiments are merely illustrative, e.g., the division of modules/units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple modules or units may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or modules or units, which may be in electrical, mechanical or other forms.
The modules/units illustrated as separate components may or may not be physically separate, and components shown as modules/units may or may not be physical modules, i.e., may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules/units may be selected according to actual needs to achieve the objectives of the embodiments of the present application. For example, functional modules/units in various embodiments of the application may be integrated into one processing module, or each module/unit may exist alone physically, or two or more modules/units may be integrated into one module/unit.
Those of ordinary skill would further appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, in computer software, or in a combination of the two, and that the elements and steps of the examples have been generally described in terms of function in the foregoing description to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
Fig. 6 is a schematic structural diagram of a chip according to an embodiment of the application. As shown in fig. 6, the present embodiment provides a chip including: the clock detection circuit described above.
The clock detection circuit includes: a trigger unit including a first trigger and a second trigger; the detected clock is input to the first trigger; the synchronous unit is connected with the output end of the first trigger and outputs a synchronous signal of the first trigger; the inverting unit is respectively connected with the output end of the synchronizing unit and the input end of the second trigger and outputs an inverting signal corresponding to the synchronizing signal, and the inverting signal is received by the second trigger and then outputs an intermediate detection signal; the reset synchronization unit is respectively connected with the reset input end of the first trigger and the output end of the second trigger, and transmits an intermediate detection signal output by the second trigger to the reset input end of the first trigger after being reset; and the clock detection unit is connected with the output end of the second trigger, and outputs a clock detection signal after detecting the intermediate detection signal output by the second trigger.
In an embodiment, the first flip-flop is a D flip-flop; the detected clock is input to the clock end of the D trigger, and the input end of the D trigger is connected with a high level.
In one embodiment, the clock detection signal comprises a clock loss signal; the clock detection unit comprises a lost period counter and a lost threshold comparator, and the lost period counter is connected with the lost threshold comparator; and responding to the intermediate detection signal to be at a high level, inputting the high level by the loss period counter, outputting a loss counting result to the loss threshold comparator, and outputting the clock loss signal by the loss threshold comparator.
In one embodiment, the clock detection signal comprises a clock recovery signal; the clock detection unit comprises a recovery period counter and a recovery threshold comparator, and the recovery period counter is connected with the recovery threshold comparator; and responding to the intermediate detection signal as a recovery clock rising edge, inputting the recovery clock rising edge by the recovery period counter, outputting a recovery counting result to the recovery threshold comparator, and outputting the clock loss signal by the recovery threshold comparator.
In one embodiment, the circuit further comprises a first parameter design unit; the first parameter design unit is used for determining that one of a plurality of detected clocks is input to the first trigger.
In an embodiment, the second flip-flop includes at least one flip-flop, and each flip-flop outputs the intermediate detection signal after cascade connection.
In an embodiment, the circuit further comprises a second parameter design unit; the second parameter design unit is used for determining at least one of the plurality of second triggers to cascade and then outputting the intermediate detection signal.
Fig. 7 is a schematic structural diagram of a communication system according to an embodiment of the application. As shown in fig. 7, the present embodiment provides a communication system including: the clock detection circuit described above; the communication system communicates using a detected clock that is clock detected by the circuit.
The clock detection circuit includes: a trigger unit including a first trigger and a second trigger; the detected clock is input to the first trigger; the synchronous unit is connected with the output end of the first trigger and outputs a synchronous signal of the first trigger; the inverting unit is respectively connected with the output end of the synchronizing unit and the input end of the second trigger and outputs an inverting signal corresponding to the synchronizing signal, and the inverting signal is received by the second trigger and then outputs an intermediate detection signal; the reset synchronization unit is respectively connected with the reset input end of the first trigger and the output end of the second trigger, and transmits an intermediate detection signal output by the second trigger to the reset input end of the first trigger after being reset; and the clock detection unit is connected with the output end of the second trigger, and outputs a clock detection signal after detecting the intermediate detection signal output by the second trigger.
In an embodiment, the first flip-flop is a D flip-flop; the detected clock is input to the clock end of the D trigger, and the input end of the D trigger is connected with a high level.
In one embodiment, the clock detection signal comprises a clock loss signal; the clock detection unit comprises a lost period counter and a lost threshold comparator, and the lost period counter is connected with the lost threshold comparator; and responding to the intermediate detection signal to be at a high level, inputting the high level by the loss period counter, outputting a loss counting result to the loss threshold comparator, and outputting the clock loss signal by the loss threshold comparator.
In one embodiment, the clock detection signal comprises a clock recovery signal; the clock detection unit comprises a recovery period counter and a recovery threshold comparator, and the recovery period counter is connected with the recovery threshold comparator; and responding to the intermediate detection signal as a recovery clock rising edge, inputting the recovery clock rising edge by the recovery period counter, outputting a recovery counting result to the recovery threshold comparator, and outputting the clock loss signal by the recovery threshold comparator.
In one embodiment, the circuit further comprises a first parameter design unit; the first parameter design unit is used for determining that one of a plurality of detected clocks is input to the first trigger.
In an embodiment, the second flip-flop includes at least one flip-flop, and each flip-flop outputs the intermediate detection signal after cascade connection.
In an embodiment, the circuit further comprises a second parameter design unit; the second parameter design unit is used for determining at least one of the plurality of second triggers to cascade and then outputting the intermediate detection signal.
The principle and the realization effect of the communication system in different application scenes are as follows:
In the first scenario, a PHY (Physical, port Physical layer, which is a common abbreviation for OSI model Physical layer), a MAC (MEDIA ACCESS Control Address, a media access Control Address, also called Physical Address) and a Switch are connected to a clock detection circuit, and a message is normally received and sent under the condition of normal clock; if the clock configuration of the PHY is closed, the message can not be normally received and transmitted, and a clock loss signal is output. Therefore, in the scene, the application can quickly remove faults which are not originated from Switch and MAC, and can quickly determine the problem of physical PHY.
In a second scenario, the configuration bus is used to access the internal register of the chip, and the clock detection circuit is accessed, so that no matter whether the chip reads or writes, the clock loss signal of the configuration clock is output. In this scenario, the present application can determine the problem of the bus read/write failure not the logical path, but the problem of the configuration clock.
The descriptions of the processes or structures corresponding to the drawings have emphasis, and the descriptions of other processes or structures may be referred to for the parts of a certain process or structure that are not described in detail.
The above embodiments are merely illustrative of the principles of the present application and its effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the application. Accordingly, it is intended that all equivalent modifications and variations of the application be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. A clock detection circuit, the circuit comprising:
A trigger unit including a first trigger and a second trigger; the detected clock is input to the first trigger;
The synchronous unit is connected with the output end of the first trigger and outputs a synchronous signal of the first trigger;
The inverting unit is respectively connected with the output end of the synchronizing unit and the input end of the second trigger and outputs an inverting signal corresponding to the synchronizing signal, and the inverting signal is received by the second trigger and then outputs an intermediate detection signal;
The reset synchronization unit is respectively connected with the reset input end of the first trigger and the output end of the second trigger, and transmits an intermediate detection signal output by the second trigger to the reset input end of the first trigger after being reset;
And the clock detection unit is connected with the output end of the second trigger, and outputs a clock detection signal after detecting the intermediate detection signal output by the second trigger.
2. The circuit of claim 1, wherein the first flip-flop is a D flip-flop;
the detected clock is input to the clock end of the D trigger, and the input end of the D trigger is connected with a high level.
3. The circuit of claim 1, wherein the clock detection signal comprises a clock loss signal;
The clock detection unit comprises a lost period counter and a lost threshold comparator, and the lost period counter is connected with the lost threshold comparator;
And responding to the intermediate detection signal to be at a high level, inputting the high level by the loss period counter, outputting a loss counting result to the loss threshold comparator, and outputting the clock loss signal by the loss threshold comparator.
4. The circuit of claim 1, wherein the clock detection signal comprises a clock recovery signal;
the clock detection unit comprises a recovery period counter and a recovery threshold comparator, and the recovery period counter is connected with the recovery threshold comparator;
and responding to the intermediate detection signal as a recovery clock rising edge, inputting the recovery clock rising edge by the recovery period counter, outputting a recovery counting result to the recovery threshold comparator, and outputting the clock loss signal by the recovery threshold comparator.
5. The circuit of claim 1, further comprising a first parameter design unit;
The first parameter design unit is used for determining that one of a plurality of detected clocks is input to the first trigger.
6. The circuit of claim 1, wherein:
the second flip-flop includes at least one flip-flop, and each flip-flop outputs the intermediate detection signal after cascade connection.
7. The circuit of claim 6, further comprising a second parameter design unit;
The second parameter design unit is used for determining at least one of the plurality of second triggers to cascade and then outputting the intermediate detection signal.
8. A method of clock detection, the method comprising:
inputting the detected clock to a first trigger;
Outputting a synchronizing signal of the first trigger;
Outputting an inverted signal corresponding to the synchronous signal, wherein the inverted signal is received by a second trigger and then an intermediate detection signal is output;
the intermediate detection signal output by the second trigger is reset and then transmitted to the input of the first trigger;
and outputting a clock detection signal after detecting the intermediate detection signal output by the second trigger.
9. A chip, the chip comprising: the circuit of any one of claims 1 to 7.
10. A communication system, the communication system comprising: the circuit of any one of claims 1 to 7; the communication system communicates using a detected clock that is clock detected by the circuit.
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