CN118035006B - Control system capable of being dynamically configured for independent and lockstep operation of three-core processor - Google Patents
Control system capable of being dynamically configured for independent and lockstep operation of three-core processor Download PDFInfo
- Publication number
- CN118035006B CN118035006B CN202410437569.8A CN202410437569A CN118035006B CN 118035006 B CN118035006 B CN 118035006B CN 202410437569 A CN202410437569 A CN 202410437569A CN 118035006 B CN118035006 B CN 118035006B
- Authority
- CN
- China
- Prior art keywords
- processor
- lockstep
- core
- independent
- slave
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012545 processing Methods 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims description 10
- 230000003111 delayed effect Effects 0.000 claims description 9
- 230000001360 synchronised effect Effects 0.000 claims description 8
- 230000008569 process Effects 0.000 claims description 7
- 230000007704 transition Effects 0.000 claims description 2
- 238000013461 design Methods 0.000 abstract description 15
- 230000008901 benefit Effects 0.000 abstract description 6
- 238000001514 detection method Methods 0.000 abstract description 3
- 238000004364 calculation method Methods 0.000 abstract description 2
- 238000005516 engineering process Methods 0.000 description 16
- 238000010586 diagram Methods 0.000 description 5
- 238000012937 correction Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 230000009897 systematic effect Effects 0.000 description 1
- 230000007306 turnover Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
- G06F11/2041—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant with more than one idle spare processing component
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1608—Error detection by comparing the output signals of redundant hardware
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
- G06F9/526—Mutual exclusion algorithms
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Quality & Reliability (AREA)
- Hardware Redundancy (AREA)
Abstract
The invention provides a control system capable of realizing independent and lockstep running dynamic configuration of a three-core processor, and the whole processor system can flexibly switch working modes according to different task scheduling by virtue of the design of an independent-lockstep state micro-system structure level, so that the performance advantage of the multi-core processor is fully exerted, and meanwhile, the lockstep strategy is configured by utilizing the redundancy characteristic of the multi-core processor, so that the system reliability is ensured while the calculation resource is not wasted. The invention adopts a processing mode of a multiprocessor clock domain, eliminates single-point faults caused by single clock crosstalk and comparison logic error overturn, and simultaneously sets the same processor result comparison before and after clock synchronization and the comparison of a plurality of processor output results after clock domain synchronization in the error detection and control module respectively, thereby realizing the accurate tracking of fault results.
Description
Technical Field
The invention relates to the technical field of fault-tolerant design of processors, in particular to a control system capable of realizing independent and lockstep operation and dynamic configuration of a three-core processor.
Background
With the development of aerospace technology, complex space tasks place more stringent demands on high-performance and high-reliability processors. Spacecraft are subject to extreme temperatures, radiation, shock, and vibration in space environments, which can lead to reduced performance or complete failure of the electronic system, thereby rendering the mission useless. Therefore, the spacecraft needs to use a specially designed fault-tolerant processor to have the characteristics of high speed, low power consumption, fault tolerance, radiation resistance and the like, so that the integrity of data and the continuous operation of the system are ensured.
The fault-tolerant design of the processor commonly used in the industry comprises a critical path register multi-mode redundancy technology, a memory error correction and detection coding technology, a multi-core lock step technology and the like. However, under the advanced nano-process scale, the improvement of the integration level also brings reliability problems such as the increase of the multi-bit turnover rate, and the traditional method for strengthening weak points in the processor in a targeted manner has hardly been effective, and a system-level fault-tolerant method mainly comprising multi-core lock steps is becoming the main stream.
The current main processor lockstep technology comprises a dual-core lockstep technology and a three-core lockstep technology, wherein the dual-core lockstep technology performs real-time comparison inspection on an inspector through dual-core output, and a fault processor is restarted through a comparison result; the latter carries out error correction through the mode of output voting, has the advantage that the reliability is high, real-time is strong. However, these designs have the following problems and disadvantages:
Under the application of extreme scenes, aiming at the functional characteristics of real-time tasks, higher requirements are respectively put forward on the processing performance and the reliability according to task classification, if the multi-core processor core is configured as a lock step, the reliability can only be ensured, flexible matching between the design reliability and the performance can not be realized, and the original performance of the design can not be effectively exerted; although a delay design is introduced in the current lockstep design, clock domains used by the delay of a processor are not subdivided, and single-point faults possibly caused by crosstalk of clock signals in the delay-synchronization process cannot be effectively protected, wherein the single-point faults originate from a lockstep system, and can be accumulated to cause serious systematic faults together with error overturn caused by external environment.
Disclosure of Invention
In order to solve the technical problems in the background art, the invention provides a control system capable of realizing independent and lockstep operation and dynamic configuration of a three-core processor, and aims to provide a control system capable of configuring a processing mode of a processor core, so that the processor realizes flexible configuration of a high-reliability lockstep redundancy mode and a high-performance independent operation mode, is suitable for space tasks with different complexity, improves the operation mode of the three-core lockstep, further perfects a time redundancy mode by means of delaying lockstep, configuring multiple clock domains and the like on the basis of space redundancy, and ensures the operation correctness of each node.
The invention is realized by the following technical scheme:
The control system comprises a main processor without a memory, two slave processors without a memory, a storage system of the main processor, a multi-bit judging device, a fault collecting and controlling unit, a discrete lockstep state control system and a time delay lockstep synchronous system, wherein the two slave processors are connected to the storage system of the main processor through buses;
The discrete lockstep state control system can enable the master processor and the slave processor to respectively operate in a lockstep mode or an independent operation mode by configuring an operation mode; in lockstep mode, three of the processors input the same signal, resulting in an output through the multi-bit arbiter; in the independent operation mode, the three processors respectively input different signals and independently output respective operation results;
The output results of the three processors are sent to a multi-bit decision device to check the correctness of the output results, and the multi-bit decision device compares the output results of the three processors one by one according to bits and outputs a final processing result according to majority decision logic;
The delay lock step synchronization system adopts a delay strategy of staggering the execution sequence of three processor cores: three clock signals with the same clock frequency are adopted for the three processor cores, a main processor core running under a main clock domain firstly fetches instructions, and the same instructions are respectively delayed for one period and two periods and then are transmitted into two slave processor cores; after the main processor core processes the instruction, the instruction is transmitted into a multi-bit decision device after being delayed for two periods and synchronized under a lock step clock domain; after the two slave processor cores process the instruction, the two slave processor cores respectively delay one period and directly output the instruction to the multi-bit decision device after synchronizing in the clock domain of the main processor; and meanwhile, the three processor signals are further compared and output error indication signals through the fault collecting and controlling unit.
As a further illustration of the present invention, the memory systems of the master and slave processors each include a CACHE domain and TCDM domain; the CACHE domain comprises a discrete instruction CACHE and a data CACHE, and is connected to a storage system of the next stage through a bus; the TCDM field includes instruction TCM and data TCM components.
As a further illustration of the present invention, when the processor is configured in lockstep mode, the master processor executes a custom software routine to configure the cores in three-core lockstep mode by configuring the associated registers such that the lockstep cores trigger interrupts to suspend their own threads to enter lockstep mode, and the interrupt service routine temporarily stores the lockstep processor internal register state in the stack registers.
As a further illustration of the present invention, when the state of a processor core is stored in a stacked register, the data information stored in the stacked register is stored in the memory system of each processor.
As a further illustration of the present invention, when a processor transitions to independent mode of operation, all processor cores are released from lockstep mode by lockstep enable indication signal control registers, while all state combination logic is turned off, and the lockstep mode to independent mode of operation is switched by clearing the core state of both slave processors and loading the state registers of both slave processors back by using the stacked registers that each store a system memory map.
As a further illustration of the present invention, the combinational logic circuit uses a hierarchical gating multiplexer for switching of circuit states.
As a further illustration of the present invention, each processor signal, after entering the fault collection and control unit, completes the output consistency comparison under different clock domains, outputs the compared signals, performs the result comparison through a three-input exclusive-or gate, and outputs the error indication signal, and simultaneously, the slave processor and the slave processor perform the exclusive-or processing, and then the comparison outputs the three-bit signals E, E signals, which are stored in the enabling latch.
Compared with the prior art, the invention has the following beneficial technical effects:
1. Through the design of the independent-lockstep state micro-architecture layer, the whole processor system can flexibly switch the working modes according to different task scheduling, the performance advantage of the multi-core processor is fully exerted, the lockstep strategy is configured by utilizing the redundancy characteristic of the multi-core processor, the calculation resource is not wasted, and the system reliability is guaranteed.
2. The processing mode of the multiprocessor clock domain is adopted, single-point faults caused by single clock crosstalk and comparison logic error overturning are eliminated, and meanwhile, the same processor result comparison before and after clock synchronization and the comparison of a plurality of processor output results after clock domain synchronization are respectively arranged in the error detection and control module, so that the accurate tracking of fault results is realized.
3. For the problem of higher power consumption caused by a combination logic circuit in multi-clock domain switching and mode switching, a hierarchical gating multiplexer is designed, so that on one hand, static power consumption optimization in the combination logic circuit is realized, and on the other hand, the hierarchical gating multiplexer is also coupled with multi-clock design in a system to form a multi-stage switching power consumption control structure.
Additional features and advantages of the present technology will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the technology. The objects and other advantages of the present technical solution may be realized and attained by the structure particularly pointed out in the written description and drawings.
The technical scheme of the technical scheme is further described in detail through the drawings and the embodiments.
Drawings
The accompanying drawings are included to provide a further understanding of the present technology and are incorporated in and constitute a part of this specification, illustrate the technology and together with the description serve to explain the example of the technology, and do not limit the technology. In the drawings:
FIG. 1 is a block diagram of a micro-architecture of a control system for independent and lockstep operation dynamically configurable for a three-core processor in accordance with the present invention.
Fig. 2 is a diagram of a finite state machine implementation of the independent-lockstep mode switching in the present invention.
FIG. 3 is a schematic diagram of a fault collection and control unit according to the present invention.
FIG. 4 is a logic diagram of a hierarchical gated multiplexer according to the present invention.
Detailed Description
The following description of the preferred embodiments of the present invention is made with reference to the accompanying drawings, and it is to be understood that the preferred embodiments described herein are for illustration and explanation of the present invention only and are not intended to limit the present invention thereto.
As shown in FIG. 1, the present invention provides a control system with independent and lock-step operation and dynamic configuration of a three-CORE processor, comprising a main processor CORE0 without a memory, two slave processors CORE1 and CORE2 without a memory, a storage system of a configurable master-slave processor, a multi-bit decision device, a fault collection and control unit, a discrete lock-step state control system and a time delay lock-step synchronization system, wherein the two slave processors are connected to the storage system of the main processor through buses.
The discrete lockstep state control system can enable the master processor CORE0 and the slave processors CORE1 and CORE2 to respectively operate in a lockstep mode or an independent operation mode by configuring an operation mode; in lockstep mode, three processors input the same signal, and the result is output through a multi-bit decision device; in the independent operation mode, the three processors respectively input different signals and independently output respective operation results.
The output results of the three processors are sent to a multi-bit decision device to check the correctness of the output results, and the multi-bit decision device compares the output results of the three processors one by one according to bits and outputs a final processing result according to majority decision logic. When data inconsistency is detected, the multi-bit decision device outputs according to the principle that most obeys a minority, and the output accuracy is ensured under the condition of any single-core fault.
The delay lock step synchronization system adopts a delay strategy for staggering the execution sequence of three processor cores. Unlike the traditional delay lock step which only carries out delay operation under one clock domain, the invention adopts three clock signals with the same clock frequency for three processor COREs, and specifically realizes that a main processor CORE (CORE 0) running under a main clock domain firstly fetches an instruction, and the same instruction is respectively delayed by one period and two periods and then is transmitted into two auxiliary processor COREs (CORE 1 and CORE 2); after the main processor CORE0 processes the instruction, the instruction is transmitted into a multi-bit decision device after being delayed for two periods and synchronized under a lock step clock domain; the slave processor COREs CORE1 and CORE2 respectively delay one period and directly output instructions to the multi-bit decision device after synchronizing in a clock domain of a main processor CORE0 after processing the instructions; and meanwhile, the three processor signals are further compared and output error indication signals through the fault collecting and controlling unit.
Further, each processor core has its own memory system, and the L1 memory system includes a CACHE domain and TCDM domains, where the CACHE domain includes a separate instruction CACHE and data CACHE, and the CACHE domain is connected to the next-level memory system through a bus; the quick SRAM memory bank with the TCDM domains is composed of instruction TCM and data TCM, and has the advantages of large capacity, quick response and flexible configuration. Meanwhile, the storage system of the TCM in the design is provided with an outward slave interface, and the storage resource of the part can be flexibly called through a host on a bus.
As shown in fig. 1, after the system is reset or before the system is started, the working modes of the processor COREs are configured through the application program scheduling according to the task requirements, when the system is configured into a three-CORE Lockstep mode (Triple Core Lock Step, TCLS, lockstep_enable=1), the Lockstep enable signals in the system turn off the input signals of CORE1 and CORE2 COREs, so that the three COREs all receive the task processing from CORE0, on the micro-architecture, CORE1 and CORE2 are connected to the storage system of CORE0 through a bus, the same instructions are all operated on the pipeline of the three processor COREs, at this time, the main processor CORE can write into the storage system through a CACHE domain or TCDM domain in the writing back process, CORE1 CORE2 does not have the writing back function, meanwhile, the writing back of CORE1 and CORE2 is controlled to be turned off through a multiplexer, an and gate logic and the like, and finally the signals output by the three COREs enter a multi-bit device and a fault collecting and controlling unit respectively after delay and synchronization, so that the correction output of the current processing results and the fault indication error indication signals are output by the CORE accurately.
When the system operates in the independent operation mode (lockstep_enable=0), CORE0 is still the CORE for normally executing the processing task, while CORE1 and CORE2 select respective input signals through lockstep_enable signals, and all three COREs use their own memory systems to execute related processing tasks respectively.
Fig. 2 is a schematic diagram of working mode conversion between an independent operation mode and a three-core lockstep mode in the present invention, mainly including an independent operation mode, a lockstep mode, an unloading mode, and a reloading mode, and specific state conversion is as follows:
When the processor needs to be configured into a Lockstep mode, a main processor CORE executes a self-defined software routine, and a CORE is configured into a three-CORE Lockstep mode by configuring related registers, so that Lockstep COREs CORE1 and CORE2 trigger interrupt to suspend own threads to enter the Lockstep mode, and an interrupt service routine temporarily stores the states of internal registers such as a Lockstep processor CORE program counter PC, a register file RF and the like into a stack register SP. The processor core participating in lockstep must be operating normally and can service interrupts, and if the processor core is still in a sleep state, the interrupt service routine will also correctly wake the processor core to participate in lockstep.
Once the state of the processor CORE is stored in the stack, the data information stored in the stack is stored in the lock CORE TCDM field or the CACHE field, so that the lock mode can be conveniently and continuously called after the subsequent exit, which indicates that the lock processor has completed the state unloading, and the lock mode can be accessed by loading the register state from the stack of the CORE0 after the state register is emptied.
Independent mode of operation: to switch to independent mode of operation, all processor COREs are released from Lockstep mode by writing state control register lockstep_enable to 0, while all state combining logic is turned off, CORE0 may continue execution because of internal state, CORE1, CORE2 CORE states are cleared, and CORE1, CORE2 PC, RF, CSR, etc. state registers are loaded back by using their respective CACHE domain, TCDM domain memory mapped SP registers, to effect Lockstep mode to independent mode switching.
In order to avoid the influence of clock signals in the traditional delay lockstep, the delay-synchronous instruction operation mechanism in the lockstep mode adopts a main clock domain and two identical clock signals of the lockstep clock domain to be respectively input into three processors as shown in tables 1-1, 1-2 and 1-3, when a processor CORE is switched to a three-CORE lockstep mode, delay and synchronization are also counted into a pipeline stage of the processor, a three-CORE delay lockstep strategy is specifically implemented as that the input of the CORE1 running in the lockstep clock domain is delayed by one period and the CORE2 is delayed by two periods, and the operation result of the CORE0 running in the main clock domain respectively enters a fault collecting and controlling unit and a multi-bit decision device after being delayed by 2 periods after being synchronized by the slave clock domain; the CORE1 and CORE2 signals are synchronized in the main clock domain after delaying for one period and two periods, and then output to the fault collecting and controlling unit and the multi-bit judging unit, one instruction needs eight periods from instruction fetching to execution completion output, wherein the delay of two periods and the synchronization of one period are included, but the actual execution performance of the main CORE and the instruction execution period number are not changed.
TABLE 1-1
TABLE 1-2
Tables 1 to 3
As shown in fig. 3, the fault collection and control unit detects and outputs relevant fault information by comparing the operation results of the operation under the three cores one by one. The processor signals synchronized by different clock domains enter the fault collecting and controlling unit, the lock step indication signal enables to control the starting and closing of the part, and when the lock step indication signal is 1, the fault collecting and controlling unit starts. In order to prevent the function of the fault collection and control unit from generating single-point faults, the invention adopts a multi-redundancy backup design structure, namely, each processor signal completes output consistency comparison under different clock domains after entering the fault collection and control unit, so as to prevent clock signal errors or fault collection and control logic errors, the compared signals are output, then result comparison is carried out through a three-input exclusive-OR gate, and error indication signals are output, meanwhile, three-bit signals E [2:0] are output through the comparison after the exclusive-OR processing of the CORE0 and the CORE1 and the CORE2, and the E signals are stored in an enabling latch so as to facilitate subsequent continuous output.
The lock step error indication signal also serves as an enabling signal for enabling the latch, when the error indication signal is 0, the latch does not work, when the error indication signal is 1, the E signal is stored in the latch so as to be output at any time, and the fault collection and control unit has double redundancy comparison result description, namely, the function definition of the E signal is shown in the table 2, so that a core processor with specific errors is mainly conveniently searched during subsequent error processing.
Furthermore, the above-mentioned combinational logic circuit uses a hierarchical gating multiplexer for switching the circuit states, and specifically, as shown in fig. 4, the invention provides a clocked combinational logic circuit, which effectively solves the problem of combinational logic power consumption in the switching circuit. The circuit design uses a hierarchical gating multiplexer for switching the circuit state, namely a group of P transistors MP1 and MP0 and a group of N transistors MN1 and MN0 controlled by clock signals are added in a transistor circuit, signal logic signals are transmitted to an output structure when the clock signals rise, and the circuit is turned off under the other conditions, so that the static power consumption of logic circuits such as the multiplexer is effectively reduced.
TABLE 2
In order to accurately adapt to the design of multiple clock domains in the design, a group of P pipes MP6 and MP7 and a group of N pipes MN6 and MN7 are added, the input of clock signals is controlled through a select_enable signal, when the control signal is 0, the MP7 and the MN7 are conducted, the clock signals from the main clock domain are connected to the transistors, meanwhile, MP4 and MN5 are conducted, MP3 and MN4 are cut off, the circuit forms a conducting route from MP4, MP2, MP0, MN3 and MN5, and at the moment, if the clock signals in MN0 and MP0 are rising edges, the input_0 of the input signals is output to an output interface to realize the selection of signals; similarly, when the control signal is 1, MP3, MP7, MN4 are turned on, the signal input_1 is Input through MP5, MN2, and is output under the control of ck_main clock domain, so that gating of the input_1 signal is realized.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present technology without departing from the spirit or scope of the technology. Thus, if such modifications and variations of the present technical solution fall within the scope of the present technical solution claims and the technical equivalents thereof, the present technical solution is also intended to include such modifications and variations.
Claims (7)
1. The control system is characterized by comprising a main processor without a memory, two slave processors without a memory, a storage system of the main processor, a multi-bit judging device, a fault collecting and controlling unit, a discrete lockstep state control system and a time delay lockstep synchronous system, wherein the two slave processors are connected to the storage system of the main processor through buses;
The discrete lockstep state control system can enable the master processor and the slave processor to respectively operate in a lockstep mode or an independent operation mode by configuring an operation mode; in lockstep mode, three of the processors input the same signal, resulting in an output through the multi-bit arbiter; in the independent operation mode, the three processors respectively input different signals and independently output respective operation results;
The output results of the three processors are sent to a multi-bit decision device to check the correctness of the output results, and the multi-bit decision device compares the output results of the three processors one by one according to bits and outputs a final processing result according to majority decision logic;
The delay lock step synchronization system adopts a delay strategy of staggering the execution sequence of three processor cores: three clock signals with the same clock frequency are adopted for the three processor cores, a main processor core running under a main clock domain firstly fetches instructions, and the same instructions are respectively delayed for one period and two periods and then are transmitted into two slave processor cores; after the main processor core processes the instruction, the instruction is transmitted into a multi-bit decision device after being delayed for two periods and synchronized under a lock step clock domain; after the two slave processor cores process the instruction, the two slave processor cores respectively delay one period and directly output the instruction to the multi-bit decision device after synchronizing in the clock domain of the main processor; and meanwhile, the three processor signals are further compared and output error indication signals through the fault collecting and controlling unit.
2. The three-core processor independent and lockstep operation dynamically configurable control system of claim 1, wherein said master-slave processor storage systems each comprise a CACHE domain and TCDM domains; the CACHE domain comprises a discrete instruction CACHE and a data CACHE, and is connected to a storage system of the next stage through a bus; the TCDM field includes an instruction TCM and a data TCM.
3. The three-core processor independent and lockstep running dynamically configurable control system of claim 1 wherein when the processor is configured in lockstep mode, the master processor executes a custom software routine, the cores are configured in three-core lockstep mode by configuring the associated registers such that the lockstep cores two slave processors trigger interrupts to suspend their own threads to enter lockstep mode, and the interrupt service routine temporarily stores the two slave processor internal register states in the stack registers.
4. The three-core processor independent and lockstep operation dynamically configurable control system of claim 3 wherein when two slave processor core states are stored in a stacked register, the data information stored in the stacked register is stored in the memory system of each processor.
5. The three-core processor independent and lockstep operation dynamically configurable control system of claim 3 wherein when the processor transitions to independent operation mode, all processor cores are released from lockstep mode by lockstep enable indication signal control registers while all state combining logic is shut down, the lockstep mode to independent operation mode switching is accomplished by clearing the core states of both slave processors and loading back the state registers of both slave processors using the stack registers that each store a system memory map.
6. The three core processor independent and lockstep operation dynamically configurable control system of claim 5, wherein the combinational logic circuit uses a hierarchical gating multiplexer for switching of circuit states.
7. The independent and lockstep operation dynamically configurable control system of claim 1, wherein each processor signal completes output consistency check under different clock domains after entering the fault collection and control unit, the checked signals are output and then result checked through a three-input exclusive-or gate and error indication signals are output, and simultaneously, by exclusive-or processing the master processor and the two slave processors, the slave processors and the slave processors output three-bit signals E, E signals after checking, which are stored in the enabling latch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410437569.8A CN118035006B (en) | 2024-04-12 | 2024-04-12 | Control system capable of being dynamically configured for independent and lockstep operation of three-core processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410437569.8A CN118035006B (en) | 2024-04-12 | 2024-04-12 | Control system capable of being dynamically configured for independent and lockstep operation of three-core processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118035006A CN118035006A (en) | 2024-05-14 |
| CN118035006B true CN118035006B (en) | 2024-06-18 |
Family
ID=91004514
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410437569.8A Active CN118035006B (en) | 2024-04-12 | 2024-04-12 | Control system capable of being dynamically configured for independent and lockstep operation of three-core processor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118035006B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118427112B (en) * | 2024-07-05 | 2024-09-06 | 西北工业大学 | Lock-step core debugging and fault-tolerant performance verification system in multi-core structure processor |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7747932B2 (en) * | 2005-06-30 | 2010-06-29 | Intel Corporation | Reducing the uncorrectable error rate in a lockstepped dual-modular redundancy system |
| US8635492B2 (en) * | 2011-02-15 | 2014-01-21 | International Business Machines Corporation | State recovery and lockstep execution restart in a system with multiprocessor pairing |
| US10831628B2 (en) * | 2018-12-12 | 2020-11-10 | Intel Corporation | Hardware lockstep checking within a fault detection interval in a system on chip |
| CN111190774B (en) * | 2019-12-26 | 2023-04-14 | 北京时代民芯科技有限公司 | Configurable dual-mode redundancy structure of multi-core processor |
| CN112667450B (en) * | 2021-01-07 | 2022-05-06 | 浙江大学 | Dynamically configurable fault-tolerant system with multi-core processor |
| CN115016997B (en) * | 2022-08-08 | 2022-11-18 | 南京芯驰半导体科技有限公司 | Rapid diagnosis system and method for register in slow clock domain lockstep module |
| CN116257342A (en) * | 2023-02-27 | 2023-06-13 | 中国科学院微小卫星创新研究院 | Configurable fault-tolerant star software task scheduling system based on multi-core processor |
| CN116821038B (en) * | 2023-08-28 | 2023-12-26 | 英特尔(中国)研究中心有限公司 | Lock step control apparatus and method for processor |
| CN117687846A (en) * | 2023-09-18 | 2024-03-12 | 张家港方博明芯集成电路有限公司 | Pipeline reinforcement method and system based on dual-core lockstep processor |
-
2024
- 2024-04-12 CN CN202410437569.8A patent/CN118035006B/en active Active
Non-Patent Citations (1)
| Title |
|---|
| 刘强 ; 关宁 ; 王冠雄 ; 杨凯 ; 黄硕 ; .基于RISC-V的多核可重构处理器架构研究.航天标准化.2020,(02),全文. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118035006A (en) | 2024-05-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3493062B1 (en) | Data processing system having lockstep operation | |
| JP4795025B2 (en) | Dynamic reconfigurable device, control method, and program | |
| US7590907B2 (en) | Method and apparatus for soft-error immune and self-correcting latches | |
| CN112667450B (en) | Dynamically configurable fault-tolerant system with multi-core processor | |
| US20090044044A1 (en) | Device and method for correcting errors in a system having at least two execution units having registers | |
| US10579536B2 (en) | Multi-mode radiation hardened multi-core microprocessors | |
| CN118035006B (en) | Control system capable of being dynamically configured for independent and lockstep operation of three-core processor | |
| CN220983766U (en) | Periodic fault detection and repair circuit for dual-core lockstep | |
| CN114649048A (en) | Concurrent computation and ECC for matrix vector operations in memory | |
| Kakoee et al. | Variation-tolerant architecture for ultra low power shared-l1 processor clusters | |
| CN105045335A (en) | FPGA information processing system with embedded 8051IP core | |
| Kempf et al. | An adaptive lockstep architecture for mixed-criticality systems | |
| CN111190774B (en) | Configurable dual-mode redundancy structure of multi-core processor | |
| US20090249174A1 (en) | Fault Tolerant Self-Correcting Non-Glitching Low Power Circuit for Static and Dynamic Data Storage | |
| US6785847B1 (en) | Soft error detection in high speed microprocessors | |
| Hong et al. | Design and implementation of fault-tolerant soft processors on FPGAs | |
| Namazi et al. | PCG: Partially clock-gating approach to reduce the power consumption of fault-tolerant register files | |
| Nakabeppu et al. | A Non-stop Fault-Tolerant Real-Time System-on-Chip/System-in-Package | |
| Imai et al. | Fault diagnosis and reconfiguration method for network-on-chip based multiple processor systems with restricted private memories | |
| CN112506701B (en) | Multiprocessor chip error recovery method based on three-mode lockstep | |
| CN116755923B (en) | Single event upset resistant memory architecture FPGA | |
| Liu et al. | Fast recoverable heterogeneous quad-core lockstep architecture | |
| Yoshimoto et al. | A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme Using Simultaneously Copyable SRAM | |
| CN116737470A (en) | Memory architecture FPGA for overcoming single event upset failure by backup backtracking | |
| CN118939320A (en) | RISC-V dual-core processing system based on FPGA |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |