CN117975897A - Display panel and driving method thereof - Google Patents
Display panel and driving method thereof Download PDFInfo
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- CN117975897A CN117975897A CN202410080807.4A CN202410080807A CN117975897A CN 117975897 A CN117975897 A CN 117975897A CN 202410080807 A CN202410080807 A CN 202410080807A CN 117975897 A CN117975897 A CN 117975897A
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 230000000630 rising effect Effects 0.000 claims description 9
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- 239000004973 liquid crystal related substance Substances 0.000 description 2
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- Microelectronics & Electronic Packaging (AREA)
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- Optics & Photonics (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The application discloses a display panel and a driving method thereof, wherein the display panel is divided into a plurality of rows of sub-pixels along the direction of a data line, each row of sub-pixels is correspondingly provided with a first scanning line connected with odd columns of sub-pixels and a second scanning line connected with even columns of sub-pixels, and two adjacent rows of sub-pixels are correspondingly provided with four grid driving units and four clock signal lines; the first scanning line corresponding to the current row of sub-pixels is connected with a first clock signal line through a first grid driving unit, and the second scanning line corresponding to the current row of sub-pixels is connected with a third clock signal line through the first grid driving unit; the first scanning line corresponding to the next row of sub-pixels is connected with the second clock signal line through the third grid driving unit, and the second scanning line corresponding to the next row of sub-pixels is connected with the fourth clock signal line through the fourth grid driving unit. According to the application, the clock signal lines connected with the scanning lines corresponding to the adjacent two rows of sub-pixels are exchanged, so that RGB single-color picture display is realized.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to a display panel and a driving method thereof.
Background
The Liquid crystal display (Liquid CRYSTAL DISPLAY, LCD) has the advantages of thin body, power saving, no radiation and the like, and is widely applied; in the development process of large-size and high-refresh rate display panels, a double-Line Gate (DLG) technology is paid attention to, and the DLG technology is also called a double-frequency refresh technology, and the principle of the DLG technology is that a panel GDL circuit simultaneously opens two rows of scanning lines, and the two rows input the same scanning signal.
In the LCD display industry, DRD (Double Row Driving) is increasingly applied at present, because it can save the number of Chip On Films (COF), reduce the cost, and the DRD display panel uses DLG technology under the DRD pixel architecture because the adjacent rows are connected with the same data line and the pixels with different colors are connected with each other, and the two pixels with different colors in DLG mode display the same gray level, so that RGB monochromatic pictures cannot be displayed, the display panel cannot normally display colors, and the problem to be solved is how to use DLG technology under the DRD pixel architecture.
Disclosure of Invention
The application aims to provide a display panel and a driving method thereof, which realize the single-color display of a DRD display panel in a DLG mode.
The application discloses a display panel, which is divided into a plurality of rows of sub-pixels along the direction of a data line, wherein each row of sub-pixels is correspondingly provided with two scanning lines, the two scanning lines are respectively a first scanning line and a second scanning line, the first scanning line is connected with odd columns of sub-pixels, the second scanning line is connected with even columns of sub-pixels, the same columns of sub-pixels in each row of sub-pixels have the same color, and each data line is connected with two adjacent columns of sub-pixels with different colors;
Four grid driving units and four clock signal lines are correspondingly arranged on two adjacent rows of sub-pixels, wherein the four grid driving units are respectively a first grid driving unit, a second grid driving unit, a third grid driving unit and a fourth grid driving unit, and the four clock signal lines are respectively a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line;
The first scanning line corresponding to the current row of sub-pixels is connected with a first clock signal line through a first grid driving unit, and the second scanning line corresponding to the current row of sub-pixels is connected with a third clock signal line through the first grid driving unit; the first scanning line corresponding to the next row of sub-pixels is connected with the second clock signal line through the third grid driving unit, and the second scanning line corresponding to the next row of sub-pixels is connected with the fourth clock signal line through the fourth grid driving unit.
Optionally, the display panel includes a refresh rate adjustment module, a clock signal control module and a timing control module, where the clock signal control module is connected with the refresh rate adjustment module and the timing control module respectively, the refresh rate adjustment module generates a refresh rate control signal according to refresh rate information, the timing control module generates a clock signal according to the refresh rate information, a first output end of the refresh rate adjustment module is connected with the clock signal line and outputs a corresponding clock signal to the clock signal line, the clock signal control module is disposed between the gate driving unit and the clock signal line, and a second output end of the refresh rate adjustment module is connected with the clock signal control module and outputs a refresh rate control signal to control communication between the clock signal line and the gate driving unit, so as to realize display of pictures with different refresh rates.
Optionally, the clock signal control module includes a first control circuit and a second control circuit, the first control circuit includes a first control switch and a second control switch, the second control circuit includes a third control switch and a fourth control switch, control ends of the first control switch and the second control switch are connected with a first control signal line, an input end of the first switch is connected with the first clock signal line, an output end of the first switch is respectively connected with an output end of the third control switch and a third gate driving unit, an input end of the second control switch is connected with the third clock signal line, and an output end of the second control switch is respectively connected with an output end of the fourth control switch and the fourth gate driving unit; the control ends of the third control switch and the fourth control switch are connected with a second control signal line, the input end of the third switch is connected with the second clock signal line, the output end of the third switch is connected with a third grid driving unit, the input end of the fourth switch is connected with the fourth clock signal line, and the output end of the fourth switch is connected with a fourth grid driving unit.
Optionally, the display panel includes a protection circuit, the protection circuit includes a fifth control switch and a sixth control switch, an input end and a control end of the fifth control switch are connected to a first control signal line, and an output end of the fifth control switch is connected to a control end of the first control switch; the input end and the control end of the sixth control switch are connected with the first control signal line, and the output end is connected with the control end of the second control switch.
Optionally, the display panel further includes a first storage circuit and a second storage circuit, one end of the first storage circuit is connected to the control end of the first control switch, one end of the first storage circuit is connected between the output end of the third control switch and the third gate driving unit, one end of the second storage circuit is connected to the control end of the second control switch, and one end of the second storage circuit is connected between the output end of the fourth control switch and the fourth gate driving unit.
The application also discloses a driving method of the display panel, which is used for driving the display panel according to any one of the above, and comprises the following steps:
outputting a frame start signal to first to fourth gate driving units corresponding to two adjacent rows of sub-pixels; and
Sequentially outputting a first clock signal to the first grid unit, a second clock signal to the third grid unit, a third clock signal to the second grid unit, and a fourth clock signal to the fourth grid unit to generate corresponding grid driving signals to two adjacent rows of sub-pixels for driving display.
Optionally, the display panel includes a refresh rate adjustment module, a clock signal control module and a timing control module, where the clock signal control module is connected with the refresh rate adjustment module and the timing control module respectively, a first output end of the refresh rate adjustment module is connected with the clock signal line, the clock signal control module is disposed between the gate driving unit and the clock signal line, a second output end of the refresh rate adjustment module is connected with the clock signal control module, and the steps of sequentially outputting a first clock signal to the first gate unit, outputting a second clock signal to the third gate unit, outputting a third clock signal to the second gate unit, and outputting a fourth clock signal to the fourth gate unit to generate corresponding gate driving signals to two adjacent rows of sub-pixels for driving and displaying include:
The refresh rate adjustment module generates a refresh rate control signal according to the refresh rate information, and the time sequence control module generates a clock signal according to the refresh rate information;
The refresh rate control signal controls the communication or disconnection between the clock signal line and the grid driving unit, inputs a first clock signal, a second clock signal, a third clock signal and a fourth clock signal to the corresponding grid driving unit in a time-sharing manner, or simultaneously outputs the first clock signal to the first grid driving unit and the third grid driving unit and outputs the third clock signal to the second grid driving unit and the fourth grid unit, so that the picture display with different refresh rates is realized;
Wherein the rising edge time of the first clock signal is earlier than the rising edge of the third clock signal.
Optionally, the clock signal control module includes a first control circuit and a second control circuit, the first control circuit includes a first control switch and a second control switch, the second control circuit includes a third control switch and a fourth control switch, control ends of the first control switch and the second control switch are connected with a first control signal line, an input end of the first switch is connected with the first clock signal line, an output end of the first switch is respectively connected with an output end of the third control switch and a third gate driving unit, an input end of the second control switch is connected with the third clock signal line, and an output end of the second control switch is respectively connected with an output end of the fourth control switch and the fourth gate driving unit; the control ends of the third control switch and the fourth control switch are connected with a second control signal line, the input end of the third switch is connected with the second clock signal line, the output end of the third switch is connected with a third grid driving unit, the input end of the fourth switch is connected with the fourth clock signal line, the output end of the fourth switch is connected with a fourth grid driving unit, the refresh rate control signal controls the communication or the disconnection between the clock signal line and the grid driving unit, a first clock signal is input in a time-sharing mode, a second clock signal, the third clock signal and the fourth clock signal are input to the corresponding grid driving units, or the first clock signal is output to the first grid driving unit and the third grid driving unit at the same time, the third clock signal is output to the second grid driving unit and the fourth grid driving unit, and the steps for realizing the picture display with different refresh rates comprise:
generating a set of refresh rate control signals of opposite level signals according to the refresh rate information, and respectively inputting the refresh rate control signals to the first control signal line and the second control signal line;
When a first control signal line receives a high level and a second control signal line receives a low level, the second control circuit is turned off, the first clock signal line simultaneously inputs a first clock signal to the first grid driving unit and a third grid driving unit, the third clock signal line simultaneously inputs a third clock signal to the second grid driving unit and a fourth grid driving unit, and the display panel realizes the picture display of a first refresh rate;
When a first control signal line receives a low level and a second control signal line receives a high level, the first control circuit is turned off, the first clock signal line inputs a first clock signal to the first grid driving unit, the second clock signal line inputs a second clock signal to the third grid driving unit, the third clock signal line inputs a third clock signal to the second grid driving unit, the fourth clock signal line inputs a fourth clock signal to the fourth grid driving unit, and the display panel realizes the picture display of a second refresh rate;
wherein the value of the first refresh rate is twice the value of the second refresh rate.
Optionally, the display panel includes a timing control module, the timing control generates a clock signal to the clock signal line, when a first control signal line receives a high level and a second control signal line receives a low level, the first control circuit is turned on, the second control circuit is turned off, the first clock signal line simultaneously inputs a first clock signal to the first gate driving unit and the third gate driving unit, and the third clock signal line simultaneously inputs a third clock signal to the second gate driving unit and the fourth gate driving unit, and the step of implementing the display of the first refresh rate of the display panel includes:
The timing control module only generates the first clock signal and the third clock signal after receiving the refresh rate control signal.
Optionally, the refresh rate adjustment module generates a refresh rate control signal according to the refresh rate information, and the step of generating the clock signal by the timing control module according to the refresh rate information includes:
The refresh rate information is generated according to the display picture of the next frame;
The refresh rate control signal controls the connection or disconnection between the clock signal line and the gate driving unit, inputs the first clock signal, the second clock signal, the third clock signal and the fourth clock signal to the corresponding gate driving unit in a time sharing manner, or outputs the first clock signal to the first gate driving unit and the third gate driving unit at the same time, and outputs the third clock signal to the second gate driving unit and the fourth gate unit, so that the steps of realizing the picture display with different refresh rates comprise:
when the next frame is a game interface or a video picture, generating first refresh rate information, generating a first refresh rate control signal according to the first refresh rate information, controlling the first clock signal line to simultaneously input a first clock signal to the first grid driving unit and a third grid driving unit, and simultaneously inputting a third clock signal to the second grid driving unit and a fourth grid driving unit by the third clock signal line, wherein the display panel realizes picture display at a first refresh rate;
When the next frame is a text picture, generating second refresh rate information, generating a second refresh rate control signal according to the second refresh rate information, controlling the first clock signal line to input a first clock signal to the first grid driving unit, the second clock signal line to input a second clock signal to the third grid driving unit, the third clock signal line to input a third clock signal to the second grid driving unit, and the fourth clock signal line to input a fourth clock signal to the fourth grid driving unit, wherein the display panel realizes picture display of a second refresh rate.
Compared with the DRD display panel scheme that single-color display cannot be realized in a DLG mode, the application provides a novel driving circuit, wherein clock signal lines connected with scanning lines corresponding to two adjacent rows of sub-pixels are exchanged, a first scanning line corresponding to a current row of sub-pixels is connected with a first clock signal line through a first grid driving unit, and a second scanning line corresponding to the current row of sub-pixels is connected with a third clock signal line through a first grid driving unit; the first scanning line corresponding to the next row of sub-pixels is connected with the second clock signal line through the third grid driving unit, the second scanning line corresponding to the next row of sub-pixels is connected with the fourth clock signal line through the fourth grid driving unit, and the odd-numbered column pixels of the first row of sub-pixels and the odd-numbered column pixels of the second sub-pixels are the same in color, so that after the first clock signal is input to the odd-numbered column pixels of the first row of sub-pixels, the second clock signal is output to the odd-numbered column pixels of the second row of pixels, and at the moment, even though the input gray scale is the same, single-color display can be realized, any signal does not need to be changed, and the method is very simple and convenient.
Drawings
The accompanying drawings, which are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the present application, from which other drawings can be obtained without inventive effort for a person skilled in the art, in which:
Fig. 1 is a schematic diagram of a cascade structure of a gate driving circuit of a display panel according to a first embodiment of the present application;
Fig. 2 is a schematic diagram of a cascade structure of gate driving circuits of a display panel according to a second embodiment of the present application;
Fig. 3 is a schematic diagram of a cascade structure of gate driving circuits of a display panel according to a third embodiment of the present application;
FIG. 4 is a timing diagram of refresh rate switching of a display panel according to a third embodiment of the present application;
fig. 5 is a schematic diagram of a cascade structure of gate driving circuits of a display panel according to a fourth embodiment of the present application;
fig. 6 is a schematic flow chart of a driving method of a display panel according to a fifth embodiment of the present application;
fig. 7 is a flowchart of a driving method of a display panel according to a sixth embodiment of the present application;
fig. 8 is a schematic flow chart of a driving method of a display panel according to a seventh embodiment of the present application;
fig. 9 is a schematic flow chart of a driving method of a display panel according to an eighth embodiment of the application.
100 Parts of a display panel; 110. a sub-pixel; 120. a scanning line; 121. a first scan line; 122. a second scanning line; 130. a gate driving unit; 131. a first gate driving unit; 132. a second gate driving unit; 133. a third gate driving unit; 134. a fourth gate driving unit; 140. a clock signal line; 141. a first clock signal line; 142. a second clock signal line; 143. a third clock signal line; 144. a fourth clock signal line; 150. a refresh rate adjustment module; 160. a timing control module; 170. a clock signal control module; 180. a first control circuit; 181. a first control switch; 182. a second control switch; 183. a first control signal line; 190. a second control circuit; 191. a third control switch; 192. a fourth control switch; 193. a second control signal line; 200. a protection circuit; 210. a fifth control switch; 220. and a sixth control switch.
Detailed Description
It is to be understood that the terminology used herein, the specific structural and functional details disclosed are merely representative for the purpose of describing particular embodiments, but that the application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
The application is described in detail below with reference to the attached drawings and alternative embodiments.
As shown in fig. 1, as a first embodiment of the present application, a display panel 100 is disclosed, wherein the display panel 100 is divided into a plurality of rows of sub-pixels 110 along a data line direction, each row of sub-pixels 110 is correspondingly provided with two scanning lines 120, the two scanning lines 120 are respectively a first scanning line 121 and a second scanning line 122, the first scanning line 121 is connected with odd columns of sub-pixels 110, the second scanning line 122 is connected with even columns of sub-pixels 110, the same columns of sub-pixels 110 in each row of sub-pixels 110 have the same color, and each data line is connected with two sub-pixels 110 with two adjacent columns and different colors; four gate driving units 130 and four clock signal lines 140 are correspondingly arranged on two adjacent rows of sub-pixels 110, the four gate driving units 130 are respectively a first gate driving unit 131, a second gate driving unit 132, a third gate driving unit 133 and a fourth gate driving unit 134, the four clock signal lines 140 are respectively a first clock signal line 141, a second clock signal line 142, a third clock signal line 143 and a fourth clock signal line 144, and rising edge moments of clock signals corresponding to the first clock signal line 141, the second clock signal line 142, the third clock signal line 143 and the fourth clock signal line 144 are sequentially arranged from early to late; the rising edge time of the clock signal corresponding to the current clock signal line 140 is earlier than the rising edge time of the clock signal corresponding to the next clock signal line 140, the falling edge time of the clock signal corresponding to the current clock signal line 140 is earlier than the falling edge time of the clock signal corresponding to the next clock signal line 140, and the pulse widths of the clock signals corresponding to different clock signal lines 140 are consistent.
The first scan line 121 corresponding to the current row of sub-pixels 110 is connected to the first clock signal line 141 through the first gate driving unit 131, and the second scan line 122 corresponding to the current row of sub-pixels 110 is connected to the third clock signal line 143 through the first gate driving unit 131; the first scan line 121 corresponding to the next row of sub-pixels 110 is connected to the second clock signal line 142 through the third gate driving unit 133, and the second scan line 122 corresponding to the next row of sub-pixels 110 is connected to the fourth clock signal line 144 through the fourth gate driving unit 134.
The application does not add extra data lines or scanning lines 120, and the clock signal CK at the common line is rearranged in the panel design; with two adjacent rows of sub-pixels 110 as a group, there is no common pixel row between the groups, that is, the first row of sub-pixels 110 and the second row of sub-pixels 110 are as a group, the third row of sub-pixels 110 and the fourth row of sub-pixels 110 are as a group, the fifth row of sub-pixels 110 and the sixth row of sub-pixels 110 are as a group, and so on; the even-numbered scanning lines 120 of the first row of sub-pixels 110 in each group are exchanged with the odd-numbered scanning lines 120 of the second sub-pixels 110, the second scanning lines 122 corresponding to the current row of sub-pixels 110 are connected with the third clock signal lines 143 through the first gate driving units 131, the first scanning lines 121 corresponding to the next row of sub-pixels 110 are connected with the second clock signal lines 142 through the third gate driving units 133, so that two adjacent sub-pixels 110 with different colors in the same row of sub-pixels 110 receive different clock signals, even if the same gray scale is received, the display of a monochromatic picture can be realized, and the problem that the DRD display panel 100 can not display RGB monochromatic pictures due to the fact that the same data line of the adjacent row is connected with different color pixels, and the two different color pixels in DLG mode can not display the same gray scale, and the display panel 100 can not normally display the color.
As shown in fig. 2, as a further refinement of the first embodiment, in the DRD display panel 100 capable of implementing monochromatic display in the DLG mode, the refresh rate may also be changed, the DRD may implement monochromatic display when the DLG is turned on, switching between Normal and DLG timing may be automatically performed, and the DLG timing may be automatically switched to high-speed video in different videos.
Specifically, the display panel 100 includes a refresh rate adjustment module 150, a clock signal control module 170, and a timing control module 160, where the clock signal control module 170 is connected to the refresh rate adjustment module 150 and the timing control module 160, the refresh rate adjustment module 150 generates a refresh rate control signal according to refresh rate information, the timing control module 160 generates a clock signal according to refresh rate information, a first output end of the refresh rate adjustment module 150 is connected to the clock signal line 140 and outputs a corresponding clock signal to the clock signal line 140, the clock signal control module 170 is disposed between the gate driving unit 130 and the clock signal line 140, and a second output end of the refresh rate adjustment module 150 is connected to the clock signal control module 170 and outputs a refresh rate control signal to control communication between the clock signal line 140 and the gate driving unit 130, so as to implement display of pictures with different refresh rates.
The clock signal control module 170 may control the corresponding clock signals to be input to different gate driving units 130, for example, the refresh rate control signal generated by the refresh rate adjustment module 150 controls the connection or disconnection between the clock signal line 140 and the gate driving unit 130, and time-sharing inputs the first clock signal, the second clock signal, the third clock signal and the fourth clock signal to the corresponding first gate driving unit 131, the second gate driving unit 132, the third gate driving unit 133 and the fourth gate driving unit 134, so as to implement low-brush display; or first outputs the first clock signal to the first gate driving unit 131 and the third gate driving unit 133 at the same time, and then outputs the third clock signal to the second gate driving unit 132 and the fourth gate unit, so as to realize high-brush display.
As shown in fig. 3 and fig. 4, as a third embodiment of the present application, which is a further limitation and improvement of the above embodiment, the clock signal control module 170 includes a first control circuit 180 and a second control circuit 190, the first control circuit 180 includes a first control switch 181 and a second control switch 182, the second control circuit 190 includes a third control switch 191 and a fourth control switch 192, control ends of the first control switch 181 and the second control switch 182 are connected to a first control signal line 183, an input end of the first switch is connected to a first clock signal line 141, an output end of the first switch is connected to an output end of the third control switch 191 and the third gate driving unit 133, respectively, an input end of the second control switch 182 is connected to a third clock signal line 143, and an output end of the second control switch 192 is connected to an output end of the fourth control switch 192 and the fourth gate driving unit 134, respectively; the control ends of the third control switch 191 and the fourth control switch 192 are connected to a second control signal line 193, the input end of the third switch is connected to the second clock signal line 142, the output end of the third switch is connected to the third gate driving unit 133, the input end of the fourth switch is connected to the fourth clock signal line 144, and the output end of the fourth switch is connected to the fourth gate driving unit 134.
Taking six rows of sub-pixels 110 as an example, each row of sub-pixels 110 corresponds to two scanning lines 120, each scanning line 120 is connected with one gate driving unit 130, six rows of sub-pixels 110 always correspond to twelve gate driving units 130, each row of gate driving units 130 is respectively connected with different clock signal lines 140, the display panel 100 comprises a plurality of gate driving units 130, the first gate driving unit 131 to the fourth gate driving unit 134 simultaneously receive frame start signals, output ends of the first gate driving unit 131 to the fourth gate driving unit are respectively connected with start ends of the seventh gate driving unit 130 to the eleventh gate unit, and output ends of the ninth gate driving unit 130 to the twelfth gate driving unit are respectively connected with reset ends of the first gate driving unit 131 to the fourth gate driving unit 134; at the time of high brushing, the capacitance load of the scanning line 120 is large, the number of the CKs of the scanning line 120 can be increased to 12 CKs to drive and reduce the load of the scanning line 120, and the scheme is applicable to the number of 6 CKs of the scanning line 120.
As shown in fig. 5, as a further improvement of the third embodiment of the present application, the display panel 100 includes a protection circuit 200, where the protection circuit 200 includes a fifth control switch 210 and a sixth control switch 220, an input end and a control end of the fifth control switch 210 are connected to the first control signal line 183, and an output end is connected to a control end of the first control switch 181; the input end and the control end of the sixth control switch 220 are connected to the first control signal line 183, the output end is connected to the control end of the second control switch 182, and the fifth control switch 210 and the sixth control switch 220 are correspondingly disposed before the first control switch 181 and the second control switch 182, so that when the high brush and the low brush are switched, the loss of the clock signal through the first control switch 181 and the second control switch 182 can be reduced, and the service lives of the first control switch 181 and the second control switch 182 can be prolonged.
Further, the display panel 100 further includes a first storage circuit and a second storage circuit, where the first storage circuit includes a first storage capacitor, the second storage circuit includes a second storage capacitor, one end of the first storage capacitor is connected to the control end of the first control switch 181, one end of the first storage capacitor is connected between the output end of the third control switch 191 and the third gate driving unit 133, one end of the second storage capacitor is connected to the control end of the second control switch 182, one end of the second storage capacitor is connected between the output end of the fourth control switch 192 and the fourth gate driving unit 134, and a storage capacitor is set to store charges, so that the threshold offset of the first control switch and the second control switch is reduced, thereby reducing the loss of the control switch.
As a fifth embodiment of the present application, as shown in fig. 6, there is disclosed a driving method of a display panel for driving the display panel according to any one of the above embodiments, the driving method comprising the steps of:
s1: outputting a frame start signal to first to fourth gate driving units corresponding to two adjacent rows of sub-pixels; and
S2: sequentially outputting a first clock signal to the first grid unit, a second clock signal to the third grid unit, a third clock signal to the second grid unit, and a fourth clock signal to the fourth grid unit to generate corresponding grid driving signals to two adjacent rows of sub-pixels for driving display.
Since the same data line of adjacent rows of the DRD display panel is connected to different color pixels, and the two different color pixels in DLG mode display the same gray level, and cannot display RGB single color images, referring to fig. 1, the clock signal line 140, which is connected to the scan line 120 corresponding to the pixel of the current row and the scan line 120 corresponding to the sub-pixel 110 of the next row, is exchanged, the second scan line 122 corresponding to the sub-pixel 110 of the current row is connected to the third clock signal line 143 through the first gate driving unit 131, the first scan line 121 corresponding to the sub-pixel 110 of the next row is connected to the second clock signal line 142 through the third gate driving unit 133, so that the adjacent two sub-pixels 110 of different colors in the sub-pixel 110 of the same row receive different clock signals, and even if the same gray level is received, the display of the single color images can be realized.
Further, referring to fig. 7, as a further refinement of the fifth embodiment of the present application, referring to fig. 1 to 4, the display panel 100 includes a refresh rate adjustment module 150, a clock signal control module 170, and a timing control module 160, the clock signal control module 170 is respectively connected to the refresh rate adjustment module 150 and the timing control module 160, a first output terminal of the refresh rate adjustment module 150 is connected to the clock signal line 140, the clock signal control module 170 is disposed between the gate driving unit 130 and the clock signal line 140, a second output terminal of the refresh rate adjustment module 150 is connected to the clock signal control module 170, and the step S2 includes:
s21: the refresh rate adjustment module generates a refresh rate control signal according to the refresh rate information, and the time sequence control module generates a clock signal according to the refresh rate information;
s22: the refresh rate control signal controls the communication or disconnection between the clock signal line and the grid driving unit, inputs a first clock signal, a second clock signal, a third clock signal and a fourth clock signal to the corresponding grid driving unit in a time-sharing manner, or simultaneously outputs the first clock signal to the first grid driving unit and the third grid driving unit and outputs the third clock signal to the second grid driving unit and the fourth grid unit, so that the picture display with different refresh rates is realized;
Wherein the rising edge time of the first clock signal is earlier than the rising edge of the third clock signal.
In this embodiment, the refresh rate adjustment module 150 can control the generation of the timing control signal output by the timing control module 160, and can also control the connection between the clock signal line 140 and the gate driving unit 130 by controlling the on or off of the clock signal control module 170, so as to change the refresh rate, and the DRD can realize monochromatic display when the DLG is turned on, automatically switch the Normal and DLG timings, and automatically switch the DLG timings in different videos to achieve high brushing.
As shown in fig. 8, as a seventh embodiment of the present application, further refinement and improvement of the fifth embodiment is provided, and the step S21 includes:
S211: the refresh rate information is generated according to the display picture of the next frame;
The step S22 includes:
S221: when the next frame is a game interface or a video picture, generating first refresh rate information, generating a first refresh rate control signal according to the first refresh rate information, controlling the first clock signal line to simultaneously input a first clock signal to the first grid driving unit and a third grid driving unit, and simultaneously inputting a third clock signal to the second grid driving unit and a fourth grid driving unit by the third clock signal line, wherein the display panel realizes picture display at a first refresh rate;
S222: when the next frame is a text picture, generating second refresh rate information, generating a second refresh rate control signal according to the second refresh rate information, controlling the first clock signal line to input a first clock signal to the first grid driving unit, the second clock signal line to input a second clock signal to the third grid driving unit, the third clock signal line to input a third clock signal to the second grid driving unit, and the fourth clock signal line to input a fourth clock signal to the fourth grid driving unit, wherein the display panel realizes picture display of a second refresh rate.
Referring to fig. 3, 4 and 7, when the next frame is high-brushing, the pulse width of the first clock signal is reduced by half compared with the original pulse width, and the first clock signal is simultaneously input to the first gate driving unit 131 and the third gate driving unit 133, and after the high level of the first clock signal is finished, that is, when the first clock signal has a falling edge, the third clock signal line 143 simultaneously inputs the third clock signal to the second gate driving unit 132 and the fourth gate driving unit 134, wherein the pulse width of the third clock signal is identical to the pulse width of the first clock signal; at this time, the timing control chip does not generate the second clock signal and the fourth clock signal.
As shown in fig. 9, as a further refinement and improvement of the fifth embodiment of the present application, referring to fig. 3, fig. 4 and fig. 8, the clock signal control module 170 includes a first control circuit 180 and a second control circuit 190, the first control circuit 180 includes a first control switch 181 and a second control switch 182, the second control circuit 190 includes a third control switch 191 and a fourth control switch 192, the control ends of the first control switch 181 and the second control switch 182 are connected to a first control signal line 183, the input end of the first switch is connected to a first clock signal line 141, the output end of the first switch is connected to the output end of the third control switch 191 and the third gate driving unit 133, the input end of the second control switch 182 is connected to the third clock signal line 143, and the output end of the second control switch 182 is connected to the output end of the fourth control switch 192 and the fourth gate driving unit 134, respectively; the control ends of the third control switch 191 and the fourth control switch 192 are connected to the second control signal line 193, the input end of the third switch is connected to the second clock signal line 142, the output end of the third switch is connected to the third gate driving unit 133, the input end of the fourth switch is connected to the fourth clock signal line 144, and the output end of the fourth switch is connected to the fourth gate driving unit 134, and the step S22 includes:
S221': generating a set of refresh rate control signals of opposite level signals according to the refresh rate information, and respectively inputting the refresh rate control signals to the first control signal line and the second control signal line;
S222': when a first control signal line receives a high level and a second control signal line receives a low level, the second control circuit is turned off, the first clock signal line simultaneously inputs a first clock signal to the first grid driving unit and a third grid driving unit, the third clock signal line simultaneously inputs a third clock signal to the second grid driving unit and a fourth grid driving unit, and the display panel realizes the picture display of a first refresh rate;
S223': when a first control signal line receives a low level and a second control signal line receives a high level, the first control circuit is turned off, the first clock signal line inputs a first clock signal to the first grid driving unit, the second clock signal line inputs a second clock signal to the third grid driving unit, the third clock signal line inputs a third clock signal to the second grid driving unit, the fourth clock signal line inputs a fourth clock signal to the fourth grid driving unit, and the display panel realizes the picture display of a second refresh rate;
wherein the value of the first refresh rate is twice the value of the second refresh rate.
In addition, the timing control generates a clock signal to the clock signal line 140, the second control circuit 190 is turned off when the first control signal line 183 receives a high level and the second control signal line 193 receives a low level, the first clock signal line 141 simultaneously inputs a first clock signal to the first and third gate driving units 131 and 133, the third clock signal line 143 simultaneously inputs a third clock signal to the second and fourth gate driving units 132 and 134, and the display panel 100 implements a picture display of a first refresh rate, the steps including:
the timing control module 160 generates only the first clock signal and the third clock signal after receiving the refresh rate control signal.
The timing control module 160 generates the first clock signal, the second clock signal, the third clock signal and the fourth clock signal according to the refresh rate information and turns on the corresponding second control circuit 190 to output to the corresponding gate driving unit 130, and the timing control module 160 generates the first clock signal and the third clock signal according to the refresh rate information and turns on the corresponding first control circuit 180, turns off the second control circuit 190, outputs the first clock signal to the first gate driving unit 131 and the third gate driving unit 133, and outputs the third clock signal to the corresponding second gate driving unit 132 and the fourth gate driving unit 134, and the corresponding second clock signal line 142 and the fourth clock signal line 144 do not need to receive the corresponding clock signal because the second control circuit 190 is turned off and the second gate driving unit 132 and the third gate driving unit 133 have already received the clock signal, so the timing control module 160 may not generate the corresponding second clock signal and the fourth clock signal to the second clock signal line 142 and the fourth clock signal line 144.
It should be noted that, the limitation of each step in the present solution is not to be considered as limiting the sequence of steps on the premise of not affecting the implementation of the specific solution, and the steps written in the previous step may be executed before, or executed after, or even executed simultaneously, so long as the implementation of the present solution is possible, all the steps should be considered as falling within the protection scope of the present application.
It should be noted that, the inventive concept of the present application can form a very large number of embodiments, but the application documents are limited in space and cannot be listed one by one, so that on the premise of no conflict, the above-described embodiments or technical features can be arbitrarily combined to form new embodiments, and after the embodiments or technical features are combined, the original technical effects will be enhanced.
The technical scheme of the application can be widely applied to driving circuits of various display panels, such as a driving circuit of a TN (TWISTED NEMATIC ) display panel, a driving circuit of an IPS (In-PLANE SWITCHING ) display panel, a driving circuit of a VA (VERTICAL ALIGNMENT ) display panel, a driving circuit of an MVA (Multi-Domain VERTICAL ALIGNMENT, multi-quadrant vertical alignment) display panel, and can be applied to driving circuits of other types of display panels, such as driving circuits of OLED (Organic Light-Emitting Diode) display panels.
The above description of the application in connection with specific alternative embodiments is further detailed and it is not intended that the application be limited to the specific embodiments disclosed. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the application, and these should be considered to be within the scope of the application.
Claims (10)
1. The display panel is characterized in that the display panel is divided into a plurality of rows of sub-pixels along the direction of a data line, each row of sub-pixels is correspondingly provided with two scanning lines, the two scanning lines are a first scanning line and a second scanning line respectively, the first scanning line is connected with odd columns of sub-pixels, the second scanning line is connected with even columns of sub-pixels, the same columns of sub-pixels in each row of sub-pixels have the same color, and each data line is connected with two adjacent columns of sub-pixels with different colors;
Four grid driving units and four clock signal lines are correspondingly arranged on two adjacent rows of sub-pixels, wherein the four grid driving units are respectively a first grid driving unit, a second grid driving unit, a third grid driving unit and a fourth grid driving unit, and the four clock signal lines are respectively a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line;
The first scanning line corresponding to the current row of sub-pixels is connected with a first clock signal line through a first grid driving unit, and the second scanning line corresponding to the current row of sub-pixels is connected with a third clock signal line through the first grid driving unit; the first scanning line corresponding to the next row of sub-pixels is connected with the second clock signal line through the third grid driving unit, and the second scanning line corresponding to the next row of sub-pixels is connected with the fourth clock signal line through the fourth grid driving unit.
2. The display panel of claim 1, wherein the display panel comprises a refresh rate adjustment module, a clock signal control module, and a timing control module, the clock signal control module is respectively connected with the refresh rate adjustment module and the timing control module, the refresh rate adjustment module generates a refresh rate control signal according to refresh rate information, the timing control module generates a clock signal according to refresh rate information, a first output end of the refresh rate adjustment module is connected with the clock signal line and outputs a corresponding clock signal to the clock signal line, the clock signal control module is disposed between the gate driving unit and the clock signal line, a second output end of the refresh rate adjustment module is connected with the clock signal control module and outputs a refresh rate control signal to control communication between the clock signal line and the gate driving unit, and display of pictures with different refresh rates is achieved.
3. The display panel according to claim 2, wherein the clock signal control module comprises a first control circuit and a second control circuit, the first control circuit comprises a first control switch and a second control switch, the second control circuit comprises a third control switch and a fourth control switch, the control ends of the first control switch and the second control switch are connected with a first control signal line, the input end of the first switch is connected with a first clock signal line, the output end of the first switch is respectively connected with the output end of the third control switch and a third gate driving unit, the input end of the second control switch is connected with a third clock signal line, and the output end of the second control switch is respectively connected with the output end of the fourth control switch and the fourth gate driving unit; the control ends of the third control switch and the fourth control switch are connected with a second control signal line, the input end of the third switch is connected with the second clock signal line, the output end of the third switch is connected with a third grid driving unit, the input end of the fourth switch is connected with the fourth clock signal line, and the output end of the fourth switch is connected with a fourth grid driving unit.
4. A display panel as claimed in claim 3, characterized in that the display panel comprises a protection circuit comprising a fifth control switch and a sixth control switch, the input and control terminals of the fifth control switch being connected to the first control signal line, the output terminal being connected to the control terminal of the first control switch; the input end and the control end of the sixth control switch are connected with the first control signal line, and the output end is connected with the control end of the second control switch.
5. The display panel according to claim 4, further comprising a first memory circuit and a second memory circuit, wherein one end of the first memory circuit is connected to the control end of the first control switch, one end is connected between the output end of the third control switch and the third gate driving unit, one end of the second memory circuit is connected to the control end of the second control switch, and one end is connected between the output end of the fourth control switch and the fourth gate driving unit.
6. A driving method of a display panel for driving the display panel according to any one of claims 1 to 5, characterized in that the driving method comprises the steps of:
outputting a frame start signal to first to fourth gate driving units corresponding to two adjacent rows of sub-pixels; and
Sequentially outputting a first clock signal to the first grid unit, a second clock signal to the third grid unit, a third clock signal to the second grid unit, and a fourth clock signal to the fourth grid unit to generate corresponding grid driving signals to two adjacent rows of sub-pixels for driving display.
7. The method for driving a display panel according to claim 6, wherein the display panel includes a refresh rate adjustment module, a clock signal control module, and a timing control module, the clock signal control module is respectively connected to the refresh rate adjustment module and the timing control module, a first output terminal of the refresh rate adjustment module is connected to the clock signal line, the clock signal control module is disposed between the gate driving unit and the clock signal line, a second output terminal of the refresh rate adjustment module is connected to the clock signal control module, the steps of sequentially outputting a first clock signal to the first gate unit, a second clock signal to the third gate unit, a third clock signal to the second gate unit, and a fourth clock signal to the fourth gate unit to generate a corresponding gate driving signal to two adjacent rows of sub-pixels for driving display include:
The refresh rate adjustment module generates a refresh rate control signal according to the refresh rate information, and the time sequence control module generates a clock signal according to the refresh rate information;
The refresh rate control signal controls the communication or disconnection between the clock signal line and the grid driving unit, inputs a first clock signal, a second clock signal, a third clock signal and a fourth clock signal to the corresponding grid driving unit in a time-sharing manner, or simultaneously outputs the first clock signal to the first grid driving unit and the third grid driving unit and outputs the third clock signal to the second grid driving unit and the fourth grid unit, so that the picture display with different refresh rates is realized;
Wherein the rising edge time of the first clock signal is earlier than the rising edge of the third clock signal.
8. The driving method of a display panel according to claim 7, wherein the clock signal control module comprises a first control circuit and a second control circuit, the first control circuit comprises a first control switch and a second control switch, the second control circuit comprises a third control switch and a fourth control switch, control ends of the first control switch and the second control switch are connected with a first control signal line, an input end of the first switch is connected with the first clock signal line, an output end of the first switch is connected with an output end of the third control switch and a third gate driving unit respectively, an input end of the second control switch is connected with the third clock signal line, and an output end of the second control switch is connected with an output end of the fourth control switch and the fourth gate driving unit respectively; the control ends of the third control switch and the fourth control switch are connected with a second control signal line, the input end of the third switch is connected with the second clock signal line, the output end of the third switch is connected with a third grid driving unit, the input end of the fourth switch is connected with the fourth clock signal line, and the output end of the fourth switch is connected with a fourth grid driving unit;
The refresh rate control signal controls the connection or disconnection between the clock signal line and the gate driving unit, inputs the first clock signal, the second clock signal, the third clock signal and the fourth clock signal to the corresponding gate driving unit in a time sharing manner, or outputs the first clock signal to the first gate driving unit and the third gate driving unit at the same time, and outputs the third clock signal to the second gate driving unit and the fourth gate unit, so that the steps of realizing the picture display with different refresh rates comprise:
generating a set of refresh rate control signals of opposite level signals according to the refresh rate information, and respectively inputting the refresh rate control signals to the first control signal line and the second control signal line;
When a first control signal line receives a high level and a second control signal line receives a low level, the second control circuit is turned off, the first clock signal line simultaneously inputs a first clock signal to the first grid driving unit and a third grid driving unit, the third clock signal line simultaneously inputs a third clock signal to the second grid driving unit and a fourth grid driving unit, and the display panel realizes the picture display of a first refresh rate;
When a first control signal line receives a low level and a second control signal line receives a high level, the first control circuit is turned off, the first clock signal line inputs a first clock signal to the first grid driving unit, the second clock signal line inputs a second clock signal to the third grid driving unit, the third clock signal line inputs a third clock signal to the second grid driving unit, the fourth clock signal line inputs a fourth clock signal to the fourth grid driving unit, and the display panel realizes the picture display of a second refresh rate;
wherein the value of the first refresh rate is twice the value of the second refresh rate.
9. The method of driving a display panel according to claim 8, wherein when the first control signal line receives a high level and the second control signal line receives a low level, the second control circuit is turned off and the first clock signal line simultaneously inputs a first clock signal to the first gate driving unit and a third clock signal to the second gate driving unit and a fourth gate driving unit, and the display panel realizes a picture display of a first refresh rate, the method comprising:
The timing control module only generates the first clock signal and the third clock signal after receiving the refresh rate control signal.
10. The method of driving a display panel according to claim 7, wherein the refresh rate adjustment module generates the refresh rate control signal according to the refresh rate information, and the timing control module generates the clock signal according to the refresh rate information comprises:
The refresh rate information is generated according to the display picture of the next frame;
The refresh rate control signal controls the connection or disconnection between the clock signal line and the gate driving unit, inputs the first clock signal, the second clock signal, the third clock signal and the fourth clock signal to the corresponding gate driving unit in a time sharing manner, or outputs the first clock signal to the first gate driving unit and the third gate driving unit at the same time, and outputs the third clock signal to the second gate driving unit and the fourth gate unit, so that the steps of realizing the picture display with different refresh rates comprise:
when the next frame is a game interface or a video picture, generating first refresh rate information, generating a first refresh rate control signal according to the first refresh rate information, controlling the first clock signal line to simultaneously input a first clock signal to the first grid driving unit and a third grid driving unit, and simultaneously inputting a third clock signal to the second grid driving unit and a fourth grid driving unit by the third clock signal line, wherein the display panel realizes picture display at a first refresh rate;
When the next frame is a text picture, generating second refresh rate information, generating a second refresh rate control signal according to the second refresh rate information, controlling the first clock signal line to input a first clock signal to the first grid driving unit, the second clock signal line to input a second clock signal to the third grid driving unit, the third clock signal line to input a third clock signal to the second grid driving unit, and the fourth clock signal line to input a fourth clock signal to the fourth grid driving unit, wherein the display panel realizes picture display of a second refresh rate.
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| US20230401991A1 (en) * | 2021-07-30 | 2023-12-14 | HKC Corporation Limited | Drive circuit for display panel and display device |
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| CN107016953A (en) * | 2017-05-22 | 2017-08-04 | 武汉天马微电子有限公司 | Display panel driving method, display panel and display device |
| US11367379B1 (en) * | 2021-03-15 | 2022-06-21 | Samsung Display Co., Ltd. | Display device and method of driving display device |
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