CN117690785A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN117690785A
CN117690785A CN202211032388.4A CN202211032388A CN117690785A CN 117690785 A CN117690785 A CN 117690785A CN 202211032388 A CN202211032388 A CN 202211032388A CN 117690785 A CN117690785 A CN 117690785A
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layer
gate
dielectric layer
forming
device region
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王蒙蒙
沈宇桐
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202211032388.4A priority Critical patent/CN117690785A/en
Priority to PCT/CN2022/134057 priority patent/WO2024040771A1/en
Publication of CN117690785A publication Critical patent/CN117690785A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A method for forming a semiconductor structure includes: forming a base, wherein the base comprises a substrate, the substrate is provided with a first device area and a second device area, the surface of the substrate is covered with a first gate dielectric layer, the surface of the substrate is covered with a second gate dielectric layer in the second device area, the thickness of the first gate dielectric layer is smaller than that of the second gate dielectric layer, and the surfaces of the first gate dielectric layer and the second gate dielectric layer are covered with high-K dielectric layers, wherein the second gate dielectric layer is formed by adopting a first photomask through a positive developing process or a negative developing process; removing the high-K dielectric layer in the second device region by adopting a first photomask through a negative development or positive development process, and exposing the second gate dielectric layer; and forming a first grid structure on the surface of the high-K dielectric layer in the first device region, and forming a second grid structure on the surface of the second grid dielectric layer in the second device region. The forming method has simple process, can reduce cost and ensures the stability of the device.

Description

Semiconductor structure and forming method thereof
Technical Field
The present disclosure relates to the field of integrated circuits, and more particularly, to a semiconductor structure and a method of forming the same.
Background
A dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor device commonly used in electronic equipment such as a computer, and is composed of a plurality of memory cells each typically including a transistor and a capacitor. The gate electrode of the transistor is electrically connected with the word line, the source electrode is electrically connected with the bit line, and the drain electrode is electrically connected with the capacitor, and the word line voltage on the word line can control the on and off of the transistor, so that the data information stored in the capacitor can be read through the bit line or written into the capacitor.
With the shrinking of DRAM dimensions, HKMG (High-K Metal Gate) technology is introduced into the process of DRAM in order to improve the leakage of transistors and to improve the reliability of devices. HKMG technology includes First Gate (First Gate) technology and Last Gate (Last Gate) technology. In a thick-oxide device, the existence of a thicker Gate dielectric material affects the dipole diffusion of the high-K dielectric layer, so that the work function metal cannot play a good role in adjusting the threshold voltage, and the threshold voltage of the Gate of the thick-oxide device is too high, thereby degrading the performance of the thick-oxide device.
Disclosure of Invention
The technical problem to be solved by the present disclosure is to provide a semiconductor structure and a forming method thereof, which can improve the stability of a semiconductor device.
In order to solve the above-mentioned problems, an embodiment of the present disclosure provides a method for forming a semiconductor structure, including: forming a base, wherein the base comprises a substrate, the substrate is provided with a first device region and a second device region, a first grid dielectric layer is covered on the surface of the substrate in the first device region, a second grid dielectric layer is covered on the surface of the substrate in the second device region, the thickness of the first grid dielectric layer is smaller than that of the second grid dielectric layer, and high-K dielectric layers are covered on the surfaces of the first grid dielectric layer and the second grid dielectric layer, wherein the second grid dielectric layer is formed by adopting a first photomask through a positive developing process or a negative developing process; removing the high-K dielectric layer in the second device region by adopting the first photomask through a negative development or positive development process, and exposing the second gate dielectric layer; and forming a first grid structure on the surface of the high-K dielectric layer in the first device region, and forming a second grid structure on the surface of the second grid dielectric layer in the second device region.
In one embodiment, the step of forming the substrate includes: providing the substrate; forming a second gate dielectric layer on the surface of the substrate in the second device region; forming a first gate dielectric layer on the surface of the substrate in the first device region; and forming a high-K dielectric layer, wherein the high-K dielectric layer covers the first gate dielectric layer and the second gate dielectric layer.
In one embodiment, the step of forming a second gate dielectric layer on the surface of the substrate in the second device region includes: forming a second gate dielectric material layer on the substrate; forming a first mask layer on the second gate dielectric material layer in the second device region by adopting the first photomask through a positive developing process or a negative developing process; taking the first mask layer as shielding, removing the second gate dielectric material layer in the first device region, and taking the second gate dielectric material layer as the second gate dielectric layer in the second device region; and removing the first mask layer.
In one embodiment, the step of forming a first gate dielectric layer on the surface of the substrate in the first device region includes: and forming a first gate dielectric material layer, wherein the first gate dielectric material layer covers the surface of the substrate in the first device region, and the first gate dielectric material layer is used as the first gate dielectric layer.
In an embodiment, in the second device region, the first gate dielectric material layer further covers a surface of the second gate dielectric material layer, and the first gate dielectric material layer and the second gate dielectric material layer are used together as the second gate dielectric layer.
In an embodiment, in the second device region, the step of removing the high-K dielectric layer and exposing the second gate dielectric layer includes: forming a second mask layer on the surface of the high-K dielectric layer in the first device region by adopting the first photomask through a negative development or positive development process; taking the second mask layer as shielding, removing the high-K dielectric layer in the second device region, and exposing the second gate dielectric layer; and removing the second mask layer.
In an embodiment, before the step of removing the high-K dielectric layer, the method further includes: forming a protective layer on the surface of the high-K dielectric layer; in the step of removing the high-K dielectric layer, the protective layer is used for protecting the high-K dielectric layer in the first device region; the protective layer is removed prior to the step of forming the first gate structure.
In an embodiment, the first device region includes a first N-well region and a first P-well region, the second device region includes a second N-well region and a second P-well region, and the step of forming the substrate further includes: and forming a silicon germanium layer on the surface of the substrate in the first N well region, wherein the first gate dielectric layer covers the silicon germanium layer.
In an embodiment, the first gate structure includes a first NMOS transistor gate structure and a first PMOS transistor gate structure, the second gate structure includes a second NMOS transistor gate structure and a second PMOS transistor gate structure, and the forming the first gate structure and the second gate structure includes: and forming a first NMOS transistor gate structure in the first P well region, forming a first PMOS transistor gate structure in the first N well region, forming a second NMOS transistor gate structure in the second P well region, and forming a second PMOS transistor gate structure in the second N well region.
In one embodiment, the step of forming the first gate structure and the second gate structure comprises: forming an NMOS transistor metal gate layer in the first P well region and the second P well region; forming a PMOS transistor metal gate layer in the first N well region and the second N well region; forming a gate composite layer, wherein the gate composite layer covers the NMOS transistor metal gate layer and the PMOS transistor metal gate layer; and patterning the gate composite material layer, the NMOS transistor metal gate layer and the PMOS transistor metal gate layer to form the first NMOS transistor gate structure, the first PMOS transistor gate structure, the second NMOS transistor gate structure and the second PMOS transistor gate structure.
Embodiments of the present disclosure also provide a semiconductor structure, comprising: a substrate having a first device region and a second device region; in the first device region, a first gate dielectric layer covers the surface of the substrate; in the second device region, a second gate dielectric layer covers the surface of the substrate, and the thickness of the first gate dielectric layer is smaller than that of the second gate dielectric layer; the high-K dielectric layer covers the surface of the first gate dielectric layer; the first grid structure is positioned on the surface of the high-K dielectric layer; and the second grid structure is positioned on the surface of the second grid dielectric layer.
In an embodiment, the first device region includes a first N-well region and a first P-well region, the first gate structure includes a first NMOS transistor gate structure and a first PMOS transistor gate structure, the first NMOS transistor gate structure is disposed on the first P-well region, and the first PMOS transistor gate structure is disposed on the first N-well region; the second device region comprises a second N-well region and a second P-well region, the second gate structure comprises a second NMOS transistor gate structure and a second PMOS transistor gate structure, the second NMOS transistor gate structure is arranged on the second P-well region, and the second PMOS transistor gate structure is arranged on the second N-well region.
In an embodiment, in the first N-well region, the semiconductor structure further includes a silicon germanium layer, and the silicon germanium layer is disposed between the first gate dielectric layer and the substrate.
In an embodiment, the first NMOS transistor gate structure and the second NMOS transistor gate structure have the same structure, and the first PMOS transistor gate structure and the second PMOS transistor gate structure have the same structure.
In an embodiment, the first NMOS transistor gate structure and the second NMOS transistor gate structure each include an NMOS transistor metal gate layer and a first gate composite layer overlying the NMOS transistor metal gate layer; the first PMOS transistor gate structure and the second PMOS transistor gate structure each include a PMOS transistor metal gate layer and a second gate composite layer overlying the PMOS transistor metal gate layer.
According to the method for forming the semiconductor structure, after the high-K dielectric layer is formed, the high-K dielectric layer of the second device region where the second gate dielectric layer with larger thickness is located is removed, the second gate dielectric layer is only reserved as an isolation layer between the second gate structure and the substrate which are formed later, namely, the high-K dielectric layer does not exist in the second device region, the problem that the diffusion of dipoles of the high-K dielectric layer is affected due to the existence of the thicker second gate dielectric layer is avoided, the second gate structure can play a good role in adjusting threshold voltage, the threshold voltage of the second device region is prevented from being too high, and the stability of a semiconductor device of the second device region is improved. Meanwhile, the forming method provided by the embodiment of the disclosure does not affect the high-K dielectric layer of the first device region due to the removal of the high-K dielectric layer of the second device region, the high-K dielectric layer is still formed in the first device region with the thinner first gate dielectric layer, and stability of the semiconductor structure of the first device region is further ensured. In addition, the forming method provided by the embodiment of the disclosure adopts the first photomask to form the second gate dielectric layer through a positive developing process or a negative developing process, adopts the first photomask to remove the high-K dielectric layer in the second device region through the negative developing process or the positive developing process, namely adopts the same photomask to form the second gate dielectric layer and remove the high-K dielectric layer, has low cost and simple preparation process, can avoid the defect that the threshold voltage cannot be well regulated by the second gate structure of the second device region without complex process, and greatly improves the practicability of the semiconductor process.
According to the semiconductor structure provided by the embodiment of the disclosure, the high-K dielectric layer is arranged between the first grid structure and the substrate in the first device region (thin oxygen device region) so as to reduce leakage current of the first grid structure, and only the second grid dielectric layer with larger thickness is adopted as the isolation layer between the second grid structure and the substrate in the second device region (thick oxygen device region), and the high-K dielectric layer is not arranged, so that the problem of dipole diffusion of the high-K dielectric layer caused by too thick second grid dielectric layer is avoided while leakage current of the second grid structure is reduced, the second grid structure can play a good role in adjusting threshold voltage, threshold voltage of the second device region is prevented from being too high, and stability of the semiconductor device of the second device region is improved.
Drawings
Fig. 1 is a schematic step diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure;
fig. 2 to 14 are schematic views of a semiconductor structure formed by main steps of a forming method according to an embodiment of the present disclosure.
Detailed Description
Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. In describing embodiments of the present disclosure in detail, the schematic drawings are not necessarily to scale and are merely illustrative and are not intended to limit the scope of the disclosure. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication. The semiconductor structure described in the embodiments of the present disclosure may be, but is not limited to, a DRAM.
Fig. 1 is a schematic step diagram of a method for forming a semiconductor structure according to an embodiment of the disclosure, referring to fig. 1, the method includes: step S10, forming a base, wherein the base comprises a substrate, the substrate is provided with a first device area and a second device area, a first grid dielectric layer is covered on the surface of the substrate in the first device area, a second grid dielectric layer is covered on the surface of the substrate in the second device area, the thickness of the first grid dielectric layer is smaller than that of the second grid dielectric layer, and high-K dielectric layers are covered on the surfaces of the first grid dielectric layer and the second grid dielectric layer, wherein the second grid dielectric layer is formed by adopting a first photomask through a positive developing process or a negative developing process; step S11, removing the high-K dielectric layer in the second device area by adopting the first photomask through a negative development or positive development process, and exposing the second gate dielectric layer; and step S12, forming a first grid structure on the surface of the high-K dielectric layer in the first device region, and forming a second grid structure on the surface of the second grid dielectric layer in the second device region.
In the method for forming the semiconductor structure provided by the embodiment of the disclosure, after the high-K dielectric layer is formed, the high-K dielectric layer of the second device region where the second gate dielectric layer with larger thickness is located is removed, and only the second gate dielectric layer is reserved as the isolation layer between the second gate structure and the substrate which are formed subsequently, namely, the high-K dielectric layer does not exist in the second device region, and the problem that the diffusion of the dipole of the high-K dielectric layer is affected due to the existence of the thicker second gate dielectric layer is avoided, so that the second gate structure can play a role in adjusting the threshold voltage well, the threshold voltage of the second device region is avoided from being too high, and the stability of the semiconductor device of the second device region is improved. Meanwhile, the forming method provided by the embodiment of the disclosure does not affect the high-K dielectric layer of the first device region due to the removal of the high-K dielectric layer of the second device region, the high-K dielectric layer is still formed in the first device region with the thinner first gate dielectric layer, and stability of the semiconductor structure of the first device region is further ensured. The forming method provided by the embodiment of the disclosure adopts the first photomask to form the second gate dielectric layer through a positive developing process or a negative developing process, adopts the first photomask to remove the high-K dielectric layer in the second device region through the negative developing process or the positive developing process, namely adopts the same photomask to form the second gate dielectric layer and remove the high-K dielectric layer, has low cost and simple preparation process, can avoid the defect that the threshold voltage cannot be well regulated in the second gate structure of the second device region without complex process, and greatly improves the practicability of the semiconductor process.
The method for forming a semiconductor device according to an embodiment of the present disclosure is described in detail below with reference to fig. 1 to 14, where fig. 2 to 14 are schematic views of a semiconductor structure formed by main steps of the method for forming a semiconductor device according to an embodiment of the present disclosure.
Referring to fig. 1 and fig. 2 to fig. 7, in step S10, a base 200 is formed, the base 200 includes a substrate 201, the substrate 201 has a first device region A1 and a second device region A2, a first gate dielectric layer 210 is covered on the surface of the substrate 201 in the first device region A1, a second gate dielectric layer 220 is covered on the surface of the substrate 201 in the second device region A2, the thickness of the first gate dielectric layer 210 is smaller than the thickness of the second gate dielectric layer 220, and a high K dielectric layer 230 is covered on the surfaces of the first gate dielectric layer 210 and the second gate dielectric layer 220, wherein the second gate dielectric layer 220 is formed by adopting a first photomask through a positive developing or negative developing process.
The substrate 201 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, an SOI substrate, or the like; the substrate may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, silicon carbide, or the like, and may also be a stacked structure, such as a silicon/germanium-silicon stack, or the like; in addition, the substrate 201 may be a substrate after ion doping, may be P-doped, or may be N-doped; the substrate 201 may also have formed therein a plurality of peripheral devices such as field effect transistors, capacitors, inductors, and/or diodes, etc. In this embodiment, the substrate 201 is a silicon substrate, and may further include other device structures, such as a transistor structure, a metal wiring structure, etc., which are not illustrated because they are irrelevant to the present invention.
In this embodiment, the first device region A1 refers to a region where a first type transistor is formed, and the second device region A2 refers to a region where a second type transistor is formed. The first type of transistor may be a thin-oxide transistor and the second type of transistor may be a thick-oxide transistor. In some embodiments, the first type of transistor comprises a logic transistor and the second type of transistor comprises an input/output transistor.
In this embodiment, the first device region A1 includes a first N-well region 202 and a first P-well region 203, the second device region A2 includes a second N-well region 204 and a second P-well region 205, and the first N-well region 202, the first P-well region 203, the second N-well region 204 and the second P-well region 205 are isolated by a shallow trench isolation structure 300. Wherein the first and second N-well regions 202 and 204 may be formed by implanting arsenic and/or phosphorus ions into the substrate 201, and the first and second P-well regions 203 and 205 may be formed by implanting boron ions into the substrate 201.
The first gate dielectric layer 210 covers the surface of the substrate 201 only in the first device region A1, the second gate dielectric layer 220 covers the surface of the substrate 201 only in the second device region A2, and the high-K dielectric layer 230 covers both the first gate dielectric layer 210 and the second gate dielectric layer 220. That is, in the first device region A1, the first gate dielectric layer 210 is disposed on the surface of the substrate 201, the high-K dielectric layer 230 is covered on the surface of the first gate dielectric layer 210, the second gate dielectric layer 220 is covered on the surface of the substrate 201 in the second device region A2, and the high-K dielectric layer 230 is covered on the surface of the second gate dielectric layer 220.
In this embodiment, a sige layer 206 is formed on the surface of the substrate 201 in the first N-well region 202, and then the first gate dielectric layer 210 covers the surface of the sige layer 206 in the first device region A1 in the first N-well region 202.
As an example, the disclosed embodiments also provide a method of forming the substrate 200. The method comprises the following steps:
referring to fig. 2 to 5, the substrate 201 is provided, and a second gate dielectric layer 220 is formed on the surface of the substrate 201 in the second device region A2.
The present embodiment provides a method for forming the second gate dielectric layer 220. The concrete explanation is as follows:
referring to fig. 2, a second gate dielectric material layer 221 is formed on the substrate 201. The second gate dielectric material layer 221 covers not only the substrate 201 surface of the second device region A2 but also the substrate 201 surface of the first device region A1. The second gate dielectric material layer 221 is an oxide layer, including but not limited to silicon oxide or silicon oxynitride. In some embodiments, the second gate dielectric material layer 221 may be formed on the surface of the substrate 201 by thermal oxidation, chemical vapor deposition, atomic layer deposition, or the like.
In this embodiment, before forming the second gate dielectric material layer 221, a step of forming the sige layer 206 in the first N-well region 202 is further included. Wherein the silicon germanium layer may be formed by a chemical vapor deposition process or the like. In this embodiment, in the first N-well region 202, the second gate dielectric material layer 221 covers the surface of the sige layer 206.
Referring to fig. 3, a first mask layer 310 is formed on the second gate dielectric material layer 221 in the second device region A2 by a positive developing or negative developing process using the first photomask. The first mask layer 310 covers only the second gate dielectric material layer 221 of the second device region A2, and the surface of the second gate dielectric material layer 221 of the first device region A1 is exposed. The first mask layer 310 is a photoresist layer, and in some embodiments, a first photomask is used to retain the photoresist layer on the surface of the second gate dielectric material layer 221 of the second device region A2 through a positive developing process or a negative developing process, as the first mask layer 310. For example, in the present embodiment, the first mask layer 310 is formed by a positive developing process using the first photomask.
Referring to fig. 4, with the first mask layer 310 as a shielding layer, in the first device region A1, the second gate dielectric material layer 221 is removed, and in the second device region A2, the second gate dielectric material layer 221 is used as the second gate dielectric layer 220. In this step, an etching process is used to remove the second gate dielectric material layer 221, for example, a dry etching process. Since the first mask layer 310 only shields the second gate dielectric material layer 221 of the second device region A2, the second gate dielectric material layer 221 located in the second device region A2 is remained, and is removed as the second gate dielectric layer 220, and the second gate dielectric material layer 221 located in the first device region A1 is removed to expose the substrate 201 and the sige layer 206.
Referring to fig. 5, the first mask layer 310 is removed to expose the second gate dielectric layer 220. In this step, the first mask layer 310 may be removed using an ashing process or the like.
After forming the second gate dielectric layer 220, referring to fig. 6, a first gate dielectric layer 210 is formed on the surface of the substrate 201 in the first device region A1.
The present embodiment provides a method for forming the first gate dielectric layer 210. The concrete explanation is as follows:
Referring to fig. 6, a first gate dielectric material layer is formed, and in the first device region A1, the first gate dielectric material layer covers the surfaces of the substrate 201 and the sige layer 206, and the first gate dielectric material layer is used as the first gate dielectric layer 210. In this step, the first gate dielectric material layer may be formed on the surface of the substrate 201 by thermal oxidation, chemical vapor deposition, atomic layer deposition, or the like.
In this embodiment, the first gate dielectric material layer is formed only on the surface of the substrate 201 and the silicon germanium layer 206 of the first device region A1, but not on the surface of the second gate dielectric material layer 221 of the second device region A2, and then the thickness of the second gate dielectric material layer 221 formed in the step of forming the second gate dielectric material layer 221 (refer to fig. 2) is greater than that of the first gate dielectric material layer, so that the thickness of the finally formed second gate dielectric layer 220 is greater than that of the first gate dielectric layer 210.
It is appreciated that in other embodiments, in the second device region A2, the first gate dielectric material layer is further formed on the surface of the second gate dielectric material layer 221, and the first gate dielectric material layer and the second gate dielectric material layer 221 together serve as the second gate dielectric layer 220. Since the thickness of the second gate dielectric layer 220 is the sum of the thicknesses of the first gate dielectric material layer and the second gate dielectric material layer 221, it is ensured that the thickness of the second gate dielectric layer 220 is greater than the thickness of the first gate dielectric layer 210.
After forming the first gate dielectric layer 210, referring to fig. 7, a high-K dielectric layer 230 is formed, and the high-K dielectric layer 230 covers the first gate dielectric layer 210 and the second gate dielectric layer 220. The high-K dielectric layer 230 is made of a material having a dielectric constant greater than that of silicon dioxide, such as hafnium dioxide (HfO 2), hafnium silicon dioxide (HfSiO 2), hafnium silicon oxynitride (HfSiON), or the like. In this step, the high-K dielectric layer 230 may be formed by a chemical vapor deposition or an atomic layer deposition process.
With continued reference to fig. 1 and fig. 8 to fig. 10, in step S11, the high-K dielectric layer 230 is removed in the second device region A2 by using the first photomask through a negative developing process or a positive developing process, so as to expose the second gate dielectric layer 220. In this step, the high-K dielectric layer 230 in the second device region A2 is removed, leaving the high-K dielectric layer 230 in the first device region A1. Illustratively, in an embodiment of the present disclosure, the step of removing the high-K dielectric layer 230 includes:
referring to fig. 8, a second mask layer 320 is formed on the surface of the high-K dielectric layer 230 in the first device region A1 by using the first photomask through a negative developing or positive developing process. The second mask layer 320 covers only the high-K dielectric layer 230 of the first device region A1, and the surface of the high-K dielectric layer 230 of the second device region A2 is exposed. The second mask layer 320 is a photoresist layer, and in some embodiments, the photoresist layer located in the first device area A1 may be retained as the second mask layer 320 by negative development or positive development.
In the embodiment of the disclosure, the purpose of forming the second gate dielectric layer and removing the high-K dielectric layer can be achieved through the same first photomask, so that the cost is greatly reduced, and the preparation process is simplified. It will be appreciated that, since the first mask layer 310 and the second mask layer 320 are disposed at complementary positions, if the first mask layer 310 is formed by a positive developing process, the second mask layer 320 is formed by a negative developing process, and if the first mask layer 310 is formed by a negative developing process, the second mask layer 320 is formed by a positive developing process.
In this embodiment, before forming the second mask layer 320, the method further includes the following steps: and forming a protective layer 330 on the surface of the high-K dielectric layer 230. The protection layer 330 is used to protect the high-K dielectric layer 230 in the first device region A1 in a subsequent process, and the protection layer 330 may be a SiN layer or a SiON layer. In this embodiment, the protective layer 330 is formed by a chemical vapor deposition process. It is understood that in the present embodiment, in the first device region A1, the second mask layer 320 is formed on the surface of the protection layer 330.
The step of forming the protective layer 330 is an optional step, and in other embodiments, the protective layer 330 may not be formed, but the second mask layer 320 may be formed directly on the surface of the high-K dielectric layer 230.
Referring to fig. 9, with the second mask layer 320 as a shielding layer, in the second device region A2, the high-K dielectric layer 230 is removed to expose the second gate dielectric layer 220. In this step, an etching process is used to remove the high-K dielectric layer 230, such as a wet etching process. Since the second mask layer 320 only shields the high-K dielectric layer 230 of the first device region A1, the high-K dielectric layer 230 located in the first device region A1 is remained, and the high-K dielectric layer 230 located in the second device region A2 is removed, exposing the second gate dielectric layer 220. In this embodiment, since the surface of the high-K dielectric layer 230 is covered with the protection layer 330, in this step, the protection layer 330 is also removed in the second device region A2, and the protection layer 330 and the second mask layer 320 together serve as a mask in the first device region A1, so as to protect the high-K dielectric layer 230 in the first device region A1.
Referring to fig. 10, the second mask layer 320 is removed to expose the high-K dielectric layer 230. In this embodiment, the protective layer 330 on the surface of the high-K dielectric layer 230 is also removed. Wherein, ashing and etching processes can be used to remove the second mask layer 320 and the protection layer 330.
With continued reference to fig. 1 and 11-14, in step S12, a first gate structure 240 is formed on the surface of the high-K dielectric layer 230 in the first device region A1, and a second gate structure 250 is formed on the surface of the second gate dielectric layer 220 in the second device region A2.
In the first device region A1, the first gate dielectric layer 210 and the high-K dielectric layer 230 are used as insulating isolation layers between the first gate structure 240 and the substrate 201, in the second device region A2, the second gate dielectric layer 220 is used as an insulating isolation layer between the second gate structure 250 and the substrate 201, that is, the high-K dielectric layer 230 is not present in the second device region A2, so that the diffusion of the dipole of the high-K dielectric layer 230 is not affected by the existence of the thicker second gate dielectric layer 220, the second gate structure 250 can play a good role in adjusting threshold voltage, so that the threshold voltage of the second device region A2 is prevented from being too high, and the stability of the semiconductor device of the second device region A2 is improved.
In this embodiment, the first gate structure 240 includes a first NMOS transistor gate structure 241 and a first PMOS transistor gate structure 242, where the first NMOS transistor gate structure 241 is disposed corresponding to the first P-well region 203, and the first PMOS transistor gate structure 242 is disposed corresponding to the first N-well region 202; the second gate structure 250 includes a second NMOS transistor gate structure 251 and a second PMOS transistor gate structure 252, the second NMOS transistor gate structure 251 is disposed corresponding to the second P-well region 205, and the second PMOS transistor gate structure 252 is disposed corresponding to the second N-well region 204.
The step of forming the first gate structure 240 and the second gate structure 250 includes: a first NMOS transistor gate structure 241 is formed in the first P-well region 203, a first PMOS transistor gate structure 242 is formed in the first N-well region 202, a second NMOS transistor gate structure 251 is formed in the second P-well region 205, and a second PMOS transistor gate structure 252 is formed in the second N-well region 204.
As an example, the disclosed embodiments also provide a method of forming the first gate structure 240 and the second gate structure 250. Specifically, the method of forming the first gate structure 240 and the second gate structure 250 includes:
referring to fig. 11, a PMOS transistor metal gate layer 260 is formed in the first N-well region 202 and the second N-well region 204. The PMOS transistor metal gate layer 260 includes a work function metal layer and/or a TiN layer. For PMOS transistor metal gate layer 260, the work function metal layer may be Al 2 O 3 A layer. As an example, in the present embodiment, the PMOS transistor metal gate layer 260 includes a TiN layer, al, which are sequentially disposed 2 O 3 A layer and a TiN layer.
Referring to fig. 12, an NMOS transistor metal gate layer 261 is formed in the first P-well region 203 and the second P-well region 205. The NMOS transistor metal gate layer 261 includes a work function metal layer and/or a TiN layer. Metal gate layer 26 for NMOS transistor 1, the work function metal layer may be La 2 O 3 A layer. As an example, in the present embodiment, the NMOS transistor metal gate layer 261 includes La sequentially arranged 2 O 3 Layer, tiN layer.
As an example, in the present embodiment, the NMOS transistor metal gate layer 261 is further formed on the surface of the PMOS transistor metal gate layer 260, that is, the PMOS transistor metal gate layer 260 and the NMOS transistor metal gate layer 261 are formed in the first N-well region 202 and the second N-well region 204.
Referring to fig. 13, a gate composite layer 262 is formed, the gate composite layer 262 covering the NMOS transistor metal gate layer 261 and the PMOS transistor metal gate layer 260. The gate composite layer 262 includes, but is not limited to, a polysilicon layer, a tungsten layer, and a silicon oxynitride layer, which are sequentially disposed, and only one layer is schematically illustrated in the drawing.
Referring to fig. 14, the gate composite layer 262, the NMOS transistor metal gate layer 261 and the PMOS transistor metal gate layer 260 are patterned to form the first NMOS transistor gate structure 241, the first PMOS transistor gate structure 242, the second NMOS transistor gate structure 251 and the second PMOS transistor gate structure 252. Photolithography and etching processes may be used in this step to pattern the gate composite layer 262, the NMOS transistor metal gate layer 261, and the PMOS transistor metal gate layer 260. Wherein the gate composite layer 262 on the NMOS transistor metal gate layer 261 forms a first gate composite layer 263, and the gate composite layer 262 on the PMOS transistor metal gate layer 260 forms a second gate composite layer 264.
In this step, the first gate dielectric layer 210, the high-K dielectric layer 230, and the second gate dielectric layer 220 are also patterned. The substrate 201 on both sides of the first NMOS transistor gate structure 241, the first PMOS transistor gate structure 242, the second NMOS transistor gate structure 251, and the second PMOS transistor gate structure 252 are exposed, and may be doped to form source and drain regions. In this embodiment, a portion of the sige layer 206 is removed, leaving only the sige layer 206 under the first PMOS transistor gate structure 242.
The method for forming the semiconductor structure provided in the embodiment of the present disclosure does not affect the high-K dielectric layer 230 of the first device region A1 due to the removal of the high-K dielectric layer 230 of the second device region A2, and the high-K dielectric layer 230 is still formed in the first device region A1, so that the stability of the semiconductor structure of the first device region A1 is further ensured. The forming method provided by the embodiment of the disclosure has a simple process, can avoid the defect that the second grid structure 250 of the second device region A2 cannot well adjust the threshold voltage without complex processes, and greatly improves the practicability of the semiconductor process.
The embodiment of the disclosure also provides a semiconductor structure formed by the forming method. Referring to fig. 14, the semiconductor structure includes a substrate 201, a first gate dielectric layer 210, a second gate dielectric layer 220, a high K dielectric layer 230, a first gate structure 240, and a second gate structure 250.
The substrate 201 has a first device region A1 and a second device region A2. In the first device region A1, the first gate dielectric layer 210 covers the surface of the substrate 201, the high-K dielectric layer 230 covers the surface of the first gate dielectric layer 210, and the first gate structure 240 is located on the surface of the high-K dielectric layer 230. In the second device region A2, a second gate dielectric layer 220 covers the surface of the substrate 201, the second gate structure 250 is located on the surface of the second gate dielectric layer 220, and the thickness of the first gate dielectric layer 210 is smaller than that of the second gate dielectric layer 220. In this embodiment, the first gate dielectric layer 210 of the first device region A1 is thinner, which is a thin-oxygen device region, and the second gate dielectric layer 220 of the second device region A2 is thicker, which is a thick-oxygen device region.
In this embodiment, the first device region A1 includes a first N-well region 202 and a first P-well region 203, the first gate structure 240 includes a first NMOS transistor gate structure 241 and a first PMOS transistor gate structure 242, the first NMOS transistor gate structure 241 is disposed on the first P-well region 203, and the first PMOS transistor gate structure 242 is disposed on the first N-well region 202.
In this embodiment, in the first N-well region 202, the semiconductor structure further includes a silicon germanium layer 206, and the silicon germanium layer 206 is disposed between the first gate dielectric layer 210 and the substrate 201. Silicon has a lattice constant of 0.543nm and germanium has a lattice constant of 0.567nm, which differ by 4.17%, so that the incorporation of elemental germanium into pure silicon forms a stressed silicon germanium (SiGe) material. The silicon germanium material changes along with the density of germanium element, the forbidden bandwidth can be changed, and a heterostructure is easy to form; meanwhile, the electron mobility and the hole mobility of the silicon germanium material are higher than those of silicon, and the adoption of the silicon germanium material as a channel is beneficial to improving the hole mobility of the channel of the semiconductor structure.
The first NMOS transistor gate structure 241 includes an NMOS transistor metal gate layer 261 and a first gate composite layer 263 that covers the NMOS transistor metal gate layer 261. The NMOS transistor metal gate layer 261 includes a work function metal layer and/or a TiN layer. For the NMOS transistor metal gate layer 261, the work function metal layer may be La 2 O 3 A layer. As an example, in the present embodiment, the NMOS transistor metal gate layer 261 includes La sequentially arranged 2 O 3 Layer, tiN layer. The first gate composite layer 263 includes, but is not limited to, a polysilicon layer, a tungsten layer, and a silicon oxynitride layer sequentially disposed.
The first PMOS transistor gate structure 242 includes a PMOS transistor metal gate layer 260 and a second gate composite layer 264 overlying the PMOS transistor metal gate layer 260. The PMOS transistor metal gate layer 260 includes a work function metal layer and/or a TiN layer. For PMOS transistor metal gate layer 260, the work function metal layer may be an Al2O3 layer. As an example, in the present embodiment, the PMOS transistor metal gate layer 260 includes a TiN layer, an Al2O3 layer, and a TiN layer, which are sequentially disposed. The second gate composite layer 264 includes, but is not limited to, a polysilicon layer, a tungsten layer, and a silicon oxynitride layer, which are sequentially disposed.
In this embodiment, the second device region A2 includes a second N-well region 204 and a second P-well region, the second gate structure 250 includes a second NMOS transistor gate structure 251 and a second PMOS transistor gate structure 252, the second NMOS transistor gate structure 251 is disposed on the second P-well region 205, and the second PMOS transistor gate structure 252 is disposed on the second N-well region 204.
The second NMOS transistor gate structure 251 includes an NMOS transistor metal gate layer 261 and a first gate composite layer 263 that covers the NMOS transistor metal gate layer 261. The NMOS transistor metal gate layer 261 includes a work function metal layer and/or a TiN layer. In this embodiment, the second NMOS transistor gate structure 251 is the same as the first NMOS transistor gate structure 241, and will not be described here again.
The second PMOS transistor gate structure 252 includes a PMOS transistor metal gate layer 260, an NMOS transistor metal gate layer 261 overlying the PMOS transistor metal gate layer 260, and a second gate composite layer 264 overlying the NMOS transistor metal gate layer 261. In this embodiment, the second PMOS transistor gate structure 252 is the same as the first PMOS transistor gate structure 242, and will not be described herein.
The semiconductor structure provided in this disclosure is configured to provide a high-K dielectric layer 230 between the first gate structure 240 and the substrate 201 in the first device region A1 (thin-oxide device region) to reduce leakage current of the first gate structure 240, and only use the second gate dielectric layer 220 with a larger thickness as an isolation layer between the second gate structure 250 and the substrate 201 in the second device region A2 (thick-oxide device region), without the high-K dielectric layer 230, so that the problem of dipole diffusion of the high-K dielectric layer 230 caused by too thick thickness of the second gate dielectric layer 220 is avoided while reducing leakage current of the second gate structure 250, so that the second gate structure 250 can perform a good threshold voltage adjustment function, avoid too high threshold voltage of the second device region A2, and improve stability of the semiconductor device in the second device region A2.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.

Claims (15)

1. A method of forming a semiconductor structure, comprising:
forming a base, wherein the base comprises a substrate, the substrate is provided with a first device region and a second device region, a first grid dielectric layer is covered on the surface of the substrate in the first device region, a second grid dielectric layer is covered on the surface of the substrate in the second device region, the thickness of the first grid dielectric layer is smaller than that of the second grid dielectric layer, and high-K dielectric layers are covered on the surfaces of the first grid dielectric layer and the second grid dielectric layer, wherein the second grid dielectric layer is formed by adopting a first photomask through a positive developing process or a negative developing process;
removing the high-K dielectric layer in the second device region by adopting the first photomask through a negative development or positive development process, and exposing the second gate dielectric layer;
and forming a first grid structure on the surface of the high-K dielectric layer in the first device region, and forming a second grid structure on the surface of the second grid dielectric layer in the second device region.
2. The method of forming a semiconductor structure of claim 1, wherein the step of forming a substrate comprises:
providing the substrate;
forming a second gate dielectric layer on the surface of the substrate in the second device region;
forming a first gate dielectric layer on the surface of the substrate in the first device region;
and forming a high-K dielectric layer, wherein the high-K dielectric layer covers the first gate dielectric layer and the second gate dielectric layer.
3. The method of claim 2, wherein forming a second gate dielectric layer on the surface of the substrate in the second device region comprises:
forming a second gate dielectric material layer on the substrate;
forming a first mask layer on the second gate dielectric material layer in the second device region by adopting the first photomask through a positive developing process or a negative developing process;
taking the first mask layer as shielding, removing the second gate dielectric material layer in the first device region, and taking the second gate dielectric material layer as the second gate dielectric layer in the second device region;
and removing the first mask layer.
4. The method of claim 3, wherein forming a first gate dielectric layer on the surface of the substrate in the first device region comprises:
And forming a first gate dielectric material layer, wherein the first gate dielectric material layer covers the surface of the substrate in the first device region, and the first gate dielectric material layer is used as the first gate dielectric layer.
5. The method of claim 4, wherein in the second device region, the first gate dielectric material layer further covers a surface of the second gate dielectric material layer, and the first gate dielectric material layer and the second gate dielectric material layer together serve as the second gate dielectric layer.
6. The method of claim 2, wherein removing the high-K dielectric layer in the second device region and exposing the second gate dielectric layer comprises:
forming a second mask layer on the surface of the high-K dielectric layer in the first device region by adopting the first photomask through a negative development or positive development process;
taking the second mask layer as shielding, removing the high-K dielectric layer in the second device region, and exposing the second gate dielectric layer;
and removing the second mask layer.
7. The method of forming a semiconductor structure of claim 1, further comprising, prior to the step of removing the high-K dielectric layer:
Forming a protective layer on the surface of the high-K dielectric layer;
in the step of removing the high-K dielectric layer, the protective layer is used for protecting the high-K dielectric layer in the first device region;
the protective layer is removed prior to the step of forming the first gate structure.
8. The method of claim 1, wherein the first device region comprises a first N-well region and a first P-well region, the second device region comprises a second N-well region and a second P-well region, and the step of forming the substrate further comprises: and forming a silicon germanium layer on the surface of the substrate in the first N well region, wherein the first gate dielectric layer covers the silicon germanium layer.
9. The method of forming a semiconductor structure of claim 8, wherein the first gate structure comprises a first NMOS transistor gate structure and a first PMOS transistor gate structure, the second gate structure comprises a second NMOS transistor gate structure and a second PMOS transistor gate structure, and the step of forming the first gate structure and the second gate structure comprises: and forming a first NMOS transistor gate structure in the first P well region, forming a first PMOS transistor gate structure in the first N well region, forming a second NMOS transistor gate structure in the second P well region, and forming a second PMOS transistor gate structure in the second N well region.
10. The method of forming a semiconductor structure of claim 9, wherein forming the first gate structure and the second gate structure comprises:
forming a PMOS transistor metal gate layer in the first N well region and the second N well region;
forming an NMOS transistor metal gate layer in the first P well region and the second P well region;
forming a gate composite layer, wherein the gate composite layer covers the PMOS transistor metal gate layer and the NMOS transistor metal gate layer;
and patterning the gate composite material layer, the PMOS transistor metal gate layer and the NMOS transistor metal gate layer to form the first PMOS transistor gate structure, the first NMOS transistor gate structure, the second PMOS transistor gate structure and the second NMOS transistor gate structure.
11. A semiconductor structure, comprising:
a substrate having a first device region and a second device region;
in the first device region, a first gate dielectric layer covers the surface of the substrate;
in the second device region, a second gate dielectric layer covers the surface of the substrate, and the thickness of the first gate dielectric layer is smaller than that of the second gate dielectric layer;
The high-K dielectric layer covers the surface of the first gate dielectric layer;
the first grid structure is positioned on the surface of the high-K dielectric layer;
and the second grid structure is positioned on the surface of the second grid dielectric layer.
12. The semiconductor structure of claim 11, wherein the first device region comprises a first N-well region and a first P-well region, the first gate structure comprising a first NMOS transistor gate structure and a first PMOS transistor gate structure, the first NMOS transistor gate structure disposed on the first P-well region, the first PMOS transistor gate structure disposed on the first N-well region; the second device region comprises a second N-well region and a second P-well region, the second gate structure comprises a second NMOS transistor gate structure and a second PMOS transistor gate structure, the second NMOS transistor gate structure is arranged on the second P-well region, and the second PMOS transistor gate structure is arranged on the second N-well region.
13. The semiconductor structure of claim 12, further comprising a silicon germanium layer in the first N-well region, the silicon germanium layer disposed between the first gate dielectric layer and the substrate.
14. The semiconductor structure of claim 12, wherein the first NMOS transistor gate structure and the second NMOS transistor gate structure have the same structure, and wherein the first PMOS transistor gate structure and the second PMOS transistor gate structure have the same structure.
15. The semiconductor structure of claim 14, wherein the first NMOS transistor gate structure and the second NMOS transistor gate structure each comprise an NMOS transistor metal gate layer and a first gate composite layer overlying the NMOS transistor metal gate layer; the first PMOS transistor gate structure and the second PMOS transistor gate structure each include a PMOS transistor metal gate layer and a second gate composite layer overlying the PMOS transistor metal gate layer.
CN202211032388.4A 2022-08-26 2022-08-26 Semiconductor structure and forming method thereof Pending CN117690785A (en)

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