CN117457610A - BGA package substrate and memory chip BGA package structure - Google Patents

BGA package substrate and memory chip BGA package structure Download PDF

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Publication number
CN117457610A
CN117457610A CN202311482768.2A CN202311482768A CN117457610A CN 117457610 A CN117457610 A CN 117457610A CN 202311482768 A CN202311482768 A CN 202311482768A CN 117457610 A CN117457610 A CN 117457610A
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China
Prior art keywords
differential pair
bga package
pads
package substrate
channel
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CN202311482768.2A
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Chinese (zh)
Inventor
谭少鹏
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Shenzhen Demingli Electronics Co Ltd
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Shenzhen Demingli Electronics Co Ltd
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Priority to CN202311482768.2A priority Critical patent/CN117457610A/en
Publication of CN117457610A publication Critical patent/CN117457610A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The application discloses BGA package substrate and memory chip BGA package structure, wherein the BGA package substrate includes base plate, first differential pair pad and second differential pair pad, the base plate includes relative first surface and second surface, first surface is used for fixed memory chip, the second surface includes first passageway region, second passageway region and is located first passageway region with isolation region between the second passageway region, first differential pair pad set up in first passageway region and next to isolation region, second differential pair pad set up in second passageway region and next to isolation region. The BGA package substrate can effectively solve the technical problem that the transmission rate is affected due to unreasonable layout of the differential pair signal pins of the BGA package in the prior art.

Description

BGA package substrate and memory chip BGA package structure
Technical Field
The present disclosure relates to semiconductor packaging technology, and more particularly, to a BGA package substrate and a BGA package structure for a memory chip.
Background
Flash (Flash Memory) is a long-life non-volatile Memory. NOR Flash and NAND Flash are two major Flash memories on the market today. Since the NAND structure provides extremely high cell density, high memory density can be achieved, and writing and erasing speeds are also fast, its physical and photographic effects can be seen in various electronic products at present. With the development of technology and the increasing demand for data transfer rates, the open Flash interface (Open NAND Flash Interface, onFi) for NAND Flash is also being updated continuously, such as in the OnFi5.0 version, where the bus bandwidth (IO frequency) has reached 2400MB/S.
Ball grid array packages (Ball Grid Array Package, BGA) are the most widely used packages for Flash memory, and are classified into BGA132 and BGA152 according to requirements, and BGA132 has one row of NC/NU contacts on both left and right sides with respect to BGA 152. A host board designed for BGA152 can easily support BGA132. However, due to limitations of existing pin definition specifications, current BGA132 and BGA152 severely impact their applications in onf 5.0 and higher requirements in pin distribution.
Referring to fig. 1, a pin layout diagram of a BGA package according to the prior art is shown. Fig. 1 shows a pin layout diagram of a BGA152 package format. In the illustrated pin layout, two groups of differential pairs of DQS_t, DQS_c and RE_t and RE_c are surrounded by other pins, the two groups of differential pairs are too close in physical distance, the two groups of differential pairs are not completely isolated from each other, signals are seriously interfered with each other, and the two groups of differential pairs of RE_t and RE_c are too far apart to influence the integrity of the signals of the differential pairs, so that the pin distribution of the flash memory BGA152 in the prior art is not suitable for higher flash memory IO frequency, and the specific application range of the flash memory is limited.
In addition, fig. 2 shows another pin layout of a BGA package (BGA 132) of the prior art, which also has similar technical problems to the BGA package pin layout shown in fig. 1.
Therefore, how to solve the problem that the pin distribution is unreasonable to adapt to the higher IO frequency in the BGA packaging technology of the memory chip is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
An objective of the embodiments of the present application is to provide a BGA package substrate, so as to solve the technical problem that in the prior art, the layout of BGA package differential pair signal pins is unreasonable and the transmission rate is affected.
In a first aspect, the present application provides a BGA package substrate, comprising:
a substrate comprising opposing first and second surfaces, wherein the first surface is for securing a memory chip, and the second surface comprises a first channel region, a second channel region, and an isolation region between the first and second channel regions;
a first differential pair pad disposed in the first channel region and immediately adjacent to the isolation region;
and the second differential pair bonding pad is arranged in the second channel region and is adjacent to the isolation region.
According to the BGA package substrate provided by the embodiment of the application, the first differential pair bonding pads and the second differential pair bonding pads for transmitting the same group of differential pair signals are respectively arranged in the first channel area and the second channel area which are mutually isolated on the second surface, so that the transmission quality of the differential pair signals of the memory chip is improved, and the technical problem that the transmission rate is influenced due to unreasonable layout of the differential pair signal pins in the prior art is solved.
In one possible embodiment, the first differential pair of pads and the second differential pair of pads are used for transmitting signals of a first channel, and the first differential pair of pads and the second differential pair of pads are symmetrically distributed about a central axis of the isolation region.
In one possible implementation, the first differential pair pad is a data bus strobe differential pair pad for transmitting a data bus strobe differential signal of a first channel; the second differential pair pad is a read enable differential pair pad for transmitting a read enable differential signal of the first channel.
In one possible embodiment, the BGA package substrate further includes a third differential pair of pads disposed in the second channel region and immediately adjacent to the isolation region and a fourth differential pair of pads disposed in the first channel region and immediately adjacent to the isolation region.
In one possible embodiment, the third differential pair pad and the fourth differential pair pad are used for transmitting signals of the second channel, and the third differential pair pad and the fourth differential pair pad are symmetrically distributed with respect to a central axis of the isolation region.
In one possible implementation, the third differential pair pad is a data bus strobe differential pair pad for transmitting a data bus strobe differential signal of the second channel; the fourth differential pair pad is a read enable differential pair pad for transmitting a read enable differential signal of the second channel.
In one possible embodiment, the first differential pair pad, the second differential pair pad, the third differential pair pad, and the fourth differential pair pad are located at a top/bottom of the first channel region.
In one possible embodiment, the BGA package substrate further includes a plurality of ground pads that are immediately adjacent to the first, second, third, and fourth differential pair pads and isolate the first, second, third, and fourth differential pair pads from other pads.
In one possible implementation manner, the BGA package substrate further includes a plurality of first data interface pads for transmitting data signals of a first channel and a plurality of second data interface pads arranged in a matrix set in the first channel region; the plurality of second data interface pads are used for transmitting data signals of a second channel, and the second data interface pads are arranged in the second channel area in a matrix set.
In one possible embodiment, the BGA package substrate further includes two pairs of power pads respectively disposed in the centers of the first and second channel regions and symmetrically disposed about the center line of the isolation region.
In a second aspect, an embodiment of the present application provides a BGA package structure of a memory chip, including:
a BGA package substrate, which is the BGA package substrate of the first aspect or any one of the possible implementation manners of the first aspect;
the storage chip is fixed on the BGA package substrate;
the plastic package is arranged on the BGA package substrate and covers the storage chip;
and a plurality of solder balls respectively connected with the plurality of bonding pads of the BGA package substrate.
According to the BGA package substrate and the memory chip BGA package structure, the paired first differential pair pads are placed together and are respectively arranged in the two channel areas isolated by the isolation areas with the other pair of differential pair pads, so that each pair of differential pair pads can correspondingly transmit complete differential pair signals, meanwhile, different differential pair pads are isolated, so that signal interference is reduced, the influence on transmission rate is reduced, and therefore the BGA package pin layout of the embodiment of the application is reasonable and reliable.
Drawings
For a clearer description of the solution in the present application, a brief description will be given below of the drawings that are needed in the description of the embodiments of the present application, it being obvious that the drawings in the following description are some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a pin layout diagram of a prior art BGA package;
FIG. 2 is a pin layout diagram of another prior art BGA package;
FIG. 3 is a schematic diagram of pin distribution of a BGA package substrate in accordance with one embodiment of the present application;
FIG. 4 is a schematic diagram of the pin distribution of a BGA package substrate in accordance with another embodiment of the present application;
fig. 5 is a schematic diagram of a BGA package structure of a memory chip according to an embodiment of the present application.
Detailed Description
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description of the applications herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having" and any variations thereof in the description and claims of the present application and in the description of the figures above are intended to cover non-exclusive inclusions. The terms first, second and the like in the description and in the claims or in the above-described figures, are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order. The terms "coupled" and "connected," as used herein, are intended to encompass both direct and indirect coupling (coupling), unless otherwise indicated.
Furthermore, the described features, operations, or characteristics of the description may be combined in any suitable manner in various embodiments. Also, various steps or acts in the method descriptions may be interchanged or modified in a manner apparent to those of ordinary skill in the art. Thus, the various orders in the description and drawings are for clarity of description of only certain embodiments, and are not meant to be required orders unless otherwise indicated.
The present application is described in further detail below with reference to the accompanying drawings by way of specific embodiments. In the following embodiments, numerous specific details are set forth in order to provide a better understanding of the present application. However, one skilled in the art will readily recognize that some of the features may be omitted, or replaced by other elements, materials, or methods in different situations. In some instances, some operations associated with the present application have not been shown or described in the specification to avoid obscuring the core portions of the present application, and may not be necessary for a person skilled in the art to describe in detail the relevant operations based on the description herein and the general knowledge of one skilled in the art.
Referring to fig. 3, a schematic diagram of pin distribution of a BGA package substrate according to an embodiment of the present application is shown. The BGA package substrate includes a substrate 1, a first differential pair of pads 110 and a second differential pair of pads 120. The substrate 1 includes opposite first and second surfaces, wherein the first surface is used for fixing a memory chip, and the second surface includes a first channel region 11, a second channel region 12, and an isolation region 13 between the first channel region 11 and the second channel region 12. The first differential pair pad 110 is disposed in the first channel region 11 and is immediately adjacent to the isolation region 13. The second differential pair pad 120 is disposed in the second channel region 12 and immediately adjacent to the isolation region 13.
According to the embodiment of the application, the first differential pair bonding pad and the second differential pair bonding pad for transmitting the same group of differential pair signals are respectively arranged in the first channel area and the second channel area which are physically isolated by the isolation area on the second surface, the isolation area is correspondingly used as a reserved space for copper-clad isolation, ground pins are arranged around the first differential pair bonding pad and the second differential pair bonding pad to form a package, the signal quality and the anti-interference capability of the differential pair signals are ensured, the transmission quality of the differential pair signals of the memory chip is improved, and the technical problem that the transmission rate is influenced due to unreasonable layout of the differential pair signal pins in the prior art is solved.
In some embodiments, the first differential pair of pads and the second differential pair of pads are configured to transmit signals of the first channel, the first differential pair of pads and the second differential pair of pads being symmetrically distributed about a center axis of the isolation region.
In some embodiments, the first differential pair pad is a data bus strobe differential pair pad for transmitting a data bus strobe differential signal of the first channel; the second differential pair pad is a read enable differential pair pad for transmitting a read enable differential signal of the first channel.
In some embodiments, the BGA package substrate further includes a third differential pair pad 210 and a fourth differential pair pad 220, the third differential pair pad 210 being disposed in the second channel region 12 and immediately adjacent to the isolation region, the fourth differential pair pad 220 being disposed in the first channel region 11 and immediately adjacent to the isolation region.
In some embodiments, the third differential pair pad and the fourth differential pair pad are for transmitting signals of the second channel, the third differential pair pad and the fourth differential pair pad being symmetrically distributed about a center line axis of the isolation region.
In some embodiments, the third differential pair pad is a data bus strobe differential pair pad for transmitting a data bus strobe differential signal of the second channel; the fourth differential pair pad is a read enable differential pair pad for transmitting a read enable differential signal of the second channel.
In some embodiments, the first differential pair pad, the second differential pair pad, the third differential pair pad, and the fourth differential pair pad are located at a top/bottom of the first channel region. In this embodiment, the first differential pair pad and the second differential pair pad, and the third differential pair pad and the fourth differential pair pad are disposed at opposite ends of the first channel region and the second channel region, respectively, and when wiring is specifically applied, the same layer and other layers can be selected for the wiring to the outside, so that the space is increased.
In some embodiments, the BGA package substrate further includes a plurality of ground pads proximate to and isolating the first, second, third and fourth differential pair pads from other pads. The ground pads may form a package for the first differential pair pad, the second differential pair pad, the third differential pair pad, and the fourth differential pair pad, thereby further improving signal quality and interference rejection of differential pair signals transmitted therein.
In some embodiments, the BGA package substrate further includes a plurality of first data interface pads (dq0_0 to dq7_0) for transmitting data signals of the first channel and a plurality of second data interface pads (dq0_1 to dq7_1) disposed in a matrix concentration in the first channel region; the plurality of second data interface pads are used for transmitting data signals of the second channel, and the second data interface pads are arranged in the second channel area in a matrix concentration mode. In this embodiment, the first data interface pad and the second data interface pad are respectively arranged in two rows in a 2X4 layout, and only two layers of wiring are needed in application, so that the wiring difficulty is reduced.
In some embodiments, the BGA package substrate further includes two pairs of power pads disposed centered on the first and second channel regions, respectively, and symmetrically disposed about a center line of the isolation region with respect to the two pairs of power pads.
As an example, the BGA package substrate of the embodiments of the present application may be used for a BGA152 specification package structure, and for specific pin numbers and corresponding pin definitions, refer to table 1. In table 1 "pin sequence number" corresponds to the row sequence number in fig. 3 (or fig. 1), for example, pin sequence number D3 indicates the pin corresponding to row 3 column of fig. 3 (or fig. 1), which is defined as VCCQ. In table 1, a column of "original definition" is the corresponding original pin definition in the prior art shown in fig. 1, and a column of "optimized" is the pin definition of BGA152 specification in the embodiment of the present application shown in fig. 3.
TABLE 1
Referring to fig. 4, a schematic diagram of pin distribution of a BGA package substrate according to another embodiment of the present application is shown. Similar to the embodiment shown in fig. 3, and has a corresponding effect, the main difference is that the BGA package in this example is of BGA132 format, and there are 132 pads (solder balls, pins). Specific pin numbers and corresponding pin definitions refer to table 2, where a column "original definition" is the corresponding pin definition in the prior art shown in fig. 2 and a column "optimized" is the BGA132 pin definition of the embodiment of the present application shown in fig. 4.
TABLE 2
Referring to fig. 5, a schematic diagram of a BGA package structure of a memory chip according to an embodiment of the present application is shown. The memory chip BGA package structure 10 includes a memory chip 100, a BGA package substrate 102, solder balls 104 and a plastic package 106. The memory chip 100 may specifically be a NAND Flash chip, where the memory chip 100 is fixed on one surface (which may be defined as a first surface) of the BGA package substrate 102, and a plurality of pads connected to pins of the memory chip 102 are disposed on the other surface (which may be defined as a second surface) of the BGA package substrate 102, and each pad is correspondingly connected to one solder ball 104, so that the memory chip of the whole BGA package structure can be connected to a PCB through the solder balls 104, and thus, can be connected to other electronic components (such as a CPU, etc.) on the PCB to generate a complete functional application circuit. The plastic package 106 is disposed on the first surface of the BGA package substrate and covers the memory chip 100, so as to protect the memory chip 100 from being packaged.
According to the BGA package substrate and the memory chip BGA package structure, the pair of first differential pair bonding pads are placed together and are respectively arranged in the two channel areas isolated by the isolation areas with the other pair of differential pair bonding pads, so that each pair of differential pair bonding pads can correspondingly transmit complete differential pair signals, meanwhile, different differential pair bonding pads are isolated, so that signal interference is reduced, the influence on transmission rate is reduced, and therefore the BGA package pin layout is reasonable and reliable.
In summary, the embodiment of the application improves the transmission quality of the differential pair signals of the memory chip, optimizes the layout of the interface pads, and improves the wiring efficiency of the circuit board in application.
It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited in order and may be performed in other orders, unless explicitly stated herein. Moreover, at least some of the steps in the flowcharts of the figures may include a plurality of sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, the order of their execution not necessarily being sequential, but may be performed in turn or alternately with other steps or at least a portion of the other steps or stages.
Reference is made to various exemplary embodiments herein. However, those skilled in the art will recognize that changes and modifications may be made to the exemplary embodiments without departing from the scope herein. For example, the various operational steps and components used to perform the operational steps may be implemented in different ways (e.g., one or more steps may be deleted, modified, or combined into other steps) depending on the particular application or taking into account any number of cost functions associated with the operation of the system.
While the principles herein have been shown in various embodiments, many modifications of structure, arrangement, proportions, elements, materials, and components, which are particularly adapted to specific environments and operative requirements, may be used without departing from the principles and scope of the present disclosure. The above modifications and other changes or modifications are intended to be included within the scope of this document.
The foregoing detailed description has been described with reference to various embodiments. However, those skilled in the art will recognize that various modifications and changes may be made without departing from the scope of the present disclosure. Accordingly, the present disclosure is to be considered as illustrative and not restrictive in character, and all such modifications are intended to be included within the scope thereof. Also, advantages, other advantages, and solutions to problems have been described above with regard to various embodiments. The benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, system, or apparatus. Furthermore, the term "couple" and any other variants thereof are used herein to refer to physical connections, electrical connections, magnetic connections, optical connections, communication connections, functional connections, and/or any other connection.
Those having skill in the art will recognize that many changes may be made to the details of the above-described embodiments without departing from the underlying principles of the present application. Accordingly, the scope of the application should be determined from the following claims.

Claims (11)

1. A BGA package substrate, comprising:
a substrate comprising opposing first and second surfaces, wherein the first surface is for securing a memory chip, and the second surface comprises a first channel region, a second channel region, and an isolation region between the first and second channel regions;
a first differential pair pad disposed in the first channel region and immediately adjacent to the isolation region;
and the second differential pair bonding pad is arranged in the second channel region and is adjacent to the isolation region.
2. The BGA package substrate of claim 1, wherein the first and second differential pair pads are configured to transmit signals of a first channel, the first and second differential pair pads being symmetrically distributed about a center line axis of the isolation region.
3. The BGA package substrate of claim 2, wherein the first differential pair of pads is a data bus strobe differential pair of pads for transmitting a data bus strobe differential signal of a first channel; the second differential pair pad is a read enable differential pair pad for transmitting a read enable differential signal of the first channel.
4. The BGA package substrate of claim 2, further comprising third and fourth differential pair pads, the third differential pair pad disposed in the second channel region and immediately adjacent to the isolation region, the fourth differential pair pad disposed in the first channel region and immediately adjacent to the isolation region.
5. The BGA package substrate of claim 4, wherein the third and fourth differential pair pads are configured to transmit signals of a second channel, the third and fourth differential pair pads being symmetrically distributed about a center line axis of the isolation region.
6. The BGA package substrate of claim 5, wherein the third differential pair of pads is a data bus strobe differential pair of pads for transmitting a data bus strobe differential signal of the second channel; the fourth differential pair pad is a read enable differential pair pad for transmitting a read enable differential signal of the second channel.
7. The BGA package substrate of claim 5, wherein the first, second, third and fourth differential pair pads are located at a top/bottom of the first channel region.
8. The BGA package substrate of claim 7, further comprising a plurality of ground pads adjacent to and isolating the first, second, third and fourth differential pair pads from other pads.
9. The BGA package substrate of claim 1, further comprising a plurality of first data interface pads for transmitting data signals of a first channel and a plurality of second data interface pads disposed in a matrix concentration in the first channel region; the plurality of second data interface pads are used for transmitting data signals of a second channel, and the second data interface pads are arranged in the second channel area in a matrix set.
10. The BGA package substrate of any one of claims 1-9, further comprising two pairs of power pads disposed centered on the first and second channel regions, respectively, and symmetrically disposed about a centerline of the isolation region.
11. A memory chip BGA package structure, comprising:
a BGA package substrate, the BGA package substrate being the BGA package substrate of any one of claims 1 to 10;
the storage chip is fixed on the BGA package substrate;
the plastic package is arranged on the BGA package substrate and covers the storage chip;
and a plurality of solder balls respectively connected with the plurality of bonding pads of the BGA package substrate.
CN202311482768.2A 2023-11-08 2023-11-08 BGA package substrate and memory chip BGA package structure Pending CN117457610A (en)

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CN202311482768.2A CN117457610A (en) 2023-11-08 2023-11-08 BGA package substrate and memory chip BGA package structure

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118693026A (en) * 2024-08-23 2024-09-24 合肥芯颖科技有限公司 Chip structure and chip structure design method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118693026A (en) * 2024-08-23 2024-09-24 合肥芯颖科技有限公司 Chip structure and chip structure design method
CN118693026B (en) * 2024-08-23 2024-11-05 合肥芯颖科技有限公司 Chip structure and chip structure design method

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