CN117312189A - Method and device for realizing fast block interleaving or de-interleaving by utilizing single chip memory - Google Patents

Abstract

The present disclosure provides a fast block interleaving or de-interleaving method implemented using a monolithic memory, which may be applied to the field of communication technology. The method comprises the following steps: writing the initial data stored in the buffer into the external memory in response to the plurality of internal memories being in a data read-out state; under the condition that a data reading request returned by a target internal memory in a plurality of internal memories is received, determining a first unit offset and a second unit offset related to the external memory based on a preset interleaving depth, a data reading and writing performance parameter of the external memory and a first data bit width of the external memory; and interleaving the initial data into the target internal memory using a first row counter and a first column counter associated with the initial data based on the first unit offset and the second unit offset. The disclosure also provides a device and an electronic device for realizing fast block interleaving or de-interleaving by using the monolithic memory.

Description

Method and device for realizing fast block interleaving or de-interleaving by utilizing single chip memory

Technical Field

The present disclosure relates to the field of communications technologies, and in particular, to the field of free space laser communications systems, and in particular, to a method and apparatus for fast block interleaving or deinterleaving implemented using a monolithic memory, and an electronic device.

Background

Free space optical communication achieves the aim of information communication by directly transmitting laser signals through space, has the advantages of high communication bandwidth, high confidentiality, unrestricted frequency and the like, and has been rapidly developed in recent years. In free-space optical channels, if the transmission path passes through the atmosphere, the quality of the optical signal is seriously deteriorated, even the signal is completely lost, due to additive noise and sudden continuous errors caused by factors such as atmospheric turbulence, floating dust particles and the like. In a satellite-to-ground laser communication system, transmission path obstruction and fading caused by atmospheric turbulence can cause burst errors of data in a spatial optical communication system, and general channel error correction coding can only correct a limited number of random errors, and for a large number of burst errors in the burst, the error correction capability of the channel error correction coding is exceeded. Thus, a combination of channel error correction coding and interleaving coding is used to correct a large number of burst errors in a burst. In the interleaving coding, the larger the interleaving depth is, the larger the dispersion is, and the better the error correction capability is. Therefore, in order to improve the error correction capability, to meet the requirement of higher interleaving depth, the interleaver is required to provide a larger storage capacity. When a programmable gate array (Field Programmable Gate Array, FPGA) chip is used as an interleaver, the storage capacity of the FPGA chip is limited, and it is difficult to meet the requirement of a higher interleaving depth on the storage capacity, so that an external high-speed memory is generally adopted to complete the interleaving process.

Because of the characteristics of the block interleaving method, row writing is required and then column reading is required, so that the read addresses are discontinuous, continuous reading operation cannot be adopted, only random reading can be performed, and the reading rate of the memory is reduced. In the related art, the requirement of a higher interleaving depth for storage capacity and the rate requirement are satisfied by employing a plurality of pieces of external memory. However, the use of multiple external memories results in higher cost, and the implementation of interleaving and de-interleaving with a single external memory is affected by the interleaving policy, resulting in a lower read-out data rate, which cannot meet the high-rate interleaving and de-interleaving requirements.

Disclosure of Invention

In view of the foregoing, the present disclosure provides a fast block interleaving or de-interleaving method, apparatus, and electronic device implemented using a monolithic memory.

According to a first aspect of the present disclosure, there is provided a fast block interleaving or deinterleaving method implemented using a monolithic memory, comprising: writing the initial data stored in the buffer into the external memory in response to the plurality of internal memories being in a data read-out state; when a data reading request returned by a target internal memory in the plurality of internal memories is received, determining a first unit offset and a second unit offset related to the external memory based on a preset interleaving depth, a data reading and writing performance parameter of the external memory and a first data bit width of the external memory; and interleaving the initial data into the target internal memory using a first row counter and a first column counter associated with the initial data based on the first unit offset and the second unit offset.

According to an embodiment of the present disclosure, the interleaving the initial data into the target internal memory using a first row counter and a first column counter associated with the initial data based on the first unit offset and the second unit offset includes: determining a storage address of initial sub-data to be processed in the initial data based on the count value of the first row counter, the count value of the first column counter, the first unit offset, and the second unit offset; writing the initial sub-data into the target internal memory based on a storage address of the initial sub-data; and updating the count values of the first row counter and the first column counter.

According to an embodiment of the present disclosure, the determining the storage address of the initial sub-data based on the count value of the first row counter, the count value of the first column counter, the first unit offset, and the second unit offset includes: determining a row address offset based on the first unit offset and a count value of the first row counter; determining a column address offset based on the second unit offset and a count value of the first column counter; and determining a storage address of the initial sub-data based on an initial storage address of the initial data, the row address offset of the initial sub-data, and the column address offset.

According to an embodiment of the present disclosure, the updating the count values of the first row counter and the first column counter includes: updating the count value of the first row counter based on a first preset step length; and updating the count value of the first column counter based on a second preset step length under the condition that the count value of the first row counter is equal to the preset interleaving depth.

According to an embodiment of the present disclosure, the above method further includes: resetting the count value of the first row counter to an initial value under the condition that the count value of the first row counter is equal to the preset interleaving depth; and resetting the count value of the first column counter to an initial value when the count value of the first column counter is equal to a preset count value, wherein the preset count value is related to the data read-write performance parameter of the external memory and the first data bit width of the external memory.

According to an embodiment of the present disclosure, the writing the initial sub-data into the target internal memory based on the storage address of the initial sub-data includes: dividing the initial sub-data into a plurality of data blocks based on the data read-write performance parameters of the external memory; determining the storage addresses of the plurality of data blocks based on the storage addresses of the initial sub-data; and writing the plurality of data blocks into the target internal memory sequentially based on the storage addresses of the plurality of data blocks.

According to an embodiment of the present disclosure, the determining a first unit offset and a second unit offset related to the external memory based on a preset interleaving depth, a data read/write performance parameter of the external memory, and a first data bit width of the external memory includes: determining the first unit offset based on the data amount of the initial data, the preset interleaving depth, and the first data bit width of the external memory; and determining the second unit offset based on the data read/write performance parameter of the external memory and the first data bit width of the external memory.

According to an embodiment of the present disclosure, the above method further includes: determining a number of rows and a number of columns associated with the internal memory based on the second bit width of the internal memory; and reading out the interleaved target data in the internal memory using a second row counter and a second column counter based on the row number value and the column number value.

A second aspect of the present disclosure provides a fast block interleaving or deinterleaving apparatus implemented using a monolithic memory, comprising: the external memory writing module is used for writing the initial data stored in the buffer into the external memory in response to the fact that the plurality of internal memories are in a data reading state; an offset determining module, configured to determine, when receiving a data read request returned by a target internal memory among the plurality of internal memories, a first unit offset and a second unit offset related to the external memory based on a preset interleaving depth, a data read-write performance parameter of the external memory, and a first data bit width of the external memory; and a memory writing module configured to interleave and write the initial data into the target internal memory using a first row counter and a first column counter associated with the initial data based on the first unit offset and the second unit offset.

A third aspect of the present disclosure provides an electronic device, comprising: one or more processors; and a memory for storing one or more programs, wherein the one or more programs, when executed by the one or more processors, cause the one or more processors to perform the fast block interleaving or de-interleaving method implemented using the monolithic memory as described above.

By responding to the fact that the plurality of internal memories are in the data reading state, initial data stored in the buffer are written into the external memory, so that the external memory performs writing operation when in an idle state without reading operation, time required for reading and writing data is saved, interleaving speed is improved, interleaving is achieved by the aid of the external memory, storage capacity of the interleaver is increased, and requirements of high interleaving depth can be met. And determining the internal memory which is not in a read state in the plurality of internal memories as the target internal memory by judging the target internal memory in the plurality of internal memories, so as to ensure that readable data exist in the plurality of internal memories. By determining the first unit offset and the second unit offset, when the initial data stored in the external memory is read out, address control is realized based on the first unit offset and the second unit offset, and high-rate interleaving is further realized.

Drawings

The foregoing and other objects, features and advantages of the disclosure will be more apparent from the following description of embodiments of the disclosure with reference to the accompanying drawings, in which:

FIG. 1 schematically illustrates an application scenario diagram of a fast block interleaving or deinterleaving method, apparatus, and device implemented with monolithic memory, in accordance with an embodiment of the present disclosure;

FIG. 2 schematically illustrates a flow chart of a fast block interleaving or deinterleaving method implemented with monolithic memory, in accordance with an embodiment of the present disclosure;

FIG. 3 schematically illustrates a flow chart of writing data to a target internal memory according to an embodiment of the disclosure;

FIG. 4 schematically illustrates a flow chart of determining an initial sub-data storage address according to an embodiment of the present disclosure;

FIG. 5 schematically illustrates a flow chart of writing initial sub-data to a target internal memory according to an embodiment of the disclosure;

FIG. 6 schematically illustrates a storage structure diagram of initial data in an external memory according to an embodiment of the present disclosure;

FIG. 7 schematically illustrates a read structure diagram of initial data in an external memory according to an embodiment of the present disclosure;

FIG. 8 schematically illustrates a flow chart of reading target data according to an embodiment of the disclosure;

FIG. 9 schematically illustrates a storage structure diagram of target data in an internal memory according to an embodiment of the present disclosure;

FIG. 10 schematically illustrates a block diagram of a fast block interleaving or deinterleaving apparatus implemented with a monolithic memory, in accordance with an embodiment of the present disclosure; and

fig. 11 schematically illustrates a block diagram of an electronic device suitable for implementing a fast block interleaving or de-interleaving method implemented using a monolithic memory according to an embodiment of the present disclosure.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The terms "comprises," "comprising," and/or the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.

All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. It should be noted that the terms used herein should be construed to have meanings consistent with the context of the present specification and should not be construed in an idealized or overly formal manner.

Where expressions like at least one of "A, B and C, etc. are used, the expressions should generally be interpreted in accordance with the meaning as commonly understood by those skilled in the art (e.g.," a system having at least one of A, B and C "shall include, but not be limited to, a system having a alone, B alone, C alone, a and B together, a and C together, B and C together, and/or A, B, C together, etc.).

In the related art, the interleaving technology utilizes an FPGA chip to achieve interleaving and de-interleaving of data, but the requirement of higher interleaving depth cannot be met due to the limited storage capacity of the FPGA chip. If the continuous error code length is in the MByte order, the error correction capability can meet the correction requirement under the condition of 2% error rate, the interleaving requires about 128MB of storage space, so that large-scale storage units are difficult to integrate in the traditional FPGA chip, namely the storage capacity of the FPGA chip can not meet the storage capacity requirements of interleaving and de-interleaving.

Embodiments of the present disclosure provide a fast block interleaving or deinterleaving method implemented using a monolithic memory, the method comprising: writing the initial data stored in the buffer into the external memory in response to the plurality of internal memories being in a data read-out state; under the condition that a data reading request returned by a target internal memory in a plurality of internal memories is received, determining a first unit offset and a second unit offset related to the external memory based on a preset interleaving depth, a data reading and writing performance parameter of the external memory and a first data bit width of the external memory; and interleaving the initial data into the target internal memory using a first row counter and a first column counter associated with the initial data based on the first unit offset and the second unit offset.

Fig. 1 schematically illustrates an application scenario diagram of a fast block interleaving or deinterleaving method implemented with a monolithic memory, in accordance with an embodiment of the present disclosure.

As shown in fig. 1, the application scenario 100 according to this embodiment may include an FPGA chip 110 and an external memory 120. The FGPA chip 110 includes three parts, namely a buffer, an internal memory, and a read-write control component. The external memory 120 is used for storing the data read out from the buffer by the read-write control component.

The buffer can perform bit width conversion on the data before being written into the external memory 120 and plays a role of buffering. The internal memory is used for storing the data read out from the external memory 120 by the read-write control component. The read-write control component is configured to write the data stored in the buffer into the external memory 120 and write the data stored in the external memory 120 into the internal memory.

It should be noted that, the fast block interleaving or deinterleaving method implemented by using the monolithic memory according to the embodiments of the present disclosure may be generally performed by the read/write control component. Accordingly, the fast block interleaving or deinterleaving apparatus implemented using a monolithic memory provided by the embodiments of the present disclosure may be generally provided in a read-write control component. The fast block interleaving or deinterleaving method implemented with monolithic memory provided by the embodiments of the present disclosure may also be performed by a component or cluster of components other than the read-write control component and capable of communicating with the buffer, the internal memory, the external memory 120, and/or the read-write control component. Accordingly, the fast block interleaving or deinterleaving apparatus implemented using a monolithic memory provided by the embodiments of the present disclosure may also be provided in a component or a cluster of components that are different from the read-write control component and are capable of communicating with the buffer, the internal memory, the external memory 120, and/or the read-write control component.

It should be understood that the number of buffers, internal memory, external memory, and read-write control components in fig. 1 are merely illustrative. There may be any number of buffers, internal memory, external memory, and read-write control components, as desired for implementation.

The fast block interleaving or deinterleaving method implemented using the monolithic memory of the disclosed embodiment will be described in detail below with reference to fig. 2 to 9 based on the scenario described in fig. 1.

Fig. 2 schematically illustrates a flow chart of a fast block interleaving or deinterleaving method implemented with a monolithic memory, in accordance with an embodiment of the present disclosure.

As shown in fig. 2, the fast block interleaving or deinterleaving method 200 implemented using a single chip memory of this embodiment includes operations S210 to S230.

In operation S210, initial data stored in the buffer is written into the external memory in response to the plurality of internal memories being in the data read-out state.

According to embodiments of the present disclosure, the number of internal memories is at least two, and may include a memory such as a simple dual-port random access memory (RandomAccess Memory, RAM) located inside the FGPA chip. The buffer may include a first-in first-out memory (First Input First Output, FIFO) located inside the FPGA chip. The initial data is stored in a buffer. The external Memory is located outside the FPGA chip and may include third generation double rate synchronous dynamic random access Memory (Double Data Rate Synchronous Dynamic Random-access Memory3, DDR 3).

According to the embodiment of the disclosure, since the external memory cannot perform the read and write operations at the same time, in order to preferentially ensure that readable data is in all of the plurality of internal memories, when all of the plurality of internal memories are in a data read state, it is not necessary to read the data in the external memory and write the data into the internal memory, and the initial data in the buffer can be written into the external memory by using the idle time of the external memory at this time, so that time is saved and efficiency is improved.

According to the embodiment of the disclosure, the FPGA chip receives external input data to be interleaved or deinterleaved, the data to be interleaved or deinterleaved is stored in the buffer, and the data can be subjected to bit width conversion and play a role in buffering before being written into the external memory.

For example, the external memory may be DDR3 with a memory bit width of 16 bits, and the amount of data read/write once is 128 bits. Therefore, the data size of the buffer processed by one read operation can be set to 128 bits, and the data size of the buffer processed by one write operation can be adjusted according to the requirements of the external front-end module.

In operation S220, in case of receiving a data read request returned from a target internal memory among the plurality of internal memories, a first unit offset and a second unit offset related to the external memory are determined based on a preset interleaving depth, a data read-write performance parameter of the external memory, and a first data bit width of the external memory.

According to an embodiment of the present disclosure, the target internal memory is an internal memory that is not in a read state among the plurality of internal memories. The data read request is a request returned by the target internal memory that requires reading data in the external memory and writing data to the target internal memory. The interleaving depth is the minimum distance between adjacent data before interleaving and after interleaving, and the preset interleaving depth is the preset value of the interleaving depth and can be adjusted according to requirements. The data read-write performance parameter of the external memory is used for representing the data quantity of the external memory which is subjected to one read or write operation, and is related to the read-write performance of the external memory. The first data bit width is used to characterize the number of data bits at each address in the external memory, and is related to the memory performance of the external memory. The first unit offset and the second unit offset are used to characterize a unit distance between an actual storage address of the data in the external memory and a base address of the external memory.

According to the embodiment of the disclosure, the internal memory which is not in the read state in the plurality of internal memories is determined to be the target internal memory, and at the moment, the target internal memory is in the idle state, and the target internal memory returns a data read request, so that readable data in the plurality of internal memories is ensured.

In operation S230, the initial data is interleaved and written into the target internal memory using a first row counter and a first column counter associated with the initial data based on the first unit offset and the second unit offset.

According to an embodiment of the present disclosure, the first row counter and the first column counter are used to determine a memory address when initial data in the external memory is read.

According to the embodiment of the present disclosure, based on the first unit offset and the second unit offset, the partial initial data to be read and written into the target internal memory can be determined using the first row counter and the first column counter.

According to the disclosed embodiment, initial data stored in the buffer is written into the external memory in response to the fact that the plurality of internal memories are in a data reading state, so that the external memory performs writing operation when in an idle state without reading operation, time required for reading and writing data is saved, the interleaving rate is improved, interleaving is realized by the aid of the external memory, the storage capacity of the interleaver is increased, and requirements of higher interleaving depth can be met. And determining the internal memory which is not in a read state in the plurality of internal memories as the target internal memory by judging the target internal memory in the plurality of internal memories, so as to ensure that readable data exist in the plurality of internal memories. By determining the first unit offset and the second unit offset, when the initial data stored in the external memory is read out, address control is realized based on the first unit offset and the second unit offset, and high-rate interleaving is further realized.

FIG. 3 schematically illustrates a flow chart of writing data to a target internal memory according to an embodiment of the disclosure.

As shown in fig. 3, the method includes operations S310 to S330.

In operation S310, a storage address of initial sub-data to be processed in the initial data is determined based on the count value of the first row counter, the count value of the first column counter, the first unit offset, and the second unit offset.

According to an embodiment of the present disclosure, the initial sub-data is a portion of the initial data to be processed, and data elements inside the initial sub-data are read out in a sequential reading manner.

According to an embodiment of the present disclosure, the count value of the first row counter is used to characterize the number of offset unit distances of the storage address of the initial sub-data with respect to the initial data base address in the row direction. The first column counter is used to characterize the number of the memory addresses of the initial sub-data shifted in the column direction by a unit distance with respect to the base address of the initial data.

According to the embodiment of the present disclosure, since interleaving of initial data is to be achieved by reading and writing of the initial data in the external memory, in the case where the initial data is sequentially written in the external memory, it is necessary to achieve random readout using address control by determining a storage address of the initial sub-data based on the count value of the first row counter, the count value of the first column counter, the first unit offset, and the second unit offset.

In operation S320, the initial sub-data is written into the target internal memory based on the storage address of the initial sub-data.

According to the embodiment of the disclosure, the initial sub-data to be processed is determined based on the storage address of the initial sub-data, and the initial sub-data to be processed in the external memory is read out and sequentially written into the target internal memory to complete interleaving of the initial data.

In operation S330, the respective count values of the first row counter and the first column counter are updated.

According to an embodiment of the present disclosure, an address of initial sub-data to be processed in initial data is determined by continuously updating respective count values of a first row counter and a first column counter.

According to the embodiment of the disclosure, when interleaving of initial data is realized in the external memory through read-write operation, the initial data is written into the external memory in a sequential manner, and then the initial data is read from the external memory in a random manner. The memory address of the first initial sub-data is first determined based on the count values of the current first row counter and the first column counter, and then the memory address of the second initial sub-data to be processed is determined through the change of the count values of the first row counter and the first column counter.

According to the embodiment of the disclosure, the storage address of the initial sub-data to be processed is determined by using the count values of the first row counter and the first column counter which are continuously updated based on the first unit offset and the second unit offset, and random reading of the initial data is realized through address control, so that interleaving of the initial data is realized.

FIG. 4 schematically illustrates a flow chart of determining an initial sub-data storage address according to an embodiment of the present disclosure.

As shown in fig. 4, the method includes operations S410 to S430.

In operation S410, a row address offset is determined based on the first unit offset and the count value of the first row counter.

According to an embodiment of the present disclosure, the row address offset is a product of a first unit offset and a count value of a first row counter, and is used to characterize an address offset of initial sub-data to be processed in a row direction.

For example, the first unit offset is 8192, the count value of the first row counter is 1, and the row address offset is 1×8192=8192.

In operation S420, a column address offset is determined based on the second unit offset and the count value of the first column counter.

According to an embodiment of the present disclosure, the column address offset is a product of the second unit offset and a count value of the first column counter, and is used to characterize an address offset of initial sub-data to be processed in a column direction.

For example, the second unit offset is 32, the count value of the second row counter is 3, and the column address offset is 3×32=96.

In operation S430, a storage address of the initial sub data is determined based on the initial storage address of the initial data, the row address offset and the column address offset of the initial sub data.

According to an embodiment of the present disclosure, the storage address of the initial sub-data is a sum of an initial storage address, a row address offset, and a column address offset of the initial data, and is used to characterize an actual storage address of the initial sub-data.

For example, the initial data has an initial memory address of 0, a row address offset of 8192, and a column address offset of 96, and the initial sub-data has a memory address of 0+8192+96=8288.

According to the embodiment of the disclosure, the actual storage address of the initial sub data is determined by calculating the row address offset and the column address offset, and the interleaving of the initial data is realized by address control.

According to an embodiment of the present disclosure, updating respective count values of a first row counter and a first column counter includes: updating the count value of the first row counter based on a first preset step length; and updating the count value of the first column counter based on the second preset step length under the condition that the count value of the first row counter is equal to the preset interleaving depth.

According to an embodiment of the present disclosure, the first preset step is a preset step value that is self-increased by the first line counter.

According to the embodiment of the disclosure, after one initial sub-data is completely written into the target internal memory, the self-increment operation is performed on the first row counter based on a first preset step size.

For example, the first preset step length is 1, the count value of the first row counter is 1, and after an initial sub-data is completely written into the target internal memory, the count value of the first row counter is self-increased by 1, and at this time, the count value of the first row counter is 2.

According to an embodiment of the present disclosure, the second preset step is a preset step value that is self-incremented by the first column counter.

According to the embodiment of the disclosure, the condition that the count value of the first row counter is equal to the preset interleaving depth indicates that one column of initial sub-data is completely written into the target internal memory, at this time, a plurality of initial sub-data to be processed in the next column needs to be determined, and based on a second preset step length, self-increasing operation is performed on the first column counter.

For example, the second preset step length is 1, the count value of the first column counter is 1, and when the count value of the first row counter is equal to the preset interleaving depth, the count value of the first column counter is self-increased by 1, and at this time, the count value of the first column counter is 2.

According to the embodiments of the present disclosure, the memory address of the initial sub-data can be accurately determined by updating the count value of the first row counter and the count value of the first column counter based on a certain condition and a preset step.

According to an embodiment of the present disclosure, in a case where it is determined that the count value of the first line counter is equal to a preset interleaving depth, the count value of the first line counter is reset to an initial value; and resetting the count value of the first column counter to an initial value under the condition that the count value of the first column counter is equal to a preset count value, wherein the preset count value is related to the data read-write performance parameter of the external memory and the first data bit width of the external memory.

According to the embodiment of the disclosure, the condition that the count value of the first row counter is equal to the preset interleaving depth indicates that one column of initial sub-data is already written into the internal memory, and at this time, the initial sub-data to be processed in the first one of the plurality of initial sub-data to be processed in the next column needs to be determined, so the count value of the first row counter needs to be reset to the initial value, and the storage address of the initial sub-data to be processed in the first one of the plurality of initial sub-data to be processed in the next column needs to be determined.

According to the embodiment of the disclosure, the preset count value is obtained by performing a division operation on the basis of the data read-write performance parameter of the external memory and the first data bit width of the external memory.

According to the embodiment of the disclosure, the condition that the count value of the first column counter is equal to the preset count value indicates that the first initial data is already written into the internal memory, at this time, the second initial data needs to be processed, the count value of the first column counter is reset to the initial value, and the initial storage address of the second initial data can be determined.

According to the embodiment of the disclosure, the first row counter and the first column counter are reset, and initial data stored in the external memory is continuously written into the internal memory through address control, so that data processing efficiency is improved.

FIG. 5 schematically illustrates a flow chart of writing initial sub-data to a target internal memory according to an embodiment of the disclosure.

As shown in FIG. 5, the method includes operations S510-S530.

In operation S510, the initial sub-data is split into a plurality of data blocks based on the data read-write performance parameters of the external memory.

According to an embodiment of the present disclosure, a data block is data that is subjected to one read or write operation processing for an external memory.

For example, the initial sub-data has a data size of 512 bits, and the external memory performs a read or write operation to process the data size of 128 bits, and then each initial sub-data is split into 4 data blocks.

In operation S520, the respective memory addresses of the plurality of data blocks are determined based on the memory addresses of the initial sub data.

According to the embodiment of the disclosure, since the initial sub data is a segment of data with consecutive storage addresses, the storage addresses of the plurality of data blocks are adjacent, and thus the respective storage addresses of the plurality of data blocks can be determined based on the storage position of the initial sub data.

In operation S530, the plurality of data blocks are sequentially written into the target internal memory based on the respective memory addresses of the plurality of data blocks.

According to an embodiment of the present disclosure, a data block is read out from an external memory and sequentially written into a target internal memory based on a storage address of the data block.

According to the embodiment of the disclosure, the reading speed of the initial data is improved by sequentially reading a plurality of data blocks in the initial sub data, and the speed of interleaving the initial data is further improved.

According to an embodiment of the present disclosure, determining a first unit offset and a second unit offset related to an external memory based on a preset interleaving depth, a data read-write performance parameter of the external memory, and a first data bit width of the external memory, includes: based on the data quantity of the initial data, presetting an interleaving depth and a first data bit width of an external memory, and determining a first unit offset; the second unit offset is determined based on the data read-write performance parameter of the external memory and the first data bit width of the external memory.

According to an embodiment of the present disclosure, initial data stored in the external memory may be regarded as a first matrix, the number of first matrix rows being equal to a preset interleaving depth. And dividing the data quantity of the initial data with a preset interleaving depth to obtain the data quantity which can be contained in each row of the matrix, and dividing the data quantity which can be contained in each row of the matrix with the first data bit width of the external memory to obtain the first unit offset. And multiplying the data quantity of the external memory subjected to one-time reading or writing operation by the times of sequential reading to obtain the continuously read data quantity, and dividing the continuously read data quantity by the first bit width of the external memory to obtain the second unit offset.

According to the embodiment of the disclosure, the initial data is divided into units by determining the first unit offset and the second unit offset, so that interleaving of the initial data is facilitated.

According to the embodiment of the present disclosure, DDR3 having a data bit width of 16 bits and a data amount of 128 bits processed by one read or write operation is taken as an external memory, a data amount of initial data is 1Gbit, and a preset interleaving depth is 8192 as an example, but not limited thereto, a storage structure of initial data in the external memory may refer to fig. 6.

Fig. 6 schematically illustrates a storage structure diagram of initial data in an external memory according to an embodiment of the present disclosure.

As shown in fig. 6, the number of first matrix rows is 8192, which is equal to the preset interleaving depth. The amount of data accommodated per line is 1 Gbit/8192=2 ¹⁷ bit. Since the first bit width of the external memory is 16 bits, i.e. the number of data bits stored in each address in the external memory is 16 bits, the data size of each first unit data is 16 bits, and the number of first matrix columns is 2 ¹⁷ bit ≡16bit = 8192, i.e. the first matrix holds 8192 first units of data per row.

According to the embodiment of the present disclosure, since the data amount of one read or write of the external memory is 128 bits, and when the initial data is written to the target internal memory, the initial sub-data is read out randomly for the initial data read-out manner, and the data block is read out sequentially for the initial sub-data read-out manner. The structure of reading initial data in the external memory may refer to the structure shown in fig. 7.

Fig. 7 schematically illustrates a read structure diagram of initial data in an external memory according to an embodiment of the present disclosure.

As shown in fig. 7, when the initial data stored in the external memory is read, the data size for continuous reading is 512 bits, that is, the data size of the initial sub-data is 512 bits, the first matrix contains 256 initial sub-data per row, the data block size is 128 bits, and 4 data blocks are contained in each initial sub-data.

According to the embodiment of the disclosure, the initial data in the external memory is read without changing the storage mode of the initial data in the external memory, and the data size of each first unit data is still 16 bits. The number of the first unit data contained in each row in the initial data is a first unit offset, and the number of the first unit data contained in each initial sub-data is a second unit offset. The memory address of the initial sub-data to be processed can be determined by the first unit offset and the second unit offset.

According to an embodiment of the present disclosure, the first unit offset is 8192 and the second unit offset is 512 bits/16 bits=32. The first preset step length and the second preset step length are both 1, the initial address of the initial data is 0, and the initial values of the first row counter and the first column counter are both 0.

According to the embodiment of the disclosure, when the row address offset is 0 and the column address offset is 0, the initial sub-data of the first row and the first column are read, the count value of the first row counter is increased by 1 after the reading is completed, and the initial sub-data to be processed, i.e. the initial sub-data of the first column of the second row, with the storage address of 1×8192+0=8192 is read. According to the method, after all the initial sub-data of the first column are read, the count value of the first column counter is increased by 1, the count value of the first row counter is reset to be an initial value of 0, and the storage address of the initial sub-data to be processed is determined to be 0+1×32=32, namely the initial sub-data of the second column of the first row. According to the method, 256 columns of initial sub-data are completely read, and the first row counter and the first column counter are reset to an initial value of 0.

Fig. 8 schematically illustrates a flowchart of reading out target data according to an embodiment of the present disclosure.

As shown in fig. 8, the method includes operations S810 to S820.

In operation S810, a number of rows and a number of columns associated with the internal memory are determined based on the second bit width of the internal memory.

According to an embodiment of the present disclosure, the second bit width of the internal memory is the number of data bits stored at each memory address in the internal memory, and is related to the memory performance of the internal memory. The second bit width characterizes a data size of each second unit data in the target data.

According to the embodiment of the disclosure, the storage structure of the internal memory may be regarded as a second matrix, where the number of rows of the second matrix is equal to a preset interleaving depth, and the size of the data amount contained in each row of the second matrix is the size of the data amount of one initial sub-data. And dividing the data volume contained in each row of the second matrix with the second bit width to obtain the column number value of the second matrix.

For example, the second bit width of the internal memory is 8 bits, and the data size stored at each memory address in the internal memory is 8 bits, i.e., the data size of each second unit data in the internal memory is 8 bits. The initial sub-data has a data size of 512 bits, and the number of columns of the second matrix has a value of 512 bits/8 bits=64.

In operation S820, the interleaved target data in the internal memory is read out using the second row counter and the second column counter based on the number of rows and the number of columns.

According to an embodiment of the present disclosure, the second row counter is used to characterize the number by which the storage address of the second unit data to be read out is shifted in the row direction with respect to the target data base address. The second column counter is used to characterize the number by which the storage address of the second unit data to be read out is shifted in the column direction with respect to the target data base address. And multiplying the count value of the second row counter with the column number value to obtain a row address of the second unit data, multiplying the count value of the second column counter with the column number value to obtain a column address of the second unit data, and adding the base address of the target data, the row address of the second unit data and the column address of the second unit data to obtain a storage address of the second unit data to be read.

For example, the number of rows of the second matrix is 8192, the number of columns is 64, the base address of the target data is 0, the count value of the second row counter is 2, the count value of the second column counter is 1, and at this time, the storage address of the second unit data to be read out is 0+2×64+1×8192=8320.

According to the embodiment of the disclosure, the size of the data amount of the internal memory for performing one read operation is set to be equal to the second bit width, and then the internal memory performs one read operation for only processing one data.

According to an embodiment of the present disclosure, the count value of the second row counter is self-incremented by 1 every time one second unit data is read out. When the count value of the second row counter is equal to the number of rows, the count value of the second row counter is reset to 0, and the count value of the second column counter is self-incremented by 1. In the case where the count value of the second column counter is equal to the column number value, the count value of the second column counter is reset to 0.

According to the embodiment of the present disclosure, since the form of writing the target data into the internal memory is sequential writing, interleaving of the target data in the internal memory is achieved by random reading. And determining the position of the second data to be read through a second row counter, a second column counter, a row number value and a column number value, and realizing random reading through address control.

According to the embodiment of the disclosure, the target data stored in the internal memory is randomly read, and is interleaved again, so that the interleaving of the data is more sufficient, and the error correction performance is improved.

According to the embodiment of the present disclosure, a RAM with a data bit width of 8 bits and a data amount of 8 bits is used as an internal memory, and the data amount of the target data is equal to the data amount of a column of initial sub-data in the initial data, but not limited thereto, and the storage structure of the target data in the internal memory may refer to fig. 9.

Fig. 9 schematically illustrates a storage structure diagram of target data in an internal memory according to an embodiment of the present disclosure.

As shown in fig. 9, the number of rows of the second matrix is 8192, which is equal to the preset interleaving depth, and the amount of data contained in each row is 512 bits of the data amount of one initial sub-data. Since the second bit width of the internal memory is 8 bits, that is, the number of data bits stored in each address in the internal memory is 8 bits, the data size of each second unit data is 8 bits, and the column number value of the second matrix is 512 bits/8 bits=64, that is, the second matrix accommodates 64 second unit data per row.

According to the embodiment of the disclosure, the data size of one read operation of the internal memory is set to be equal to the second bit width, and the data size of one read operation of the internal memory is set to be 8 bits.

According to the embodiment of the disclosure, the initial values of the second row counter and the second column counter are both 0, the base address of the target data in the internal memory is 0, at this time, the second unit data with the storage address of 0, that is, the second unit data of the first row and the first column in the second matrix, is read out, the count value of the second row counter is self-increased by 1 after the reading out is completed, and the storage address of the second unit data to be read is determined to be 0+1×64+0=64. According to the method, after one row of second unit data in the target data is completely read out, the second row counter is self-increased by 1, the second row counter is reset to 0, and the storage address of the second unit data to be processed is determined to be 0+0+1×8192=8192, namely the second unit data of the second row of the first row. After the reading of the 64 columns of the second unit data is completed according to the method, the count values of the second row counter and the second column counter are reset to 0.

Based on the above-mentioned fast block interleaving or de-interleaving method implemented by using the monolithic memory, the present disclosure also provides a fast block interleaving or de-interleaving device implemented by using the monolithic memory. The device will be described in detail below in connection with fig. 10.

Fig. 10 schematically illustrates a block diagram of a fast block interleaving or deinterleaving apparatus implemented using a monolithic memory, in accordance with an embodiment of the present disclosure.

As shown in fig. 10, the fast block interleaving or deinterleaving apparatus 1000 implemented using a single chip memory of this embodiment includes a memory writing module 1010, an offset determining module 1020, and a memory writing module 1030.

The external memory writing module 1010 is configured to write the initial data stored in the buffer into the external memory in response to the plurality of internal memories being in the data read state. In an embodiment, the external memory writing module 1010 may be used to perform the operation S210 described above, which is not described herein.

The offset determining module 1020 is configured to determine, when receiving a data read request returned by a target internal memory of the plurality of internal memories, a first unit offset and a second unit offset related to the external memory based on a preset interleaving depth, a data read-write performance parameter of the external memory, and a first data bit width of the external memory. In an embodiment, the offset determining module 1020 may be configured to perform the operation S220 described above, which is not described herein.

The memory writing module 1030 is configured to interleave and write the initial data into the target internal memory using a first row counter and a first column counter associated with the initial data based on the first unit offset and the second unit offset. In an embodiment, the memory writing module 1030 may be used to perform the operation S230 described above, which is not described herein.

According to an embodiment of the present disclosure, the memory writing module further includes an address determination sub-module, a data writing sub-module, and a count value updating sub-module.

The address determining sub-module is used for determining a storage address of initial sub-data to be processed in the initial data based on the count value of the first row counter, the count value of the first column counter, the first unit offset and the second unit offset.

The data writing sub-module is used for writing the initial sub-data into the target internal memory based on the storage address of the initial sub-data.

The count value updating sub-module is used for updating the count value of each of the first row counter and the first column counter.

According to an embodiment of the present disclosure, the address determination sub-module further includes a first determination unit, a second determination unit, and an address determination unit.

The first determining unit is configured to determine a row address offset based on the first unit offset and a count value of the first row counter.

The second determining unit is configured to determine a column address offset based on the second unit offset and a count value of the first column counter.

The address determining unit is used for determining a storage address of the initial sub-data based on an initial storage address of the initial data, the row address offset and the column address offset of the initial sub-data.

According to an embodiment of the present disclosure, the count update sub-module further includes a row update unit and a column update unit.

The row updating unit is used for updating the count value of the first row counter based on a first preset step length.

The column updating unit is used for updating the count value of the first column counter based on a second preset step length under the condition that the count value of the first row counter is equal to the preset interleaving depth.

According to an embodiment of the present disclosure, the count update sub-module further includes a row reset unit and a column reset unit.

The row resetting unit is used for resetting the count value of the first row counter to an initial value under the condition that the count value of the first row counter is equal to the preset interleaving depth.

The column resetting unit is used for resetting the count value of the first column counter to an initial value under the condition that the count value of the first column counter is equal to a preset count value, wherein the preset count value is related to the data read-write performance parameter of the external memory and the first data bit width of the external memory.

According to an embodiment of the present disclosure, the data writing sub-module further includes a data block segmentation unit, a data block determination unit, and a data block writing unit.

The data block segmentation unit is used for segmenting the initial sub-data into a plurality of data blocks based on the data read-write performance parameters of the external memory.

The data block determining unit is used for determining the storage addresses of the plurality of data blocks respectively based on the storage addresses of the initial sub-data.

The data block writing unit is used for writing the plurality of data blocks into the target internal memory in sequence based on the storage addresses of the plurality of data blocks.

According to an embodiment of the present disclosure, the offset determination module 1020 further includes a first determination sub-module and a second determination sub-module.

The first determining submodule is used for determining the first unit offset based on the data quantity of the initial data, the preset interleaving depth and the first data bit width of the external memory.

The second determining submodule is used for determining the second unit offset based on the data read-write performance parameter of the external memory and the first data bit width of the external memory.

According to an embodiment of the present disclosure, the fast block interleaving or deinterleaving apparatus 1000 implemented with a monolithic memory further includes a rank number determination module and a memory readout module.

The rank number determining module is used for determining a row number value and a column number value related to the internal memory based on the second bit width of the internal memory.

The memory reading module is used for reading the target data obtained by interleaving in the internal memory by utilizing a second row counter and a second column counter based on the row number value and the column number value.

Any of the memory writing module 1010, the offset determining module 1020, and the memory writing module 1030 may be combined in one module to be implemented, or any of the modules may be split into a plurality of modules according to an embodiment of the present disclosure. Alternatively, at least some of the functionality of one or more of the modules may be combined with at least some of the functionality of other modules and implemented in one module. At least one of the memory write module 1010, the offset determination module 1020, and the memory write module 1030 may be implemented at least in part as hardware circuitry, such as a Field Programmable Gate Array (FPGA), a Programmable Logic Array (PLA), a system on a chip, a system on a substrate, a system on a package, an Application Specific Integrated Circuit (ASIC), or in hardware or firmware in any other reasonable manner of integrating or packaging circuitry, or in any one of or a suitable combination of three of software, hardware, and firmware, according to embodiments of the present disclosure. Alternatively, at least one of the memory writing module 1010, the offset determining module 1020, and the memory writing module 1030 may be at least partially implemented as a computer program module that, when executed, performs the corresponding functions.

Fig. 11 schematically illustrates a block diagram of an electronic device suitable for implementing a fast block interleaving or de-interleaving method implemented using a monolithic memory according to an embodiment of the present disclosure.

As shown in fig. 11, an electronic device 1100 according to an embodiment of the present disclosure includes a processor 1101 that can perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM) 1102 or a program loaded from a storage section 1108 into a Random Access Memory (RAM) 1103. The processor 1101 may include, for example, a general purpose microprocessor (e.g., a CPU), an instruction set processor and/or an associated chipset and/or a special purpose microprocessor (e.g., an Application Specific Integrated Circuit (ASIC)), or the like. The processor 1101 may also include on-board memory for caching purposes. The processor 1101 may comprise a single processing unit or a plurality of processing units for performing the different actions of the method flow according to embodiments of the present disclosure.

In the RAM 1103, various programs and data necessary for the operation of the electronic device 1100 are stored. The processor 1101, ROM 1102, and RAM 1103 are connected to each other by a bus 1104. The processor 1101 performs various operations of the method flow according to the embodiments of the present disclosure by executing programs in the ROM 1102 and/or the RAM 1103. Note that the program may be stored in one or more memories other than the ROM 1102 and the RAM 1103. The processor 1101 may also perform various operations of the method flow according to embodiments of the present disclosure by executing programs stored in the one or more memories.

According to an embodiment of the disclosure, the electronic device 1100 may also include an input/output (I/O) interface 1105, the input/output (I/O) interface 1105 also being connected to the bus 1104. The electronic device 1100 may also include one or more of the following components connected to the I/O interface 1105: an input section 1106 including a keyboard, a mouse, and the like; an output portion 1107 including a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), and the like, a speaker, and the like; a storage section 1108 including a hard disk or the like; and a communication section 1109 including a network interface card such as a LAN card, a modem, and the like. The communication section 1109 performs communication processing via a network such as the internet. The drive 1110 is also connected to the I/O interface 1105 as needed. Removable media 1111, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like, is installed as needed in drive 1110, so that a computer program read therefrom is installed as needed in storage section 1108.

The present disclosure also provides a computer-readable storage medium that may be embodied in the apparatus/device/system described in the above embodiments; or may exist alone without being assembled into the apparatus/device/system. The computer-readable storage medium carries one or more programs which, when executed, implement methods in accordance with embodiments of the present disclosure.

According to embodiments of the present disclosure, the computer-readable storage medium may be a non-volatile computer-readable storage medium, which may include, for example, but is not limited to: a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this disclosure, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. For example, according to embodiments of the present disclosure, the computer-readable storage medium may include ROM 1102 and/or RAM 1103 described above and/or one or more memories other than ROM 1102 and RAM 1103.

Embodiments of the present disclosure also include a computer program product comprising a computer program containing program code for performing the methods shown in the flowcharts. The program code, when executed in a computer system, causes the computer system to implement the item recommendation method provided by embodiments of the present disclosure.

The above-described functions defined in the system/apparatus of the embodiments of the present disclosure are performed when the computer program is executed by the processor 1101. The systems, apparatus, modules, units, etc. described above may be implemented by computer program modules according to embodiments of the disclosure.

In one embodiment, the computer program may be based on a tangible storage medium such as an optical storage device, a magnetic storage device, or the like. In another embodiment, the computer program can also be transmitted, distributed over a network medium in the form of signals, downloaded and installed via the communication portion 1109, and/or installed from the removable media 1111. The computer program may include program code that may be transmitted using any appropriate network medium, including but not limited to: wireless, wired, etc., or any suitable combination of the foregoing.

In such an embodiment, the computer program can be downloaded and installed from a network via the communication portion 1109, and/or installed from the removable media 1111. The above-described functions defined in the system of the embodiments of the present disclosure are performed when the computer program is executed by the processor 1101. The systems, devices, apparatus, modules, units, etc. described above may be implemented by computer program modules according to embodiments of the disclosure.

According to embodiments of the present disclosure, program code for performing computer programs provided by embodiments of the present disclosure may be written in any combination of one or more programming languages, and in particular, such computer programs may be implemented in high-level procedural and/or object-oriented programming languages, and/or assembly/machine languages. Programming languages include, but are not limited to, such as Java, c++, python, "C" or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, partly on a remote computing device, or entirely on the remote computing device or server. In the case of remote computing devices, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., connected via the Internet using an Internet service provider).

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Those skilled in the art will appreciate that the features recited in the various embodiments of the disclosure and/or in the claims may be provided in a variety of combinations and/or combinations, even if such combinations or combinations are not explicitly recited in the disclosure. In particular, the features recited in the various embodiments of the present disclosure and/or the claims may be variously combined and/or combined without departing from the spirit and teachings of the present disclosure. All such combinations and/or combinations fall within the scope of the present disclosure.

The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.

Claims (10)

1. A fast block interleaving or de-interleaving method implemented using a monolithic memory, comprising:

writing the initial data stored in the buffer into the external memory in response to the plurality of internal memories being in a data read-out state;

Under the condition that a data reading request returned by a target internal memory in the plurality of internal memories is received, determining a first unit offset and a second unit offset related to the external memory based on a preset interleaving depth, a data reading and writing performance parameter of the external memory and a first data bit width of the external memory; and

the initial data is interleaved and written into the target internal memory using a first row counter and a first column counter associated with the initial data based on the first unit offset and the second unit offset.

2. The method of claim 1, wherein the interleaving the initial data into the target internal memory based on the first unit offset and the second unit offset using a first row counter and a first column counter associated with the initial data comprises:

determining a storage address of initial sub-data to be processed in the initial data based on the count value of the first row counter, the count value of the first column counter, the first unit offset and the second unit offset;

writing the initial sub-data into the target internal memory based on the storage address of the initial sub-data; and

And updating the count values of the first row counter and the first column counter respectively.

3. The method of claim 2, wherein the determining the storage address of the initial sub-data based on the count value of the first row counter, the count value of the first column counter, the first unit offset, and the second unit offset comprises:

determining a row address offset based on the first unit offset and a count value of the first row counter;

determining a column address offset based on the second unit offset and a count value of the first column counter; and

a storage address of the initial sub-data is determined based on an initial storage address of the initial data, the row address offset and the column address offset of the initial sub-data.

4. The method of claim 2, wherein the updating the respective count values of the first row counter and the first column counter comprises:

updating the count value of the first row counter based on a first preset step length; and

and updating the count value of the first column counter based on a second preset step length under the condition that the count value of the first row counter is equal to the preset interleaving depth.

5. The method of claim 4, further comprising:

resetting the count value of the first row counter to an initial value under the condition that the count value of the first row counter is equal to the preset interleaving depth; and

and resetting the count value of the first column counter to an initial value under the condition that the count value of the first column counter is equal to a preset count value, wherein the preset count value is related to the data read-write performance parameter of the external memory and the first data bit width of the external memory.

6. The method of claim 2, wherein the writing the initial sub-data to the target internal memory based on the storage address of the initial sub-data comprises:

dividing the initial sub-data into a plurality of data blocks based on the data read-write performance parameters of the external memory;

determining the storage addresses of the data blocks respectively based on the storage addresses of the initial sub-data; and

and writing the plurality of data blocks into the target internal memory in turn based on the respective memory addresses of the plurality of data blocks.

7. The method of claim 1, wherein the determining the first unit offset and the second unit offset associated with the external memory based on the preset interleaving depth, the data read-write performance parameter of the external memory, and the first data bit width of the external memory comprises:

Determining the first unit offset based on the data amount of the initial data, the preset interleaving depth and the first data bit width of the external memory; and

and determining the second unit offset based on the data read-write performance parameter of the external memory and the first data bit width of the external memory.

8. The method of claim 1, further comprising:

determining a number of rows and a number of columns associated with the internal memory based on a second bit width of the internal memory; and

and reading out the interleaved target data in the internal memory by using a second row counter and a second column counter based on the row number value and the column number value.

9. A fast block interleaving or de-interleaving apparatus implemented using a monolithic memory, comprising:

the external memory writing module is used for writing the initial data stored in the buffer into the external memory in response to the fact that the plurality of internal memories are in a data reading state;

the offset determining module is used for determining a first unit offset and a second unit offset related to the external memory based on a preset interleaving depth, a data read-write performance parameter of the external memory and a first data bit width of the external memory under the condition that a data read request returned by a target internal memory in the plurality of internal memories is received; and

And the memory writing module is used for interweaving and writing the initial data into the target internal memory by using a first row counter and a first column counter which are related to the initial data based on the first unit offset and the second unit offset.

10. An electronic device, comprising:

one or more processors;

storage means for storing one or more programs,

wherein the one or more programs, when executed by the one or more processors, cause the one or more processors to perform the method of any of claims 1-8.