CN117007861A - FPGA-based spectrum analysis system and method - Google Patents

FPGA-based spectrum analysis system and method Download PDF

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CN117007861A
CN117007861A CN202310952702.9A CN202310952702A CN117007861A CN 117007861 A CN117007861 A CN 117007861A CN 202310952702 A CN202310952702 A CN 202310952702A CN 117007861 A CN117007861 A CN 117007861A
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spectrum analysis
frequency
fft
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fpga
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苏立新
宋美艳
雷超
焦龙
钟庆尧
李卓
管磊
高少华
辛志波
孙浩沩
张斌
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Xian Thermal Power Research Institute Co Ltd
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Abstract

The application belongs to the technical field of spectrum analysis, and discloses a spectrum analysis system and a method based on FPGA; the spectrum analysis system includes: the system comprises a clock and reset unit, a system reset unit, an SPI unit, a register read-write distribution unit and a plurality of channel spectrum analysis units which are realized based on an FPGA; wherein each channel spectrum analysis unit includes: the ADC control unit is used for acquiring a digital signal to be subjected to spectrum analysis; the FIR filtering unit is used for performing filtering processing to obtain a filtered digital signal; the FFT calculation unit is used for carrying out FFT calculation and obtaining an initial spectrum analysis result; and the FFT calibration compensation unit is used for performing calibration compensation to obtain a final spectrum analysis result. According to the application, through software filtering, the filtering parameters are adjustable; the accuracy of the calculation of the sampled signal as a multiple of non-Fs/N subharmonic can be improved.

Description

FPGA-based spectrum analysis system and method
Technical Field
The application belongs to the technical field of spectrum analysis, and particularly relates to a spectrum analysis system and method based on FPGA (Field Programmable Gate Array ).
Background
In industrial control, in order to acquire the operation state of the working equipment, it is generally necessary to acquire and perform spectral analysis on a relevant signal reflecting the operation state of the equipment.
Currently, in the existing spectrum analysis scheme, an ADC (Analog-to-digital converter) and FPGA are mainly used in combination; exemplary, manufacturers such as mitsubishi relate to the development of FFT cards. However, in the existing spectrum analysis scheme, the ADC sampling frequency is fixed, and the application range is limited by hardware filtering; in addition, for the result that the sampled signal is not the multiple subharmonic of Fs/N, the existing scheme does not perform calculation compensation, and the defect of inaccurate calculation result exists; illustratively, fs is the sampling frequency and N is the FFT (Fast Fourier Transformation, fast fourier transform) calculation point number.
Disclosure of Invention
The application aims to provide a spectrum analysis system and a spectrum analysis method based on an FPGA, which are used for solving one or more technical problems. In the technical scheme provided by the application, through software filtering, the filtering parameters are adjustable, and the application range is wider; the accuracy of the calculation result of the sampled signal as a multiple of subharmonics other than Fs/N can be improved by calculation compensation.
In order to achieve the above purpose, the application adopts the following technical scheme:
the application provides a spectrum analysis system based on FPGA, comprising: the system comprises a clock and reset unit, a system reset unit, an SPI unit, a register read-write distribution unit and a plurality of channel spectrum analysis units which are realized based on an FPGA; wherein,
each of the plurality of channel spectrum analysis units includes:
the ADC control unit is used for being connected with an external ADC through an ADC interface and periodically driving the ADC to work so as to acquire a digital signal to be subjected to spectrum analysis;
the FIR filtering unit is used for inputting the digital signal acquired by the ADC control unit and carrying out filtering processing to acquire a filtered digital signal;
the FFT calculation unit is used for converting the filtered digital signals into a data format required by an FFT IP core, and carrying out FFT calculation to obtain an initial spectrum analysis result;
the FFT calibration compensation unit is used for carrying out calibration compensation on the initial spectrum analysis result to obtain a final spectrum analysis result; the step of performing calibration compensation specifically includes: the initial frequency spectrum analysis output frequency point is calculated to be under the configured fundamental wave frequency, and the calculated frequency is obtained; searching a pre-stored scaling factor according to the calculated frequency; and performing calibration compensation based on the scaling coefficient to obtain a final spectrum analysis result.
In the FFT calibration compensation unit, in the step of calculating the initial frequency spectrum analysis output frequency point to the configured fundamental wave frequency and obtaining the calculated frequency,
the reduction expression is f j ＝round(n i ×F s /N/f j0 )×f j0 ；
Wherein f j The frequency after the calculation; round is a rounding function; n is n i The index of the FFT output frequency point is taken as 0 to (N-1), and N is the FFT calculation point number; f (F) s Is the sampling frequency; f (f) j0 Is the calculated fundamental frequency.
The application further improves that, in the FFT calibration compensation unit, the step of searching the pre-stored scaling coefficient according to the frequency after the reduction comprises the following steps:
taking the frequency after the reduction as a ROM address, and reading a pre-stored scaling coefficient in the ROM according to the ROM address;
under different frequencies, scaling coefficients between the FFT output result and an actual value or a code value are pre-stored in an initialization file of the FPGAROM; the address of the initialization file is frequency, and the output signal is a scaling factor.
The application further improves that under the different frequencies, the step of obtaining the scaling coefficient between the FFT output result and the actual value or the code value comprises the following steps:
sequentially carrying out FFT analysis on signals with amplitude being An and frequency being 1-Fs/2 in An enumeration mode, dividing the amplitude being of the signals under each frequency by the maximum value Am of FFT analysis results, and obtaining a scaling factor kn under the corresponding frequency; wherein the calculation expression is kn=an/Am.
The application further improves that, in the FFT calibration compensation unit, the calibration compensation is carried out based on the scaling coefficient, and the step of obtaining the final spectrum analysis result comprises the following steps:
multiplying the obtained scaling coefficient with the FFT harmonic amplitude before the reduction in the initial spectrum analysis result to obtain the amplitude of the calibrated and compensated harmonic, and obtaining the final spectrum analysis result.
A further improvement of the present application is that,
the clock and reset unit is used for providing a unified internal clock for the spectrum analysis system based on the phase-locked loop and resetting the phase-locked loop when the clock locking signal is unlocked;
the system reset unit is used for generating a system reset signal when the clock locking signal is out of lock, and delaying to cancel the system reset signal after the internal clock is normal, so that all the function units of the FPGA are in a stable state;
the SPI unit is used for interacting with an external MCU, analyzing SPI interface signals sent by the MCU, extracting addresses, commands and lengths, and writing and reading data of the FPGA register by the MCU according to read-write commands;
the register unit comprises an ADC sampling frequency configuration register, a filter parameter configuration register, an FFT calibration compensation configuration register and an FFT calculation result register;
the register read-write distribution unit is used for converting the command extracted according to the SPI interface signal into read-write operation for the internal registers and respectively generating corresponding read-write operation signals for the registers which belong to different functions.
A further improvement of the present application is that,
the ADC sampling frequency configuration register is used for configuring the sampling frequency of the ADC according to the fundamental wave frequency, and periodically starting the ADC to acquire signals;
the filter parameter configuration register is used for pre-storing a plurality of groups of filter parameters and configuring a required filter on line according to requirements;
the FFT calibration compensation configuration register is used for configuring fundamental frequency of the sampled signal;
the FFT calculation result register is used for storing a final spectrum analysis result so as to read data by the register read-write distribution unit.
A further improvement of the present application is that each of the plurality of channel spectrum analysis units further comprises:
and the comparison unit is used for finding out the maximum value of each frequency band and the corresponding frequency point from the final frequency spectrum analysis result of the corresponding channel according to the frequency band configuration, and writing the maximum value and the corresponding frequency point into the corresponding register.
The second aspect of the application provides a spectrum analysis method based on an FPGA, which is based on the spectrum analysis system based on the FPGA of the first aspect of the application;
the FPGA-based spectrum analysis method comprises the following steps of:
the ADC control unit is connected with an external ADC through an ADC interface and periodically drives the ADC to work to acquire a digital signal to be subjected to spectrum analysis;
the FIR filtering unit inputs the digital signal obtained by the ADC control unit and performs filtering processing to obtain a filtered digital signal;
the FFT calculation unit converts the filtered digital signal into a data format required by an FFT IP core, and performs FFT calculation to obtain an initial spectrum analysis result;
the FFT calibration compensation unit performs calibration compensation on the initial spectrum analysis result to obtain a final spectrum analysis result; the step of performing calibration compensation specifically includes: the initial frequency spectrum analysis output frequency point is calculated to be under the configured fundamental wave frequency, and the calculated frequency is obtained; searching a pre-stored scaling factor according to the calculated frequency; and performing calibration compensation based on the scaling coefficient to obtain a final spectrum analysis result.
The application is further improved in that, in the step of calculating the initial frequency spectrum analysis output frequency point to the configured fundamental wave frequency and obtaining the calculated frequency,
the reduction expression is f j ＝round(n i ×F s /N/f j0 )×f j0 ；
Wherein f j The frequency after the calculation; round is a rounding function; n is n i The index of the FFT output frequency point is taken as 0 to (N-1), and N is the FFT calculation point number; f (F) s Is the sampling frequency; f (f) j0 The fundamental frequency is calculated;
the step of searching for pre-stored scaling factors according to the calculated frequency comprises the following steps: taking the frequency after the reduction as a ROM address, and reading a pre-stored scaling coefficient in the ROM according to the ROM address; under different frequencies, scaling coefficients between the FFT output result and an actual value or a code value are pre-stored in an initialization file of the FPGA ROM; the address of the initialization file is frequency, and the output signal is a scaling factor.
Compared with the prior art, the application has the following beneficial effects:
the FPGA-based spectrum analysis system provided by the application is provided with the FIR filtering unit, different filtering parameters are configured through the register to carry out software filtering, and the filtering parameters are adjustable and have a wider application range; an FFT calibration compensation unit is arranged, and the accuracy of the calculation result of the sampled signal which is not the multiple of Fs/N subharmonic can be improved through calculation compensation. Further specifically explaining, ADC sampling frequency and software FIR filtering parameters can be modified in a register configuration mode, the sampling frequency spectrum is wider, corresponding sampling frequency can be configured according to fundamental waves of signals, and the calculation accuracy of FFT calculation is improved; and an FFT calibration compensation module is added, calibration compensation is carried out on the sampled signal which is not the multiple harmonic of fs/N, and the calculation accuracy is improved. In summary, the application is suitable for FFT of arbitrary fundamental wave frequency and harmonic wave thereof, and can effectively improve the calculation accuracy and the application range of FFT analysis.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following description of the embodiments or the drawings used in the description of the prior art will make a brief description; it will be apparent to those of ordinary skill in the art that the drawings in the following description are of some embodiments of the application and that other drawings may be derived from them without undue effort.
Fig. 1 is a schematic diagram of each channel spectrum analysis unit in a spectrum analysis system based on FPGA according to an embodiment of the present application;
FIG. 2 is a schematic diagram of the internal logic architecture of an FPGA according to an embodiment of the present application;
FIG. 3 is a schematic diagram of the data flow of the present FFT card in the prior art;
fig. 4 is a schematic diagram of the relation between the FFT calculation result and the code value amplitude, where n=1024, the fundamental wave frequency of the signal is Fs/N, and the fundamental wave is arbitrary in the embodiment of the present application; wherein, the example parameter is fs=51.2 kHz, the graph (a) in fig. 4 is a schematic diagram with fundamental wave frequency of 1-Fs/2, and the graph (b) in fig. 4 is a schematic diagram with fundamental wave frequency of 50 Hz;
FIG. 5 is a comparison of uncompensated FFT results with calibration compensated FFT results for an embodiment of the application where N=1024, fs=51.2 kHz, and the fundamental frequency is 60Hz (not satisfying the fundamental frequency of Fs/N); in fig. 5, the graph (a) shows a schematic time domain waveform of an ac signal, and the signal composition is 2·sin (2·pi·60·t) +sin (2·pi·12·60·t) +sin (2·pi·99·60·t) +sin (2·pi·199·60·t); FIG. 5 (b) is a schematic diagram of an uncalibrated spectrum; FIG. 5 (c) is a diagram of the spectrum after calibration according to an embodiment of the present application;
fig. 6 is a data flow diagram of an FFT card according to an embodiment of the present application.
Detailed Description
In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The application is described in further detail below with reference to the attached drawing figures:
referring to fig. 1, an FPGA-based spectrum analysis system according to an embodiment of the present application includes a clock and reset unit implemented based on an FPGA, a system reset unit, an SPI (Serial Perripheral Interface, serial peripheral interface) unit, a register unit, and a plurality of channel spectrum analysis units; wherein,
each of the plurality of channel spectrum analysis units includes:
the ADC control unit is used for being connected with an external ADC through an ADC interface and periodically driving the ADC to work so as to acquire a digital signal to be subjected to spectrum analysis;
the FIR filtering unit is used for inputting the digital signal acquired by the ADC control unit and carrying out filtering processing to acquire a filtered digital signal;
the FFT calculation unit is used for converting the filtered digital signals into a data format required by an FFT IP core, and carrying out FFT calculation to obtain an initial spectrum analysis result;
the FFT calibration compensation unit is used for carrying out calibration compensation on the initial spectrum analysis result to obtain a final spectrum analysis result; the step of performing calibration compensation specifically includes: the frequency spectrum output frequency is reduced to the configured fundamental wave frequency, and the reduced frequency is obtained; and searching a pre-stored scaling coefficient according to the calculated frequency, and performing calibration compensation based on the scaling coefficient.
In the embodiment of the application, the frequency points of the initial frequency spectrum analysis output are reduced to the configured fundamental wave frequency, and the reduced frequency is obtained,
the reduction expression is f j ＝round(n i ×F s /N/f j0 )×f j0 ；
Wherein f j The frequency after the calculation; round is a rounding function; n is n i The index of the FFT output frequency point is taken as 0 to (N-1), and N is the FFT calculation point number; f (F) s Is the sampling frequency; f (f) j0 Is the calculated fundamental frequency.
In the embodiment of the application, the step of searching the pre-stored scaling factor according to the calculated frequency comprises the following steps: the scaling factor between the FFT output result and the actual value (or code value) can be calculated by MATLAB under different frequencies, and the scaling factor is stored in an initialization file of an FPGA ROM (read only memory); the MATIA calculating method comprises the following steps: sequentially carrying out FFT analysis on signals with amplitude being An and frequency being 1-Fs/2 in An enumeration mode, dividing the amplitude being of the signals under each frequency by the maximum value Am of FFT analysis results to obtain a scaling factor kn=an/Am under the frequency; the address of the ROM initialization file is frequency, and the output signal is a scaling coefficient;
the frequency after the reduction, i.e., the address of the ROM is obtained, and the scaling factor in the ROM can be read out based on the address.
According to the technical scheme provided by the embodiment of the application, based on FPGA, the FIR filtering unit is arranged, different filtering parameters are configured through the register to carry out software filtering, the filtering parameters are adjustable, and the application range is wider; an FFT calibration compensation unit is arranged, and the accuracy of the calculation result of the sampled signal which is not the multiple of Fs/N subharmonic can be improved through calculation compensation.
The clock and reset unit is used for providing a unified internal clock for the spectrum analysis system based on the phase-locked loop and resetting the phase-locked loop when a clock locking signal is unlocked;
the system reset unit is used for generating a system reset signal when the clock locking signal is out of lock, and delaying to cancel the system reset signal after the internal clock is normal, so that all the function units of the FPGA are in a stable state;
the SPI unit is used for interacting with an external MCU, analyzing SPI interface signals sent by the MCU, extracting addresses, commands and lengths, and writing and reading FPGA data by the MCU according to read-write commands;
the register read-write distribution unit is used for converting the command extracted according to the SPI interface signal into read-write operation for the internal registers and respectively generating corresponding read-write operation signals for the registers which belong to different functions.
In the embodiment of the application, the method further comprises the following steps: the register unit is used for realizing the register of preset key data; specific examples may include an ADC sampling frequency configuration register, a filter parameter configuration register, an FFT calibration compensation configuration register, an FFT calculation result register; the ADC sampling frequency configuration register may configure the sampling frequency of the ADC by a user, periodically start the ADC to collect signals, and further specifically, for example, when the fundamental frequency is 50Hz, the sampling frequency may be configured to 1024×50=51.2 kHz; if the fundamental frequency is 60Hz, the sampling frequency can be configured to 1024×60=61.44 kHz, and so on. The filter parameter configuration register can pre-store several groups of filter parameters, and a user can configure the on-line filter required by the site according to the needs; the FFT calibration compensation configuration register can configure fundamental frequency of the sampled signal, and calibrate and compensate FFT results according to the fundamental frequency; the FFT calculation result register can store the final calculation result of FFT, and the register read-write distribution unit reads data.
In an embodiment of the present application, each of the plurality of channel spectrum analysis units includes:
the ADC control unit is used for being connected with an external ADC through an ADC interface and periodically driving the ADC to work so as to acquire a digital signal to be subjected to spectrum analysis; in a power generation system, whether the power quality meets the power generation requirement is often judged by detecting the harmonic condition of the alternating voltage output by the system, and if the harmonic content is large, the harmonic with the large content needs to be filtered according to the FFT analysis result;
the FIR filtering unit is used for inputting the digital signal acquired by the ADC control unit, filtering the digital signal and acquiring a filtered digital signal; wherein the FIR filtering unit is configured to: the user sets the filtering parameters according to the sampling frequency set in advance and the frequency spectrum range (the frequency spectrum range of interest of the user) required to be calculated by the FFT; the filtering parameters support the online configuration of users besides the parameters of the spectrum analysis system, and the filtered signals are sent to the FFT calculation unit for calculation; the filtering parameters are adjustable on line, so that the spectrum analysis system is more flexible to apply and wider in application range;
the FFT calculation unit is used for converting the filtered digital signals into a data format required by an FFT IP core, and carrying out FFT calculation to obtain an initial spectrum analysis result;
and the FFT calibration compensation unit is used for carrying out calibration compensation on the initial spectrum analysis result to obtain a final spectrum analysis result.
In the technical scheme provided by the embodiment of the application, the software filtering is adopted, so that the hardware cost can be saved, and the FPGA software resource is fully utilized; the software filtering parameters and the ADC sampling frequency are configurable, so that the sampling frequency spectrum is wider, and the corresponding sampling frequency can be configured according to the fundamental wave of the signal, thereby improving the calculation accuracy of the FFT; and an FFT calibration compensation module is added, so that the accuracy of FFT calculation results is higher, and the accurate monitoring of the running state of working equipment is facilitated.
In a further preferred technical solution of the embodiment of the present application, each of the plurality of channel spectrum analysis units further includes:
the buffer unit is used for temporarily storing the final spectrum analysis result of the corresponding channel to be read by the MCU; by way of specific example, it may be composed of adcchannum RAMs, each RAM corresponding to 1 channel.
In a further preferred technical solution of the embodiment of the present application, each of the plurality of channel spectrum analysis units further includes:
the comparison unit is used for finding out the maximum value of each frequency band and the corresponding frequency point thereof from the final frequency spectrum analysis result of the corresponding channel according to the frequency band configuration of the user, writing the maximum value of each frequency band and the corresponding frequency point thereof into the corresponding register, and waiting for the MCU to read; for example, the comparison module may be formed by adc_chan_num, where each module corresponds to 1 channel.
Referring to fig. 2, 2 ADCs are provided in the embodiment of the present application, and each ADC has 8 channels for sampling analog data; the units realize the following functions:
a clock unit, configured to provide a unified internal clock for the spectrum analysis system based on a phase-locked loop; by way of example, an 80MHz internal clock may be generated from an externally input 50MHz clock by a phase locked loop PLL;
the PLL reset unit is used for resetting the phase-locked loop when the clock locking signal is out of lock; illustratively, a clock lock signal is monitored during operation, and when an out-of-lock is detected, the PLL is reset;
the system reset unit is used for generating a system reset signal when the clock locking signal is out of lock, and delaying to cancel the system reset signal after the internal clock is normal, so that all the functional units of the FPGA are in a stable state;
QSPI (Quad SPI) unit for interacting with external MCU, analyzing QSPI interface signal sent by MCU, extracting address, command and length, and implementing MCU writing and reading FPGA register data according to read-write command;
the register read-write distribution unit is used for converting the QSPI interface command into read-write operation on the internal registers and respectively generating corresponding read-write operation signals for the registers which belong to different functions;
the register unit is used for realizing the register of preset key data;
each of the plurality of channel spectrum analysis units includes:
an ADC control unit configured to: a. according to the sampling period configured by the user, the ADC conversion is started periodically to generate a signal meeting the time sequence requirement of an ADC interface; b. the ADC is controlled to work and read back the conversion value, and the read back voltage value is sent to a corresponding cache control module according to the ADC channel; c. sending the data sampled by the ADC into an FIR filter unit for filtering;
an FIR filtering unit for: a. filtering the ADC sampling data according to filtering parameters configured by a user; b. storing the filtered data into a RAM with a bit width of 16 x adc_chan_num (adc_chan_num is the number of channels used by the current ADC), and sending the cache information of each channel of the ADC to an FFT calculation unit by taking 1024 sampling points as a conversion period, and reading the data and calculating;
the FFT calculation unit is used for converting the filtered digital signals into a data format required by an FFT IP core, and carrying out FFT calculation to obtain an initial spectrum analysis result;
the FFT calibration compensation unit is used for carrying out calibration compensation on the initial spectrum analysis result to obtain a final spectrum analysis result; the step of performing calibration compensation specifically includes:
1) According to the FFT calibration compensation configuration register, the frequency spectrum output frequency is reduced to the configured fundamental wave frequency; for example, n=1024, fs=51.2 kHz, for a system with a fundamental wave of 50Hz, the scaling relationship between the FFT output result and the actual value is as in fig. 4 (b), and calibration is not required; if for a system with the fundamental wave frequency of 60Hz, the frequency of 50Hz needs to be reduced to 60Hz, and the reduction method is as follows: f (f) 60 ＝round(n 50 X 50/60) x 60, where n 50 The index of the FFT output result is 0 to 1023, f 60 The frequency after the calculation;
2) According to the frequency f after the reduction 60 Searching the coefficients stored in ROM for compensation; (the coefficients in ROM are shown in the graph (a) in FIG. 4, calculated by MATLAB and stored in FPGA ROM.
In the embodiment of the application, the frequency spectrums before and after compensation are shown in fig. 5, and for a system with n=1024, fs=51.2 kHz and fundamental wave frequency of 60Hz, errors exist between the frequency spectrums before compensation and the theory, and the correct frequency spectrums can be accurately reflected by the FFT after compensation, so that the FFT accurate analysis under any fundamental wave frequency can be realized by the compensation.
For further explanation, referring to fig. 3 and 4, the data flow of the current FFT card is shown in fig. 3, the ADC collects the actual analog quantity to obtain the code value, and uses 1024 (1024 is the FFT calculation period) sampling points as a group, and sends the data flow to the FFT for calculation, so as to convert the calculation result into the frequency spectrum of the code value, and finally into the frequency spectrum of the actual analog quantity value required by the user analysis. In the above steps, in the data processing from the FFT calculation unit to the ADC sampling code value spectrum, the FFT result N is given to the direct current amount in the spectrum, and the result N (N/2) is given to the alternating current amount; in this calculation method, the calculation result is accurate for a signal with the sampling signal frequency of Fs/N or multiples thereof (as shown in fig. 4), but the FFT calculation result is error for a signal with a frequency other than Fs/N or multiples thereof.
For further explanation, referring to fig. 5 and 6, the FFT clamp in the embodiment of the present application is used for detecting the related signal of the gas turbine, where the fundamental wave is 50Hz, and if n=1024, the sampling frequency fs=50 kHz is obvious. The frequency of the signal of interest to the user is not a multiple of Fs/N and therefore analysis of the signal spectrum using conventional methods is inaccurate, as shown in particular in fig. 5. As shown in fig. 5 (b), for the equipment of the gas turbine taking 50Hz as the fundamental wave, the FFT calculation result and the harmonic frequency are in a periodic relationship, so the application stores the proportional relationship between the FFT calculation result and the code value amplitude in the ROM at different harmonic frequencies in one period, and calibrates the code value amplitude according to the frequency obtained by the FFT calculation, and the final implementation method is shown in fig. 6, and the compensation is compared with that shown in fig. 5 before and after compensation.
The FPGA-based spectrum analysis method provided by the embodiment of the application is based on the FPGA-based spectrum analysis system provided by the embodiment of the application;
the FPGA-based spectrum analysis method comprises the following steps of:
the ADC control unit is connected with an external ADC through an ADC interface and periodically drives the ADC to work to acquire a digital signal to be subjected to spectrum analysis;
the FIR filtering unit inputs the digital signal obtained by the ADC control unit and performs filtering processing to obtain a filtered digital signal;
the FFT calculation unit converts the filtered digital signal into a data format required by an FFT IP core, and performs FFT calculation to obtain an initial spectrum analysis result;
the FFT calibration compensation unit performs calibration compensation on the initial spectrum analysis result to obtain a final spectrum analysis result; the step of performing calibration compensation specifically includes: the initial frequency spectrum analysis output frequency point is calculated to be under the configured fundamental wave frequency, and the calculated frequency is obtained; searching a pre-stored scaling factor according to the calculated frequency; and performing calibration compensation based on the scaling coefficient to obtain a final spectrum analysis result.
In the embodiment of the application, the calculation accuracy of FFT can be improved by the compensation method provided by the application under the condition that the sampling frequency is fixed and the signal frequency is not Fs/N.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Finally, it should be noted that: the above embodiments are only for illustrating the technical aspects of the present application and not for limiting the same, and although the present application has been described in detail with reference to the above embodiments, it should be understood by those of ordinary skill in the art that: modifications and equivalents may be made to the specific embodiments of the application without departing from the spirit and scope of the application, which is intended to be covered by the claims.

Claims (10)

1. A FPGA-based spectrum analysis system, comprising: the system comprises a clock and reset unit, a system reset unit, an SPI unit, a register read-write distribution unit and a plurality of channel spectrum analysis units which are realized based on an FPGA; wherein,
each of the plurality of channel spectrum analysis units includes:
the ADC control unit is used for being connected with an external ADC through an ADC interface and periodically driving the ADC to work so as to acquire a digital signal to be subjected to spectrum analysis;
the FIR filtering unit is used for inputting the digital signal acquired by the ADC control unit and carrying out filtering processing to acquire a filtered digital signal;
the FFT calculation unit is used for converting the filtered digital signals into a data format required by an FFT IP core, and carrying out FFT calculation to obtain an initial spectrum analysis result;
the FFT calibration compensation unit is used for carrying out calibration compensation on the initial spectrum analysis result to obtain a final spectrum analysis result; the step of performing calibration compensation specifically includes: the initial frequency spectrum analysis output frequency point is calculated to be under the configured fundamental wave frequency, and the calculated frequency is obtained; searching a pre-stored scaling factor according to the calculated frequency; and performing calibration compensation based on the scaling coefficient to obtain a final spectrum analysis result.
2. The FPGA-based spectrum analysis system according to claim 1, wherein in the FFT calibration compensation unit, the initial frequency spectrum analysis output frequency point is reduced to the configured fundamental frequency, and the reduced frequency is obtained,
reduction expressionIs f j ＝round(n i ×F s /N/f j0 )×f j0 ；
Wherein f j The frequency after the calculation; round is a rounding function; n is n i The index of the FFT output frequency point is taken as 0 to (N-1), and N is the FFT calculation point number; f (F) s Is the sampling frequency; f (f) j0 Is the calculated fundamental frequency.
3. The FPGA-based spectrum analysis system of claim 1, wherein the FFT calibration compensation unit searches for pre-stored scaling factors according to the calculated frequency, the method comprising:
taking the frequency after the reduction as a ROM address, and reading a pre-stored scaling coefficient in the ROM according to the ROM address;
under different frequencies, scaling coefficients between the FFT output result and an actual value or a code value are pre-stored in an initialization file of the FPGAROM; the address of the initialization file is frequency, and the output signal is a scaling factor.
4. A FPGA-based spectrum analysis system according to claim 3, wherein the step of obtaining the scaling factor between the FFT output result and the actual value or code value at the different frequencies comprises:
sequentially carrying out FFT analysis on signals with amplitude being An and frequency being 1-Fs/2 in An enumeration mode, dividing the amplitude being of the signals under each frequency by the maximum value Am of FFT analysis results, and obtaining a scaling factor kn under the corresponding frequency; wherein the calculation expression is kn=an/Am.
5. The FPGA-based spectrum analysis system according to claim 1, wherein the FFT calibration and compensation unit performs calibration and compensation based on the scaling factor, and the step of obtaining a final spectrum analysis result includes:
multiplying the obtained scaling coefficient with the FFT harmonic amplitude before the reduction in the initial spectrum analysis result to obtain the amplitude of the calibrated and compensated harmonic, and obtaining the final spectrum analysis result.
6. The FPGA-based spectrum analysis system of claim 1, wherein,
the clock and reset unit is used for providing a unified internal clock for the spectrum analysis system based on the phase-locked loop and resetting the phase-locked loop when the clock locking signal is unlocked;
the system reset unit is used for generating a system reset signal when the clock locking signal is out of lock, and delaying to cancel the system reset signal after the internal clock is normal, so that all the function units of the FPGA are in a stable state;
the SPI unit is used for interacting with an external MCU, analyzing SPI interface signals sent by the MCU, extracting addresses, commands and lengths, and writing and reading data of the FPGA register by the MCU according to read-write commands;
the register unit comprises an ADC sampling frequency configuration register, a filter parameter configuration register, an FFT calibration compensation configuration register and an FFT calculation result register;
the register read-write distribution unit is used for converting the command extracted according to the SPI interface signal into read-write operation for the internal registers and respectively generating corresponding read-write operation signals for the registers which belong to different functions.
7. The FPGA-based spectrum analysis system of claim 6, wherein,
the ADC sampling frequency configuration register is used for configuring the sampling frequency of the ADC according to the fundamental wave frequency, and periodically starting the ADC to acquire signals;
the filter parameter configuration register is used for pre-storing a plurality of groups of filter parameters and configuring a required filter on line according to requirements;
the FFT calibration compensation configuration register is used for configuring fundamental frequency of the sampled signal;
the FFT calculation result register is used for storing a final spectrum analysis result so as to read data by the register read-write distribution unit.
8. The FPGA-based spectrum analysis system of claim 1, wherein each of the plurality of channel spectrum analysis units further comprises:
and the comparison unit is used for finding out the maximum value of each frequency band and the corresponding frequency point from the final frequency spectrum analysis result of the corresponding channel according to the frequency band configuration, and writing the maximum value and the corresponding frequency point into the corresponding register.
9. An FPGA-based spectrum analysis method, characterized in that it is based on the FPGA-based spectrum analysis system of claim 1;
the FPGA-based spectrum analysis method comprises the following steps of:
the ADC control unit is connected with an external ADC through an ADC interface and periodically drives the ADC to work to acquire a digital signal to be subjected to spectrum analysis;
the FIR filtering unit inputs the digital signal obtained by the ADC control unit and performs filtering processing to obtain a filtered digital signal;
the FFT calculation unit converts the filtered digital signal into a data format required by an FFT IP core, and performs FFT calculation to obtain an initial spectrum analysis result;
the FFT calibration compensation unit performs calibration compensation on the initial spectrum analysis result to obtain a final spectrum analysis result; the step of performing calibration compensation specifically includes: the initial frequency spectrum analysis output frequency point is calculated to be under the configured fundamental wave frequency, and the calculated frequency is obtained; searching a pre-stored scaling factor according to the calculated frequency; and performing calibration compensation based on the scaling coefficient to obtain a final spectrum analysis result.
10. The method of spectrum analysis based on FPGA of claim 9,
the step of obtaining the calculated frequency by calculating the initial frequency spectrum analysis output frequency point to the configured fundamental wave frequency,
the reduction expression is f j ＝round(n i ×F s /N/f j0 )×f j0 ；
Wherein f j The frequency after the calculation; round is a rounding function; n is n i The index of the FFT output frequency point is taken as 0 to (N-1), and N is the FFT calculation point number; f (F) s Is the sampling frequency; f (f) j0 The fundamental frequency is calculated;
the step of searching for pre-stored scaling factors according to the calculated frequency comprises the following steps: taking the frequency after the reduction as a ROM address, and reading a pre-stored scaling coefficient in the ROM according to the ROM address; under different frequencies, scaling coefficients between the FFT output result and an actual value or a code value are pre-stored in an initialization file of the FPGA ROM; the address of the initialization file is frequency, and the output signal is a scaling factor.
CN202310952702.9A 2023-07-31 2023-07-31 FPGA-based spectrum analysis system and method Pending CN117007861A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118584195A (en) * 2024-08-05 2024-09-03 南京典格通信科技有限公司 Low-cost spectrum analysis method of 5G communication system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118584195A (en) * 2024-08-05 2024-09-03 南京典格通信科技有限公司 Low-cost spectrum analysis method of 5G communication system

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