CN116978874A

CN116978874A - Packaging structure and manufacturing method thereof

Info

Publication number: CN116978874A
Application number: CN202310854998.0A
Authority: CN
Inventors: 朱国振
Original assignee: Changxin Technology Group Co ltd
Current assignee: Changxin Technology Group Co ltd
Priority date: 2023-07-12
Filing date: 2023-07-12
Publication date: 2023-10-31

Abstract

The embodiment of the application provides a packaging structure and a manufacturing method thereof, wherein the packaging structure comprises: a substrate; at least one chip stacked above the substrate in the thickness direction of the substrate; an interconnect structure between the substrate and the at least one chip connecting the at least one chip and circuitry in the substrate; an encapsulation structure encapsulating the at least one chip and the interconnect structure; and a heat conductive structure extending from the top surface of the encapsulation structure along the thickness direction of the substrate, and comprising a first heat conductive member positioned on at least one chip and/or a second heat conductive member positioned at the periphery of the at least one chip and spaced from the at least one chip.

Description

Packaging structure and manufacturing method thereof

Technical Field

The embodiment of the application relates to the technical field of semiconductors, in particular to a packaging structure and a manufacturing method thereof.

Background

The current integrated circuit package structure is miniaturized, ultra-thinned and smaller in size, and as the process capability is further improved, the density of transistors of the semiconductor device is improved, so that the power of the semiconductor device is improved. This results in excessive heat generation during operation of the semiconductor device, which increases the temperature of the semiconductor device, which may degrade the electrical performance of the chip.

In order to avoid such phenomena, it is necessary to increase the heat dissipation capability of the integrated circuit package structure.

Disclosure of Invention

In view of the above, the embodiment of the application provides a packaging structure and a manufacturing method thereof for solving at least one technical problem existing in the prior art.

According to a first aspect of an embodiment of the present application, there is provided a package structure, including: a substrate; at least one chip stacked above the substrate in the thickness direction of the substrate; an interconnect structure between the substrate and the at least one chip connecting the at least one chip and circuitry in the substrate; an encapsulation structure encapsulating the at least one chip and the interconnect structure; and a heat conductive structure extending from the top surface of the encapsulation structure along the thickness direction of the substrate, and comprising a first heat conductive member positioned on at least one chip and/or a second heat conductive member positioned at the periphery of the at least one chip and spaced from the at least one chip.

In the above scheme, the second heat conducting member is located on part of the interconnection structure; a portion of the interconnect structure is connected to a thermally conductive member in the substrate; the distance between the bottom surface of the first heat conduction piece and at least one chip is smaller than a first preset value; the distance between the bottom surface of the second heat conduction piece and part of the interconnection structure is smaller than a second preset value; the second preset value is smaller than the first preset value.

In the above scheme, a first distance is arranged between the bottom surface of the first heat conducting piece and at least one chip; the bottom surface of the second heat conductive member is in contact with a portion of the interconnect structure, and is in contact with the heat conductive member in the substrate through the portion of the interconnect structure contact.

In the above aspect, the first heat conducting member includes a plurality of first heat conducting columns spaced apart from each other; the second heat conductive member includes a plurality of second heat conductive posts spaced apart from each other.

In the above scheme, the number of the second heat conducting columns is larger than that of the first heat conducting columns; and/or the bottom surface area of the second heat conduction column is larger than the bottom surface area of the first heat conduction column.

In the above scheme, the distribution density of the first conductive pillars is smaller than that of the second conductive pillars.

In the above scheme, at least part of the first heat conduction columns comprise step surfaces; and/or at least part of the second heat conduction column comprises a step surface; wherein the step surfaces in the different first heat conducting columns and/or the different second heat conducting columns are at different distances from the top surface of the encapsulation structure.

In the above scheme, the thermal conductivity of the material of the thermal conductive structure is greater than that of the material of the encapsulation structure.

In the above scheme, the package structure further includes: a wire structure connecting the at least one chip and the interconnect structure;

a third heat conductive member located on the wire structure; wherein, a second distance is arranged between the bottom surface of the third heat conduction piece and the line structure; the second distance is greater than the first distance.

According to a second aspect of the embodiment of the present application, there is provided a method for manufacturing a package structure, including: providing a substrate; forming an interconnection structure; the interconnect structure includes opposing first and second sides; providing at least one chip, and stacking the at least one chip on a first side along the thickness direction of the interconnection structure; forming an encapsulation structure encapsulating the at least one chip and the interconnect structure; forming a heat conduction structure extending from the top surface of the encapsulation structure along the thickness direction of the substrate; the heat conducting structure comprises a first heat conducting piece positioned on at least one chip and/or a second heat conducting piece positioned at the periphery of the at least one chip and spaced from the at least one chip; and contacting the substrate with the interconnect structure on the second side; the circuitry in the substrate is connected to the at least one chip by an interconnect structure.

In the embodiments of the application, the first heat conducting piece extending from the top surface of the encapsulation structure to the upper side of the chip along the thickness direction of the substrate and/or the second heat conducting piece extending from the top surface of the encapsulation structure to the periphery of the chip along the thickness direction of the substrate are arranged in the encapsulation structure, so that the heat conducting capability of the chip is increased by the first heat conducting piece in the encapsulation structure, and/or the heat conducting capability of the substrate is increased by the second heat conducting piece in the encapsulation structure, the heat radiating performance of the encapsulation structure is improved, and the running speed and the transmission efficiency of the chip work are improved.

According to the embodiment, a large number of heat conducting pieces are added in the encapsulation structure, and the heat conducting pieces can reduce heat resistance in the heat path transfer process, so that heat generated by the substrate is dissipated from the heat conducting pieces and cannot be transferred to the chip, and the chip performance is guaranteed. Meanwhile, the heat conducting piece is also placed on the chip, and the heat conducting piece can also rapidly dissipate heat generated by the chip, so that the heat dissipation of the chip is quickened.

Drawings

Fig. 1 is a schematic cross-sectional view of a first semiconductor device package-on-package structure;

fig. 2 is a schematic cross-sectional view of one of the heat propagation paths of the semiconductor device package-on-package structure of fig. 1;

FIG. 3 is a schematic cross-sectional view of a second heat propagation path of the semiconductor device package-on-package structure of FIG. 1;

fig. 4A is a schematic cross-sectional view of a first package structure according to an embodiment of the present application;

fig. 4B is a schematic cross-sectional view of a second package structure according to an embodiment of the present application;

FIG. 4C is a partial top view of the package structure of FIG. 4A or FIG. 4B;

fig. 5 is a flow chart of a method for manufacturing a package structure according to an embodiment of the present application;

fig. 6A to 6F are schematic cross-sectional views illustrating a manufacturing process of a package structure according to an embodiment of the application;

fig. 7A is a schematic cross-sectional view of a fourth package structure according to an embodiment of the present application;

FIG. 7B is a schematic diagram of a temperature distribution of a bottom view of the package structure of FIG. 7A;

FIG. 8A is a schematic cross-sectional view of a control group of the package structure of FIG. 7A;

fig. 8B is a schematic diagram of a temperature distribution of a bottom view of the package structure of fig. 8A.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which embodiments of the application are shown, and in which embodiments of the application are shown, by way of illustration only, and not in any way. All other embodiments, based on the embodiments of the application, which are apparent to those of ordinary skill in the art without inventive faculty, are intended to be within the scope of the application.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent to one skilled in the art that the present application may be practiced without one or more of these details. In other instances, well-known features have not been described in detail so as not to obscure the application; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present.

Spatially relative terms, such as "under … …," "under … …," "below," "under … …," "above … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to provide a thorough understanding of the present application, detailed steps and detailed structures will be presented in the following description in order to explain the technical solution of the present application. Preferred embodiments of the present application are described in detail below, however, the present application may have other embodiments in addition to these detailed descriptions.

Here and hereinafter, for convenience of description, the first direction and the second direction are represented as two orthogonal directions parallel to the plane of the substrate (or carrier substrate/package substrate) in the embodiments of the present application; the third direction is a direction perpendicular to the plane of the substrate; the substrate plane is understood to be a plane parallel to the direction of extension of the channel. The first direction may be denoted as X-direction in the drawing; the second direction may be denoted as Y-direction in the drawing; the third direction may be denoted as Z-direction in the drawing.

Fig. 1 is a schematic cross-sectional view of a first semiconductor device package-on-package structure. Referring to fig. 1, the upper layer of the package structure includes a memory device 10, and the memory device 10 may be a plurality of stacked chips (die) 14, such as dynamic random access memory (Dynamic Random Access Memory, DRAM), and heat of the memory device 10 may be transferred out through the encapsulation layer 16 and the metal layer 40. The lower layer of the package structure includes a System On Chip (SOC) 20. The underside of the system on chip 20 is a second Ball Grid Array (BGA) 22 interconnected with a printed circuit board (Printed Circuit Board, PCB) 30, and the interior of the system on chip 20 interconnects a substrate 24 and an interposer 26, so that the system on chip 20 package has the characteristics of high power, high integration, etc., and more heat generated by the system on chip 20 is transferred to the upper memory device 10; the memory device 10 is interconnected to the interposer 26 by the first ball grid array 12 so that some of the heat generated by the system-on-chip 20 is transferred to the memory device 10.

Fig. 2 is a schematic cross-sectional view of one of the heat propagation paths of the semiconductor device package-on-package structure of fig. 1. Referring to fig. 2, the dashed arrow shows that the heat generated by the system-on-chip 20 may be partially transferred to the heat propagation path TP1 of the memory device 10, and the number of stacked chips 10 of the memory device is higher and higher, so that the heat generation of the memory device 10 is not negligible.

The chip temperature is too high, which reduces the electrical performance of the chip, and causes thermal expansion caused by heating of the packaging material, and the thermal expansion coefficients (Coefficient of thermal expansion, CTE) of the various packaging materials have significant differences, and the higher the temperature is, the larger the warpage value generated by the packaging material is, which may cause the phenomenon of fatigue of welding spots between the upper layer and the lower layer of the packaging structure. In order to avoid such a phenomenon, it is necessary to improve the heat dissipation capability of the package structure.

Fig. 3 is a schematic cross-sectional view of a second heat propagation path of the semiconductor device package-on-package structure of fig. 1. Referring to fig. 3, the package heat of the semiconductor device package-on-package structure can be transferred only from the board direction of the printed wiring board 30, and the dotted arrow of fig. 3 shows a heat propagation path TP2 through which the heat generated by the system-on-chip 20 can be transferred only from the board direction of the printed wiring board 30. However, the heat of the system on chip 20 is transferred to the memory device 10 through the first ball grid array 12, which causes heat accumulation phenomenon of the memory device 10, such as long-time operation of the device, increased temperature of the package structure, and reduced performance of the semiconductor device, which is manifested as burn-in and jamming, and affects the user experience.

Fig. 4A is a schematic cross-sectional view of a first package structure according to an embodiment of the present application; fig. 4B is a schematic cross-sectional view of a second package structure according to an embodiment of the present application; fig. 4C is a schematic top view of a portion of the package structure of fig. 4A or fig. 4B.

It should be noted that, compared to the package structure of fig. 4A, the package structure of fig. 4B is at least different in that the second heat conductive member is in contact with a portion of the interconnection structure, and the distances between the step surfaces of the different first heat conductive pillars and the top surface of the package structure are different. Fig. 4C mainly illustrates a layout diagram of the first and second heat conductive members of the package structure of fig. 4A or 4B.

Referring to fig. 4A, 4B and 4C, according to a first aspect of an embodiment of the present application, there is provided a package structure including:

a substrate;

at least one chip 302 stacked above the substrate in the thickness direction of the substrate;

an interconnect structure 202 between the substrate and the at least one chip 302, connecting the at least one chip 302 to circuitry in the substrate;

an encapsulation structure 304 encapsulating the at least one chip 302 and the interconnect structure 202; and

the thermally conductive structure 306 extends from the top surface of the encapsulation structure 304 along the thickness direction of the substrate, and includes a first thermally conductive member 3061 located on the at least one die 302 and/or a second thermally conductive member 3062 located at the periphery of the at least one die 302 and spaced apart from the at least one die 302.

In some embodiments, the substrates include a carrier substrate 104 and a package substrate 102 on the carrier substrate 104.

The carrier substrate 104 may be configured as a substrate for a package structure, and the carrier substrate 104 may include a printed circuit board, a ceramic substrate, a glass substrate, and a tape wiring board. In practice, the carrier substrate 104 may include a copper-clad laminate and a wiring layer (not shown in fig. 4A and 4B) on a surface of the copper-clad laminate.

In some embodiments, at least one semiconductor chip 108 is located on the package substrate 102.

The semiconductor chip 108 includes a processor (e.g., central processing unit (Central Processing Unit, CPU)) or a system-on-chip (e.g., application processor (Application Processor, AP)) of an electronic device.

The semiconductor chip 108 may include a doped or undoped active layer. The semiconductor chip 108 may include a wide variety of active and passive devices (e.g., capacitors, resistors, inductors, and the like) that meet the desired structural and functional requirements of the design. The active devices and passive devices may be formed within the semiconductor chip 108 or on the active layer of the semiconductor chip 108 using any suitable method.

In some embodiments, the substrate of the semiconductor chip 108 and the interposer 106 are interconnected inside the package substrate 102.

In some embodiments, the package structure further includes bumps; bumps are located between the interconnect structure 202 and the substrate, connecting the interconnect structure 202 and the substrate. Illustratively, the package substrate 102 is interconnected with the interconnect structure 202 by the first bump 402, and the wiring layer of the package substrate 102 on the surface proximate to the chip 302 is interconnected with the interconnect structure 202 by the first bump 402; the carrier substrate 104 is interconnected with the interposer 106 by the second bumps 404, and the wiring layer of the carrier substrate 104 on the surface near the package substrate 102 is interconnected with the interposer 106 by the second bumps.

It is appreciated that the size of the first bump 402 may be smaller than the size of the second bump 404 based on current magnitude considerations. In some embodiments, a molding compound may be further filled between the interconnect structure 202 and the package substrate 102, so as to further ensure the working performance of the interconnect structure 202, and thus the size of the first bump 402 needs to be set smaller, so as to facilitate filling of the molding compound.

The bumps include a first bump 402, a second bump 404; the material of the bump may comprise an alloy of carbon (C) with at least one or more of the following metals: copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), zinc (Zn).

The interposer 106 may have: one or more insulating layers 114 and one or more wiring layers 110 respectively disposed on the one or more insulating layers 114; and one or more Through silicon-n Via (TSV) 112, which penetrates each of the one or more insulating layers and connects one or more wiring layers to the first bump 402 and the second bump 404, or connects the wiring layers 110 disposed on different levels electrically to each other. It is understood that the plurality of through silicon vias 112 and the plurality of wiring layers 110 form the basic load bearing components of the interposer 106 connection.

The wiring layer 110 may include a metal material including the following metals or an alloy thereof: copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium (Ti). The wiring layer may perform various functions according to design. Through silicon vias 112 may comprise a metallic material or an alloy thereof comprising: copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium (Ti). The through silicon via may be configured as a conformal through silicon via in which the metal material fills in the via or in which the metal material forms along an inner wall of the via. The insulating layer 114 material includes, but is not limited to, at least one of a thermosetting resin (e.g., epoxy resin), a thermoplastic resin (e.g., polyimide), or an inorganic filler and/or glass fiber (glass cloth or glass fabric) therein, etc.

The interconnect structure 202 includes one or more insulating layers 214 and one or more wiring layers 210 disposed on the one or more insulating layers 214, respectively; and one or more through silicon vias 212 penetrating each of the one or more insulating layers and connecting one or more wiring layers to at least one chip and the first bump 402 or electrically connecting the wiring layers 210 disposed on different levels to each other. It is understood that the plurality of through silicon vias 212 and the plurality of wiring levels 210 form the basic load bearing components of the interconnect structure 202 connection.

The materials of the wiring layer 110, the through silicon via 112, and the insulating layer 114 of the interconnect structure 202 may be understood with reference to the materials of the wiring layer 110, the through silicon via 112, and the insulating layer 114 of the interposer 106, respectively, and are not described herein.

The dimensions of wiring layer 110, through silicon vias 112 and insulating layer 114 of interconnect structure 202 may be smaller than the dimensions of wiring layer 110, through silicon vias 112 and insulating layer 114 of interposer 106,

the chip 302 includes DRAM, which may be low power memory (Low Power Double Data Rate, LPDDR) DRAM, for example. The number of chips 302 is one less, and here and hereinafter, the number of stacked chips 302 is four, including a first chip 3021, a second chip 3022, a third chip 3023, and a fourth chip 3024 stacked in this order. At least one of the first to fourth chips 3021 to 3024 includes a DRAM, which may be LPDDR DRAM, for example. The first chip 3021 and the interconnect structure 202 may be connected before and between the first to fourth chips 3021 to 3024 by a Die Attach Film (DAF).

An encapsulation structure 304 encapsulates the gaps around the at least one chip 302 and over the interconnect structure 202. An encapsulation structure 304 may be molded around the at least one chip 302 and over the interconnect structure 202.

In some embodiments, the material of the encapsulation structure 304 may be made of a molding compound, a molding underfill, an epoxy molding compound (Epoxy Molding Compound, EMC), a resin, the like, or a combination thereof.

The thermally conductive structure 306 includes a first thermally conductive member 3061 and/or a second thermally conductive member 3062. The first heat conductive member 3061 extends from the top surface of the encapsulation structure 304 onto the fourth chip 3024 in the thickness direction of the substrate. The second thermally conductive member 3062 is located at the periphery of the chip 302 and spaced apart from the chip 302.

In some embodiments, the thermal conductivity of the material of the thermally conductive structure 306 is greater than the thermal conductivity of the material of the encapsulation structure 304.

In some embodiments, the material of the encapsulating structure includes an epoxy molding compound; the material of the thermally conductive structure includes a thermally conductive interface material (Thermal Interface Material, TIM). Illustratively, the material of the thermally conductive structure 306 may include silicone grease (thermal grease), silicone gel (thermal gel), or thermally conductive gel (thermal conductive adhensive).

Embodiments of the present application provide a through hole (for forming the heat conducting structure 306) in the encapsulation structure 304, so that the surface of the encapsulation structure 304 is improved to have a heat dissipation area extending from the inside of the encapsulation structure 304 to the top surface of the encapsulation structure 304, and the heat conducting structure 306 is formed in the through hole, and the heat conducting structure 306 itself has a structure for increasing the heat dissipation contact area of the surface, so that the heat conduction capability of the encapsulation structure 304 in the encapsulation structure is further increased.

The basic principle of the embodiments of the present application is to reduce the thermal resistance in the heat path transfer process, and add the heat conducting structure 306 in the encapsulation structure 304, which is equal to the parallel connection of the components with small thermal resistance in principle, wherein in the parallel connection of the heat paths, the thermal resistance is mainly determined by the thermal components with small resistance; increasing the contact area of the surface of the encapsulation structure 304 is in principle equivalent to decreasing the thermal resistance of the node. By combining the two methods, the thermal resistance of the branch path from the heat source to the surface of the encapsulation structure 304 is further reduced, and the heat transfer efficiency is improved.

Therefore, through increasing the heat radiating area through the through holes and increasing the two heat radiating ways of the surface heat radiating contact area through the heat conducting structure, the heat conductivity coefficient from the substrate to the surface of the encapsulation structure is improved, more heat of the substrate can be directly transferred from the substrate to the surface of the encapsulation structure without passing through the chip, the heat conductivity coefficient from the chip to the surface of the encapsulation structure is improved, more heat generated by the chip can be transferred to the surface of the encapsulation structure, the heat radiating effect is improved, and the operation rate and the transmission efficiency of the chip work are improved. Therefore, the performance of the chip is improved, the user experience is optimized, and the service life is prolonged.

Referring to fig. 4A and 4B, in some embodiments, a second thermally conductive member 3062 is located on a portion of the interconnect structure 202; part of the interconnect structure 202 is connected to a thermally conductive member in the substrate (not shown in fig. 4A and 4B);

wherein, the distance between the bottom surface of the first heat conducting member 3061 and the at least one chip 302 is smaller than a first preset value; the distance between the bottom surface of the second heat conductive member 3062 and the portion of the interconnect structure 202 is less than a second preset value; the second preset value is smaller than the first preset value.

Here, the second heat conductive member 3062 is located on a portion of the interconnect structure 202, and the portion of the interconnect structure 202 is connected to a heat conductive member (not shown in fig. 4A and 4B) in the substrate, and the second heat conductive member 3062 may be used to conduct out heat generated in the substrate.

Illustratively, the distance between the bottom surface of the first heat conductive member 3061 and the fourth chip 3024 (the first distance D1) is smaller than a first preset value, and the first heat conductive member 3061 may be used to conduct out heat generated by the first to fourth chips 3021 to 3024; the distance (third distance D3) between the bottom surface of the second heat conductive member 3062 and the portion of the interconnect structure 202 is smaller than a second preset value, and the second heat conductive member 3062 may be used to conduct out heat generated in the substrate; the second preset value is smaller than the first preset value. The first heat conducting member 3061 does not directly contact the fourth chip 3024, preventing the first heat conducting member 3061 from being pressed greatly against the fourth chip 3024 when the first heat conducting member 3061 is ground.

Illustratively, the first distance D1 is 15 μm and the third distance D3 is 10 μm.

Referring to fig. 4A and 4B, in some embodiments, a first distance D1 is provided between a bottom surface of the first heat conductive member 3061 and the at least one chip 302; the bottom surface of the second thermally conductive member 3062 is in contact with a portion of the interconnect structure 202, through which contact is made with the thermally conductive member in the substrate.

In some embodiments, the first distance D1 ranges from 10 μm to 15 μm. In some embodiments, the bottom surface of the second thermally conductive member 3062 is in contact with a portion of the interconnect structure 202, and the third distance D3 is 0.

Referring to fig. 4A, 4B, and 4C, in some embodiments, the first heat conductive member 3061 includes a plurality of first heat conductive posts spaced apart from one another; the second heat conductive member 3062 includes a plurality of second heat conductive posts spaced apart from each other.

Illustratively, a plurality of first thermally conductive pillars are disposed apart from one another on the fourth chip 3024; the plurality of second heat conductive pillars are spaced apart from the die 302 at the periphery of the die 302 and are spaced apart from each other.

Referring to fig. 4A, 4B, and 4C, in some embodiments, the number of second heat conductive posts is greater than the number of first heat conductive posts; and/or the bottom surface area of the second heat conduction column is larger than the bottom surface area of the first heat conduction column.

Referring to fig. 4A, 4B, and 4C, in some embodiments, the distribution density of the first conductive pillars is less than the distribution density of the second conductive pillars.

Referring to fig. 4B, in some embodiments, at least a portion of the first thermally conductive post includes a stepped surface; and/or at least part of the second heat conduction column comprises a step surface;

wherein the step surfaces in the different first heat conducting columns and/or the different second heat conducting columns are at different distances from the top surface of the encapsulation structure.

Here, the step surface may be a plane extending in parallel with the X-Y plane. The step surfaces of different first heat conduction columns are different from the top surface of the encapsulation structure, so that the distribution density of the step surfaces in the encapsulation structure can be improved and the heat conduction area of the first heat conduction columns can be increased under the condition that a plurality of first heat conduction columns with large areas are not formed on the fourth chip 3024. Because, if a plurality of first heat conductive pillars are formed on the fourth chip in a large area, the material CTE of the first heat conductive pillars is different from that of the encapsulation structure for reasons of the first heat conductive pillars, warpage of the encapsulation structure may be caused, which may adversely affect the encapsulation structure.

Illustratively, at least a portion of the first thermally conductive posts have a step surface S1 and at least another portion of the first thermally conductive posts have a step surface S2, the step surface S1 being less than the step surface S2 (the fourth distance D4) from the top surface of the encapsulation structure (the fifth distance D5). The step surface S1 and the step surface S2 are distributed in different X-Y planes, so that the distribution density of the step surface in the encapsulation structure can be improved, and the heat conduction area of the first heat conduction column is increased.

Details of the inclusion of the stepped surface in at least a portion of the second thermally conductive post will be understood with reference to details of the inclusion of the stepped surface S1 in at least a portion of the first thermally conductive post.

Therefore, the surface morphology of the encapsulation structure is changed, the step shape of the heat conduction area is improved, and the high heat conduction material is added on the surface, so that the heat dissipation efficiency is improved.

Referring to fig. 4A and 4B, in some embodiments, the package structure further includes:

a wire structure 310 connecting the at least one chip 302 and the interconnect structure 202;

a third heat conductive member 308 on the wire structure 310;

wherein, a second distance D2 is provided between the bottom surface of the third heat conducting member 308 and the line structure 310; the second distance D2 is greater than the first distance D1.

Illustratively, the wire structure 310 is located between the second thermally conductive member 3062 and the chip 302.

In this way, the third heat conductive member 308 can increase the heat at the lead-out wire structure 310, avoiding or reducing the heat generated in the substrate from being transferred to the first to fourth chips 3021 to 3024 through the wire structure 310.

In the embodiments of the present application, the heat conducted by the second heat conducting member 3062 is ensured to be greater than the heat conducted by the first heat conducting member 3061, so that the heat generated in the substrate is prevented from being transferred to the first to fourth chips 3021 to 3024, and meanwhile, the first heat conducting member 3061 can be used for conducting the heat generated by the first to fourth chips 3021 to 3024, so that heat accumulation of the first to fourth chips 3021 to 3024 can be reduced or avoided, and performance of the first to fourth chips 3021 to 3024 is improved.

An embodiment of the present application provides a memory device including the package structure of any one of the above embodiments.

In an exemplary embodiment, the memory device may be any of a variety of memory devices supporting high speed operation, such as a dynamic random access memory. For example, the test may be performed in response to a test command sent by a memory controller (not shown in the present application). The Memory device may be implemented in a module structure such as a Dual-Inline-Memory-Modules (DIMM) or a high bandwidth Memory (High Bandwidth Memory, HBM) device in which the Memory device and the Memory controller are integrated into one substrate (not shown in the present application).

Fig. 5 is a flow chart of a method for manufacturing a package structure according to an embodiment of the present application. Referring to fig. 5, according to a second aspect of the embodiment of the present application, there is provided a package structure and a manufacturing method thereof, including the steps of:

step S501, providing a substrate;

step S502, forming an interconnection structure; the interconnect structure includes opposing first and second sides;

step S503, providing at least one chip, and stacking the at least one chip on a first side along the thickness direction of the interconnection structure;

step S504, forming an encapsulation structure for encapsulating at least one chip and the interconnection structure;

step S505, forming a heat conduction structure extending from the top surface of the encapsulation structure along the thickness direction of the substrate; the heat conducting structure comprises a first heat conducting piece positioned on at least one chip and/or a second heat conducting piece positioned at the periphery of the at least one chip and spaced from the at least one chip; and

step S506, contacting the substrate with the interconnection structure at the second side; the circuitry in the substrate is connected to the at least one chip by an interconnect structure.

It should be understood that the steps shown in fig. 5 are not exclusive and that other steps may be performed before, after, or between any of the steps in the illustrated operations. The steps shown in fig. 5 can be sequentially adjusted according to actual needs.

Fig. 6A to fig. 6F are schematic cross-sectional views illustrating a manufacturing process of a package structure according to an embodiment of the application. The steps shown in fig. 6A-6F are not exclusive and other steps may be performed before, after, or between any of the illustrated operations; the steps shown in fig. 6A to 6F may be sequentially adjusted according to actual needs.

The following describes in detail the manufacturing method of the package structure according to the embodiment of the present application with reference to fig. 5 and fig. 6A to 6F.

Steps S501 to S503 are performed to provide a substrate, form an interconnect structure, and laminate at least one chip.

The substrate, the interconnect structure and the at least one chip may be understood with reference to the specific structure in fig. 4A and 4B; methods of forming the substrate, forming the interconnect structure, and stacking the at least one chip may be understood with reference to the related art, and will not be described herein.

Steps S504 and S505 are performed to form an encapsulation structure and a heat conduction structure.

In some embodiments, forming the encapsulation structure and forming the thermally conductive structure includes:

referring to fig. 6A, an encapsulant material encapsulating at least one chip and interconnect structures is formed using a mold 506 having a first thermally conductive member shape 5061 and a second thermally conductive member shape 5062;

referring to fig. 6B, after removing the mold, an encapsulation structure is obtained; the encapsulation structure comprises a first opening T1 on at least one chip and a second opening T2 on a part of the interconnection structure at the periphery of at least one chip; the distance between the bottom surface of the first opening and at least one chip is smaller than a first preset value; the distance between the bottom surface of the second opening and a part of the interconnection structure is smaller than a second preset value; the second preset value is smaller than the first preset value;

referring to fig. 6C, the first and second openings T1 and T2 are filled with a heat conductive material, resulting in the first and second heat conductive members 3061 and 3062.

Illustratively, as shown in fig. 6A, in some embodiments, the molding material is subjected to a pressure molding process (pressure molding process) by a pressure plate (pressure plate) or die (not shown) to shape the molding material. In order to simplify the molding process, a novel mold 506 for simultaneously molding the through hole T1 and the step surface S1 is proposed (refer to fig. 6B). A schematic of the mold 506 is shown in fig. 6A, where the mold 506 will block the molding material from forming.

As shown in fig. 6B, after removing the mold 506, an encapsulation structure 304 having a first opening T1 and a second opening T2 is obtained; the distance between the bottom surface of the first opening T1 and the at least one chip (fourth distance D4) is less than 15 μm; the bottom surface of the second opening is in contact with a portion of the interconnect structure.

As shown in fig. 6C, after the pressure molding process is completed, the surface is sprayed with the heat conductive interface material to the hollowed-out portion by using the nozzle, and the heat conductive interface material may be filled in the first opening T1 and the second opening T2.

In some embodiments, referring to fig. 6A, the mold 506 further includes a third thermally conductive member shape 5063; referring to fig. 6B, the encapsulation structure obtained after removing the mold further includes a third opening T3 between the first opening T1 and the second opening T2; the distance between the bottom surface of the third opening T3 and the at least one chip is greater than the distance between the bottom surface of the first opening T1 and the at least one chip; referring to fig. 6C, the third opening T3 is filled with a heat conductive material, resulting in a third heat conductive member 308.

Step S506 is performed, where the substrate and the interconnect structure form an interconnect.

In some embodiments, contacting the substrate with the interconnect structure on the second side includes:

referring to fig. 6E, on a second side, bumps 402 are formed in contact with the interconnect structure 202;

the interconnect structure 202 with bumps 402 is in contact with the substrate; the interconnect structure 202 is connected to the substrate by bumps 402 (see fig. 4A and 4B).

Illustratively, as shown in fig. 6E, the package structure is inverted, a ball attach process is performed normally, and on the second side, bumps 402 are formed in contact with the interconnect structure 202.

Therefore, by utilizing one process flow, the ball-planting process and the through-die via forming process are respectively completed on two sides of the packaging structure, and the process completion efficiency is improved.

In some embodiments, after filling the first opening and the second opening with the thermally conductive material, the method of making further comprises:

referring to fig. 6D, a cover layer 502 is formed covering the thermally conductive material and the encapsulation structure;

forming a bump 402 on the second side;

referring to fig. 6F, after the bump 402 is formed, the cap layer 502 is removed.

Illustratively, as shown in fig. 6D, the surface covering is sealed after the first opening and the second opening are filled with a suitable volume of thermally conductive interface material. The material of the cover layer may be a low adhesion material.

Illustratively, as shown in fig. 6F, the cover layer 502 is removed after returning to normal temperature, and a package structure filled with the through mold vias (Through Molding Via, TMV) of the thermal interface material after molding can be obtained.

Fig. 7A is a schematic cross-sectional view of a fourth package structure according to an embodiment of the present application; fig. 7B is a schematic diagram of a temperature distribution of a bottom view of the package structure of fig. 7A. FIG. 8A is a schematic cross-sectional view of a control group of the package structure of FIG. 7A; fig. 8B is a schematic diagram of a temperature distribution of a bottom view of the package structure of fig. 8A.

Note that, the package structure of fig. 7A may refer to the package structures shown in fig. 4A and 4B, and fig. 8A serves as a control group of the package structures of fig. 7A. Compared to the package structure of fig. 7A, the package structure of fig. 8A is at least different in that: the package structure of fig. 8A is not provided with a heat conductive structure in the package structure.

From the comparison of the temperatures of fig. 7B and 8B, it can be seen that: compared with the packaging structure of the control group, the packaging temperature of the packaging structure provided by the application embodiment is reduced, and the temperature of a gap between the environment and the packaging is reduced. Illustratively, compared with the packaging structure of the control group, the packaging temperature of the packaging structure provided by the application embodiment is reduced by 0.5-2 ℃, and the temperature of the gap between the environment and the packaging is reduced by 1-3 ℃.

The package structure manufactured by the manufacturing method of the package structure provided by the embodiment of the present application is similar to the package structure in the above embodiment, and for the technical features of the embodiment of the present application that are not disclosed in detail, please refer to the above embodiment for understanding, and details are not repeated here.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present application, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by the functions and internal logic thereof, and should not constitute any limitation on the implementation process of the embodiments of the present application. The foregoing embodiment numbers of the present application are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.

The foregoing description is only of the preferred embodiments of the present application, and is not intended to limit the scope of the application, but rather, the equivalent structural changes made by the description of the present application and the accompanying drawings or the direct/indirect application in other related technical fields are included in the scope of the application.

Claims

1. A package structure, comprising:

a substrate;

at least one chip stacked above the substrate in a thickness direction of the substrate;

an interconnect structure between the substrate and the at least one chip connecting the at least one chip and circuitry in the substrate;

an encapsulation structure encapsulating the at least one chip and the interconnect structure; and

and the heat conducting structure extends from the top surface of the encapsulation structure along the thickness direction of the substrate and comprises a first heat conducting piece positioned on the at least one chip and/or a second heat conducting piece positioned at the periphery of the at least one chip and spaced from the at least one chip.

2. The package structure of claim 1, wherein the second thermally conductive member is located on a portion of the interconnect structure; a portion of the interconnect structure is connected to a thermally conductive member in the substrate;

the distance between the bottom surface of the first heat conduction piece and the at least one chip is smaller than a first preset value; the distance between the bottom surface of the second heat conduction piece and part of the interconnection structure is smaller than a second preset value; the second preset value is smaller than the first preset value.

3. The package structure of claim 2, wherein a first distance is provided between the bottom surface of the first thermally conductive member and the at least one chip; the bottom surface of the second heat conducting member is in contact with a part of the interconnection structure, and is in contact with the heat conducting member in the substrate through a part of the interconnection structure contact.

4. The package structure of claim 1, wherein the first heat conductive member comprises a plurality of first heat conductive pillars spaced apart from one another; the second heat conductive member includes a plurality of second heat conductive posts spaced apart from each other.

5. The package structure of claim 4, wherein the number of second heat conductive pillars is greater than the number of first heat conductive pillars; and/or, the bottom surface area of the second heat conduction column is larger than the bottom surface area of the first heat conduction column.

6. The package structure of claim 4, wherein a distribution density of the first conductive pillars is less than a distribution density of the second conductive pillars.

7. The package structure of claim 4, wherein at least a portion of the first thermally conductive post comprises a stepped surface; and/or, at least part of the second heat conduction columns comprise step surfaces;

wherein the step surfaces in the different first heat conducting columns and/or the different second heat conducting columns are different in distance from the top surface of the encapsulation structure.

8. The package structure of claim 1, wherein the thermal conductivity of the material of the thermally conductive structure is greater than the thermal conductivity of the material of the encapsulation structure.

9. The package structure of claim 1, further comprising:

a wire structure connecting the at least one chip and the interconnect structure;

a third heat conductive member located on the wire structure;

wherein a second distance is provided between the bottom surface of the third heat conducting member and the wire structure; the second distance is greater than the first distance.

10. The manufacturing method of the packaging structure is characterized by comprising the following steps:

providing a substrate;

forming an interconnection structure; the interconnect structure includes opposing first and second sides;

providing at least one chip, and stacking the at least one chip on the first side along the thickness direction of the interconnection structure;

forming an encapsulation structure encapsulating the at least one chip and the interconnect structure;

forming a heat conduction structure extending from the top surface of the encapsulation structure along the thickness direction of the substrate; the heat conducting structure comprises a first heat conducting piece positioned on the at least one chip and/or a second heat conducting piece positioned at the periphery of the at least one chip and spaced from the at least one chip; and

contacting the substrate with the interconnect structure on the second side; the circuitry in the substrate is connected to the at least one chip through the interconnect structure.