CN116978415A

CN116978415A - Storage equipment

Info

Publication number: CN116978415A
Application number: CN202210429322.2A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Timi Xinchuang Shanghai Technology Co ltd
Current assignee: Timi Xinchuang Shanghai Technology Co ltd
Priority date: 2022-04-22
Filing date: 2022-04-22
Publication date: 2023-10-31

Abstract

The invention discloses a memory device, which is used for supplying power to a data signal driver in a memory chip by connecting a VDDQ solder ball of a package body with a VDDQ solder pad in the memory chip; and add a VDD2 bonding pad in the memory chip, two VDD2 bonding pads are separated each other and are all connected with VDD2 solder balls of the package body, one VDD2 bonding pad is used for supplying power to the combined circuit in the memory chip, another VDD2 bonding pad is used for supplying power to the control path in the memory chip, thus optimizing the on-chip power supply connection mode, avoiding power supply noise and realizing the characteristic of ensuring good signal integrity of data.

Description

Storage equipment

Technical Field

The present invention relates to the field of storage devices, and in particular, to a storage device capable of optimizing an on-chip power connection mode.

Background

The input/output standard has different power supply voltages (powers) depending on the application. For example, various power supply voltages are used in the Low Power Double Data Rate (LPDDR) standard for interfacing between mobile computers (e.g., smartphones and tablet computers) and synchronous dynamic random access memory (Synchronous Dynamic Random Access Memory, SDRAM for short). In the LPDDR3 standard, the nominal supply voltage is 1.2V, whereas for the LPDDR4X (LP 4X) standard, the nominal supply voltage is 0.6V. In general, more modern standards reduce the supply voltage in order to save power.

As the power supply voltage of a System (System) is lower, the data rate (data rate) thereof is gradually increased, so that one of the direct characteristics of a memory device (memory device) and a System on a chip (SoC), the characteristic of signal integrity (signal integrity) of data becomes particularly important. The signal integrity of the data of a memory device is derived from jitter of a combination circuit (combination) inside a memory chip (memory chip) because of power noise (power noise) inside the chip.

Each power ball (power ball) of the Package (Package) is directly connected to each power PAD (power PAD) inside the memory chip. The existing on-chip power connection mode is generally as follows: the VDDQ solder balls of the package are connected to VDDQ pads inside the memory chip, and are mainly used to power circuits related to Read/Write paths (Read/Write paths) of DQ/DQs, such as a data signal driver (DQ driver), a data signal sequencer (DQ sequencer), and the like. In the conventional memory device, since a power supply voltage passing through the VDDQ pad is used not only to supply power to the data signal driver but also to supply power to a data path (data path) circuit inside the memory chip, there is a power supply noise, resulting in poor characteristics of signal integrity of data.

Therefore, a solution to the above-described problems is needed.

Disclosure of Invention

The invention aims to provide a memory device which can optimize an on-chip power supply connection mode and ensure the characteristic of good signal integrity of data.

In order to achieve the above object, the present invention provides a storage device including: the first power supply voltage welding pad is arranged inside the memory chip and connected to a first power supply voltage welding ball arranged on the packaging body for supplying power to a first path circuit inside the memory chip; the second power supply voltage welding pad is arranged inside the memory chip and connected to the first power supply voltage welding ball so as to be used for supplying power to a second path circuit inside the memory chip; and a third power supply voltage welding pad arranged inside the memory chip and connected to a second power supply voltage welding ball arranged on the packaging body for supplying power to a third path circuit inside the memory chip.

The storage device is used for supplying power to a data signal driver in the storage chip by connecting the VDDQ solder balls of the package body with the VDDQ solder pads in the storage chip; and add a VDD2 bonding pad in the memory chip, two VDD2 bonding pads are separated each other and are all connected with VDD2 solder balls of the package body, one VDD2 bonding pad is used for supplying power to the combined circuit in the memory chip, another VDD2 bonding pad is used for supplying power to the control path in the memory chip, thus optimizing the on-chip power supply connection mode, avoiding power supply noise and realizing the characteristic of ensuring good signal integrity of data.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that are required to be used in the description of the embodiments will be briefly described below. It is evident that the drawings in the following description are only some embodiments of the present invention and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.

FIG. 1 is a schematic diagram of an on-chip power connection scheme according to an embodiment of the prior art;

FIG. 2 is a schematic diagram of a memory device according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of an on-chip power connection scheme of a memory device according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of an embodiment of the portion A in FIG. 3;

FIG. 5 is a schematic diagram of a mode selection embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.

Fig. 1 is a schematic diagram of an on-chip power connection method according to an embodiment of the prior art. As shown in fig. 1, VDDQ solder balls of a package (package) 11 are connected to VDDQ pads inside a memory chip (memory chip) 12, and are used to supply power to a data signal driver (DQ driver) 121 and a data signal sequencer (DQ sequencer) 122 inside the memory chip 12, respectively; the VDD2 solder balls of the package 11 are connected to the VDD2 pads inside the memory chip 12 for supplying power to a combination circuit (combination) 123 inside the memory chip 12. In the conventional memory device, since a power supply voltage passing through the VDDQ pad is used not only to supply power to the data signal driver but also to supply power to a data path (data path) circuit inside the memory chip, there is a power supply noise, resulting in poor characteristics of signal integrity of data.

Based on the above-mentioned problems, the present invention provides a memory device capable of optimizing on-chip power connection, which is configured to connect VDDQ solder balls of a package with VDDQ pads inside a memory chip and only supply power to a data signal driver inside the memory chip; a VDD2 welding pad is additionally arranged in the memory chip, the two VDD2 welding pads are mutually separated and are connected with the VDD2 welding ball of the packaging body, one VDD2 welding pad is used for supplying power to a combined circuit in the memory chip, and the other VDD2 welding pad is used for supplying power to a control path (such as a data signal sequencer) in the memory chip; power supply noise is avoided and the feature of ensuring good signal integrity of the data is achieved.

Fig. 2 is a schematic diagram of a memory device according to an embodiment of the invention. As shown in fig. 2, the storage device 20 provided in this embodiment includes: a package (package) 21 and a memory chip (memory chip) 22. The memory chip 22 is internally provided with a plurality of power supply voltage pads. Specifically, the storage device 20 includes: a first power PAD (1 st power PAD) 221, a second power PAD (2 nd power PAD) 222, and a third power PAD (3 rd power PAD) 223.

The first power supply voltage pad 221 is disposed inside the memory chip 22 and connected to a first power supply voltage solder ball 211 disposed on the package body 21 for supplying power to a first path circuit 224 inside the memory chip 22. The second power supply voltage pad 222 is disposed inside the memory chip 22 and connected to the first power supply voltage solder ball 211 for supplying power to the second path circuit 225 inside the memory chip 22. The third power supply voltage pad 223 is disposed inside the memory chip 22 and connected to a second power supply voltage solder ball 212 disposed on the package 21 for supplying power to a third path circuit 226 inside the memory chip 22.

In some embodiments, the first power supply voltage pad 221 and the second power supply voltage pad 222 are formed in the same metal layer and are separated from each other; therefore, circuits of different paths can be respectively supplied with power, and voltage interference among different paths is avoided.

In some embodiments, the first power voltage solder balls 211 may be VDD2 solder balls (VDD 2 ball), and the first power voltage PADs 221 and the second power voltage PADs 222 are VDD2 PADs (VDD 2 PAD). Accordingly, the first path circuit 223 may be a critical path (critical path) circuit. In particular, the critical path may include a data path (data path) and an internal clock path (internal clock path). Accordingly, the second path circuit 224 may be a control path (control path) circuit. In particular, the control path circuitry may include all but the critical path circuitry, for example, may include at least a data signal sequencer (DQ sequencer). Since the power supply used in the critical path circuit and the power supply used in the control path circuit are separated from each other in the same metal layer, voltage interference is avoided.

In some embodiments, the second power supply voltage solder balls 212 may be VDDQ solder balls (VDDQ ball) and the third power supply voltage PADs 223 may be VDDQ PADs (VDDQ PAD). Accordingly, the third path circuit 226 includes a data signal driver (DQ driver). That is, the VDDQ solder balls on the package are connected with the VDDQ pads on the memory chip, and are only used to supply power to the data signal driver, thereby avoiding power supply noise and realizing the characteristic of ensuring good signal integrity of data.

In some embodiments, the storage device 20 further comprises: a data signal PAD (DQPAD) 227; the data signal pads 227 are disposed inside the memory chip 22 and connected to a data signal solder ball (DQ ball) 213 disposed on the package 21 and to the third path circuit 226, respectively; for example to a data signal driver.

Referring to fig. 3 to fig. 5, fig. 3 is a schematic diagram of an on-chip power connection mode of a memory device according to an embodiment of the invention, fig. 4 is a schematic diagram of an embodiment of a portion a in fig. 3, and fig. 5 is a schematic diagram of a mode selection embodiment of the invention.

As shown in fig. 3, in the present embodiment, the first power voltage solder ball 211 is a VDD2 solder ball (VDD 2 ball), and the first power voltage PAD 221 and the second power voltage PAD 222 are both VDD2 PADs (VDD 2 PAD). The first path circuit 223 is a combination circuit (combination) inside the memory chip 22; the second path circuit 224 includes a data signal sequencer (DQ sequencer). Since the first path circuit 223 and the second path circuit 224 are distributed and connected to different VDD2 PADs, and the VDD2 PADs are separated from each other in the same metal layer, voltage interference is avoided.

As shown in fig. 3, in the present embodiment, the second power supply voltage solder ball 212 is a VDDQ solder ball (VDDQ ball), and the third power supply voltage solder PAD 223 is a VDDQ solder PAD (VDDQ PAD). The third path circuit 226 includes a data signal driver (DQ driver). Because the VDDQ solder balls on the package body are connected with the VDDQ solder pads on the memory chip, the power supply is only used for supplying power to the data signal driver, so that power supply noise is avoided, and the characteristic of ensuring good signal integrity of data is realized.

As shown in fig. 3, in this embodiment, the storage device 20 further includes: a data signal PAD (DQPAD) 227; the data signal pads 227 are disposed inside the memory chip 22 and connected to a data signal solder ball (DQ ball) 213 disposed on the package 21 and the data signal driver, respectively.

As shown in fig. 4, in some embodiments, the third path circuit 226 includes a first data signal driver 41, a second data signal driver 42, and a Demultiplexer (Demultiplexer) 43; the demultiplexer 43 is configured to select one of the first data signal driver 41 and the second data signal driver 42 to form a data path with a data signal pad DQ in response to a mode selection signal. That is, a combined design of different low power double data rate standards (e.g., LP4 and LP 4X) may be performed with one memory chip.

In some embodiments, the first data signal driver 41 is a low power double data rate 4 data signal driver (LP 4 DQ driver), and the second data signal driver 42 is a low power double data rate 4X data signal driver (LP 4X DQ driver). By composing DQ drivers capable of covering Rtt (Round-Trip Time) of LP4 and LP4X and switching LP4 and LP4X with mode selection signals, the combination design of LP4 and LP4X can be performed with one memory chip. For example, default (default) is LP4X mode, and the mode is switched to LP4 mode by fuse. Accordingly, as in FIG. 4, reference numeral 401 illustrates an LP4 data-path, and reference numeral 402 illustrates an LP4X data-path; in the default state, the LP4 data path forms a path, and after the fuse is switched, the LP4X data path forms a path.

In some embodiments, the memory device 20 further includes a voltage generator for generating different supply voltages at the third supply voltage pad according to a mode select signal to provide operating voltages for DQ drivers of different modes. For example, generating a first power supply voltage at the third power supply voltage pad according to a first mode selection signal as an operating voltage of the LP4 mode; generating a second power supply voltage at the third power supply voltage pad according to a second mode selection signal as an operating voltage of the LP4X mode; therefore, the power supply voltage generated at the third power supply voltage welding pad, especially the output high level (VOH level), meets the specification requirements of different standard modes.

As shown in fig. 5, in some embodiments, the voltage generator 51 comprises; the first transistor P1, the second transistor P2, the first resistor string R11 and the second resistor string R12. The control terminal of the first transistor P1 is configured to receive a first mode selection signal, a first terminal thereof is connected to the third power supply voltage pad, and a second terminal thereof is connected to the first resistor string R11. The first resistor string R11 is connected in series with the second resistor string R12 and then grounded, and at least one resistor in the second resistor string R12 is controlled to be connected to the reference voltage Vref. The control terminal of the second transistor P2 is configured to receive a second mode selection signal, a first terminal thereof is connected to the third power supply voltage pad, and a second terminal thereof is connected to the first resistor string R11 and the common terminal R12 of the second resistor string. A first power supply voltage is generated at the third power supply voltage pad when the first transistor P1 is turned on in response to the first mode selection signal, and a second power supply voltage is generated at the third power supply voltage pad when the second transistor P2 is turned on in response to the second mode selection signal.

In this embodiment, the signal trend of the DRAM read path (read path) is: the data is read out from a DQ sequencer (sequencer) in the second path circuit to a DQ driver in the third path circuit via a DQ pad; the signal trend of the DRAM write path (write path) is: the data is written from the DQ pad to a DQ receiving terminal (DQ Rx) in the third path circuit, the DQ receiving terminal receives the reference voltage Vref at the same time, and an output signal of the DQ receiving terminal is written via a DQ deserializer (de-seriizer) in the second path circuit.

Specifically, the third power supply voltage pad is a VDDQ pad, and when the first transistor P1 is turned on in response to the first mode selection signal, a first power supply voltage (e.g., vddq=1.1v) is generated at the VDDQ pad as an operating voltage of the LP4 mode; when the second transistor P2 is turned on in response to the second mode selection signal, a second power supply voltage (e.g., vddq=0.6v) is generated at the VDDQ pad as an operating voltage of the LP4X mode. Since the operating voltages of different low power double data rate standards, particularly the range of output high levels (VOH levels), vary in specification, by varying the number of resistors, operating voltages that meet different low power double data rate standards are generated.

In some embodiments, the first mode select signal is an LP4 enable signal and the second mode select signal is an LP4X enable signal; the first transistor P1 and the second transistor P2 are PMOS transistors. Assuming that the default (default) operation mode is the LP4X standard mode, the PMOS transistor P1 receiving the LP4 enable signal input is turned off, and the LP4X enable signal drives P2 to be turned on; when the mode is required to be switched, fuse processing is performed on the LP4 DQ driver, so that the LP4 enable signal drives P1 on, and the PMOS transistor P2 receiving the LP4X enable signal input is turned off.

In some embodiments, the first resistor string R11 includes 83 series resistors having the same resistance value, and the second resistor string R12 includes 167 series resistors having the same resistance value; the reference voltage is connected to the second resistor string R12 via a plurality of controlled switches (which may be connected to a plurality of resistors via switches, respectively). That is, in the LP4 mode of operation, 250 resistors are employed for generating a series of Vref values and operating voltages VDDQ that meet the LP4 standard; in the LP4X mode of operation, 167 resistors are employed for generating a range of Vref values and operating voltages VDDQ that meet the JEDEC (solid state technology association, the leading standards body of the microelectronics industry) recommendations. That is, the reference voltage (specifically VrefCA, vrefDQ) standard (level) used in the data writing path is converted to a standard conforming to LP4 and LP4X by the voltage generator 51. When the memory system works, vrefCA is a reference voltage signal for serving command and address signals, and VrefDQ is a reference voltage signal for serving a data bus.

In some embodiments, the memory device 20 may be a dynamic random access memory Device (DRAM), a Double Data Rate (DDR) synchronous dynamic random access memory device (SDRAM), a low power double data rate 4 (LPDDR 4) SDRAM, or a low power double data rate 4X (LPDDR 4X) SDRAM.

As can be seen from the above, the memory device provided in this embodiment is used only for supplying power to the data signal driver inside the memory chip by connecting the VDDQ solder balls of the package body with the VDDQ pads inside the memory chip; and add a VDD2 bonding pad in the memory chip, two VDD2 bonding pads are separated each other and are all connected with VDD2 solder balls of the package body, one VDD2 bonding pad is used for supplying power to the combined circuit in the memory chip, another VDD2 bonding pad is used for supplying power to the control path in the memory chip, thus optimizing the on-chip power supply connection mode, avoiding power supply noise and realizing the characteristic of ensuring good signal integrity of data.

Within the scope of the inventive concept, embodiments may be described and illustrated in terms of blocks that perform one or more of the functions described. These blocks (which may be referred to herein as units or modules, etc.) are physically implemented by analog and/or digital circuits, for example logic gates, integrated circuits, microprocessors, microcontrollers, storage device circuits, passive electronic elements, active electronic elements, optical components, hardwired circuits, etc., and may optionally be driven by firmware and/or software. The circuitry may be implemented, for example, in one or more semiconductor chips. The circuitry comprising a block may be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware that performs some of the functions of the block and a processor that performs other functions of the block. Each block of the embodiments may be physically separated into two or more interactive and discrete blocks without departing from the scope of the inventive concept. Likewise, the blocks of the embodiments may be physically combined into more complex blocks without departing from the scope of the inventive concept.

It should be noted that references in the specification to "one embodiment," "an embodiment," "some embodiments," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the relevant art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

Generally, the terms may be understood, at least in part, from the usage in the context. For example, the term "one or more" as used herein, depending at least in part on the context, may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a feature, structure, or combination of features in a plural sense. Similarly, terms such as "a," "an," or "the" may also be construed to express singular usage or plural usage depending at least in part on the context. In addition, the term "based on" may be understood as not necessarily intended to express a set of exclusive factors, but may instead, depending at least in part on the context, allow for other factors that are not necessarily explicitly described. It should also be noted in this specification that "connected/coupled" means not only that one component is directly coupled to another component, but also that one component is indirectly coupled to another component through intervening components.

It should be noted that the terms "comprising" and "having" and their variants are referred to in the document of the present invention and are intended to cover non-exclusive inclusion. The terms "first," "second," and the like are used to distinguish similar objects and not necessarily to describe a particular order or sequence unless otherwise indicated by context, it should be understood that the data so used may be interchanged where appropriate. In addition, the embodiments of the present invention and the features in the embodiments may be combined with each other without collision. In addition, in the above description, descriptions of well-known components and techniques are omitted so as to not unnecessarily obscure the present invention.

The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.

Claims

1. A memory device, comprising:

the first power supply voltage welding pad is arranged inside the memory chip and connected to a first power supply voltage welding ball arranged on the packaging body for supplying power to a first path circuit inside the memory chip; the second power supply voltage welding pad is arranged inside the memory chip and connected to the first power supply voltage welding ball so as to be used for supplying power to a second path circuit inside the memory chip; and

and a third power supply voltage welding pad arranged inside the memory chip and connected to a second power supply voltage welding ball arranged on the packaging body for supplying power to a third path circuit inside the memory chip.

2. The memory device of claim 1, wherein the first power supply voltage pad and the second power supply voltage pad are formed in the same metal layer and are separated from each other.

3. The memory device of claim 1, wherein the first power supply voltage solder ball is a VDD2 solder ball, and the first power supply voltage pad and the second power supply voltage pad are both VDD2 pads.

4. The storage device of claim 3,

the first path circuit is a critical path circuit, and the critical path comprises a data path and an internal clock path;

the second path circuit is a control path circuit, and the control path circuit at least comprises a data signal sequencer.

5. The memory device of claim 1, wherein the second supply voltage solder balls are VDDQ solder balls and the third supply voltage pads are VDDQ pads; the third path circuit includes a data signal driver.

6. The storage device of claim 1, wherein the storage device further comprises:

and a data signal welding pad arranged inside the memory chip and respectively connected to a data signal welding ball arranged on the packaging body and the third path circuit.

7. The memory device of claim 6, wherein the third path circuit comprises a first data signal driver, a second data signal driver, and a demultiplexer;

the demultiplexer is configured to select one of the first data signal driver and the second data signal driver to form a data path with the data signal pad in response to a mode selection signal.

8. The memory device of claim 7, wherein the first data signal driver is a low power double data rate 4 data signal driver and the second data signal driver is a low power double data rate 4X data signal driver.

9. The memory device of claim 1 or 7, wherein the memory device further comprises a voltage generator, the voltage generator comprising;

a first transistor having a control terminal for receiving a first mode selection signal, a first terminal connected to the third power supply voltage pad, and a second terminal connected to a first resistor string;

the first resistor string is connected with the second resistor string in series and then grounded, and at least one resistor in the second resistor string is connected to a reference voltage in a controlled manner;

a second transistor, a control end of which is used for receiving a second mode selection signal, a first end of which is connected to the third power supply voltage welding pad, and a second end of which is connected to a common end of the first resistor string and the second resistor string;

wherein a first power supply voltage is generated at the third power supply voltage pad when the first transistor is turned on in response to the first mode selection signal, and a second power supply voltage is generated at the third power supply voltage pad when the second transistor is turned on in response to the second mode selection signal.

10. The memory device of claim 9, wherein the first mode select signal is a LP4 enable signal and the second mode select signal is a LP4X enable signal;

the first transistor and the second transistor are PMOS transistors;

the first resistor string comprises 83 series resistors with the same resistance value, and the second resistor string comprises 167 series resistors with the same resistance value.